tests/ahci-test.c

   1 /*
   2  * AHCI test cases
   3  *
   4  * Copyright (c) 2014 John Snow <jsnow@redhat.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include <stdint.h>
  26 #include <string.h>
  27 #include <stdio.h>
  28 #include <getopt.h>
  29 #include <glib.h>
  30
  31 #include "libqtest.h"
  32 #include "libqos/libqos-pc.h"
  33 #include "libqos/ahci.h"
  34 #include "libqos/pci-pc.h"
  35
  36 #include "qemu-common.h"
  37 #include "qemu/host-utils.h"
  38
  39 #include "hw/pci/pci_ids.h"
  40 #include "hw/pci/pci_regs.h"
  41
  42 /* Test-specific defines. */
  43 #define TEST_IMAGE_SIZE    (64 * 1024 * 1024)
  44
  45 /*** Globals ***/
  46 static char tmp_path[] = "/tmp/qtest.XXXXXX";
  47 static bool ahci_pedantic;
  48
  49 /*** Function Declarations ***/
  50 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port);
  51 static void ahci_test_pci_spec(AHCIQState *ahci);
  52 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
  53                                uint8_t offset);
  54 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset);
  55 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset);
  56 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset);
  57
  58 /*** Utilities ***/
  59
  60 static void string_bswap16(uint16_t *s, size_t bytes)
  61 {
  62     g_assert_cmphex((bytes & 1), ==, 0);
  63     bytes /= 2;
  64
  65     while (bytes--) {
  66         *s = bswap16(*s);
  67         s++;
  68     }
  69 }
  70
  71 /*** Test Setup & Teardown ***/
  72
  73 /**
  74  * Start a Q35 machine and bookmark a handle to the AHCI device.
  75  */
  76 static AHCIQState *ahci_boot(void)
  77 {
  78     AHCIQState *s;
  79     const char *cli;
  80
  81     s = g_malloc0(sizeof(AHCIQState));
  82
  83     cli = "-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s"
  84         ",format=raw"
  85         " -M q35 "
  86         "-device ide-hd,drive=drive0 "
  87         "-global ide-hd.ver=%s";
  88     s->parent = qtest_pc_boot(cli, tmp_path, "testdisk", "version");
  89     alloc_set_flags(s->parent->alloc, ALLOC_LEAK_ASSERT);
  90
  91     /* Verify that we have an AHCI device present. */
  92     s->dev = get_ahci_device(&s->fingerprint);
  93
  94     return s;
  95 }
  96
  97 /**
  98  * Clean up the PCI device, then terminate the QEMU instance.
  99  */
 100 static void ahci_shutdown(AHCIQState *ahci)
 101 {
 102     QOSState *qs = ahci->parent;
 103
 104     ahci_clean_mem(ahci);
 105     free_ahci_device(ahci->dev);
 106     g_free(ahci);
 107     qtest_shutdown(qs);
 108 }
 109
 110 /*** Specification Adherence Tests ***/
 111
 112 /**
 113  * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
 114  */
 115 static void ahci_test_pci_spec(AHCIQState *ahci)
 116 {
 117     uint8_t datab;
 118     uint16_t data;
 119     uint32_t datal;
 120
 121     /* Most of these bits should start cleared until we turn them on. */
 122     data = qpci_config_readw(ahci->dev, PCI_COMMAND);
 123     ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY);
 124     ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER);
 125     ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL);     /* Reserved */
 126     ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE); /* Reserved */
 127     ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY);
 128     ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT);        /* Reserved */
 129     ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR);
 130     ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK);
 131     ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE);
 132     ASSERT_BIT_CLEAR(data, 0xF800);                  /* Reserved */
 133
 134     data = qpci_config_readw(ahci->dev, PCI_STATUS);
 135     ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04);     /* Reserved */
 136     ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT);
 137     ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST);      /* must be set */
 138     ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF);         /* Reserved */
 139     ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY);
 140     ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT);
 141     ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT);
 142     ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT);
 143     ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR);
 144     ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY);
 145
 146     /* RID occupies the low byte, CCs occupy the high three. */
 147     datal = qpci_config_readl(ahci->dev, PCI_CLASS_REVISION);
 148     if (ahci_pedantic) {
 149         /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
 150          * Though in practice this is likely seldom true. */
 151         ASSERT_BIT_CLEAR(datal, 0xFF);
 152     }
 153
 154     /* BCC *must* equal 0x01. */
 155     g_assert_cmphex(PCI_BCC(datal), ==, 0x01);
 156     if (PCI_SCC(datal) == 0x01) {
 157         /* IDE */
 158         ASSERT_BIT_SET(0x80000000, datal);
 159         ASSERT_BIT_CLEAR(0x60000000, datal);
 160     } else if (PCI_SCC(datal) == 0x04) {
 161         /* RAID */
 162         g_assert_cmphex(PCI_PI(datal), ==, 0);
 163     } else if (PCI_SCC(datal) == 0x06) {
 164         /* AHCI */
 165         g_assert_cmphex(PCI_PI(datal), ==, 0x01);
 166     } else {
 167         g_assert_not_reached();
 168     }
 169
 170     datab = qpci_config_readb(ahci->dev, PCI_CACHE_LINE_SIZE);
 171     g_assert_cmphex(datab, ==, 0);
 172
 173     datab = qpci_config_readb(ahci->dev, PCI_LATENCY_TIMER);
 174     g_assert_cmphex(datab, ==, 0);
 175
 176     /* Only the bottom 7 bits must be off. */
 177     datab = qpci_config_readb(ahci->dev, PCI_HEADER_TYPE);
 178     ASSERT_BIT_CLEAR(datab, 0x7F);
 179
 180     /* BIST is optional, but the low 7 bits must always start off regardless. */
 181     datab = qpci_config_readb(ahci->dev, PCI_BIST);
 182     ASSERT_BIT_CLEAR(datab, 0x7F);
 183
 184     /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
 185     datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
 186     g_assert_cmphex(datal, ==, 0);
 187
 188     qpci_config_writel(ahci->dev, PCI_BASE_ADDRESS_5, 0xFFFFFFFF);
 189     datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5);
 190     /* ABAR must be 32-bit, memory mapped, non-prefetchable and
 191      * must be >= 512 bytes. To that end, bits 0-8 must be off. */
 192     ASSERT_BIT_CLEAR(datal, 0xFF);
 193
 194     /* Capability list MUST be present, */
 195     datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST);
 196     /* But these bits are reserved. */
 197     ASSERT_BIT_CLEAR(datal, ~0xFF);
 198     g_assert_cmphex(datal, !=, 0);
 199
 200     /* Check specification adherence for capability extenstions. */
 201     data = qpci_config_readw(ahci->dev, datal);
 202
 203     switch (ahci->fingerprint) {
 204     case AHCI_INTEL_ICH9:
 205         /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
 206         g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI);
 207         break;
 208     default:
 209         /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
 210         g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM);
 211     }
 212
 213     ahci_test_pci_caps(ahci, data, (uint8_t)datal);
 214
 215     /* Reserved. */
 216     datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST + 4);
 217     g_assert_cmphex(datal, ==, 0);
 218
 219     /* IPIN might vary, but ILINE must be off. */
 220     datab = qpci_config_readb(ahci->dev, PCI_INTERRUPT_LINE);
 221     g_assert_cmphex(datab, ==, 0);
 222 }
 223
 224 /**
 225  * Test PCI capabilities for AHCI specification adherence.
 226  */
 227 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
 228                                uint8_t offset)
 229 {
 230     uint8_t cid = header & 0xFF;
 231     uint8_t next = header >> 8;
 232
 233     g_test_message("CID: %02x; next: %02x", cid, next);
 234
 235     switch (cid) {
 236     case PCI_CAP_ID_PM:
 237         ahci_test_pmcap(ahci, offset);
 238         break;
 239     case PCI_CAP_ID_MSI:
 240         ahci_test_msicap(ahci, offset);
 241         break;
 242     case PCI_CAP_ID_SATA:
 243         ahci_test_satacap(ahci, offset);
 244         break;
 245
 246     default:
 247         g_test_message("Unknown CAP 0x%02x", cid);
 248     }
 249
 250     if (next) {
 251         ahci_test_pci_caps(ahci, qpci_config_readw(ahci->dev, next), next);
 252     }
 253 }
 254
 255 /**
 256  * Test SATA PCI capabilitity for AHCI specification adherence.
 257  */
 258 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset)
 259 {
 260     uint16_t dataw;
 261     uint32_t datal;
 262
 263     g_test_message("Verifying SATACAP");
 264
 265     /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
 266     dataw = qpci_config_readw(ahci->dev, offset + 2);
 267     g_assert_cmphex(dataw, ==, 0x10);
 268
 269     /* Grab the SATACR1 register. */
 270     datal = qpci_config_readw(ahci->dev, offset + 4);
 271
 272     switch (datal & 0x0F) {
 273     case 0x04: /* BAR0 */
 274     case 0x05: /* BAR1 */
 275     case 0x06:
 276     case 0x07:
 277     case 0x08:
 278     case 0x09: /* BAR5 */
 279     case 0x0F: /* Immediately following SATACR1 in PCI config space. */
 280         break;
 281     default:
 282         /* Invalid BARLOC for the Index Data Pair. */
 283         g_assert_not_reached();
 284     }
 285
 286     /* Reserved. */
 287     g_assert_cmphex((datal >> 24), ==, 0x00);
 288 }
 289
 290 /**
 291  * Test MSI PCI capability for AHCI specification adherence.
 292  */
 293 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset)
 294 {
 295     uint16_t dataw;
 296     uint32_t datal;
 297
 298     g_test_message("Verifying MSICAP");
 299
 300     dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_FLAGS);
 301     ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE);
 302     ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE);
 303     ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED);
 304
 305     datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_LO);
 306     g_assert_cmphex(datal, ==, 0);
 307
 308     if (dataw & PCI_MSI_FLAGS_64BIT) {
 309         g_test_message("MSICAP is 64bit");
 310         datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_HI);
 311         g_assert_cmphex(datal, ==, 0);
 312         dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_64);
 313         g_assert_cmphex(dataw, ==, 0);
 314     } else {
 315         g_test_message("MSICAP is 32bit");
 316         dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_32);
 317         g_assert_cmphex(dataw, ==, 0);
 318     }
 319 }
 320
 321 /**
 322  * Test Power Management PCI capability for AHCI specification adherence.
 323  */
 324 static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset)
 325 {
 326     uint16_t dataw;
 327
 328     g_test_message("Verifying PMCAP");
 329
 330     dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_PMC);
 331     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK);
 332     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED);
 333     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1);
 334     ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2);
 335
 336     dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_CTRL);
 337     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK);
 338     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED);
 339     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK);
 340     ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK);
 341 }
 342
 343 static void ahci_test_hba_spec(AHCIQState *ahci)
 344 {
 345     unsigned i;
 346     uint32_t reg;
 347     uint32_t ports;
 348     uint8_t nports_impl;
 349     uint8_t maxports;
 350
 351     g_assert(ahci != NULL);
 352
 353     /*
 354      * Note that the AHCI spec does expect the BIOS to set up a few things:
 355      * CAP.SSS    - Support for staggered spin-up            (t/f)
 356      * CAP.SMPS   - Support for mechanical presence switches (t/f)
 357      * PI         - Ports Implemented                        (1-32)
 358      * PxCMD.HPCP - Hot Plug Capable Port
 359      * PxCMD.MPSP - Mechanical Presence Switch Present
 360      * PxCMD.CPD  - Cold Presence Detection support
 361      *
 362      * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
 363      * Foreach Port Implemented:
 364      * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
 365      * -PxCLB/U and PxFB/U are set to valid regions in memory
 366      * -PxSUD is set to 1.
 367      * -PxSSTS.DET is polled for presence; if detected, we continue:
 368      * -PxSERR is cleared with 1's.
 369      * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
 370      *  the device is ready.
 371      */
 372
 373     /* 1 CAP - Capabilities Register */
 374     ahci->cap = ahci_rreg(ahci, AHCI_CAP);
 375     ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED);
 376
 377     /* 2 GHC - Global Host Control */
 378     reg = ahci_rreg(ahci, AHCI_GHC);
 379     ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR);
 380     ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE);
 381     ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM);
 382     if (BITSET(ahci->cap, AHCI_CAP_SAM)) {
 383         g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
 384         ASSERT_BIT_SET(reg, AHCI_GHC_AE);
 385     } else {
 386         g_test_message("Supports AHCI/Legacy mix.");
 387         ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE);
 388     }
 389
 390     /* 3 IS - Interrupt Status */
 391     reg = ahci_rreg(ahci, AHCI_IS);
 392     g_assert_cmphex(reg, ==, 0);
 393
 394     /* 4 PI - Ports Implemented */
 395     ports = ahci_rreg(ahci, AHCI_PI);
 396     /* Ports Implemented must be non-zero. */
 397     g_assert_cmphex(ports, !=, 0);
 398     /* Ports Implemented must be <= Number of Ports. */
 399     nports_impl = ctpopl(ports);
 400     g_assert_cmpuint(((AHCI_CAP_NP & ahci->cap) + 1), >=, nports_impl);
 401
 402     /* Ports must be within the proper range. Given a mapping of SIZE,
 403      * 256 bytes are used for global HBA control, and the rest is used
 404      * for ports data, at 0x80 bytes each. */
 405     g_assert_cmphex(ahci->barsize, >, 0);
 406     maxports = (ahci->barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE;
 407     /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
 408     g_assert_cmphex((reg >> maxports), ==, 0);
 409
 410     /* 5 AHCI Version */
 411     reg = ahci_rreg(ahci, AHCI_VS);
 412     switch (reg) {
 413     case AHCI_VERSION_0_95:
 414     case AHCI_VERSION_1_0:
 415     case AHCI_VERSION_1_1:
 416     case AHCI_VERSION_1_2:
 417     case AHCI_VERSION_1_3:
 418         break;
 419     default:
 420         g_assert_not_reached();
 421     }
 422
 423     /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
 424     reg = ahci_rreg(ahci, AHCI_CCCCTL);
 425     if (BITSET(ahci->cap, AHCI_CAP_CCCS)) {
 426         ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN);
 427         ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED);
 428         ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC);
 429         ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV);
 430     } else {
 431         g_assert_cmphex(reg, ==, 0);
 432     }
 433
 434     /* 7 CCC_PORTS */
 435     reg = ahci_rreg(ahci, AHCI_CCCPORTS);
 436     /* Must be zeroes initially regardless of CAP.CCCS */
 437     g_assert_cmphex(reg, ==, 0);
 438
 439     /* 8 EM_LOC */
 440     reg = ahci_rreg(ahci, AHCI_EMLOC);
 441     if (BITCLR(ahci->cap, AHCI_CAP_EMS)) {
 442         g_assert_cmphex(reg, ==, 0);
 443     }
 444
 445     /* 9 EM_CTL */
 446     reg = ahci_rreg(ahci, AHCI_EMCTL);
 447     if (BITSET(ahci->cap, AHCI_CAP_EMS)) {
 448         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR);
 449         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM);
 450         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST);
 451         ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED);
 452     } else {
 453         g_assert_cmphex(reg, ==, 0);
 454     }
 455
 456     /* 10 CAP2 -- Capabilities Extended */
 457     ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2);
 458     ASSERT_BIT_CLEAR(ahci->cap2, AHCI_CAP2_RESERVED);
 459
 460     /* 11 BOHC -- Bios/OS Handoff Control */
 461     reg = ahci_rreg(ahci, AHCI_BOHC);
 462     g_assert_cmphex(reg, ==, 0);
 463
 464     /* 12 -- 23: Reserved */
 465     g_test_message("Verifying HBA reserved area is empty.");
 466     for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) {
 467         reg = ahci_rreg(ahci, i);
 468         g_assert_cmphex(reg, ==, 0);
 469     }
 470
 471     /* 24 -- 39: NVMHCI */
 472     if (BITCLR(ahci->cap2, AHCI_CAP2_NVMP)) {
 473         g_test_message("Verifying HBA/NVMHCI area is empty.");
 474         for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) {
 475             reg = ahci_rreg(ahci, i);
 476             g_assert_cmphex(reg, ==, 0);
 477         }
 478     }
 479
 480     /* 40 -- 63: Vendor */
 481     g_test_message("Verifying HBA/Vendor area is empty.");
 482     for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) {
 483         reg = ahci_rreg(ahci, i);
 484         g_assert_cmphex(reg, ==, 0);
 485     }
 486
 487     /* 64 -- XX: Port Space */
 488     for (i = 0; ports || (i < maxports); ports >>= 1, ++i) {
 489         if (BITSET(ports, 0x1)) {
 490             g_test_message("Testing port %u for spec", i);
 491             ahci_test_port_spec(ahci, i);
 492         } else {
 493             uint16_t j;
 494             uint16_t low = AHCI_PORTS + (32 * i);
 495             uint16_t high = AHCI_PORTS + (32 * (i + 1));
 496             g_test_message("Asserting unimplemented port %u "
 497                            "(reg [%u-%u]) is empty.",
 498                            i, low, high - 1);
 499             for (j = low; j < high; ++j) {
 500                 reg = ahci_rreg(ahci, j);
 501                 g_assert_cmphex(reg, ==, 0);
 502             }
 503         }
 504     }
 505 }
 506
 507 /**
 508  * Test the memory space for one port for specification adherence.
 509  */
 510 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port)
 511 {
 512     uint32_t reg;
 513     unsigned i;
 514
 515     /* (0) CLB */
 516     reg = ahci_px_rreg(ahci, port, AHCI_PX_CLB);
 517     ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED);
 518
 519     /* (1) CLBU */
 520     if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
 521         reg = ahci_px_rreg(ahci, port, AHCI_PX_CLBU);
 522         g_assert_cmphex(reg, ==, 0);
 523     }
 524
 525     /* (2) FB */
 526     reg = ahci_px_rreg(ahci, port, AHCI_PX_FB);
 527     ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED);
 528
 529     /* (3) FBU */
 530     if (BITCLR(ahci->cap, AHCI_CAP_S64A)) {
 531         reg = ahci_px_rreg(ahci, port, AHCI_PX_FBU);
 532         g_assert_cmphex(reg, ==, 0);
 533     }
 534
 535     /* (4) IS */
 536     reg = ahci_px_rreg(ahci, port, AHCI_PX_IS);
 537     g_assert_cmphex(reg, ==, 0);
 538
 539     /* (5) IE */
 540     reg = ahci_px_rreg(ahci, port, AHCI_PX_IE);
 541     g_assert_cmphex(reg, ==, 0);
 542
 543     /* (6) CMD */
 544     reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD);
 545     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE);
 546     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED);
 547     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS);
 548     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
 549     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
 550     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA); /* And RW only if CAP.SPM */
 551     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE); /* RW only if CAP2.APST */
 552     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI);
 553     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE);
 554     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE);  /* RW only if CAP.SALP */
 555     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP);   /* RW only if CAP.SALP */
 556     ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC);
 557     /* If CPDetect support does not exist, CPState must be off. */
 558     if (BITCLR(reg, AHCI_PX_CMD_CPD)) {
 559         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS);
 560     }
 561     /* If MPSPresence is not set, MPSState must be off. */
 562     if (BITCLR(reg, AHCI_PX_CMD_MPSP)) {
 563         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
 564     }
 565     /* If we do not support MPS, MPSS and MPSP must be off. */
 566     if (BITCLR(ahci->cap, AHCI_CAP_SMPS)) {
 567         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
 568         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP);
 569     }
 570     /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
 571     if (BITANY(reg, AHCI_PX_CMD_CPD || AHCI_PX_CMD_MPSP)) {
 572         ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP);
 573     }
 574     /* HPCP and ESP cannot both be active. */
 575     g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP));
 576     /* If CAP.FBSS is not set, FBSCP must not be set. */
 577     if (BITCLR(ahci->cap, AHCI_CAP_FBSS)) {
 578         ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP);
 579     }
 580
 581     /* (7) RESERVED */
 582     reg = ahci_px_rreg(ahci, port, AHCI_PX_RES1);
 583     g_assert_cmphex(reg, ==, 0);
 584
 585     /* (8) TFD */
 586     reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);
 587     /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
 588      * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
 589     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
 590     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1);
 591     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ);
 592     ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2);
 593     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
 594     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
 595     ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED);
 596
 597     /* (9) SIG */
 598     /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
 599      * Even when GHC.ST is zero, the AHCI HBA may receive the initial
 600      * D2H register FIS and update the signature asynchronously,
 601      * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
 602
 603     /* (10) SSTS / SCR0: SStatus */
 604     reg = ahci_px_rreg(ahci, port, AHCI_PX_SSTS);
 605     ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED);
 606     /* Even though the register should be 0 at boot, it is asynchronous and
 607      * prone to change, so we cannot test any well known value. */
 608
 609     /* (11) SCTL / SCR2: SControl */
 610     reg = ahci_px_rreg(ahci, port, AHCI_PX_SCTL);
 611     g_assert_cmphex(reg, ==, 0);
 612
 613     /* (12) SERR / SCR1: SError */
 614     reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR);
 615     g_assert_cmphex(reg, ==, 0);
 616
 617     /* (13) SACT / SCR3: SActive */
 618     reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT);
 619     g_assert_cmphex(reg, ==, 0);
 620
 621     /* (14) CI */
 622     reg = ahci_px_rreg(ahci, port, AHCI_PX_CI);
 623     g_assert_cmphex(reg, ==, 0);
 624
 625     /* (15) SNTF */
 626     reg = ahci_px_rreg(ahci, port, AHCI_PX_SNTF);
 627     g_assert_cmphex(reg, ==, 0);
 628
 629     /* (16) FBS */
 630     reg = ahci_px_rreg(ahci, port, AHCI_PX_FBS);
 631     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN);
 632     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC);
 633     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE);
 634     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV);
 635     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE);
 636     ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED);
 637     if (BITSET(ahci->cap, AHCI_CAP_FBSS)) {
 638         /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
 639         g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2);
 640     }
 641
 642     /* [17 -- 27] RESERVED */
 643     for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) {
 644         reg = ahci_px_rreg(ahci, port, i);
 645         g_assert_cmphex(reg, ==, 0);
 646     }
 647
 648     /* [28 -- 31] Vendor-Specific */
 649     for (i = AHCI_PX_VS; i < 32; ++i) {
 650         reg = ahci_px_rreg(ahci, port, i);
 651         if (reg) {
 652             g_test_message("INFO: Vendor register %u non-empty", i);
 653         }
 654     }
 655 }
 656
 657 /**
 658  * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
 659  * device we see, then read and check the response.
 660  */
 661 static void ahci_test_identify(AHCIQState *ahci)
 662 {
 663     uint16_t buff[256];
 664     unsigned px;
 665     int rc;
 666     uint16_t sect_size;
 667     const size_t buffsize = 512;
 668
 669     g_assert(ahci != NULL);
 670
 671     /**
 672      * This serves as a bit of a tutorial on AHCI device programming:
 673      *
 674      * (1) Create a data buffer for the IDENTIFY response to be sent to
 675      * (2) Create a Command Table buffer, where we will store the
 676      *     command and PRDT (Physical Region Descriptor Table)
 677      * (3) Construct an FIS host-to-device command structure, and write it to
 678      *     the top of the Command Table buffer.
 679      * (4) Create one or more Physical Region Descriptors (PRDs) that describe
 680      *     a location in memory where data may be stored/retrieved.
 681      * (5) Write these PRDTs to the bottom (offset 0x80) of the Command Table.
 682      * (6) Each AHCI port has up to 32 command slots. Each slot contains a
 683      *     header that points to a Command Table buffer. Pick an unused slot
 684      *     and update it to point to the Command Table we have built.
 685      * (7) Now: Command #n points to our Command Table, and our Command Table
 686      *     contains the FIS (that describes our command) and the PRDTL, which
 687      *     describes our buffer.
 688      * (8) We inform the HBA via PxCI (Command Issue) that the command in slot
 689      *     #n is ready for processing.
 690      */
 691
 692     /* Pick the first implemented and running port */
 693     px = ahci_port_select(ahci);
 694     g_test_message("Selected port %u for test", px);
 695
 696     /* Clear out the FIS Receive area and any pending interrupts. */
 697     ahci_port_clear(ahci, px);
 698
 699     /* "Read" 512 bytes using CMD_IDENTIFY into the host buffer. */
 700     ahci_io(ahci, px, CMD_IDENTIFY, &buff, buffsize);
 701
 702     /* Check serial number/version in the buffer */
 703     /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
 704      * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
 705      * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
 706      * as a consequence, only needs to unchunk the data on LE machines. */
 707     string_bswap16(&buff[10], 20);
 708     rc = memcmp(&buff[10], "testdisk            ", 20);
 709     g_assert_cmphex(rc, ==, 0);
 710
 711     string_bswap16(&buff[23], 8);
 712     rc = memcmp(&buff[23], "version ", 8);
 713     g_assert_cmphex(rc, ==, 0);
 714
 715     sect_size = le16_to_cpu(*((uint16_t *)(&buff[5])));
 716     g_assert_cmphex(sect_size, ==, 0x200);
 717 }
 718
 719 static void ahci_test_dma_rw_simple(AHCIQState *ahci)
 720 {
 721     uint64_t ptr;
 722     uint8_t port;
 723     unsigned i;
 724     const unsigned bufsize = 4096;
 725     unsigned char *tx = g_malloc(bufsize);
 726     unsigned char *rx = g_malloc0(bufsize);
 727
 728     g_assert(ahci != NULL);
 729
 730     /* Pick the first running port and clear it. */
 731     port = ahci_port_select(ahci);
 732     ahci_port_clear(ahci, port);
 733
 734     /*** Create pattern and transfer to guest ***/
 735     /* Data buffer in the guest */
 736     ptr = ahci_alloc(ahci, bufsize);
 737     g_assert(ptr);
 738
 739     /* Write some indicative pattern to our 4K buffer. */
 740     for (i = 0; i < bufsize; i++) {
 741         tx[i] = (bufsize - i);
 742     }
 743     memwrite(ptr, tx, bufsize);
 744
 745     /* Write this buffer to disk, then read it back to the DMA buffer. */
 746     ahci_guest_io(ahci, port, CMD_WRITE_DMA, ptr, bufsize);
 747     qmemset(ptr, 0x00, bufsize);
 748     ahci_guest_io(ahci, port, CMD_READ_DMA, ptr, bufsize);
 749
 750     /*** Read back the Data ***/
 751     memread(ptr, rx, bufsize);
 752     g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0);
 753
 754     ahci_free(ahci, ptr);
 755     g_free(tx);
 756     g_free(rx);
 757 }
 758
 759 /******************************************************************************/
 760 /* Test Interfaces                                                            */
 761 /******************************************************************************/
 762
 763 /**
 764  * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
 765  */
 766 static void test_sanity(void)
 767 {
 768     AHCIQState *ahci;
 769     ahci = ahci_boot();
 770     ahci_shutdown(ahci);
 771 }
 772
 773 /**
 774  * Ensure that the PCI configuration space for the AHCI device is in-line with
 775  * the AHCI 1.3 specification for initial values.
 776  */
 777 static void test_pci_spec(void)
 778 {
 779     AHCIQState *ahci;
 780     ahci = ahci_boot();
 781     ahci_test_pci_spec(ahci);
 782     ahci_shutdown(ahci);
 783 }
 784
 785 /**
 786  * Engage the PCI AHCI device and sanity check the response.
 787  * Perform additional PCI config space bringup for the HBA.
 788  */
 789 static void test_pci_enable(void)
 790 {
 791     AHCIQState *ahci;
 792
 793     ahci = ahci_boot();
 794     ahci_pci_enable(ahci);
 795     ahci_shutdown(ahci);
 796 }
 797
 798 /**
 799  * Investigate the memory mapped regions of the HBA,
 800  * and test them for AHCI specification adherence.
 801  */
 802 static void test_hba_spec(void)
 803 {
 804     AHCIQState *ahci;
 805
 806     ahci = ahci_boot();
 807     ahci_pci_enable(ahci);
 808     ahci_test_hba_spec(ahci);
 809     ahci_shutdown(ahci);
 810 }
 811
 812 /**
 813  * Engage the HBA functionality of the AHCI PCI device,
 814  * and bring it into a functional idle state.
 815  */
 816 static void test_hba_enable(void)
 817 {
 818     AHCIQState *ahci;
 819
 820     ahci = ahci_boot();
 821     ahci_pci_enable(ahci);
 822     ahci_hba_enable(ahci);
 823     ahci_shutdown(ahci);
 824 }
 825
 826 /**
 827  * Bring up the device and issue an IDENTIFY command.
 828  * Inspect the state of the HBA device and the data returned.
 829  */
 830 static void test_identify(void)
 831 {
 832     AHCIQState *ahci;
 833
 834     ahci = ahci_boot();
 835     ahci_pci_enable(ahci);
 836     ahci_hba_enable(ahci);
 837     ahci_test_identify(ahci);
 838     ahci_shutdown(ahci);
 839 }
 840
 841 /**
 842  * Perform a simple DMA R/W test, using a single PRD and non-NCQ commands.
 843  */
 844 static void test_dma_rw_simple(void)
 845 {
 846     AHCIQState *ahci;
 847
 848     ahci = ahci_boot();
 849     ahci_pci_enable(ahci);
 850     ahci_hba_enable(ahci);
 851     ahci_test_dma_rw_simple(ahci);
 852     ahci_shutdown(ahci);
 853 }
 854
 855 /******************************************************************************/
 856
 857 int main(int argc, char **argv)
 858 {
 859     const char *arch;
 860     int fd;
 861     int ret;
 862     int c;
 863
 864     static struct option long_options[] = {
 865         {"pedantic", no_argument, 0, 'p' },
 866         {0, 0, 0, 0},
 867     };
 868
 869     /* Should be first to utilize g_test functionality, So we can see errors. */
 870     g_test_init(&argc, &argv, NULL);
 871
 872     while (1) {
 873         c = getopt_long(argc, argv, "", long_options, NULL);
 874         if (c == -1) {
 875             break;
 876         }
 877         switch (c) {
 878         case -1:
 879             break;
 880         case 'p':
 881             ahci_pedantic = 1;
 882             break;
 883         default:
 884             fprintf(stderr, "Unrecognized ahci_test option.\n");
 885             g_assert_not_reached();
 886         }
 887     }
 888
 889     /* Check architecture */
 890     arch = qtest_get_arch();
 891     if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
 892         g_test_message("Skipping test for non-x86");
 893         return 0;
 894     }
 895
 896     /* Create a temporary raw image */
 897     fd = mkstemp(tmp_path);
 898     g_assert(fd >= 0);
 899     ret = ftruncate(fd, TEST_IMAGE_SIZE);
 900     g_assert(ret == 0);
 901     close(fd);
 902
 903     /* Run the tests */
 904     qtest_add_func("/ahci/sanity",     test_sanity);
 905     qtest_add_func("/ahci/pci_spec",   test_pci_spec);
 906     qtest_add_func("/ahci/pci_enable", test_pci_enable);
 907     qtest_add_func("/ahci/hba_spec",   test_hba_spec);
 908     qtest_add_func("/ahci/hba_enable", test_hba_enable);
 909     qtest_add_func("/ahci/identify",   test_identify);
 910     qtest_add_func("/ahci/dma/simple", test_dma_rw_simple);
 911
 912     ret = g_test_run();
 913
 914     /* Cleanup */
 915     unlink(tmp_path);
 916
 917     return ret;
 918 }