4 * Copyright (c) 2004 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * Based on OpenPic implementations:
28 * - Intel GW80314 I/O companion chip developer's manual
29 * - Motorola MPC8245 & MPC8540 user manuals.
30 * - Motorola MCP750 (aka Raven) programmer manual.
31 * - Motorola Harrier programmer manuel
33 * Serial interrupts, as implemented in Raven chipset are not supported yet.
37 #include "hw/ppc/mac.h"
38 #include "hw/pci/pci.h"
39 #include "hw/ppc/openpic.h"
40 #include "hw/ppc/ppc_e500.h"
41 #include "hw/sysbus.h"
42 #include "hw/pci/msi.h"
43 #include "qemu/bitops.h"
44 #include "qapi/qmp/qerror.h"
46 //#define DEBUG_OPENPIC
49 static const int debug_openpic
= 1;
51 static const int debug_openpic
= 0;
54 #define DPRINTF(fmt, ...) do { \
55 if (debug_openpic) { \
56 printf(fmt , ## __VA_ARGS__); \
62 #define VID 0x03 /* MPIC version ID */
64 /* OpenPIC capability flags */
65 #define OPENPIC_FLAG_IDR_CRIT (1 << 0)
66 #define OPENPIC_FLAG_ILR (2 << 0)
68 /* OpenPIC address map */
69 #define OPENPIC_GLB_REG_START 0x0
70 #define OPENPIC_GLB_REG_SIZE 0x10F0
71 #define OPENPIC_TMR_REG_START 0x10F0
72 #define OPENPIC_TMR_REG_SIZE 0x220
73 #define OPENPIC_MSI_REG_START 0x1600
74 #define OPENPIC_MSI_REG_SIZE 0x200
75 #define OPENPIC_SUMMARY_REG_START 0x3800
76 #define OPENPIC_SUMMARY_REG_SIZE 0x800
77 #define OPENPIC_SRC_REG_START 0x10000
78 #define OPENPIC_SRC_REG_SIZE (OPENPIC_MAX_SRC * 0x20)
79 #define OPENPIC_CPU_REG_START 0x20000
80 #define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
83 #define RAVEN_MAX_CPU 2
84 #define RAVEN_MAX_EXT 48
85 #define RAVEN_MAX_IRQ 64
86 #define RAVEN_MAX_TMR OPENPIC_MAX_TMR
87 #define RAVEN_MAX_IPI OPENPIC_MAX_IPI
89 /* Interrupt definitions */
90 #define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */
91 #define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */
92 #define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */
93 #define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */
94 /* First doorbell IRQ */
95 #define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
97 typedef struct FslMpicInfo
{
101 static FslMpicInfo fsl_mpic_20
= {
105 static FslMpicInfo fsl_mpic_42
= {
109 #define FRR_NIRQ_SHIFT 16
110 #define FRR_NCPU_SHIFT 8
111 #define FRR_VID_SHIFT 0
113 #define VID_REVISION_1_2 2
114 #define VID_REVISION_1_3 3
116 #define VIR_GENERIC 0x00000000 /* Generic Vendor ID */
118 #define GCR_RESET 0x80000000
119 #define GCR_MODE_PASS 0x00000000
120 #define GCR_MODE_MIXED 0x20000000
121 #define GCR_MODE_PROXY 0x60000000
123 #define TBCR_CI 0x80000000 /* count inhibit */
124 #define TCCR_TOG 0x80000000 /* toggles when decrement to zero */
126 #define IDR_EP_SHIFT 31
127 #define IDR_EP_MASK (1U << IDR_EP_SHIFT)
128 #define IDR_CI0_SHIFT 30
129 #define IDR_CI1_SHIFT 29
130 #define IDR_P1_SHIFT 1
131 #define IDR_P0_SHIFT 0
133 #define ILR_INTTGT_MASK 0x000000ff
134 #define ILR_INTTGT_INT 0x00
135 #define ILR_INTTGT_CINT 0x01 /* critical */
136 #define ILR_INTTGT_MCP 0x02 /* machine check */
138 /* The currently supported INTTGT values happen to be the same as QEMU's
139 * openpic output codes, but don't depend on this. The output codes
140 * could change (unlikely, but...) or support could be added for
141 * more INTTGT values.
143 static const int inttgt_output
[][2] = {
144 { ILR_INTTGT_INT
, OPENPIC_OUTPUT_INT
},
145 { ILR_INTTGT_CINT
, OPENPIC_OUTPUT_CINT
},
146 { ILR_INTTGT_MCP
, OPENPIC_OUTPUT_MCK
},
149 static int inttgt_to_output(int inttgt
)
153 for (i
= 0; i
< ARRAY_SIZE(inttgt_output
); i
++) {
154 if (inttgt_output
[i
][0] == inttgt
) {
155 return inttgt_output
[i
][1];
159 fprintf(stderr
, "%s: unsupported inttgt %d\n", __func__
, inttgt
);
160 return OPENPIC_OUTPUT_INT
;
163 static int output_to_inttgt(int output
)
167 for (i
= 0; i
< ARRAY_SIZE(inttgt_output
); i
++) {
168 if (inttgt_output
[i
][1] == output
) {
169 return inttgt_output
[i
][0];
176 #define MSIIR_OFFSET 0x140
177 #define MSIIR_SRS_SHIFT 29
178 #define MSIIR_SRS_MASK (0x7 << MSIIR_SRS_SHIFT)
179 #define MSIIR_IBS_SHIFT 24
180 #define MSIIR_IBS_MASK (0x1f << MSIIR_IBS_SHIFT)
182 static int get_current_cpu(void)
188 return current_cpu
->cpu_index
;
191 static uint32_t openpic_cpu_read_internal(void *opaque
, hwaddr addr
,
193 static void openpic_cpu_write_internal(void *opaque
, hwaddr addr
,
194 uint32_t val
, int idx
);
195 static void openpic_reset(DeviceState
*d
);
197 typedef enum IRQType
{
199 IRQ_TYPE_FSLINT
, /* FSL internal interrupt -- level only */
200 IRQ_TYPE_FSLSPECIAL
, /* FSL timer/IPI interrupt, edge, no polarity */
203 typedef struct IRQQueue
{
204 /* Round up to the nearest 64 IRQs so that the queue length
205 * won't change when moving between 32 and 64 bit hosts.
207 unsigned long queue
[BITS_TO_LONGS((OPENPIC_MAX_IRQ
+ 63) & ~63)];
212 typedef struct IRQSource
{
213 uint32_t ivpr
; /* IRQ vector/priority register */
214 uint32_t idr
; /* IRQ destination register */
215 uint32_t destmask
; /* bitmap of CPU destinations */
217 int output
; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */
218 int pending
; /* TRUE if IRQ is pending */
220 bool level
:1; /* level-triggered */
221 bool nomask
:1; /* critical interrupts ignore mask on some FSL MPICs */
224 #define IVPR_MASK_SHIFT 31
225 #define IVPR_MASK_MASK (1U << IVPR_MASK_SHIFT)
226 #define IVPR_ACTIVITY_SHIFT 30
227 #define IVPR_ACTIVITY_MASK (1U << IVPR_ACTIVITY_SHIFT)
228 #define IVPR_MODE_SHIFT 29
229 #define IVPR_MODE_MASK (1U << IVPR_MODE_SHIFT)
230 #define IVPR_POLARITY_SHIFT 23
231 #define IVPR_POLARITY_MASK (1U << IVPR_POLARITY_SHIFT)
232 #define IVPR_SENSE_SHIFT 22
233 #define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT)
235 #define IVPR_PRIORITY_MASK (0xFU << 16)
236 #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16))
237 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
239 /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */
240 #define IDR_EP 0x80000000 /* external pin */
241 #define IDR_CI 0x40000000 /* critical interrupt */
243 typedef struct IRQDest
{
244 int32_t ctpr
; /* CPU current task priority */
249 /* Count of IRQ sources asserting on non-INT outputs */
250 uint32_t outputs_active
[OPENPIC_OUTPUT_NB
];
253 #define OPENPIC(obj) OBJECT_CHECK(OpenPICState, (obj), TYPE_OPENPIC)
255 typedef struct OpenPICState
{
257 SysBusDevice parent_obj
;
262 /* Behavior control */
268 uint32_t vir
; /* Vendor identification register */
269 uint32_t vector_mask
;
274 uint32_t mpic_mode_mask
;
277 MemoryRegion sub_io_mem
[6];
279 /* Global registers */
280 uint32_t frr
; /* Feature reporting register */
281 uint32_t gcr
; /* Global configuration register */
282 uint32_t pir
; /* Processor initialization register */
283 uint32_t spve
; /* Spurious vector register */
284 uint32_t tfrr
; /* Timer frequency reporting register */
285 /* Source registers */
286 IRQSource src
[OPENPIC_MAX_IRQ
];
287 /* Local registers per output pin */
288 IRQDest dst
[MAX_CPU
];
290 /* Timer registers */
292 uint32_t tccr
; /* Global timer current count register */
293 uint32_t tbcr
; /* Global timer base count register */
294 } timers
[OPENPIC_MAX_TMR
];
295 /* Shared MSI registers */
297 uint32_t msir
; /* Shared Message Signaled Interrupt Register */
305 static inline void IRQ_setbit(IRQQueue
*q
, int n_IRQ
)
307 set_bit(n_IRQ
, q
->queue
);
310 static inline void IRQ_resetbit(IRQQueue
*q
, int n_IRQ
)
312 clear_bit(n_IRQ
, q
->queue
);
315 static void IRQ_check(OpenPICState
*opp
, IRQQueue
*q
)
322 irq
= find_next_bit(q
->queue
, opp
->max_irq
, irq
+ 1);
323 if (irq
== opp
->max_irq
) {
327 DPRINTF("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n",
328 irq
, IVPR_PRIORITY(opp
->src
[irq
].ivpr
), priority
);
330 if (IVPR_PRIORITY(opp
->src
[irq
].ivpr
) > priority
) {
332 priority
= IVPR_PRIORITY(opp
->src
[irq
].ivpr
);
337 q
->priority
= priority
;
340 static int IRQ_get_next(OpenPICState
*opp
, IRQQueue
*q
)
348 static void IRQ_local_pipe(OpenPICState
*opp
, int n_CPU
, int n_IRQ
,
349 bool active
, bool was_active
)
355 dst
= &opp
->dst
[n_CPU
];
356 src
= &opp
->src
[n_IRQ
];
358 DPRINTF("%s: IRQ %d active %d was %d\n",
359 __func__
, n_IRQ
, active
, was_active
);
361 if (src
->output
!= OPENPIC_OUTPUT_INT
) {
362 DPRINTF("%s: output %d irq %d active %d was %d count %d\n",
363 __func__
, src
->output
, n_IRQ
, active
, was_active
,
364 dst
->outputs_active
[src
->output
]);
366 /* On Freescale MPIC, critical interrupts ignore priority,
367 * IACK, EOI, etc. Before MPIC v4.1 they also ignore
371 if (!was_active
&& dst
->outputs_active
[src
->output
]++ == 0) {
372 DPRINTF("%s: Raise OpenPIC output %d cpu %d irq %d\n",
373 __func__
, src
->output
, n_CPU
, n_IRQ
);
374 qemu_irq_raise(dst
->irqs
[src
->output
]);
377 if (was_active
&& --dst
->outputs_active
[src
->output
] == 0) {
378 DPRINTF("%s: Lower OpenPIC output %d cpu %d irq %d\n",
379 __func__
, src
->output
, n_CPU
, n_IRQ
);
380 qemu_irq_lower(dst
->irqs
[src
->output
]);
387 priority
= IVPR_PRIORITY(src
->ivpr
);
389 /* Even if the interrupt doesn't have enough priority,
390 * it is still raised, in case ctpr is lowered later.
393 IRQ_setbit(&dst
->raised
, n_IRQ
);
395 IRQ_resetbit(&dst
->raised
, n_IRQ
);
398 IRQ_check(opp
, &dst
->raised
);
400 if (active
&& priority
<= dst
->ctpr
) {
401 DPRINTF("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n",
402 __func__
, n_IRQ
, priority
, dst
->ctpr
, n_CPU
);
407 if (IRQ_get_next(opp
, &dst
->servicing
) >= 0 &&
408 priority
<= dst
->servicing
.priority
) {
409 DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
410 __func__
, n_IRQ
, dst
->servicing
.next
, n_CPU
);
412 DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n",
413 __func__
, n_CPU
, n_IRQ
, dst
->raised
.next
);
414 qemu_irq_raise(opp
->dst
[n_CPU
].irqs
[OPENPIC_OUTPUT_INT
]);
417 IRQ_get_next(opp
, &dst
->servicing
);
418 if (dst
->raised
.priority
> dst
->ctpr
&&
419 dst
->raised
.priority
> dst
->servicing
.priority
) {
420 DPRINTF("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n",
421 __func__
, n_IRQ
, dst
->raised
.next
, dst
->raised
.priority
,
422 dst
->ctpr
, dst
->servicing
.priority
, n_CPU
);
423 /* IRQ line stays asserted */
425 DPRINTF("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n",
426 __func__
, n_IRQ
, dst
->ctpr
, dst
->servicing
.priority
, n_CPU
);
427 qemu_irq_lower(opp
->dst
[n_CPU
].irqs
[OPENPIC_OUTPUT_INT
]);
432 /* update pic state because registers for n_IRQ have changed value */
433 static void openpic_update_irq(OpenPICState
*opp
, int n_IRQ
)
436 bool active
, was_active
;
439 src
= &opp
->src
[n_IRQ
];
440 active
= src
->pending
;
442 if ((src
->ivpr
& IVPR_MASK_MASK
) && !src
->nomask
) {
443 /* Interrupt source is disabled */
444 DPRINTF("%s: IRQ %d is disabled\n", __func__
, n_IRQ
);
448 was_active
= !!(src
->ivpr
& IVPR_ACTIVITY_MASK
);
451 * We don't have a similar check for already-active because
452 * ctpr may have changed and we need to withdraw the interrupt.
454 if (!active
&& !was_active
) {
455 DPRINTF("%s: IRQ %d is already inactive\n", __func__
, n_IRQ
);
460 src
->ivpr
|= IVPR_ACTIVITY_MASK
;
462 src
->ivpr
&= ~IVPR_ACTIVITY_MASK
;
465 if (src
->destmask
== 0) {
467 DPRINTF("%s: IRQ %d has no target\n", __func__
, n_IRQ
);
471 if (src
->destmask
== (1 << src
->last_cpu
)) {
472 /* Only one CPU is allowed to receive this IRQ */
473 IRQ_local_pipe(opp
, src
->last_cpu
, n_IRQ
, active
, was_active
);
474 } else if (!(src
->ivpr
& IVPR_MODE_MASK
)) {
475 /* Directed delivery mode */
476 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
477 if (src
->destmask
& (1 << i
)) {
478 IRQ_local_pipe(opp
, i
, n_IRQ
, active
, was_active
);
482 /* Distributed delivery mode */
483 for (i
= src
->last_cpu
+ 1; i
!= src
->last_cpu
; i
++) {
484 if (i
== opp
->nb_cpus
) {
487 if (src
->destmask
& (1 << i
)) {
488 IRQ_local_pipe(opp
, i
, n_IRQ
, active
, was_active
);
496 static void openpic_set_irq(void *opaque
, int n_IRQ
, int level
)
498 OpenPICState
*opp
= opaque
;
501 if (n_IRQ
>= OPENPIC_MAX_IRQ
) {
502 fprintf(stderr
, "%s: IRQ %d out of range\n", __func__
, n_IRQ
);
506 src
= &opp
->src
[n_IRQ
];
507 DPRINTF("openpic: set irq %d = %d ivpr=0x%08x\n",
508 n_IRQ
, level
, src
->ivpr
);
510 /* level-sensitive irq */
511 src
->pending
= level
;
512 openpic_update_irq(opp
, n_IRQ
);
514 /* edge-sensitive irq */
517 openpic_update_irq(opp
, n_IRQ
);
520 if (src
->output
!= OPENPIC_OUTPUT_INT
) {
521 /* Edge-triggered interrupts shouldn't be used
522 * with non-INT delivery, but just in case,
523 * try to make it do something sane rather than
524 * cause an interrupt storm. This is close to
525 * what you'd probably see happen in real hardware.
528 openpic_update_irq(opp
, n_IRQ
);
533 static inline uint32_t read_IRQreg_idr(OpenPICState
*opp
, int n_IRQ
)
535 return opp
->src
[n_IRQ
].idr
;
538 static inline uint32_t read_IRQreg_ilr(OpenPICState
*opp
, int n_IRQ
)
540 if (opp
->flags
& OPENPIC_FLAG_ILR
) {
541 return output_to_inttgt(opp
->src
[n_IRQ
].output
);
547 static inline uint32_t read_IRQreg_ivpr(OpenPICState
*opp
, int n_IRQ
)
549 return opp
->src
[n_IRQ
].ivpr
;
552 static inline void write_IRQreg_idr(OpenPICState
*opp
, int n_IRQ
, uint32_t val
)
554 IRQSource
*src
= &opp
->src
[n_IRQ
];
555 uint32_t normal_mask
= (1UL << opp
->nb_cpus
) - 1;
556 uint32_t crit_mask
= 0;
557 uint32_t mask
= normal_mask
;
558 int crit_shift
= IDR_EP_SHIFT
- opp
->nb_cpus
;
561 if (opp
->flags
& OPENPIC_FLAG_IDR_CRIT
) {
562 crit_mask
= mask
<< crit_shift
;
563 mask
|= crit_mask
| IDR_EP
;
566 src
->idr
= val
& mask
;
567 DPRINTF("Set IDR %d to 0x%08x\n", n_IRQ
, src
->idr
);
569 if (opp
->flags
& OPENPIC_FLAG_IDR_CRIT
) {
570 if (src
->idr
& crit_mask
) {
571 if (src
->idr
& normal_mask
) {
572 DPRINTF("%s: IRQ configured for multiple output types, using "
573 "critical\n", __func__
);
576 src
->output
= OPENPIC_OUTPUT_CINT
;
580 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
581 int n_ci
= IDR_CI0_SHIFT
- i
;
583 if (src
->idr
& (1UL << n_ci
)) {
584 src
->destmask
|= 1UL << i
;
588 src
->output
= OPENPIC_OUTPUT_INT
;
590 src
->destmask
= src
->idr
& normal_mask
;
593 src
->destmask
= src
->idr
;
597 static inline void write_IRQreg_ilr(OpenPICState
*opp
, int n_IRQ
, uint32_t val
)
599 if (opp
->flags
& OPENPIC_FLAG_ILR
) {
600 IRQSource
*src
= &opp
->src
[n_IRQ
];
602 src
->output
= inttgt_to_output(val
& ILR_INTTGT_MASK
);
603 DPRINTF("Set ILR %d to 0x%08x, output %d\n", n_IRQ
, src
->idr
,
606 /* TODO: on MPIC v4.0 only, set nomask for non-INT */
610 static inline void write_IRQreg_ivpr(OpenPICState
*opp
, int n_IRQ
, uint32_t val
)
614 /* NOTE when implementing newer FSL MPIC models: starting with v4.0,
615 * the polarity bit is read-only on internal interrupts.
617 mask
= IVPR_MASK_MASK
| IVPR_PRIORITY_MASK
| IVPR_SENSE_MASK
|
618 IVPR_POLARITY_MASK
| opp
->vector_mask
;
620 /* ACTIVITY bit is read-only */
621 opp
->src
[n_IRQ
].ivpr
=
622 (opp
->src
[n_IRQ
].ivpr
& IVPR_ACTIVITY_MASK
) | (val
& mask
);
624 /* For FSL internal interrupts, The sense bit is reserved and zero,
625 * and the interrupt is always level-triggered. Timers and IPIs
626 * have no sense or polarity bits, and are edge-triggered.
628 switch (opp
->src
[n_IRQ
].type
) {
629 case IRQ_TYPE_NORMAL
:
630 opp
->src
[n_IRQ
].level
= !!(opp
->src
[n_IRQ
].ivpr
& IVPR_SENSE_MASK
);
633 case IRQ_TYPE_FSLINT
:
634 opp
->src
[n_IRQ
].ivpr
&= ~IVPR_SENSE_MASK
;
637 case IRQ_TYPE_FSLSPECIAL
:
638 opp
->src
[n_IRQ
].ivpr
&= ~(IVPR_POLARITY_MASK
| IVPR_SENSE_MASK
);
642 openpic_update_irq(opp
, n_IRQ
);
643 DPRINTF("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ
, val
,
644 opp
->src
[n_IRQ
].ivpr
);
647 static void openpic_gcr_write(OpenPICState
*opp
, uint64_t val
)
649 bool mpic_proxy
= false;
651 if (val
& GCR_RESET
) {
652 openpic_reset(DEVICE(opp
));
656 opp
->gcr
&= ~opp
->mpic_mode_mask
;
657 opp
->gcr
|= val
& opp
->mpic_mode_mask
;
659 /* Set external proxy mode */
660 if ((val
& opp
->mpic_mode_mask
) == GCR_MODE_PROXY
) {
664 ppce500_set_mpic_proxy(mpic_proxy
);
667 static void openpic_gbl_write(void *opaque
, hwaddr addr
, uint64_t val
,
670 OpenPICState
*opp
= opaque
;
674 DPRINTF("%s: addr %#" HWADDR_PRIx
" <= %08" PRIx64
"\n",
675 __func__
, addr
, val
);
680 case 0x00: /* Block Revision Register1 (BRR1) is Readonly */
690 openpic_cpu_write_internal(opp
, addr
, val
, get_current_cpu());
692 case 0x1000: /* FRR */
694 case 0x1020: /* GCR */
695 openpic_gcr_write(opp
, val
);
697 case 0x1080: /* VIR */
699 case 0x1090: /* PIR */
700 for (idx
= 0; idx
< opp
->nb_cpus
; idx
++) {
701 if ((val
& (1 << idx
)) && !(opp
->pir
& (1 << idx
))) {
702 DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx
);
703 dst
= &opp
->dst
[idx
];
704 qemu_irq_raise(dst
->irqs
[OPENPIC_OUTPUT_RESET
]);
705 } else if (!(val
& (1 << idx
)) && (opp
->pir
& (1 << idx
))) {
706 DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx
);
707 dst
= &opp
->dst
[idx
];
708 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_RESET
]);
713 case 0x10A0: /* IPI_IVPR */
719 idx
= (addr
- 0x10A0) >> 4;
720 write_IRQreg_ivpr(opp
, opp
->irq_ipi0
+ idx
, val
);
723 case 0x10E0: /* SPVE */
724 opp
->spve
= val
& opp
->vector_mask
;
731 static uint64_t openpic_gbl_read(void *opaque
, hwaddr addr
, unsigned len
)
733 OpenPICState
*opp
= opaque
;
736 DPRINTF("%s: addr %#" HWADDR_PRIx
"\n", __func__
, addr
);
742 case 0x1000: /* FRR */
745 case 0x1020: /* GCR */
748 case 0x1080: /* VIR */
751 case 0x1090: /* PIR */
754 case 0x00: /* Block Revision Register1 (BRR1) */
765 retval
= openpic_cpu_read_internal(opp
, addr
, get_current_cpu());
767 case 0x10A0: /* IPI_IVPR */
773 idx
= (addr
- 0x10A0) >> 4;
774 retval
= read_IRQreg_ivpr(opp
, opp
->irq_ipi0
+ idx
);
777 case 0x10E0: /* SPVE */
783 DPRINTF("%s: => 0x%08x\n", __func__
, retval
);
788 static void openpic_tmr_write(void *opaque
, hwaddr addr
, uint64_t val
,
791 OpenPICState
*opp
= opaque
;
796 DPRINTF("%s: addr %#" HWADDR_PRIx
" <= %08" PRIx64
"\n",
797 __func__
, addr
, val
);
802 if (addr
== 0x10f0) {
808 idx
= (addr
>> 6) & 0x3;
811 switch (addr
& 0x30) {
812 case 0x00: /* TCCR */
814 case 0x10: /* TBCR */
815 if ((opp
->timers
[idx
].tccr
& TCCR_TOG
) != 0 &&
816 (val
& TBCR_CI
) == 0 &&
817 (opp
->timers
[idx
].tbcr
& TBCR_CI
) != 0) {
818 opp
->timers
[idx
].tccr
&= ~TCCR_TOG
;
820 opp
->timers
[idx
].tbcr
= val
;
822 case 0x20: /* TVPR */
823 write_IRQreg_ivpr(opp
, opp
->irq_tim0
+ idx
, val
);
826 write_IRQreg_idr(opp
, opp
->irq_tim0
+ idx
, val
);
831 static uint64_t openpic_tmr_read(void *opaque
, hwaddr addr
, unsigned len
)
833 OpenPICState
*opp
= opaque
;
834 uint32_t retval
= -1;
837 DPRINTF("%s: addr %#" HWADDR_PRIx
"\n", __func__
, addr
);
841 idx
= (addr
>> 6) & 0x3;
847 switch (addr
& 0x30) {
848 case 0x00: /* TCCR */
849 retval
= opp
->timers
[idx
].tccr
;
851 case 0x10: /* TBCR */
852 retval
= opp
->timers
[idx
].tbcr
;
854 case 0x20: /* TIPV */
855 retval
= read_IRQreg_ivpr(opp
, opp
->irq_tim0
+ idx
);
857 case 0x30: /* TIDE (TIDR) */
858 retval
= read_IRQreg_idr(opp
, opp
->irq_tim0
+ idx
);
863 DPRINTF("%s: => 0x%08x\n", __func__
, retval
);
868 static void openpic_src_write(void *opaque
, hwaddr addr
, uint64_t val
,
871 OpenPICState
*opp
= opaque
;
874 DPRINTF("%s: addr %#" HWADDR_PRIx
" <= %08" PRIx64
"\n",
875 __func__
, addr
, val
);
877 addr
= addr
& 0xffff;
880 switch (addr
& 0x1f) {
882 write_IRQreg_ivpr(opp
, idx
, val
);
885 write_IRQreg_idr(opp
, idx
, val
);
888 write_IRQreg_ilr(opp
, idx
, val
);
893 static uint64_t openpic_src_read(void *opaque
, uint64_t addr
, unsigned len
)
895 OpenPICState
*opp
= opaque
;
899 DPRINTF("%s: addr %#" HWADDR_PRIx
"\n", __func__
, addr
);
902 addr
= addr
& 0xffff;
905 switch (addr
& 0x1f) {
907 retval
= read_IRQreg_ivpr(opp
, idx
);
910 retval
= read_IRQreg_idr(opp
, idx
);
913 retval
= read_IRQreg_ilr(opp
, idx
);
917 DPRINTF("%s: => 0x%08x\n", __func__
, retval
);
921 static void openpic_msi_write(void *opaque
, hwaddr addr
, uint64_t val
,
924 OpenPICState
*opp
= opaque
;
925 int idx
= opp
->irq_msi
;
928 DPRINTF("%s: addr %#" HWADDR_PRIx
" <= 0x%08" PRIx64
"\n",
929 __func__
, addr
, val
);
936 srs
= val
>> MSIIR_SRS_SHIFT
;
938 ibs
= (val
& MSIIR_IBS_MASK
) >> MSIIR_IBS_SHIFT
;
939 opp
->msi
[srs
].msir
|= 1 << ibs
;
940 openpic_set_irq(opp
, idx
, 1);
943 /* most registers are read-only, thus ignored */
948 static uint64_t openpic_msi_read(void *opaque
, hwaddr addr
, unsigned size
)
950 OpenPICState
*opp
= opaque
;
954 DPRINTF("%s: addr %#" HWADDR_PRIx
"\n", __func__
, addr
);
969 case 0x70: /* MSIRs */
970 r
= opp
->msi
[srs
].msir
;
972 opp
->msi
[srs
].msir
= 0;
973 openpic_set_irq(opp
, opp
->irq_msi
+ srs
, 0);
975 case 0x120: /* MSISR */
976 for (i
= 0; i
< MAX_MSI
; i
++) {
977 r
|= (opp
->msi
[i
].msir
? 1 : 0) << i
;
985 static uint64_t openpic_summary_read(void *opaque
, hwaddr addr
, unsigned size
)
989 DPRINTF("%s: addr %#" HWADDR_PRIx
"\n", __func__
, addr
);
991 /* TODO: EISR/EIMR */
996 static void openpic_summary_write(void *opaque
, hwaddr addr
, uint64_t val
,
999 DPRINTF("%s: addr %#" HWADDR_PRIx
" <= 0x%08" PRIx64
"\n",
1000 __func__
, addr
, val
);
1002 /* TODO: EISR/EIMR */
1005 static void openpic_cpu_write_internal(void *opaque
, hwaddr addr
,
1006 uint32_t val
, int idx
)
1008 OpenPICState
*opp
= opaque
;
1013 DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx
" <= 0x%08x\n", __func__
, idx
,
1023 dst
= &opp
->dst
[idx
];
1026 case 0x40: /* IPIDR */
1030 idx
= (addr
- 0x40) >> 4;
1031 /* we use IDE as mask which CPUs to deliver the IPI to still. */
1032 opp
->src
[opp
->irq_ipi0
+ idx
].destmask
|= val
;
1033 openpic_set_irq(opp
, opp
->irq_ipi0
+ idx
, 1);
1034 openpic_set_irq(opp
, opp
->irq_ipi0
+ idx
, 0);
1036 case 0x80: /* CTPR */
1037 dst
->ctpr
= val
& 0x0000000F;
1039 DPRINTF("%s: set CPU %d ctpr to %d, raised %d servicing %d\n",
1040 __func__
, idx
, dst
->ctpr
, dst
->raised
.priority
,
1041 dst
->servicing
.priority
);
1043 if (dst
->raised
.priority
<= dst
->ctpr
) {
1044 DPRINTF("%s: Lower OpenPIC INT output cpu %d due to ctpr\n",
1046 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_INT
]);
1047 } else if (dst
->raised
.priority
> dst
->servicing
.priority
) {
1048 DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d\n",
1049 __func__
, idx
, dst
->raised
.next
);
1050 qemu_irq_raise(dst
->irqs
[OPENPIC_OUTPUT_INT
]);
1054 case 0x90: /* WHOAMI */
1055 /* Read-only register */
1057 case 0xA0: /* IACK */
1058 /* Read-only register */
1060 case 0xB0: /* EOI */
1062 s_IRQ
= IRQ_get_next(opp
, &dst
->servicing
);
1065 DPRINTF("%s: EOI with no interrupt in service\n", __func__
);
1069 IRQ_resetbit(&dst
->servicing
, s_IRQ
);
1070 /* Set up next servicing IRQ */
1071 s_IRQ
= IRQ_get_next(opp
, &dst
->servicing
);
1072 /* Check queued interrupts. */
1073 n_IRQ
= IRQ_get_next(opp
, &dst
->raised
);
1074 src
= &opp
->src
[n_IRQ
];
1077 IVPR_PRIORITY(src
->ivpr
) > dst
->servicing
.priority
)) {
1078 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
1080 qemu_irq_raise(opp
->dst
[idx
].irqs
[OPENPIC_OUTPUT_INT
]);
1088 static void openpic_cpu_write(void *opaque
, hwaddr addr
, uint64_t val
,
1091 openpic_cpu_write_internal(opaque
, addr
, val
, (addr
& 0x1f000) >> 12);
1095 static uint32_t openpic_iack(OpenPICState
*opp
, IRQDest
*dst
, int cpu
)
1100 DPRINTF("Lower OpenPIC INT output\n");
1101 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_INT
]);
1103 irq
= IRQ_get_next(opp
, &dst
->raised
);
1104 DPRINTF("IACK: irq=%d\n", irq
);
1107 /* No more interrupt pending */
1111 src
= &opp
->src
[irq
];
1112 if (!(src
->ivpr
& IVPR_ACTIVITY_MASK
) ||
1113 !(IVPR_PRIORITY(src
->ivpr
) > dst
->ctpr
)) {
1114 fprintf(stderr
, "%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n",
1115 __func__
, irq
, dst
->ctpr
, src
->ivpr
);
1116 openpic_update_irq(opp
, irq
);
1119 /* IRQ enter servicing state */
1120 IRQ_setbit(&dst
->servicing
, irq
);
1121 retval
= IVPR_VECTOR(opp
, src
->ivpr
);
1125 /* edge-sensitive IRQ */
1126 src
->ivpr
&= ~IVPR_ACTIVITY_MASK
;
1128 IRQ_resetbit(&dst
->raised
, irq
);
1131 if ((irq
>= opp
->irq_ipi0
) && (irq
< (opp
->irq_ipi0
+ OPENPIC_MAX_IPI
))) {
1132 src
->destmask
&= ~(1 << cpu
);
1133 if (src
->destmask
&& !src
->level
) {
1134 /* trigger on CPUs that didn't know about it yet */
1135 openpic_set_irq(opp
, irq
, 1);
1136 openpic_set_irq(opp
, irq
, 0);
1137 /* if all CPUs knew about it, set active bit again */
1138 src
->ivpr
|= IVPR_ACTIVITY_MASK
;
1145 static uint32_t openpic_cpu_read_internal(void *opaque
, hwaddr addr
,
1148 OpenPICState
*opp
= opaque
;
1152 DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx
"\n", __func__
, idx
, addr
);
1153 retval
= 0xFFFFFFFF;
1162 dst
= &opp
->dst
[idx
];
1165 case 0x80: /* CTPR */
1168 case 0x90: /* WHOAMI */
1171 case 0xA0: /* IACK */
1172 retval
= openpic_iack(opp
, dst
, idx
);
1174 case 0xB0: /* EOI */
1180 DPRINTF("%s: => 0x%08x\n", __func__
, retval
);
1185 static uint64_t openpic_cpu_read(void *opaque
, hwaddr addr
, unsigned len
)
1187 return openpic_cpu_read_internal(opaque
, addr
, (addr
& 0x1f000) >> 12);
1190 static const MemoryRegionOps openpic_glb_ops_le
= {
1191 .write
= openpic_gbl_write
,
1192 .read
= openpic_gbl_read
,
1193 .endianness
= DEVICE_LITTLE_ENDIAN
,
1195 .min_access_size
= 4,
1196 .max_access_size
= 4,
1200 static const MemoryRegionOps openpic_glb_ops_be
= {
1201 .write
= openpic_gbl_write
,
1202 .read
= openpic_gbl_read
,
1203 .endianness
= DEVICE_BIG_ENDIAN
,
1205 .min_access_size
= 4,
1206 .max_access_size
= 4,
1210 static const MemoryRegionOps openpic_tmr_ops_le
= {
1211 .write
= openpic_tmr_write
,
1212 .read
= openpic_tmr_read
,
1213 .endianness
= DEVICE_LITTLE_ENDIAN
,
1215 .min_access_size
= 4,
1216 .max_access_size
= 4,
1220 static const MemoryRegionOps openpic_tmr_ops_be
= {
1221 .write
= openpic_tmr_write
,
1222 .read
= openpic_tmr_read
,
1223 .endianness
= DEVICE_BIG_ENDIAN
,
1225 .min_access_size
= 4,
1226 .max_access_size
= 4,
1230 static const MemoryRegionOps openpic_cpu_ops_le
= {
1231 .write
= openpic_cpu_write
,
1232 .read
= openpic_cpu_read
,
1233 .endianness
= DEVICE_LITTLE_ENDIAN
,
1235 .min_access_size
= 4,
1236 .max_access_size
= 4,
1240 static const MemoryRegionOps openpic_cpu_ops_be
= {
1241 .write
= openpic_cpu_write
,
1242 .read
= openpic_cpu_read
,
1243 .endianness
= DEVICE_BIG_ENDIAN
,
1245 .min_access_size
= 4,
1246 .max_access_size
= 4,
1250 static const MemoryRegionOps openpic_src_ops_le
= {
1251 .write
= openpic_src_write
,
1252 .read
= openpic_src_read
,
1253 .endianness
= DEVICE_LITTLE_ENDIAN
,
1255 .min_access_size
= 4,
1256 .max_access_size
= 4,
1260 static const MemoryRegionOps openpic_src_ops_be
= {
1261 .write
= openpic_src_write
,
1262 .read
= openpic_src_read
,
1263 .endianness
= DEVICE_BIG_ENDIAN
,
1265 .min_access_size
= 4,
1266 .max_access_size
= 4,
1270 static const MemoryRegionOps openpic_msi_ops_be
= {
1271 .read
= openpic_msi_read
,
1272 .write
= openpic_msi_write
,
1273 .endianness
= DEVICE_BIG_ENDIAN
,
1275 .min_access_size
= 4,
1276 .max_access_size
= 4,
1280 static const MemoryRegionOps openpic_summary_ops_be
= {
1281 .read
= openpic_summary_read
,
1282 .write
= openpic_summary_write
,
1283 .endianness
= DEVICE_BIG_ENDIAN
,
1285 .min_access_size
= 4,
1286 .max_access_size
= 4,
1290 static void openpic_save_IRQ_queue(QEMUFile
* f
, IRQQueue
*q
)
1294 for (i
= 0; i
< ARRAY_SIZE(q
->queue
); i
++) {
1295 /* Always put the lower half of a 64-bit long first, in case we
1296 * restore on a 32-bit host. The least significant bits correspond
1297 * to lower IRQ numbers in the bitmap.
1299 qemu_put_be32(f
, (uint32_t)q
->queue
[i
]);
1300 #if LONG_MAX > 0x7FFFFFFF
1301 qemu_put_be32(f
, (uint32_t)(q
->queue
[i
] >> 32));
1305 qemu_put_sbe32s(f
, &q
->next
);
1306 qemu_put_sbe32s(f
, &q
->priority
);
1309 static void openpic_save(QEMUFile
* f
, void *opaque
)
1311 OpenPICState
*opp
= (OpenPICState
*)opaque
;
1314 qemu_put_be32s(f
, &opp
->gcr
);
1315 qemu_put_be32s(f
, &opp
->vir
);
1316 qemu_put_be32s(f
, &opp
->pir
);
1317 qemu_put_be32s(f
, &opp
->spve
);
1318 qemu_put_be32s(f
, &opp
->tfrr
);
1320 qemu_put_be32s(f
, &opp
->nb_cpus
);
1322 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
1323 qemu_put_sbe32s(f
, &opp
->dst
[i
].ctpr
);
1324 openpic_save_IRQ_queue(f
, &opp
->dst
[i
].raised
);
1325 openpic_save_IRQ_queue(f
, &opp
->dst
[i
].servicing
);
1326 qemu_put_buffer(f
, (uint8_t *)&opp
->dst
[i
].outputs_active
,
1327 sizeof(opp
->dst
[i
].outputs_active
));
1330 for (i
= 0; i
< OPENPIC_MAX_TMR
; i
++) {
1331 qemu_put_be32s(f
, &opp
->timers
[i
].tccr
);
1332 qemu_put_be32s(f
, &opp
->timers
[i
].tbcr
);
1335 for (i
= 0; i
< opp
->max_irq
; i
++) {
1336 qemu_put_be32s(f
, &opp
->src
[i
].ivpr
);
1337 qemu_put_be32s(f
, &opp
->src
[i
].idr
);
1338 qemu_get_be32s(f
, &opp
->src
[i
].destmask
);
1339 qemu_put_sbe32s(f
, &opp
->src
[i
].last_cpu
);
1340 qemu_put_sbe32s(f
, &opp
->src
[i
].pending
);
1344 static void openpic_load_IRQ_queue(QEMUFile
* f
, IRQQueue
*q
)
1348 for (i
= 0; i
< ARRAY_SIZE(q
->queue
); i
++) {
1351 val
= qemu_get_be32(f
);
1352 #if LONG_MAX > 0x7FFFFFFF
1354 val
|= qemu_get_be32(f
);
1360 qemu_get_sbe32s(f
, &q
->next
);
1361 qemu_get_sbe32s(f
, &q
->priority
);
1364 static int openpic_load(QEMUFile
* f
, void *opaque
, int version_id
)
1366 OpenPICState
*opp
= (OpenPICState
*)opaque
;
1367 unsigned int i
, nb_cpus
;
1369 if (version_id
!= 1) {
1373 qemu_get_be32s(f
, &opp
->gcr
);
1374 qemu_get_be32s(f
, &opp
->vir
);
1375 qemu_get_be32s(f
, &opp
->pir
);
1376 qemu_get_be32s(f
, &opp
->spve
);
1377 qemu_get_be32s(f
, &opp
->tfrr
);
1379 qemu_get_be32s(f
, &nb_cpus
);
1380 if (opp
->nb_cpus
!= nb_cpus
) {
1383 assert(nb_cpus
> 0 && nb_cpus
<= MAX_CPU
);
1385 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
1386 qemu_get_sbe32s(f
, &opp
->dst
[i
].ctpr
);
1387 openpic_load_IRQ_queue(f
, &opp
->dst
[i
].raised
);
1388 openpic_load_IRQ_queue(f
, &opp
->dst
[i
].servicing
);
1389 qemu_get_buffer(f
, (uint8_t *)&opp
->dst
[i
].outputs_active
,
1390 sizeof(opp
->dst
[i
].outputs_active
));
1393 for (i
= 0; i
< OPENPIC_MAX_TMR
; i
++) {
1394 qemu_get_be32s(f
, &opp
->timers
[i
].tccr
);
1395 qemu_get_be32s(f
, &opp
->timers
[i
].tbcr
);
1398 for (i
= 0; i
< opp
->max_irq
; i
++) {
1401 val
= qemu_get_be32(f
);
1402 write_IRQreg_idr(opp
, i
, val
);
1403 val
= qemu_get_be32(f
);
1404 write_IRQreg_ivpr(opp
, i
, val
);
1406 qemu_get_be32s(f
, &opp
->src
[i
].ivpr
);
1407 qemu_get_be32s(f
, &opp
->src
[i
].idr
);
1408 qemu_get_be32s(f
, &opp
->src
[i
].destmask
);
1409 qemu_get_sbe32s(f
, &opp
->src
[i
].last_cpu
);
1410 qemu_get_sbe32s(f
, &opp
->src
[i
].pending
);
1416 static void openpic_reset(DeviceState
*d
)
1418 OpenPICState
*opp
= OPENPIC(d
);
1421 opp
->gcr
= GCR_RESET
;
1422 /* Initialise controller registers */
1423 opp
->frr
= ((opp
->nb_irqs
- 1) << FRR_NIRQ_SHIFT
) |
1424 ((opp
->nb_cpus
- 1) << FRR_NCPU_SHIFT
) |
1425 (opp
->vid
<< FRR_VID_SHIFT
);
1428 opp
->spve
= -1 & opp
->vector_mask
;
1429 opp
->tfrr
= opp
->tfrr_reset
;
1430 /* Initialise IRQ sources */
1431 for (i
= 0; i
< opp
->max_irq
; i
++) {
1432 opp
->src
[i
].ivpr
= opp
->ivpr_reset
;
1433 switch (opp
->src
[i
].type
) {
1434 case IRQ_TYPE_NORMAL
:
1435 opp
->src
[i
].level
= !!(opp
->ivpr_reset
& IVPR_SENSE_MASK
);
1438 case IRQ_TYPE_FSLINT
:
1439 opp
->src
[i
].ivpr
|= IVPR_POLARITY_MASK
;
1442 case IRQ_TYPE_FSLSPECIAL
:
1446 write_IRQreg_idr(opp
, i
, opp
->idr_reset
);
1448 /* Initialise IRQ destinations */
1449 for (i
= 0; i
< MAX_CPU
; i
++) {
1450 opp
->dst
[i
].ctpr
= 15;
1451 memset(&opp
->dst
[i
].raised
, 0, sizeof(IRQQueue
));
1452 opp
->dst
[i
].raised
.next
= -1;
1453 memset(&opp
->dst
[i
].servicing
, 0, sizeof(IRQQueue
));
1454 opp
->dst
[i
].servicing
.next
= -1;
1456 /* Initialise timers */
1457 for (i
= 0; i
< OPENPIC_MAX_TMR
; i
++) {
1458 opp
->timers
[i
].tccr
= 0;
1459 opp
->timers
[i
].tbcr
= TBCR_CI
;
1461 /* Go out of RESET state */
1465 typedef struct MemReg
{
1467 MemoryRegionOps
const *ops
;
1472 static void fsl_common_init(OpenPICState
*opp
)
1475 int virq
= OPENPIC_MAX_SRC
;
1477 opp
->vid
= VID_REVISION_1_2
;
1478 opp
->vir
= VIR_GENERIC
;
1479 opp
->vector_mask
= 0xFFFF;
1480 opp
->tfrr_reset
= 0;
1481 opp
->ivpr_reset
= IVPR_MASK_MASK
;
1482 opp
->idr_reset
= 1 << 0;
1483 opp
->max_irq
= OPENPIC_MAX_IRQ
;
1485 opp
->irq_ipi0
= virq
;
1486 virq
+= OPENPIC_MAX_IPI
;
1487 opp
->irq_tim0
= virq
;
1488 virq
+= OPENPIC_MAX_TMR
;
1490 assert(virq
<= OPENPIC_MAX_IRQ
);
1494 msi_supported
= true;
1495 for (i
= 0; i
< opp
->fsl
->max_ext
; i
++) {
1496 opp
->src
[i
].level
= false;
1499 /* Internal interrupts, including message and MSI */
1500 for (i
= 16; i
< OPENPIC_MAX_SRC
; i
++) {
1501 opp
->src
[i
].type
= IRQ_TYPE_FSLINT
;
1502 opp
->src
[i
].level
= true;
1505 /* timers and IPIs */
1506 for (i
= OPENPIC_MAX_SRC
; i
< virq
; i
++) {
1507 opp
->src
[i
].type
= IRQ_TYPE_FSLSPECIAL
;
1508 opp
->src
[i
].level
= false;
1512 static void map_list(OpenPICState
*opp
, const MemReg
*list
, int *count
)
1514 while (list
->name
) {
1515 assert(*count
< ARRAY_SIZE(opp
->sub_io_mem
));
1517 memory_region_init_io(&opp
->sub_io_mem
[*count
], OBJECT(opp
), list
->ops
,
1518 opp
, list
->name
, list
->size
);
1520 memory_region_add_subregion(&opp
->mem
, list
->start_addr
,
1521 &opp
->sub_io_mem
[*count
]);
1528 static void openpic_init(Object
*obj
)
1530 OpenPICState
*opp
= OPENPIC(obj
);
1532 memory_region_init(&opp
->mem
, obj
, "openpic", 0x40000);
1535 static void openpic_realize(DeviceState
*dev
, Error
**errp
)
1537 SysBusDevice
*d
= SYS_BUS_DEVICE(dev
);
1538 OpenPICState
*opp
= OPENPIC(dev
);
1541 static const MemReg list_le
[] = {
1542 {"glb", &openpic_glb_ops_le
,
1543 OPENPIC_GLB_REG_START
, OPENPIC_GLB_REG_SIZE
},
1544 {"tmr", &openpic_tmr_ops_le
,
1545 OPENPIC_TMR_REG_START
, OPENPIC_TMR_REG_SIZE
},
1546 {"src", &openpic_src_ops_le
,
1547 OPENPIC_SRC_REG_START
, OPENPIC_SRC_REG_SIZE
},
1548 {"cpu", &openpic_cpu_ops_le
,
1549 OPENPIC_CPU_REG_START
, OPENPIC_CPU_REG_SIZE
},
1552 static const MemReg list_be
[] = {
1553 {"glb", &openpic_glb_ops_be
,
1554 OPENPIC_GLB_REG_START
, OPENPIC_GLB_REG_SIZE
},
1555 {"tmr", &openpic_tmr_ops_be
,
1556 OPENPIC_TMR_REG_START
, OPENPIC_TMR_REG_SIZE
},
1557 {"src", &openpic_src_ops_be
,
1558 OPENPIC_SRC_REG_START
, OPENPIC_SRC_REG_SIZE
},
1559 {"cpu", &openpic_cpu_ops_be
,
1560 OPENPIC_CPU_REG_START
, OPENPIC_CPU_REG_SIZE
},
1563 static const MemReg list_fsl
[] = {
1564 {"msi", &openpic_msi_ops_be
,
1565 OPENPIC_MSI_REG_START
, OPENPIC_MSI_REG_SIZE
},
1566 {"summary", &openpic_summary_ops_be
,
1567 OPENPIC_SUMMARY_REG_START
, OPENPIC_SUMMARY_REG_SIZE
},
1571 if (opp
->nb_cpus
> MAX_CPU
) {
1572 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
,
1573 TYPE_OPENPIC
, "nb_cpus", (uint64_t)opp
->nb_cpus
,
1574 (uint64_t)0, (uint64_t)MAX_CPU
);
1578 switch (opp
->model
) {
1579 case OPENPIC_MODEL_FSL_MPIC_20
:
1581 opp
->fsl
= &fsl_mpic_20
;
1582 opp
->brr1
= 0x00400200;
1583 opp
->flags
|= OPENPIC_FLAG_IDR_CRIT
;
1585 opp
->mpic_mode_mask
= GCR_MODE_MIXED
;
1587 fsl_common_init(opp
);
1588 map_list(opp
, list_be
, &list_count
);
1589 map_list(opp
, list_fsl
, &list_count
);
1593 case OPENPIC_MODEL_FSL_MPIC_42
:
1594 opp
->fsl
= &fsl_mpic_42
;
1595 opp
->brr1
= 0x00400402;
1596 opp
->flags
|= OPENPIC_FLAG_ILR
;
1598 opp
->mpic_mode_mask
= GCR_MODE_PROXY
;
1600 fsl_common_init(opp
);
1601 map_list(opp
, list_be
, &list_count
);
1602 map_list(opp
, list_fsl
, &list_count
);
1606 case OPENPIC_MODEL_RAVEN
:
1607 opp
->nb_irqs
= RAVEN_MAX_EXT
;
1608 opp
->vid
= VID_REVISION_1_3
;
1609 opp
->vir
= VIR_GENERIC
;
1610 opp
->vector_mask
= 0xFF;
1611 opp
->tfrr_reset
= 4160000;
1612 opp
->ivpr_reset
= IVPR_MASK_MASK
| IVPR_MODE_MASK
;
1614 opp
->max_irq
= RAVEN_MAX_IRQ
;
1615 opp
->irq_ipi0
= RAVEN_IPI_IRQ
;
1616 opp
->irq_tim0
= RAVEN_TMR_IRQ
;
1618 opp
->mpic_mode_mask
= GCR_MODE_MIXED
;
1620 if (opp
->nb_cpus
!= 1) {
1621 error_setg(errp
, "Only UP supported today");
1625 map_list(opp
, list_le
, &list_count
);
1629 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
1630 opp
->dst
[i
].irqs
= g_new0(qemu_irq
, OPENPIC_OUTPUT_NB
);
1631 for (j
= 0; j
< OPENPIC_OUTPUT_NB
; j
++) {
1632 sysbus_init_irq(d
, &opp
->dst
[i
].irqs
[j
]);
1636 register_savevm(dev
, "openpic", 0, 2,
1637 openpic_save
, openpic_load
, opp
);
1639 sysbus_init_mmio(d
, &opp
->mem
);
1640 qdev_init_gpio_in(dev
, openpic_set_irq
, opp
->max_irq
);
1643 static Property openpic_properties
[] = {
1644 DEFINE_PROP_UINT32("model", OpenPICState
, model
, OPENPIC_MODEL_FSL_MPIC_20
),
1645 DEFINE_PROP_UINT32("nb_cpus", OpenPICState
, nb_cpus
, 1),
1646 DEFINE_PROP_END_OF_LIST(),
1649 static void openpic_class_init(ObjectClass
*oc
, void *data
)
1651 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1653 dc
->realize
= openpic_realize
;
1654 dc
->props
= openpic_properties
;
1655 dc
->reset
= openpic_reset
;
1658 static const TypeInfo openpic_info
= {
1659 .name
= TYPE_OPENPIC
,
1660 .parent
= TYPE_SYS_BUS_DEVICE
,
1661 .instance_size
= sizeof(OpenPICState
),
1662 .instance_init
= openpic_init
,
1663 .class_init
= openpic_class_init
,
1666 static void openpic_register_types(void)
1668 type_register_static(&openpic_info
);
1671 type_init(openpic_register_types
)