2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/cutils.h"
23 #include "qemu/bitops.h"
24 #include "qemu/qemu-print.h"
27 #include "exec/exec-all.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/reset.h"
30 #include "sysemu/hvf.h"
31 #include "sysemu/cpus.h"
35 #include "qemu/error-report.h"
36 #include "qemu/module.h"
37 #include "qemu/option.h"
38 #include "qemu/config-file.h"
39 #include "qapi/error.h"
40 #include "qapi/qapi-visit-machine.h"
41 #include "qapi/qapi-visit-run-state.h"
42 #include "qapi/qmp/qdict.h"
43 #include "qapi/qmp/qerror.h"
44 #include "qapi/visitor.h"
45 #include "qom/qom-qobject.h"
46 #include "sysemu/arch_init.h"
47 #include "qapi/qapi-commands-machine-target.h"
49 #include "standard-headers/asm-x86/kvm_para.h"
51 #include "sysemu/sysemu.h"
52 #include "sysemu/tcg.h"
53 #include "hw/qdev-properties.h"
54 #include "hw/i386/topology.h"
55 #ifndef CONFIG_USER_ONLY
56 #include "exec/address-spaces.h"
57 #include "hw/xen/xen.h"
58 #include "hw/i386/apic_internal.h"
59 #include "hw/boards.h"
62 #include "disas/capstone.h"
64 /* Helpers for building CPUID[2] descriptors: */
66 struct CPUID2CacheDescriptorInfo
{
75 * Known CPUID 2 cache descriptors.
76 * From Intel SDM Volume 2A, CPUID instruction
78 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors
[] = {
79 [0x06] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 8 * KiB
,
80 .associativity
= 4, .line_size
= 32, },
81 [0x08] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 16 * KiB
,
82 .associativity
= 4, .line_size
= 32, },
83 [0x09] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 32 * KiB
,
84 .associativity
= 4, .line_size
= 64, },
85 [0x0A] = { .level
= 1, .type
= DATA_CACHE
, .size
= 8 * KiB
,
86 .associativity
= 2, .line_size
= 32, },
87 [0x0C] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
88 .associativity
= 4, .line_size
= 32, },
89 [0x0D] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
90 .associativity
= 4, .line_size
= 64, },
91 [0x0E] = { .level
= 1, .type
= DATA_CACHE
, .size
= 24 * KiB
,
92 .associativity
= 6, .line_size
= 64, },
93 [0x1D] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 128 * KiB
,
94 .associativity
= 2, .line_size
= 64, },
95 [0x21] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 256 * KiB
,
96 .associativity
= 8, .line_size
= 64, },
97 /* lines per sector is not supported cpuid2_cache_descriptor(),
98 * so descriptors 0x22, 0x23 are not included
100 [0x24] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
101 .associativity
= 16, .line_size
= 64, },
102 /* lines per sector is not supported cpuid2_cache_descriptor(),
103 * so descriptors 0x25, 0x20 are not included
105 [0x2C] = { .level
= 1, .type
= DATA_CACHE
, .size
= 32 * KiB
,
106 .associativity
= 8, .line_size
= 64, },
107 [0x30] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 32 * KiB
,
108 .associativity
= 8, .line_size
= 64, },
109 [0x41] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 128 * KiB
,
110 .associativity
= 4, .line_size
= 32, },
111 [0x42] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 256 * KiB
,
112 .associativity
= 4, .line_size
= 32, },
113 [0x43] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
114 .associativity
= 4, .line_size
= 32, },
115 [0x44] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
116 .associativity
= 4, .line_size
= 32, },
117 [0x45] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
118 .associativity
= 4, .line_size
= 32, },
119 [0x46] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 4 * MiB
,
120 .associativity
= 4, .line_size
= 64, },
121 [0x47] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 8 * MiB
,
122 .associativity
= 8, .line_size
= 64, },
123 [0x48] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 3 * MiB
,
124 .associativity
= 12, .line_size
= 64, },
125 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
126 [0x4A] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 6 * MiB
,
127 .associativity
= 12, .line_size
= 64, },
128 [0x4B] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 8 * MiB
,
129 .associativity
= 16, .line_size
= 64, },
130 [0x4C] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 12 * MiB
,
131 .associativity
= 12, .line_size
= 64, },
132 [0x4D] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 16 * MiB
,
133 .associativity
= 16, .line_size
= 64, },
134 [0x4E] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 6 * MiB
,
135 .associativity
= 24, .line_size
= 64, },
136 [0x60] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
137 .associativity
= 8, .line_size
= 64, },
138 [0x66] = { .level
= 1, .type
= DATA_CACHE
, .size
= 8 * KiB
,
139 .associativity
= 4, .line_size
= 64, },
140 [0x67] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
141 .associativity
= 4, .line_size
= 64, },
142 [0x68] = { .level
= 1, .type
= DATA_CACHE
, .size
= 32 * KiB
,
143 .associativity
= 4, .line_size
= 64, },
144 [0x78] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
145 .associativity
= 4, .line_size
= 64, },
146 /* lines per sector is not supported cpuid2_cache_descriptor(),
147 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
149 [0x7D] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
150 .associativity
= 8, .line_size
= 64, },
151 [0x7F] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
152 .associativity
= 2, .line_size
= 64, },
153 [0x80] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
154 .associativity
= 8, .line_size
= 64, },
155 [0x82] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 256 * KiB
,
156 .associativity
= 8, .line_size
= 32, },
157 [0x83] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
158 .associativity
= 8, .line_size
= 32, },
159 [0x84] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
160 .associativity
= 8, .line_size
= 32, },
161 [0x85] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
162 .associativity
= 8, .line_size
= 32, },
163 [0x86] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
164 .associativity
= 4, .line_size
= 64, },
165 [0x87] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
166 .associativity
= 8, .line_size
= 64, },
167 [0xD0] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
168 .associativity
= 4, .line_size
= 64, },
169 [0xD1] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
170 .associativity
= 4, .line_size
= 64, },
171 [0xD2] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
172 .associativity
= 4, .line_size
= 64, },
173 [0xD6] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
174 .associativity
= 8, .line_size
= 64, },
175 [0xD7] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
176 .associativity
= 8, .line_size
= 64, },
177 [0xD8] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 4 * MiB
,
178 .associativity
= 8, .line_size
= 64, },
179 [0xDC] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 1.5 * MiB
,
180 .associativity
= 12, .line_size
= 64, },
181 [0xDD] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 3 * MiB
,
182 .associativity
= 12, .line_size
= 64, },
183 [0xDE] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 6 * MiB
,
184 .associativity
= 12, .line_size
= 64, },
185 [0xE2] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
186 .associativity
= 16, .line_size
= 64, },
187 [0xE3] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 4 * MiB
,
188 .associativity
= 16, .line_size
= 64, },
189 [0xE4] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 8 * MiB
,
190 .associativity
= 16, .line_size
= 64, },
191 [0xEA] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 12 * MiB
,
192 .associativity
= 24, .line_size
= 64, },
193 [0xEB] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 18 * MiB
,
194 .associativity
= 24, .line_size
= 64, },
195 [0xEC] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 24 * MiB
,
196 .associativity
= 24, .line_size
= 64, },
200 * "CPUID leaf 2 does not report cache descriptor information,
201 * use CPUID leaf 4 to query cache parameters"
203 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
206 * Return a CPUID 2 cache descriptor for a given cache.
207 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
209 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo
*cache
)
213 assert(cache
->size
> 0);
214 assert(cache
->level
> 0);
215 assert(cache
->line_size
> 0);
216 assert(cache
->associativity
> 0);
217 for (i
= 0; i
< ARRAY_SIZE(cpuid2_cache_descriptors
); i
++) {
218 struct CPUID2CacheDescriptorInfo
*d
= &cpuid2_cache_descriptors
[i
];
219 if (d
->level
== cache
->level
&& d
->type
== cache
->type
&&
220 d
->size
== cache
->size
&& d
->line_size
== cache
->line_size
&&
221 d
->associativity
== cache
->associativity
) {
226 return CACHE_DESCRIPTOR_UNAVAILABLE
;
229 /* CPUID Leaf 4 constants: */
232 #define CACHE_TYPE_D 1
233 #define CACHE_TYPE_I 2
234 #define CACHE_TYPE_UNIFIED 3
236 #define CACHE_LEVEL(l) (l << 5)
238 #define CACHE_SELF_INIT_LEVEL (1 << 8)
241 #define CACHE_NO_INVD_SHARING (1 << 0)
242 #define CACHE_INCLUSIVE (1 << 1)
243 #define CACHE_COMPLEX_IDX (1 << 2)
245 /* Encode CacheType for CPUID[4].EAX */
246 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
247 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
248 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
249 0 /* Invalid value */)
252 /* Encode cache info for CPUID[4] */
253 static void encode_cache_cpuid4(CPUCacheInfo
*cache
,
254 int num_apic_ids
, int num_cores
,
255 uint32_t *eax
, uint32_t *ebx
,
256 uint32_t *ecx
, uint32_t *edx
)
258 assert(cache
->size
== cache
->line_size
* cache
->associativity
*
259 cache
->partitions
* cache
->sets
);
261 assert(num_apic_ids
> 0);
262 *eax
= CACHE_TYPE(cache
->type
) |
263 CACHE_LEVEL(cache
->level
) |
264 (cache
->self_init
? CACHE_SELF_INIT_LEVEL
: 0) |
265 ((num_cores
- 1) << 26) |
266 ((num_apic_ids
- 1) << 14);
268 assert(cache
->line_size
> 0);
269 assert(cache
->partitions
> 0);
270 assert(cache
->associativity
> 0);
271 /* We don't implement fully-associative caches */
272 assert(cache
->associativity
< cache
->sets
);
273 *ebx
= (cache
->line_size
- 1) |
274 ((cache
->partitions
- 1) << 12) |
275 ((cache
->associativity
- 1) << 22);
277 assert(cache
->sets
> 0);
278 *ecx
= cache
->sets
- 1;
280 *edx
= (cache
->no_invd_sharing
? CACHE_NO_INVD_SHARING
: 0) |
281 (cache
->inclusive
? CACHE_INCLUSIVE
: 0) |
282 (cache
->complex_indexing
? CACHE_COMPLEX_IDX
: 0);
285 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
286 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo
*cache
)
288 assert(cache
->size
% 1024 == 0);
289 assert(cache
->lines_per_tag
> 0);
290 assert(cache
->associativity
> 0);
291 assert(cache
->line_size
> 0);
292 return ((cache
->size
/ 1024) << 24) | (cache
->associativity
<< 16) |
293 (cache
->lines_per_tag
<< 8) | (cache
->line_size
);
296 #define ASSOC_FULL 0xFF
298 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
299 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
309 a == ASSOC_FULL ? 0xF : \
310 0 /* invalid value */)
313 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
316 static void encode_cache_cpuid80000006(CPUCacheInfo
*l2
,
318 uint32_t *ecx
, uint32_t *edx
)
320 assert(l2
->size
% 1024 == 0);
321 assert(l2
->associativity
> 0);
322 assert(l2
->lines_per_tag
> 0);
323 assert(l2
->line_size
> 0);
324 *ecx
= ((l2
->size
/ 1024) << 16) |
325 (AMD_ENC_ASSOC(l2
->associativity
) << 12) |
326 (l2
->lines_per_tag
<< 8) | (l2
->line_size
);
329 assert(l3
->size
% (512 * 1024) == 0);
330 assert(l3
->associativity
> 0);
331 assert(l3
->lines_per_tag
> 0);
332 assert(l3
->line_size
> 0);
333 *edx
= ((l3
->size
/ (512 * 1024)) << 18) |
334 (AMD_ENC_ASSOC(l3
->associativity
) << 12) |
335 (l3
->lines_per_tag
<< 8) | (l3
->line_size
);
342 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
343 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
344 * Define the constants to build the cpu topology. Right now, TOPOEXT
345 * feature is enabled only on EPYC. So, these constants are based on
346 * EPYC supported configurations. We may need to handle the cases if
347 * these values change in future.
349 /* Maximum core complexes in a node */
351 /* Maximum cores in a core complex */
352 #define MAX_CORES_IN_CCX 4
353 /* Maximum cores in a node */
354 #define MAX_CORES_IN_NODE 8
355 /* Maximum nodes in a socket */
356 #define MAX_NODES_PER_SOCKET 4
359 * Figure out the number of nodes required to build this config.
360 * Max cores in a node is 8
362 static int nodes_in_socket(int nr_cores
)
366 nodes
= DIV_ROUND_UP(nr_cores
, MAX_CORES_IN_NODE
);
368 /* Hardware does not support config with 3 nodes, return 4 in that case */
369 return (nodes
== 3) ? 4 : nodes
;
373 * Decide the number of cores in a core complex with the given nr_cores using
374 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
375 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
376 * L3 cache is shared across all cores in a core complex. So, this will also
377 * tell us how many cores are sharing the L3 cache.
379 static int cores_in_core_complex(int nr_cores
)
383 /* Check if we can fit all the cores in one core complex */
384 if (nr_cores
<= MAX_CORES_IN_CCX
) {
387 /* Get the number of nodes required to build this config */
388 nodes
= nodes_in_socket(nr_cores
);
391 * Divide the cores accros all the core complexes
392 * Return rounded up value
394 return DIV_ROUND_UP(nr_cores
, nodes
* MAX_CCX
);
397 /* Encode cache info for CPUID[8000001D] */
398 static void encode_cache_cpuid8000001d(CPUCacheInfo
*cache
, CPUState
*cs
,
399 uint32_t *eax
, uint32_t *ebx
,
400 uint32_t *ecx
, uint32_t *edx
)
403 assert(cache
->size
== cache
->line_size
* cache
->associativity
*
404 cache
->partitions
* cache
->sets
);
406 *eax
= CACHE_TYPE(cache
->type
) | CACHE_LEVEL(cache
->level
) |
407 (cache
->self_init
? CACHE_SELF_INIT_LEVEL
: 0);
409 /* L3 is shared among multiple cores */
410 if (cache
->level
== 3) {
411 l3_cores
= cores_in_core_complex(cs
->nr_cores
);
412 *eax
|= ((l3_cores
* cs
->nr_threads
) - 1) << 14;
414 *eax
|= ((cs
->nr_threads
- 1) << 14);
417 assert(cache
->line_size
> 0);
418 assert(cache
->partitions
> 0);
419 assert(cache
->associativity
> 0);
420 /* We don't implement fully-associative caches */
421 assert(cache
->associativity
< cache
->sets
);
422 *ebx
= (cache
->line_size
- 1) |
423 ((cache
->partitions
- 1) << 12) |
424 ((cache
->associativity
- 1) << 22);
426 assert(cache
->sets
> 0);
427 *ecx
= cache
->sets
- 1;
429 *edx
= (cache
->no_invd_sharing
? CACHE_NO_INVD_SHARING
: 0) |
430 (cache
->inclusive
? CACHE_INCLUSIVE
: 0) |
431 (cache
->complex_indexing
? CACHE_COMPLEX_IDX
: 0);
434 /* Data structure to hold the configuration info for a given core index */
435 struct core_topology
{
436 /* core complex id of the current core index */
439 * Adjusted core index for this core in the topology
440 * This can be 0,1,2,3 with max 4 cores in a core complex
443 /* Node id for this core index */
445 /* Number of nodes in this config */
450 * Build the configuration closely match the EPYC hardware. Using the EPYC
451 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
452 * right now. This could change in future.
453 * nr_cores : Total number of cores in the config
454 * core_id : Core index of the current CPU
455 * topo : Data structure to hold all the config info for this core index
457 static void build_core_topology(int nr_cores
, int core_id
,
458 struct core_topology
*topo
)
460 int nodes
, cores_in_ccx
;
462 /* First get the number of nodes required */
463 nodes
= nodes_in_socket(nr_cores
);
465 cores_in_ccx
= cores_in_core_complex(nr_cores
);
467 topo
->node_id
= core_id
/ (cores_in_ccx
* MAX_CCX
);
468 topo
->ccx_id
= (core_id
% (cores_in_ccx
* MAX_CCX
)) / cores_in_ccx
;
469 topo
->core_id
= core_id
% cores_in_ccx
;
470 topo
->num_nodes
= nodes
;
473 /* Encode cache info for CPUID[8000001E] */
474 static void encode_topo_cpuid8000001e(CPUState
*cs
, X86CPU
*cpu
,
475 uint32_t *eax
, uint32_t *ebx
,
476 uint32_t *ecx
, uint32_t *edx
)
478 struct core_topology topo
= {0};
482 build_core_topology(cs
->nr_cores
, cpu
->core_id
, &topo
);
485 * CPUID_Fn8000001E_EBX
487 * 15:8 Threads per core (The number of threads per core is
488 * Threads per core + 1)
489 * 7:0 Core id (see bit decoding below)
499 if (cs
->nr_threads
- 1) {
500 *ebx
= ((cs
->nr_threads
- 1) << 8) | (topo
.node_id
<< 3) |
501 (topo
.ccx_id
<< 2) | topo
.core_id
;
503 *ebx
= (topo
.node_id
<< 4) | (topo
.ccx_id
<< 3) | topo
.core_id
;
506 * CPUID_Fn8000001E_ECX
508 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
509 * 7:0 Node id (see bit decoding below)
513 if (topo
.num_nodes
<= 4) {
514 *ecx
= ((topo
.num_nodes
- 1) << 8) | (cpu
->socket_id
<< 2) |
518 * Node id fix up. Actual hardware supports up to 4 nodes. But with
519 * more than 32 cores, we may end up with more than 4 nodes.
520 * Node id is a combination of socket id and node id. Only requirement
521 * here is that this number should be unique accross the system.
522 * Shift the socket id to accommodate more nodes. We dont expect both
523 * socket id and node id to be big number at the same time. This is not
524 * an ideal config but we need to to support it. Max nodes we can have
525 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
526 * 5 bits for nodes. Find the left most set bit to represent the total
527 * number of nodes. find_last_bit returns last set bit(0 based). Left
528 * shift(+1) the socket id to represent all the nodes.
530 nodes
= topo
.num_nodes
- 1;
531 shift
= find_last_bit(&nodes
, 8);
532 *ecx
= ((topo
.num_nodes
- 1) << 8) | (cpu
->socket_id
<< (shift
+ 1)) |
539 * Definitions of the hardcoded cache entries we expose:
540 * These are legacy cache values. If there is a need to change any
541 * of these values please use builtin_x86_defs
545 static CPUCacheInfo legacy_l1d_cache
= {
554 .no_invd_sharing
= true,
557 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
558 static CPUCacheInfo legacy_l1d_cache_amd
= {
568 .no_invd_sharing
= true,
571 /* L1 instruction cache: */
572 static CPUCacheInfo legacy_l1i_cache
= {
573 .type
= INSTRUCTION_CACHE
,
581 .no_invd_sharing
= true,
584 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
585 static CPUCacheInfo legacy_l1i_cache_amd
= {
586 .type
= INSTRUCTION_CACHE
,
595 .no_invd_sharing
= true,
598 /* Level 2 unified cache: */
599 static CPUCacheInfo legacy_l2_cache
= {
600 .type
= UNIFIED_CACHE
,
608 .no_invd_sharing
= true,
611 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
612 static CPUCacheInfo legacy_l2_cache_cpuid2
= {
613 .type
= UNIFIED_CACHE
,
621 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
622 static CPUCacheInfo legacy_l2_cache_amd
= {
623 .type
= UNIFIED_CACHE
,
633 /* Level 3 unified cache: */
634 static CPUCacheInfo legacy_l3_cache
= {
635 .type
= UNIFIED_CACHE
,
645 .complex_indexing
= true,
648 /* TLB definitions: */
650 #define L1_DTLB_2M_ASSOC 1
651 #define L1_DTLB_2M_ENTRIES 255
652 #define L1_DTLB_4K_ASSOC 1
653 #define L1_DTLB_4K_ENTRIES 255
655 #define L1_ITLB_2M_ASSOC 1
656 #define L1_ITLB_2M_ENTRIES 255
657 #define L1_ITLB_4K_ASSOC 1
658 #define L1_ITLB_4K_ENTRIES 255
660 #define L2_DTLB_2M_ASSOC 0 /* disabled */
661 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
662 #define L2_DTLB_4K_ASSOC 4
663 #define L2_DTLB_4K_ENTRIES 512
665 #define L2_ITLB_2M_ASSOC 0 /* disabled */
666 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
667 #define L2_ITLB_4K_ASSOC 4
668 #define L2_ITLB_4K_ENTRIES 512
670 /* CPUID Leaf 0x14 constants: */
671 #define INTEL_PT_MAX_SUBLEAF 0x1
673 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
674 * MSR can be accessed;
675 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
676 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
677 * of Intel PT MSRs across warm reset;
678 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
680 #define INTEL_PT_MINIMAL_EBX 0xf
682 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
683 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
685 * bit[01]: ToPA tables can hold any number of output entries, up to the
686 * maximum allowed by the MaskOrTableOffset field of
687 * IA32_RTIT_OUTPUT_MASK_PTRS;
688 * bit[02]: Support Single-Range Output scheme;
690 #define INTEL_PT_MINIMAL_ECX 0x7
691 /* generated packets which contain IP payloads have LIP values */
692 #define INTEL_PT_IP_LIP (1 << 31)
693 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
694 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
695 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
696 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
697 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
699 static void x86_cpu_vendor_words2str(char *dst
, uint32_t vendor1
,
700 uint32_t vendor2
, uint32_t vendor3
)
703 for (i
= 0; i
< 4; i
++) {
704 dst
[i
] = vendor1
>> (8 * i
);
705 dst
[i
+ 4] = vendor2
>> (8 * i
);
706 dst
[i
+ 8] = vendor3
>> (8 * i
);
708 dst
[CPUID_VENDOR_SZ
] = '\0';
711 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
712 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
713 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
714 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
715 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
716 CPUID_PSE36 | CPUID_FXSR)
717 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
718 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
719 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
720 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
721 CPUID_PAE | CPUID_SEP | CPUID_APIC)
723 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
724 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
725 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
726 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
727 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
728 /* partly implemented:
729 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
731 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
732 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
733 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
734 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
735 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
736 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
739 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
740 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
741 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
742 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
746 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
748 #define TCG_EXT2_X86_64_FEATURES 0
751 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
752 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
753 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
754 TCG_EXT2_X86_64_FEATURES)
755 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
756 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
757 #define TCG_EXT4_FEATURES 0
758 #define TCG_SVM_FEATURES CPUID_SVM_NPT
759 #define TCG_KVM_FEATURES 0
760 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
761 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
762 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
763 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
766 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
767 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
768 CPUID_7_0_EBX_RDSEED */
769 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
770 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
772 #define TCG_7_0_EDX_FEATURES 0
773 #define TCG_7_1_EAX_FEATURES 0
774 #define TCG_APM_FEATURES 0
775 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
776 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
778 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
780 typedef enum FeatureWordType
{
785 typedef struct FeatureWordInfo
{
786 FeatureWordType type
;
787 /* feature flags names are taken from "Intel Processor Identification and
788 * the CPUID Instruction" and AMD's "CPUID Specification".
789 * In cases of disagreement between feature naming conventions,
790 * aliases may be added.
792 const char *feat_names
[64];
794 /* If type==CPUID_FEATURE_WORD */
796 uint32_t eax
; /* Input EAX for CPUID */
797 bool needs_ecx
; /* CPUID instruction uses ECX as input */
798 uint32_t ecx
; /* Input ECX value for CPUID */
799 int reg
; /* output register (R_* constant) */
801 /* If type==MSR_FEATURE_WORD */
806 uint64_t tcg_features
; /* Feature flags supported by TCG */
807 uint64_t unmigratable_flags
; /* Feature flags known to be unmigratable */
808 uint64_t migratable_flags
; /* Feature flags known to be migratable */
809 /* Features that shouldn't be auto-enabled by "-cpu host" */
810 uint64_t no_autoenable_flags
;
813 static FeatureWordInfo feature_word_info
[FEATURE_WORDS
] = {
815 .type
= CPUID_FEATURE_WORD
,
817 "fpu", "vme", "de", "pse",
818 "tsc", "msr", "pae", "mce",
819 "cx8", "apic", NULL
, "sep",
820 "mtrr", "pge", "mca", "cmov",
821 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
822 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
823 "fxsr", "sse", "sse2", "ss",
824 "ht" /* Intel htt */, "tm", "ia64", "pbe",
826 .cpuid
= {.eax
= 1, .reg
= R_EDX
, },
827 .tcg_features
= TCG_FEATURES
,
830 .type
= CPUID_FEATURE_WORD
,
832 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
833 "ds-cpl", "vmx", "smx", "est",
834 "tm2", "ssse3", "cid", NULL
,
835 "fma", "cx16", "xtpr", "pdcm",
836 NULL
, "pcid", "dca", "sse4.1",
837 "sse4.2", "x2apic", "movbe", "popcnt",
838 "tsc-deadline", "aes", "xsave", NULL
/* osxsave */,
839 "avx", "f16c", "rdrand", "hypervisor",
841 .cpuid
= { .eax
= 1, .reg
= R_ECX
, },
842 .tcg_features
= TCG_EXT_FEATURES
,
844 /* Feature names that are already defined on feature_name[] but
845 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
846 * names on feat_names below. They are copied automatically
847 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
849 [FEAT_8000_0001_EDX
] = {
850 .type
= CPUID_FEATURE_WORD
,
852 NULL
/* fpu */, NULL
/* vme */, NULL
/* de */, NULL
/* pse */,
853 NULL
/* tsc */, NULL
/* msr */, NULL
/* pae */, NULL
/* mce */,
854 NULL
/* cx8 */, NULL
/* apic */, NULL
, "syscall",
855 NULL
/* mtrr */, NULL
/* pge */, NULL
/* mca */, NULL
/* cmov */,
856 NULL
/* pat */, NULL
/* pse36 */, NULL
, NULL
/* Linux mp */,
857 "nx", NULL
, "mmxext", NULL
/* mmx */,
858 NULL
/* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
859 NULL
, "lm", "3dnowext", "3dnow",
861 .cpuid
= { .eax
= 0x80000001, .reg
= R_EDX
, },
862 .tcg_features
= TCG_EXT2_FEATURES
,
864 [FEAT_8000_0001_ECX
] = {
865 .type
= CPUID_FEATURE_WORD
,
867 "lahf-lm", "cmp-legacy", "svm", "extapic",
868 "cr8legacy", "abm", "sse4a", "misalignsse",
869 "3dnowprefetch", "osvw", "ibs", "xop",
870 "skinit", "wdt", NULL
, "lwp",
871 "fma4", "tce", NULL
, "nodeid-msr",
872 NULL
, "tbm", "topoext", "perfctr-core",
873 "perfctr-nb", NULL
, NULL
, NULL
,
874 NULL
, NULL
, NULL
, NULL
,
876 .cpuid
= { .eax
= 0x80000001, .reg
= R_ECX
, },
877 .tcg_features
= TCG_EXT3_FEATURES
,
879 * TOPOEXT is always allowed but can't be enabled blindly by
880 * "-cpu host", as it requires consistent cache topology info
881 * to be provided so it doesn't confuse guests.
883 .no_autoenable_flags
= CPUID_EXT3_TOPOEXT
,
885 [FEAT_C000_0001_EDX
] = {
886 .type
= CPUID_FEATURE_WORD
,
888 NULL
, NULL
, "xstore", "xstore-en",
889 NULL
, NULL
, "xcrypt", "xcrypt-en",
890 "ace2", "ace2-en", "phe", "phe-en",
891 "pmm", "pmm-en", NULL
, NULL
,
892 NULL
, NULL
, NULL
, NULL
,
893 NULL
, NULL
, NULL
, NULL
,
894 NULL
, NULL
, NULL
, NULL
,
895 NULL
, NULL
, NULL
, NULL
,
897 .cpuid
= { .eax
= 0xC0000001, .reg
= R_EDX
, },
898 .tcg_features
= TCG_EXT4_FEATURES
,
901 .type
= CPUID_FEATURE_WORD
,
903 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
904 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
905 NULL
, "kvm-pv-tlb-flush", NULL
, "kvm-pv-ipi",
906 "kvm-poll-control", "kvm-pv-sched-yield", NULL
, NULL
,
907 NULL
, NULL
, NULL
, NULL
,
908 NULL
, NULL
, NULL
, NULL
,
909 "kvmclock-stable-bit", NULL
, NULL
, NULL
,
910 NULL
, NULL
, NULL
, NULL
,
912 .cpuid
= { .eax
= KVM_CPUID_FEATURES
, .reg
= R_EAX
, },
913 .tcg_features
= TCG_KVM_FEATURES
,
916 .type
= CPUID_FEATURE_WORD
,
918 "kvm-hint-dedicated", NULL
, NULL
, NULL
,
919 NULL
, NULL
, NULL
, NULL
,
920 NULL
, NULL
, NULL
, NULL
,
921 NULL
, NULL
, NULL
, NULL
,
922 NULL
, NULL
, NULL
, NULL
,
923 NULL
, NULL
, NULL
, NULL
,
924 NULL
, NULL
, NULL
, NULL
,
925 NULL
, NULL
, NULL
, NULL
,
927 .cpuid
= { .eax
= KVM_CPUID_FEATURES
, .reg
= R_EDX
, },
928 .tcg_features
= TCG_KVM_FEATURES
,
930 * KVM hints aren't auto-enabled by -cpu host, they need to be
931 * explicitly enabled in the command-line.
933 .no_autoenable_flags
= ~0U,
936 * .feat_names are commented out for Hyper-V enlightenments because we
937 * don't want to have two different ways for enabling them on QEMU command
938 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
939 * enabling several feature bits simultaneously, exposing these bits
940 * individually may just confuse guests.
942 [FEAT_HYPERV_EAX
] = {
943 .type
= CPUID_FEATURE_WORD
,
945 NULL
/* hv_msr_vp_runtime_access */, NULL
/* hv_msr_time_refcount_access */,
946 NULL
/* hv_msr_synic_access */, NULL
/* hv_msr_stimer_access */,
947 NULL
/* hv_msr_apic_access */, NULL
/* hv_msr_hypercall_access */,
948 NULL
/* hv_vpindex_access */, NULL
/* hv_msr_reset_access */,
949 NULL
/* hv_msr_stats_access */, NULL
/* hv_reftsc_access */,
950 NULL
/* hv_msr_idle_access */, NULL
/* hv_msr_frequency_access */,
951 NULL
/* hv_msr_debug_access */, NULL
/* hv_msr_reenlightenment_access */,
953 NULL
, NULL
, NULL
, NULL
,
954 NULL
, NULL
, NULL
, NULL
,
955 NULL
, NULL
, NULL
, NULL
,
956 NULL
, NULL
, NULL
, NULL
,
958 .cpuid
= { .eax
= 0x40000003, .reg
= R_EAX
, },
960 [FEAT_HYPERV_EBX
] = {
961 .type
= CPUID_FEATURE_WORD
,
963 NULL
/* hv_create_partitions */, NULL
/* hv_access_partition_id */,
964 NULL
/* hv_access_memory_pool */, NULL
/* hv_adjust_message_buffers */,
965 NULL
/* hv_post_messages */, NULL
/* hv_signal_events */,
966 NULL
/* hv_create_port */, NULL
/* hv_connect_port */,
967 NULL
/* hv_access_stats */, NULL
, NULL
, NULL
/* hv_debugging */,
968 NULL
/* hv_cpu_power_management */, NULL
/* hv_configure_profiler */,
970 NULL
, NULL
, NULL
, NULL
,
971 NULL
, NULL
, NULL
, NULL
,
972 NULL
, NULL
, NULL
, NULL
,
973 NULL
, NULL
, NULL
, NULL
,
975 .cpuid
= { .eax
= 0x40000003, .reg
= R_EBX
, },
977 [FEAT_HYPERV_EDX
] = {
978 .type
= CPUID_FEATURE_WORD
,
980 NULL
/* hv_mwait */, NULL
/* hv_guest_debugging */,
981 NULL
/* hv_perf_monitor */, NULL
/* hv_cpu_dynamic_part */,
982 NULL
/* hv_hypercall_params_xmm */, NULL
/* hv_guest_idle_state */,
984 NULL
, NULL
, NULL
/* hv_guest_crash_msr */, NULL
,
985 NULL
, NULL
, NULL
, NULL
,
986 NULL
, NULL
, NULL
, NULL
,
987 NULL
, NULL
, NULL
, NULL
,
988 NULL
, NULL
, NULL
, NULL
,
989 NULL
, NULL
, NULL
, NULL
,
991 .cpuid
= { .eax
= 0x40000003, .reg
= R_EDX
, },
993 [FEAT_HV_RECOMM_EAX
] = {
994 .type
= CPUID_FEATURE_WORD
,
996 NULL
/* hv_recommend_pv_as_switch */,
997 NULL
/* hv_recommend_pv_tlbflush_local */,
998 NULL
/* hv_recommend_pv_tlbflush_remote */,
999 NULL
/* hv_recommend_msr_apic_access */,
1000 NULL
/* hv_recommend_msr_reset */,
1001 NULL
/* hv_recommend_relaxed_timing */,
1002 NULL
/* hv_recommend_dma_remapping */,
1003 NULL
/* hv_recommend_int_remapping */,
1004 NULL
/* hv_recommend_x2apic_msrs */,
1005 NULL
/* hv_recommend_autoeoi_deprecation */,
1006 NULL
/* hv_recommend_pv_ipi */,
1007 NULL
/* hv_recommend_ex_hypercalls */,
1008 NULL
/* hv_hypervisor_is_nested */,
1009 NULL
/* hv_recommend_int_mbec */,
1010 NULL
/* hv_recommend_evmcs */,
1012 NULL
, NULL
, NULL
, NULL
,
1013 NULL
, NULL
, NULL
, NULL
,
1014 NULL
, NULL
, NULL
, NULL
,
1015 NULL
, NULL
, NULL
, NULL
,
1017 .cpuid
= { .eax
= 0x40000004, .reg
= R_EAX
, },
1019 [FEAT_HV_NESTED_EAX
] = {
1020 .type
= CPUID_FEATURE_WORD
,
1021 .cpuid
= { .eax
= 0x4000000A, .reg
= R_EAX
, },
1024 .type
= CPUID_FEATURE_WORD
,
1026 "npt", "lbrv", "svm-lock", "nrip-save",
1027 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1028 NULL
, NULL
, "pause-filter", NULL
,
1029 "pfthreshold", NULL
, NULL
, NULL
,
1030 NULL
, NULL
, NULL
, NULL
,
1031 NULL
, NULL
, NULL
, NULL
,
1032 NULL
, NULL
, NULL
, NULL
,
1033 NULL
, NULL
, NULL
, NULL
,
1035 .cpuid
= { .eax
= 0x8000000A, .reg
= R_EDX
, },
1036 .tcg_features
= TCG_SVM_FEATURES
,
1039 .type
= CPUID_FEATURE_WORD
,
1041 "fsgsbase", "tsc-adjust", NULL
, "bmi1",
1042 "hle", "avx2", NULL
, "smep",
1043 "bmi2", "erms", "invpcid", "rtm",
1044 NULL
, NULL
, "mpx", NULL
,
1045 "avx512f", "avx512dq", "rdseed", "adx",
1046 "smap", "avx512ifma", "pcommit", "clflushopt",
1047 "clwb", "intel-pt", "avx512pf", "avx512er",
1048 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
1052 .needs_ecx
= true, .ecx
= 0,
1055 .tcg_features
= TCG_7_0_EBX_FEATURES
,
1058 .type
= CPUID_FEATURE_WORD
,
1060 NULL
, "avx512vbmi", "umip", "pku",
1061 NULL
/* ospke */, "waitpkg", "avx512vbmi2", NULL
,
1062 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
1063 "avx512bitalg", NULL
, "avx512-vpopcntdq", NULL
,
1064 "la57", NULL
, NULL
, NULL
,
1065 NULL
, NULL
, "rdpid", NULL
,
1066 NULL
, "cldemote", NULL
, "movdiri",
1067 "movdir64b", NULL
, NULL
, NULL
,
1071 .needs_ecx
= true, .ecx
= 0,
1074 .tcg_features
= TCG_7_0_ECX_FEATURES
,
1077 .type
= CPUID_FEATURE_WORD
,
1079 NULL
, NULL
, "avx512-4vnniw", "avx512-4fmaps",
1080 NULL
, NULL
, NULL
, NULL
,
1081 NULL
, NULL
, "md-clear", NULL
,
1082 NULL
, NULL
, NULL
, NULL
,
1083 NULL
, NULL
, NULL
/* pconfig */, NULL
,
1084 NULL
, NULL
, NULL
, NULL
,
1085 NULL
, NULL
, "spec-ctrl", "stibp",
1086 NULL
, "arch-capabilities", "core-capability", "ssbd",
1090 .needs_ecx
= true, .ecx
= 0,
1093 .tcg_features
= TCG_7_0_EDX_FEATURES
,
1096 .type
= CPUID_FEATURE_WORD
,
1098 NULL
, NULL
, NULL
, NULL
,
1099 NULL
, "avx512-bf16", NULL
, NULL
,
1100 NULL
, NULL
, NULL
, NULL
,
1101 NULL
, NULL
, NULL
, NULL
,
1102 NULL
, NULL
, NULL
, NULL
,
1103 NULL
, NULL
, NULL
, NULL
,
1104 NULL
, NULL
, NULL
, NULL
,
1105 NULL
, NULL
, NULL
, NULL
,
1109 .needs_ecx
= true, .ecx
= 1,
1112 .tcg_features
= TCG_7_1_EAX_FEATURES
,
1114 [FEAT_8000_0007_EDX
] = {
1115 .type
= CPUID_FEATURE_WORD
,
1117 NULL
, NULL
, NULL
, NULL
,
1118 NULL
, NULL
, NULL
, NULL
,
1119 "invtsc", NULL
, NULL
, NULL
,
1120 NULL
, NULL
, NULL
, NULL
,
1121 NULL
, NULL
, NULL
, NULL
,
1122 NULL
, NULL
, NULL
, NULL
,
1123 NULL
, NULL
, NULL
, NULL
,
1124 NULL
, NULL
, NULL
, NULL
,
1126 .cpuid
= { .eax
= 0x80000007, .reg
= R_EDX
, },
1127 .tcg_features
= TCG_APM_FEATURES
,
1128 .unmigratable_flags
= CPUID_APM_INVTSC
,
1130 [FEAT_8000_0008_EBX
] = {
1131 .type
= CPUID_FEATURE_WORD
,
1133 "clzero", NULL
, "xsaveerptr", NULL
,
1134 NULL
, NULL
, NULL
, NULL
,
1135 NULL
, "wbnoinvd", NULL
, NULL
,
1136 "ibpb", NULL
, NULL
, "amd-stibp",
1137 NULL
, NULL
, NULL
, NULL
,
1138 NULL
, NULL
, NULL
, NULL
,
1139 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL
,
1140 NULL
, NULL
, NULL
, NULL
,
1142 .cpuid
= { .eax
= 0x80000008, .reg
= R_EBX
, },
1144 .unmigratable_flags
= 0,
1147 .type
= CPUID_FEATURE_WORD
,
1149 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1150 NULL
, NULL
, NULL
, NULL
,
1151 NULL
, NULL
, NULL
, NULL
,
1152 NULL
, NULL
, NULL
, NULL
,
1153 NULL
, NULL
, NULL
, NULL
,
1154 NULL
, NULL
, NULL
, NULL
,
1155 NULL
, NULL
, NULL
, NULL
,
1156 NULL
, NULL
, NULL
, NULL
,
1160 .needs_ecx
= true, .ecx
= 1,
1163 .tcg_features
= TCG_XSAVE_FEATURES
,
1166 .type
= CPUID_FEATURE_WORD
,
1168 NULL
, NULL
, "arat", NULL
,
1169 NULL
, NULL
, NULL
, NULL
,
1170 NULL
, NULL
, NULL
, NULL
,
1171 NULL
, NULL
, NULL
, NULL
,
1172 NULL
, NULL
, NULL
, NULL
,
1173 NULL
, NULL
, NULL
, NULL
,
1174 NULL
, NULL
, NULL
, NULL
,
1175 NULL
, NULL
, NULL
, NULL
,
1177 .cpuid
= { .eax
= 6, .reg
= R_EAX
, },
1178 .tcg_features
= TCG_6_EAX_FEATURES
,
1180 [FEAT_XSAVE_COMP_LO
] = {
1181 .type
= CPUID_FEATURE_WORD
,
1184 .needs_ecx
= true, .ecx
= 0,
1187 .tcg_features
= ~0U,
1188 .migratable_flags
= XSTATE_FP_MASK
| XSTATE_SSE_MASK
|
1189 XSTATE_YMM_MASK
| XSTATE_BNDREGS_MASK
| XSTATE_BNDCSR_MASK
|
1190 XSTATE_OPMASK_MASK
| XSTATE_ZMM_Hi256_MASK
| XSTATE_Hi16_ZMM_MASK
|
1193 [FEAT_XSAVE_COMP_HI
] = {
1194 .type
= CPUID_FEATURE_WORD
,
1197 .needs_ecx
= true, .ecx
= 0,
1200 .tcg_features
= ~0U,
1202 /*Below are MSR exposed features*/
1203 [FEAT_ARCH_CAPABILITIES
] = {
1204 .type
= MSR_FEATURE_WORD
,
1206 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1207 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
1208 "taa-no", NULL
, NULL
, NULL
,
1209 NULL
, NULL
, NULL
, NULL
,
1210 NULL
, NULL
, NULL
, NULL
,
1211 NULL
, NULL
, NULL
, NULL
,
1212 NULL
, NULL
, NULL
, NULL
,
1213 NULL
, NULL
, NULL
, NULL
,
1216 .index
= MSR_IA32_ARCH_CAPABILITIES
,
1219 [FEAT_CORE_CAPABILITY
] = {
1220 .type
= MSR_FEATURE_WORD
,
1222 NULL
, NULL
, NULL
, NULL
,
1223 NULL
, "split-lock-detect", NULL
, NULL
,
1224 NULL
, NULL
, NULL
, NULL
,
1225 NULL
, NULL
, NULL
, NULL
,
1226 NULL
, NULL
, NULL
, NULL
,
1227 NULL
, NULL
, NULL
, NULL
,
1228 NULL
, NULL
, NULL
, NULL
,
1229 NULL
, NULL
, NULL
, NULL
,
1232 .index
= MSR_IA32_CORE_CAPABILITY
,
1236 [FEAT_VMX_PROCBASED_CTLS
] = {
1237 .type
= MSR_FEATURE_WORD
,
1239 NULL
, NULL
, "vmx-vintr-pending", "vmx-tsc-offset",
1240 NULL
, NULL
, NULL
, "vmx-hlt-exit",
1241 NULL
, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1242 "vmx-rdtsc-exit", NULL
, NULL
, "vmx-cr3-load-noexit",
1243 "vmx-cr3-store-noexit", NULL
, NULL
, "vmx-cr8-load-exit",
1244 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1245 "vmx-io-exit", "vmx-io-bitmap", NULL
, "vmx-mtf",
1246 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1249 .index
= MSR_IA32_VMX_TRUE_PROCBASED_CTLS
,
1253 [FEAT_VMX_SECONDARY_CTLS
] = {
1254 .type
= MSR_FEATURE_WORD
,
1256 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1257 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1258 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1259 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1260 "vmx-rdseed-exit", "vmx-pml", NULL
, NULL
,
1261 "vmx-xsaves", NULL
, NULL
, NULL
,
1262 NULL
, NULL
, NULL
, NULL
,
1263 NULL
, NULL
, NULL
, NULL
,
1266 .index
= MSR_IA32_VMX_PROCBASED_CTLS2
,
1270 [FEAT_VMX_PINBASED_CTLS
] = {
1271 .type
= MSR_FEATURE_WORD
,
1273 "vmx-intr-exit", NULL
, NULL
, "vmx-nmi-exit",
1274 NULL
, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1275 NULL
, NULL
, NULL
, NULL
,
1276 NULL
, NULL
, NULL
, NULL
,
1277 NULL
, NULL
, NULL
, NULL
,
1278 NULL
, NULL
, NULL
, NULL
,
1279 NULL
, NULL
, NULL
, NULL
,
1280 NULL
, NULL
, NULL
, NULL
,
1283 .index
= MSR_IA32_VMX_TRUE_PINBASED_CTLS
,
1287 [FEAT_VMX_EXIT_CTLS
] = {
1288 .type
= MSR_FEATURE_WORD
,
1290 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1294 NULL
, NULL
, "vmx-exit-nosave-debugctl", NULL
,
1295 NULL
, NULL
, NULL
, NULL
,
1296 NULL
, NULL
/* vmx-exit-host-addr-space-size */, NULL
, NULL
,
1297 "vmx-exit-load-perf-global-ctrl", NULL
, NULL
, "vmx-exit-ack-intr",
1298 NULL
, NULL
, "vmx-exit-save-pat", "vmx-exit-load-pat",
1299 "vmx-exit-save-efer", "vmx-exit-load-efer",
1300 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1301 NULL
, "vmx-exit-clear-rtit-ctl", NULL
, NULL
,
1302 NULL
, NULL
, NULL
, NULL
,
1305 .index
= MSR_IA32_VMX_TRUE_EXIT_CTLS
,
1309 [FEAT_VMX_ENTRY_CTLS
] = {
1310 .type
= MSR_FEATURE_WORD
,
1312 NULL
, NULL
, "vmx-entry-noload-debugctl", NULL
,
1313 NULL
, NULL
, NULL
, NULL
,
1314 NULL
, "vmx-entry-ia32e-mode", NULL
, NULL
,
1315 NULL
, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1316 "vmx-entry-load-bndcfgs", NULL
, "vmx-entry-load-rtit-ctl", NULL
,
1317 NULL
, NULL
, NULL
, NULL
,
1318 NULL
, NULL
, NULL
, NULL
,
1319 NULL
, NULL
, NULL
, NULL
,
1322 .index
= MSR_IA32_VMX_TRUE_ENTRY_CTLS
,
1327 .type
= MSR_FEATURE_WORD
,
1329 NULL
, NULL
, NULL
, NULL
,
1330 NULL
, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1331 "vmx-activity-wait-sipi", NULL
, NULL
, NULL
,
1332 NULL
, NULL
, NULL
, NULL
,
1333 NULL
, NULL
, NULL
, NULL
,
1334 NULL
, NULL
, NULL
, NULL
,
1335 NULL
, NULL
, NULL
, NULL
,
1336 NULL
, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL
,
1339 .index
= MSR_IA32_VMX_MISC
,
1343 [FEAT_VMX_EPT_VPID_CAPS
] = {
1344 .type
= MSR_FEATURE_WORD
,
1346 "vmx-ept-execonly", NULL
, NULL
, NULL
,
1347 NULL
, NULL
, "vmx-page-walk-4", "vmx-page-walk-5",
1348 NULL
, NULL
, NULL
, NULL
,
1349 NULL
, NULL
, NULL
, NULL
,
1350 "vmx-ept-2mb", "vmx-ept-1gb", NULL
, NULL
,
1351 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL
,
1352 NULL
, "vmx-invept-single-context", "vmx-invept-all-context", NULL
,
1353 NULL
, NULL
, NULL
, NULL
,
1354 "vmx-invvpid", NULL
, NULL
, NULL
,
1355 NULL
, NULL
, NULL
, NULL
,
1356 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1357 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1358 NULL
, NULL
, NULL
, NULL
,
1359 NULL
, NULL
, NULL
, NULL
,
1360 NULL
, NULL
, NULL
, NULL
,
1361 NULL
, NULL
, NULL
, NULL
,
1362 NULL
, NULL
, NULL
, NULL
,
1365 .index
= MSR_IA32_VMX_EPT_VPID_CAP
,
1369 [FEAT_VMX_BASIC
] = {
1370 .type
= MSR_FEATURE_WORD
,
1372 [54] = "vmx-ins-outs",
1373 [55] = "vmx-true-ctls",
1376 .index
= MSR_IA32_VMX_BASIC
,
1378 /* Just to be safe - we don't support setting the MSEG version field. */
1379 .no_autoenable_flags
= MSR_VMX_BASIC_DUAL_MONITOR
,
1382 [FEAT_VMX_VMFUNC
] = {
1383 .type
= MSR_FEATURE_WORD
,
1385 [0] = "vmx-eptp-switching",
1388 .index
= MSR_IA32_VMX_VMFUNC
,
1394 typedef struct FeatureMask
{
1399 typedef struct FeatureDep
{
1400 FeatureMask from
, to
;
1403 static FeatureDep feature_dependencies
[] = {
1405 .from
= { FEAT_7_0_EDX
, CPUID_7_0_EDX_ARCH_CAPABILITIES
},
1406 .to
= { FEAT_ARCH_CAPABILITIES
, ~0ull },
1409 .from
= { FEAT_7_0_EDX
, CPUID_7_0_EDX_CORE_CAPABILITY
},
1410 .to
= { FEAT_CORE_CAPABILITY
, ~0ull },
1413 .from
= { FEAT_1_ECX
, CPUID_EXT_VMX
},
1414 .to
= { FEAT_VMX_PROCBASED_CTLS
, ~0ull },
1417 .from
= { FEAT_1_ECX
, CPUID_EXT_VMX
},
1418 .to
= { FEAT_VMX_PINBASED_CTLS
, ~0ull },
1421 .from
= { FEAT_1_ECX
, CPUID_EXT_VMX
},
1422 .to
= { FEAT_VMX_EXIT_CTLS
, ~0ull },
1425 .from
= { FEAT_1_ECX
, CPUID_EXT_VMX
},
1426 .to
= { FEAT_VMX_ENTRY_CTLS
, ~0ull },
1429 .from
= { FEAT_1_ECX
, CPUID_EXT_VMX
},
1430 .to
= { FEAT_VMX_MISC
, ~0ull },
1433 .from
= { FEAT_1_ECX
, CPUID_EXT_VMX
},
1434 .to
= { FEAT_VMX_BASIC
, ~0ull },
1437 .from
= { FEAT_8000_0001_EDX
, CPUID_EXT2_LM
},
1438 .to
= { FEAT_VMX_ENTRY_CTLS
, VMX_VM_ENTRY_IA32E_MODE
},
1441 .from
= { FEAT_VMX_PROCBASED_CTLS
, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
},
1442 .to
= { FEAT_VMX_SECONDARY_CTLS
, ~0ull },
1445 .from
= { FEAT_XSAVE
, CPUID_XSAVE_XSAVES
},
1446 .to
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_XSAVES
},
1449 .from
= { FEAT_1_ECX
, CPUID_EXT_RDRAND
},
1450 .to
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_RDRAND_EXITING
},
1453 .from
= { FEAT_7_0_EBX
, CPUID_7_0_EBX_INVPCID
},
1454 .to
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_ENABLE_INVPCID
},
1457 .from
= { FEAT_7_0_EBX
, CPUID_7_0_EBX_RDSEED
},
1458 .to
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_RDSEED_EXITING
},
1461 .from
= { FEAT_8000_0001_EDX
, CPUID_EXT2_RDTSCP
},
1462 .to
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_RDTSCP
},
1465 .from
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_ENABLE_EPT
},
1466 .to
= { FEAT_VMX_EPT_VPID_CAPS
, 0xffffffffull
},
1469 .from
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_ENABLE_EPT
},
1470 .to
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
},
1473 .from
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_ENABLE_VPID
},
1474 .to
= { FEAT_VMX_EPT_VPID_CAPS
, 0xffffffffull
<< 32 },
1477 .from
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_ENABLE_VMFUNC
},
1478 .to
= { FEAT_VMX_VMFUNC
, ~0ull },
1482 typedef struct X86RegisterInfo32
{
1483 /* Name of register */
1485 /* QAPI enum value register */
1486 X86CPURegister32 qapi_enum
;
1487 } X86RegisterInfo32
;
1489 #define REGISTER(reg) \
1490 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1491 static const X86RegisterInfo32 x86_reg_info_32
[CPU_NB_REGS32
] = {
1503 typedef struct ExtSaveArea
{
1504 uint32_t feature
, bits
;
1505 uint32_t offset
, size
;
1508 static const ExtSaveArea x86_ext_save_areas
[] = {
1510 /* x87 FP state component is always enabled if XSAVE is supported */
1511 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
1512 /* x87 state is in the legacy region of the XSAVE area */
1514 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
1516 [XSTATE_SSE_BIT
] = {
1517 /* SSE state component is always enabled if XSAVE is supported */
1518 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
1519 /* SSE state is in the legacy region of the XSAVE area */
1521 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
1524 { .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_AVX
,
1525 .offset
= offsetof(X86XSaveArea
, avx_state
),
1526 .size
= sizeof(XSaveAVX
) },
1527 [XSTATE_BNDREGS_BIT
] =
1528 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
1529 .offset
= offsetof(X86XSaveArea
, bndreg_state
),
1530 .size
= sizeof(XSaveBNDREG
) },
1531 [XSTATE_BNDCSR_BIT
] =
1532 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
1533 .offset
= offsetof(X86XSaveArea
, bndcsr_state
),
1534 .size
= sizeof(XSaveBNDCSR
) },
1535 [XSTATE_OPMASK_BIT
] =
1536 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
1537 .offset
= offsetof(X86XSaveArea
, opmask_state
),
1538 .size
= sizeof(XSaveOpmask
) },
1539 [XSTATE_ZMM_Hi256_BIT
] =
1540 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
1541 .offset
= offsetof(X86XSaveArea
, zmm_hi256_state
),
1542 .size
= sizeof(XSaveZMM_Hi256
) },
1543 [XSTATE_Hi16_ZMM_BIT
] =
1544 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
1545 .offset
= offsetof(X86XSaveArea
, hi16_zmm_state
),
1546 .size
= sizeof(XSaveHi16_ZMM
) },
1548 { .feature
= FEAT_7_0_ECX
, .bits
= CPUID_7_0_ECX_PKU
,
1549 .offset
= offsetof(X86XSaveArea
, pkru_state
),
1550 .size
= sizeof(XSavePKRU
) },
1553 static uint32_t xsave_area_size(uint64_t mask
)
1558 for (i
= 0; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
1559 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
1560 if ((mask
>> i
) & 1) {
1561 ret
= MAX(ret
, esa
->offset
+ esa
->size
);
1567 static inline bool accel_uses_host_cpuid(void)
1569 return kvm_enabled() || hvf_enabled();
1572 static inline uint64_t x86_cpu_xsave_components(X86CPU
*cpu
)
1574 return ((uint64_t)cpu
->env
.features
[FEAT_XSAVE_COMP_HI
]) << 32 |
1575 cpu
->env
.features
[FEAT_XSAVE_COMP_LO
];
1578 const char *get_register_name_32(unsigned int reg
)
1580 if (reg
>= CPU_NB_REGS32
) {
1583 return x86_reg_info_32
[reg
].name
;
1587 * Returns the set of feature flags that are supported and migratable by
1588 * QEMU, for a given FeatureWord.
1590 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w
)
1592 FeatureWordInfo
*wi
= &feature_word_info
[w
];
1596 for (i
= 0; i
< 64; i
++) {
1597 uint64_t f
= 1ULL << i
;
1599 /* If the feature name is known, it is implicitly considered migratable,
1600 * unless it is explicitly set in unmigratable_flags */
1601 if ((wi
->migratable_flags
& f
) ||
1602 (wi
->feat_names
[i
] && !(wi
->unmigratable_flags
& f
))) {
1609 void host_cpuid(uint32_t function
, uint32_t count
,
1610 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
1615 asm volatile("cpuid"
1616 : "=a"(vec
[0]), "=b"(vec
[1]),
1617 "=c"(vec
[2]), "=d"(vec
[3])
1618 : "0"(function
), "c"(count
) : "cc");
1619 #elif defined(__i386__)
1620 asm volatile("pusha \n\t"
1622 "mov %%eax, 0(%2) \n\t"
1623 "mov %%ebx, 4(%2) \n\t"
1624 "mov %%ecx, 8(%2) \n\t"
1625 "mov %%edx, 12(%2) \n\t"
1627 : : "a"(function
), "c"(count
), "S"(vec
)
1643 void host_vendor_fms(char *vendor
, int *family
, int *model
, int *stepping
)
1645 uint32_t eax
, ebx
, ecx
, edx
;
1647 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
1648 x86_cpu_vendor_words2str(vendor
, ebx
, edx
, ecx
);
1650 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
1652 *family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
1655 *model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
1658 *stepping
= eax
& 0x0F;
1662 /* CPU class name definitions: */
1664 /* Return type name for a given CPU model name
1665 * Caller is responsible for freeing the returned string.
1667 static char *x86_cpu_type_name(const char *model_name
)
1669 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name
);
1672 static ObjectClass
*x86_cpu_class_by_name(const char *cpu_model
)
1674 g_autofree
char *typename
= x86_cpu_type_name(cpu_model
);
1675 return object_class_by_name(typename
);
1678 static char *x86_cpu_class_get_model_name(X86CPUClass
*cc
)
1680 const char *class_name
= object_class_get_name(OBJECT_CLASS(cc
));
1681 assert(g_str_has_suffix(class_name
, X86_CPU_TYPE_SUFFIX
));
1682 return g_strndup(class_name
,
1683 strlen(class_name
) - strlen(X86_CPU_TYPE_SUFFIX
));
1686 typedef struct PropValue
{
1687 const char *prop
, *value
;
1690 typedef struct X86CPUVersionDefinition
{
1691 X86CPUVersion version
;
1695 } X86CPUVersionDefinition
;
1697 /* Base definition for a CPU model */
1698 typedef struct X86CPUDefinition
{
1702 /* vendor is zero-terminated, 12 character ASCII string */
1703 char vendor
[CPUID_VENDOR_SZ
+ 1];
1707 FeatureWordArray features
;
1708 const char *model_id
;
1709 CPUCaches
*cache_info
;
1711 * Definitions for alternative versions of CPU model.
1712 * List is terminated by item with version == 0.
1713 * If NULL, version 1 will be registered automatically.
1715 const X86CPUVersionDefinition
*versions
;
1718 /* Reference to a specific CPU model version */
1719 struct X86CPUModel
{
1720 /* Base CPU definition */
1721 X86CPUDefinition
*cpudef
;
1722 /* CPU model version */
1723 X86CPUVersion version
;
1726 * If true, this is an alias CPU model.
1727 * This matters only for "-cpu help" and query-cpu-definitions
1732 /* Get full model name for CPU version */
1733 static char *x86_cpu_versioned_model_name(X86CPUDefinition
*cpudef
,
1734 X86CPUVersion version
)
1736 assert(version
> 0);
1737 return g_strdup_printf("%s-v%d", cpudef
->name
, (int)version
);
1740 static const X86CPUVersionDefinition
*x86_cpu_def_get_versions(X86CPUDefinition
*def
)
1742 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1743 static const X86CPUVersionDefinition default_version_list
[] = {
1745 { /* end of list */ }
1748 return def
->versions
?: default_version_list
;
1751 static CPUCaches epyc_cache_info
= {
1752 .l1d_cache
= &(CPUCacheInfo
) {
1762 .no_invd_sharing
= true,
1764 .l1i_cache
= &(CPUCacheInfo
) {
1765 .type
= INSTRUCTION_CACHE
,
1774 .no_invd_sharing
= true,
1776 .l2_cache
= &(CPUCacheInfo
) {
1777 .type
= UNIFIED_CACHE
,
1786 .l3_cache
= &(CPUCacheInfo
) {
1787 .type
= UNIFIED_CACHE
,
1791 .associativity
= 16,
1797 .complex_indexing
= true,
1801 static CPUCaches epyc_rome_cache_info
= {
1802 .l1d_cache
= &(CPUCacheInfo
) {
1812 .no_invd_sharing
= true,
1814 .l1i_cache
= &(CPUCacheInfo
) {
1815 .type
= INSTRUCTION_CACHE
,
1824 .no_invd_sharing
= true,
1826 .l2_cache
= &(CPUCacheInfo
) {
1827 .type
= UNIFIED_CACHE
,
1836 .l3_cache
= &(CPUCacheInfo
) {
1837 .type
= UNIFIED_CACHE
,
1841 .associativity
= 16,
1847 .complex_indexing
= true,
1851 /* The following VMX features are not supported by KVM and are left out in the
1854 * Dual-monitor support (all processors)
1856 * Deactivate dual-monitor treatment
1857 * Number of CR3-target values
1858 * Shutdown activity state
1859 * Wait-for-SIPI activity state
1860 * PAUSE-loop exiting (Westmere and newer)
1861 * EPT-violation #VE (Broadwell and newer)
1862 * Inject event with insn length=0 (Skylake and newer)
1863 * Conceal non-root operation from PT
1864 * Conceal VM exits from PT
1865 * Conceal VM entries from PT
1866 * Enable ENCLS exiting
1867 * Mode-based execute control (XS/XU)
1868 s TSC scaling (Skylake Server and newer)
1869 * GPA translation for PT (IceLake and newer)
1870 * User wait and pause
1872 * Load IA32_RTIT_CTL
1873 * Clear IA32_RTIT_CTL
1874 * Advanced VM-exit information for EPT violations
1875 * Sub-page write permissions
1876 * PT in VMX operation
1879 static X86CPUDefinition builtin_x86_defs
[] = {
1883 .vendor
= CPUID_VENDOR_AMD
,
1887 .features
[FEAT_1_EDX
] =
1889 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
1891 .features
[FEAT_1_ECX
] =
1892 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
1893 .features
[FEAT_8000_0001_EDX
] =
1894 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1895 .features
[FEAT_8000_0001_ECX
] =
1896 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
,
1897 .xlevel
= 0x8000000A,
1898 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
1903 .vendor
= CPUID_VENDOR_AMD
,
1907 /* Missing: CPUID_HT */
1908 .features
[FEAT_1_EDX
] =
1910 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
1911 CPUID_PSE36
| CPUID_VME
,
1912 .features
[FEAT_1_ECX
] =
1913 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
1915 .features
[FEAT_8000_0001_EDX
] =
1916 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
1917 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
1918 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
1919 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1921 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1922 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
1923 .features
[FEAT_8000_0001_ECX
] =
1924 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
1925 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
1926 /* Missing: CPUID_SVM_LBRV */
1927 .features
[FEAT_SVM
] =
1929 .xlevel
= 0x8000001A,
1930 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
1935 .vendor
= CPUID_VENDOR_INTEL
,
1939 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1940 .features
[FEAT_1_EDX
] =
1942 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
1943 CPUID_PSE36
| CPUID_VME
| CPUID_ACPI
| CPUID_SS
,
1944 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
1945 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
1946 .features
[FEAT_1_ECX
] =
1947 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
1949 .features
[FEAT_8000_0001_EDX
] =
1950 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1951 .features
[FEAT_8000_0001_ECX
] =
1953 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
,
1954 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
,
1955 .features
[FEAT_VMX_EXIT_CTLS
] = VMX_VM_EXIT_ACK_INTR_ON_EXIT
,
1956 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
1957 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
1958 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
,
1959 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
1960 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
1961 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
1962 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
1963 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
1964 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
1965 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
1966 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
1967 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
1968 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
1969 .features
[FEAT_VMX_SECONDARY_CTLS
] =
1970 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
,
1971 .xlevel
= 0x80000008,
1972 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1977 .vendor
= CPUID_VENDOR_INTEL
,
1981 /* Missing: CPUID_HT */
1982 .features
[FEAT_1_EDX
] =
1983 PPRO_FEATURES
| CPUID_VME
|
1984 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
1986 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
1987 .features
[FEAT_1_ECX
] =
1988 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
1989 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
1990 .features
[FEAT_8000_0001_EDX
] =
1991 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1992 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1993 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1994 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1995 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
1996 .features
[FEAT_8000_0001_ECX
] =
1998 /* VMX features from Cedar Mill/Prescott */
1999 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
,
2000 .features
[FEAT_VMX_EXIT_CTLS
] = VMX_VM_EXIT_ACK_INTR_ON_EXIT
,
2001 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2002 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2003 VMX_PIN_BASED_NMI_EXITING
,
2004 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2005 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2006 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2007 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2008 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2009 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2010 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2011 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
,
2012 .xlevel
= 0x80000008,
2013 .model_id
= "Common KVM processor"
2018 .vendor
= CPUID_VENDOR_INTEL
,
2022 .features
[FEAT_1_EDX
] =
2024 .features
[FEAT_1_ECX
] =
2026 .xlevel
= 0x80000004,
2027 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
2032 .vendor
= CPUID_VENDOR_INTEL
,
2036 .features
[FEAT_1_EDX
] =
2037 PPRO_FEATURES
| CPUID_VME
|
2038 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
2039 .features
[FEAT_1_ECX
] =
2041 .features
[FEAT_8000_0001_ECX
] =
2043 /* VMX features from Yonah */
2044 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
,
2045 .features
[FEAT_VMX_EXIT_CTLS
] = VMX_VM_EXIT_ACK_INTR_ON_EXIT
,
2046 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2047 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2048 VMX_PIN_BASED_NMI_EXITING
,
2049 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2050 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2051 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2052 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2053 VMX_CPU_BASED_MOV_DR_EXITING
| VMX_CPU_BASED_UNCOND_IO_EXITING
|
2054 VMX_CPU_BASED_USE_IO_BITMAPS
| VMX_CPU_BASED_MONITOR_EXITING
|
2055 VMX_CPU_BASED_PAUSE_EXITING
| VMX_CPU_BASED_USE_MSR_BITMAPS
,
2056 .xlevel
= 0x80000008,
2057 .model_id
= "Common 32-bit KVM processor"
2062 .vendor
= CPUID_VENDOR_INTEL
,
2066 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2067 .features
[FEAT_1_EDX
] =
2068 PPRO_FEATURES
| CPUID_VME
|
2069 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_ACPI
|
2071 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
2072 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
2073 .features
[FEAT_1_ECX
] =
2074 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
,
2075 .features
[FEAT_8000_0001_EDX
] =
2077 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
,
2078 .features
[FEAT_VMX_EXIT_CTLS
] = VMX_VM_EXIT_ACK_INTR_ON_EXIT
,
2079 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2080 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2081 VMX_PIN_BASED_NMI_EXITING
,
2082 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2083 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2084 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2085 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2086 VMX_CPU_BASED_MOV_DR_EXITING
| VMX_CPU_BASED_UNCOND_IO_EXITING
|
2087 VMX_CPU_BASED_USE_IO_BITMAPS
| VMX_CPU_BASED_MONITOR_EXITING
|
2088 VMX_CPU_BASED_PAUSE_EXITING
| VMX_CPU_BASED_USE_MSR_BITMAPS
,
2089 .xlevel
= 0x80000008,
2090 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
2095 .vendor
= CPUID_VENDOR_INTEL
,
2099 .features
[FEAT_1_EDX
] =
2107 .vendor
= CPUID_VENDOR_INTEL
,
2111 .features
[FEAT_1_EDX
] =
2119 .vendor
= CPUID_VENDOR_INTEL
,
2123 .features
[FEAT_1_EDX
] =
2131 .vendor
= CPUID_VENDOR_INTEL
,
2135 .features
[FEAT_1_EDX
] =
2143 .vendor
= CPUID_VENDOR_AMD
,
2147 .features
[FEAT_1_EDX
] =
2148 PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
|
2150 .features
[FEAT_8000_0001_EDX
] =
2151 CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
2152 .xlevel
= 0x80000008,
2153 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
2158 .vendor
= CPUID_VENDOR_INTEL
,
2162 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2163 .features
[FEAT_1_EDX
] =
2165 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
|
2166 CPUID_ACPI
| CPUID_SS
,
2167 /* Some CPUs got no CPUID_SEP */
2168 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2170 .features
[FEAT_1_ECX
] =
2171 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
2173 .features
[FEAT_8000_0001_EDX
] =
2175 .features
[FEAT_8000_0001_ECX
] =
2177 .xlevel
= 0x80000008,
2178 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2183 .vendor
= CPUID_VENDOR_INTEL
,
2187 .features
[FEAT_1_EDX
] =
2188 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2189 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2190 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2191 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2192 CPUID_DE
| CPUID_FP87
,
2193 .features
[FEAT_1_ECX
] =
2194 CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
2195 .features
[FEAT_8000_0001_EDX
] =
2196 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2197 .features
[FEAT_8000_0001_ECX
] =
2199 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
,
2200 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
,
2201 .features
[FEAT_VMX_EXIT_CTLS
] = VMX_VM_EXIT_ACK_INTR_ON_EXIT
,
2202 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2203 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2204 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
,
2205 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2206 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2207 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2208 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2209 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2210 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2211 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2212 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2213 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2214 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2215 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2216 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
,
2217 .xlevel
= 0x80000008,
2218 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2223 .vendor
= CPUID_VENDOR_INTEL
,
2227 .features
[FEAT_1_EDX
] =
2228 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2229 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2230 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2231 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2232 CPUID_DE
| CPUID_FP87
,
2233 .features
[FEAT_1_ECX
] =
2234 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2236 .features
[FEAT_8000_0001_EDX
] =
2237 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2238 .features
[FEAT_8000_0001_ECX
] =
2240 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
,
2241 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2242 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
2243 .features
[FEAT_VMX_EXIT_CTLS
] = VMX_VM_EXIT_ACK_INTR_ON_EXIT
|
2244 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
2245 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2246 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2247 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
,
2248 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2249 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2250 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2251 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2252 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2253 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2254 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2255 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2256 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2257 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2258 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2259 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2260 VMX_SECONDARY_EXEC_WBINVD_EXITING
,
2261 .xlevel
= 0x80000008,
2262 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2267 .vendor
= CPUID_VENDOR_INTEL
,
2271 .features
[FEAT_1_EDX
] =
2272 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2273 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2274 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2275 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2276 CPUID_DE
| CPUID_FP87
,
2277 .features
[FEAT_1_ECX
] =
2278 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
2279 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
2280 .features
[FEAT_8000_0001_EDX
] =
2281 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
2282 .features
[FEAT_8000_0001_ECX
] =
2284 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
2285 MSR_VMX_BASIC_TRUE_CTLS
,
2286 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2287 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
2288 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
2289 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
2290 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
2291 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
2292 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
2293 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
2294 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
2295 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
,
2296 .features
[FEAT_VMX_EXIT_CTLS
] =
2297 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
2298 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2299 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
2300 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
2301 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
2302 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2303 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2304 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
2305 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
,
2306 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2307 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2308 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2309 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2310 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2311 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2312 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2313 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2314 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2315 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
2316 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
2317 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2318 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2319 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2320 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
2321 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
2322 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2323 VMX_SECONDARY_EXEC_ENABLE_VPID
,
2324 .xlevel
= 0x80000008,
2325 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
2326 .versions
= (X86CPUVersionDefinition
[]) {
2330 .alias
= "Nehalem-IBRS",
2331 .props
= (PropValue
[]) {
2332 { "spec-ctrl", "on" },
2334 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2335 { /* end of list */ }
2338 { /* end of list */ }
2344 .vendor
= CPUID_VENDOR_INTEL
,
2348 .features
[FEAT_1_EDX
] =
2349 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2350 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2351 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2352 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2353 CPUID_DE
| CPUID_FP87
,
2354 .features
[FEAT_1_ECX
] =
2355 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
2356 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2357 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
2358 .features
[FEAT_8000_0001_EDX
] =
2359 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
2360 .features
[FEAT_8000_0001_ECX
] =
2362 .features
[FEAT_6_EAX
] =
2364 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
2365 MSR_VMX_BASIC_TRUE_CTLS
,
2366 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2367 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
2368 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
2369 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
2370 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
2371 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
2372 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
2373 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
2374 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
2375 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
,
2376 .features
[FEAT_VMX_EXIT_CTLS
] =
2377 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
2378 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2379 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
2380 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
2381 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
2382 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
2383 MSR_VMX_MISC_STORE_LMA
,
2384 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2385 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
2386 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
,
2387 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2388 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2389 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2390 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2391 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2392 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2393 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2394 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2395 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2396 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
2397 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
2398 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2399 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2400 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2401 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
2402 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
2403 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2404 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
,
2405 .xlevel
= 0x80000008,
2406 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
2407 .versions
= (X86CPUVersionDefinition
[]) {
2411 .alias
= "Westmere-IBRS",
2412 .props
= (PropValue
[]) {
2413 { "spec-ctrl", "on" },
2415 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2416 { /* end of list */ }
2419 { /* end of list */ }
2423 .name
= "SandyBridge",
2425 .vendor
= CPUID_VENDOR_INTEL
,
2429 .features
[FEAT_1_EDX
] =
2430 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2431 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2432 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2433 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2434 CPUID_DE
| CPUID_FP87
,
2435 .features
[FEAT_1_ECX
] =
2436 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2437 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
2438 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
2439 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
2441 .features
[FEAT_8000_0001_EDX
] =
2442 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2444 .features
[FEAT_8000_0001_ECX
] =
2446 .features
[FEAT_XSAVE
] =
2447 CPUID_XSAVE_XSAVEOPT
,
2448 .features
[FEAT_6_EAX
] =
2450 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
2451 MSR_VMX_BASIC_TRUE_CTLS
,
2452 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2453 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
2454 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
2455 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
2456 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
2457 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
2458 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
2459 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
2460 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
2461 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
,
2462 .features
[FEAT_VMX_EXIT_CTLS
] =
2463 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
2464 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2465 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
2466 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
2467 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
2468 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
2469 MSR_VMX_MISC_STORE_LMA
,
2470 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2471 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
2472 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
,
2473 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2474 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2475 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2476 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2477 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2478 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2479 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2480 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2481 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2482 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
2483 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
2484 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2485 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2486 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2487 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
2488 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
2489 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2490 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
,
2491 .xlevel
= 0x80000008,
2492 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
2493 .versions
= (X86CPUVersionDefinition
[]) {
2497 .alias
= "SandyBridge-IBRS",
2498 .props
= (PropValue
[]) {
2499 { "spec-ctrl", "on" },
2501 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2502 { /* end of list */ }
2505 { /* end of list */ }
2509 .name
= "IvyBridge",
2511 .vendor
= CPUID_VENDOR_INTEL
,
2515 .features
[FEAT_1_EDX
] =
2516 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2517 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2518 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2519 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2520 CPUID_DE
| CPUID_FP87
,
2521 .features
[FEAT_1_ECX
] =
2522 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2523 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
2524 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
2525 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
2526 CPUID_EXT_SSE3
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2527 .features
[FEAT_7_0_EBX
] =
2528 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_SMEP
|
2530 .features
[FEAT_8000_0001_EDX
] =
2531 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2533 .features
[FEAT_8000_0001_ECX
] =
2535 .features
[FEAT_XSAVE
] =
2536 CPUID_XSAVE_XSAVEOPT
,
2537 .features
[FEAT_6_EAX
] =
2539 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
2540 MSR_VMX_BASIC_TRUE_CTLS
,
2541 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2542 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
2543 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
2544 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
2545 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
2546 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
2547 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
2548 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
2549 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
2550 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
,
2551 .features
[FEAT_VMX_EXIT_CTLS
] =
2552 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
2553 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2554 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
2555 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
2556 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
2557 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
2558 MSR_VMX_MISC_STORE_LMA
,
2559 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2560 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
2561 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
2562 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2563 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2564 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2565 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2566 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2567 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2568 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2569 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2570 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2571 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
2572 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
2573 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2574 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2575 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2576 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
2577 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
2578 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2579 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2580 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2581 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2582 VMX_SECONDARY_EXEC_RDRAND_EXITING
,
2583 .xlevel
= 0x80000008,
2584 .model_id
= "Intel Xeon E3-12xx v2 (Ivy Bridge)",
2585 .versions
= (X86CPUVersionDefinition
[]) {
2589 .alias
= "IvyBridge-IBRS",
2590 .props
= (PropValue
[]) {
2591 { "spec-ctrl", "on" },
2593 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2594 { /* end of list */ }
2597 { /* end of list */ }
2603 .vendor
= CPUID_VENDOR_INTEL
,
2607 .features
[FEAT_1_EDX
] =
2608 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2609 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2610 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2611 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2612 CPUID_DE
| CPUID_FP87
,
2613 .features
[FEAT_1_ECX
] =
2614 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2615 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2616 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2617 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2618 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2619 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2620 .features
[FEAT_8000_0001_EDX
] =
2621 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2623 .features
[FEAT_8000_0001_ECX
] =
2624 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
2625 .features
[FEAT_7_0_EBX
] =
2626 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2627 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2628 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2630 .features
[FEAT_XSAVE
] =
2631 CPUID_XSAVE_XSAVEOPT
,
2632 .features
[FEAT_6_EAX
] =
2634 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
2635 MSR_VMX_BASIC_TRUE_CTLS
,
2636 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2637 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
2638 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
2639 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
2640 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
2641 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
2642 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
2643 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
2644 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
2645 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
2646 .features
[FEAT_VMX_EXIT_CTLS
] =
2647 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
2648 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2649 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
2650 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
2651 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
2652 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
2653 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
2654 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2655 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
2656 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
2657 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2658 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2659 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2660 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2661 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2662 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2663 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2664 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2665 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2666 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
2667 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
2668 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2669 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2670 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2671 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
2672 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
2673 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2674 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2675 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2676 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2677 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
2678 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
,
2679 .features
[FEAT_VMX_VMFUNC
] = MSR_VMX_VMFUNC_EPT_SWITCHING
,
2680 .xlevel
= 0x80000008,
2681 .model_id
= "Intel Core Processor (Haswell)",
2682 .versions
= (X86CPUVersionDefinition
[]) {
2686 .alias
= "Haswell-noTSX",
2687 .props
= (PropValue
[]) {
2690 { "stepping", "1" },
2691 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2692 { /* end of list */ }
2697 .alias
= "Haswell-IBRS",
2698 .props
= (PropValue
[]) {
2699 /* Restore TSX features removed by -v2 above */
2703 * Haswell and Haswell-IBRS had stepping=4 in
2704 * QEMU 4.0 and older
2706 { "stepping", "4" },
2707 { "spec-ctrl", "on" },
2709 "Intel Core Processor (Haswell, IBRS)" },
2710 { /* end of list */ }
2715 .alias
= "Haswell-noTSX-IBRS",
2716 .props
= (PropValue
[]) {
2719 /* spec-ctrl was already enabled by -v3 above */
2720 { "stepping", "1" },
2722 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2723 { /* end of list */ }
2726 { /* end of list */ }
2730 .name
= "Broadwell",
2732 .vendor
= CPUID_VENDOR_INTEL
,
2736 .features
[FEAT_1_EDX
] =
2737 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2738 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2739 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2740 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2741 CPUID_DE
| CPUID_FP87
,
2742 .features
[FEAT_1_ECX
] =
2743 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2744 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2745 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2746 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2747 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2748 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2749 .features
[FEAT_8000_0001_EDX
] =
2750 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2752 .features
[FEAT_8000_0001_ECX
] =
2753 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2754 .features
[FEAT_7_0_EBX
] =
2755 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2756 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2757 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2758 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2760 .features
[FEAT_XSAVE
] =
2761 CPUID_XSAVE_XSAVEOPT
,
2762 .features
[FEAT_6_EAX
] =
2764 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
2765 MSR_VMX_BASIC_TRUE_CTLS
,
2766 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2767 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
2768 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
2769 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
2770 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
2771 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
2772 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
2773 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
2774 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
2775 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
2776 .features
[FEAT_VMX_EXIT_CTLS
] =
2777 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
2778 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2779 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
2780 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
2781 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
2782 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
2783 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
2784 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2785 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
2786 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
2787 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2788 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2789 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2790 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2791 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2792 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2793 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2794 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2795 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2796 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
2797 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
2798 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2799 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2800 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2801 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
2802 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
2803 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2804 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2805 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2806 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2807 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
2808 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
2809 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
2810 .features
[FEAT_VMX_VMFUNC
] = MSR_VMX_VMFUNC_EPT_SWITCHING
,
2811 .xlevel
= 0x80000008,
2812 .model_id
= "Intel Core Processor (Broadwell)",
2813 .versions
= (X86CPUVersionDefinition
[]) {
2817 .alias
= "Broadwell-noTSX",
2818 .props
= (PropValue
[]) {
2821 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2822 { /* end of list */ }
2827 .alias
= "Broadwell-IBRS",
2828 .props
= (PropValue
[]) {
2829 /* Restore TSX features removed by -v2 above */
2832 { "spec-ctrl", "on" },
2834 "Intel Core Processor (Broadwell, IBRS)" },
2835 { /* end of list */ }
2840 .alias
= "Broadwell-noTSX-IBRS",
2841 .props
= (PropValue
[]) {
2844 /* spec-ctrl was already enabled by -v3 above */
2846 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2847 { /* end of list */ }
2850 { /* end of list */ }
2854 .name
= "Skylake-Client",
2856 .vendor
= CPUID_VENDOR_INTEL
,
2860 .features
[FEAT_1_EDX
] =
2861 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2862 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2863 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2864 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2865 CPUID_DE
| CPUID_FP87
,
2866 .features
[FEAT_1_ECX
] =
2867 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2868 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2869 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2870 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2871 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2872 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2873 .features
[FEAT_8000_0001_EDX
] =
2874 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2876 .features
[FEAT_8000_0001_ECX
] =
2877 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2878 .features
[FEAT_7_0_EBX
] =
2879 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2880 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2881 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2882 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2884 /* Missing: XSAVES (not supported by some Linux versions,
2885 * including v4.1 to v4.12).
2886 * KVM doesn't yet expose any XSAVES state save component,
2887 * and the only one defined in Skylake (processor tracing)
2888 * probably will block migration anyway.
2890 .features
[FEAT_XSAVE
] =
2891 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2892 CPUID_XSAVE_XGETBV1
,
2893 .features
[FEAT_6_EAX
] =
2895 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2896 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
2897 MSR_VMX_BASIC_TRUE_CTLS
,
2898 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2899 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
2900 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
2901 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
2902 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
2903 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
2904 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
2905 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
2906 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
2907 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
2908 .features
[FEAT_VMX_EXIT_CTLS
] =
2909 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
2910 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2911 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
2912 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
2913 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
2914 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
2915 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
2916 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2917 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
2918 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
,
2919 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2920 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2921 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2922 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2923 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2924 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2925 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2926 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2927 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2928 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
2929 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
2930 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2931 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2932 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2933 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
2934 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
2935 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2936 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
2937 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
2938 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
2939 .features
[FEAT_VMX_VMFUNC
] = MSR_VMX_VMFUNC_EPT_SWITCHING
,
2940 .xlevel
= 0x80000008,
2941 .model_id
= "Intel Core Processor (Skylake)",
2942 .versions
= (X86CPUVersionDefinition
[]) {
2946 .alias
= "Skylake-Client-IBRS",
2947 .props
= (PropValue
[]) {
2948 { "spec-ctrl", "on" },
2950 "Intel Core Processor (Skylake, IBRS)" },
2951 { /* end of list */ }
2956 .alias
= "Skylake-Client-noTSX-IBRS",
2957 .props
= (PropValue
[]) {
2961 "Intel Core Processor (Skylake, IBRS, no TSX)" },
2962 { /* end of list */ }
2965 { /* end of list */ }
2969 .name
= "Skylake-Server",
2971 .vendor
= CPUID_VENDOR_INTEL
,
2975 .features
[FEAT_1_EDX
] =
2976 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2977 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2978 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2979 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2980 CPUID_DE
| CPUID_FP87
,
2981 .features
[FEAT_1_ECX
] =
2982 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2983 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2984 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2985 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2986 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2987 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2988 .features
[FEAT_8000_0001_EDX
] =
2989 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
2990 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2991 .features
[FEAT_8000_0001_ECX
] =
2992 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2993 .features
[FEAT_7_0_EBX
] =
2994 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2995 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2996 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2997 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2998 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
2999 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
3000 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
3001 CPUID_7_0_EBX_AVX512VL
| CPUID_7_0_EBX_CLFLUSHOPT
,
3002 .features
[FEAT_7_0_ECX
] =
3004 /* Missing: XSAVES (not supported by some Linux versions,
3005 * including v4.1 to v4.12).
3006 * KVM doesn't yet expose any XSAVES state save component,
3007 * and the only one defined in Skylake (processor tracing)
3008 * probably will block migration anyway.
3010 .features
[FEAT_XSAVE
] =
3011 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3012 CPUID_XSAVE_XGETBV1
,
3013 .features
[FEAT_6_EAX
] =
3015 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3016 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
3017 MSR_VMX_BASIC_TRUE_CTLS
,
3018 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
3019 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
3020 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3021 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
3022 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
3023 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
3024 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3025 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3026 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3027 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
3028 .features
[FEAT_VMX_EXIT_CTLS
] =
3029 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3030 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3031 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
3032 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3033 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3034 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
3035 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
3036 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
3037 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
3038 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
3039 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3040 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3041 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3042 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3043 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3044 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3045 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3046 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3047 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3048 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3049 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3050 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3051 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3052 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3053 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3054 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3055 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3056 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3057 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3058 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3059 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3060 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3061 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
3062 .xlevel
= 0x80000008,
3063 .model_id
= "Intel Xeon Processor (Skylake)",
3064 .versions
= (X86CPUVersionDefinition
[]) {
3068 .alias
= "Skylake-Server-IBRS",
3069 .props
= (PropValue
[]) {
3070 /* clflushopt was not added to Skylake-Server-IBRS */
3071 /* TODO: add -v3 including clflushopt */
3072 { "clflushopt", "off" },
3073 { "spec-ctrl", "on" },
3075 "Intel Xeon Processor (Skylake, IBRS)" },
3076 { /* end of list */ }
3081 .alias
= "Skylake-Server-noTSX-IBRS",
3082 .props
= (PropValue
[]) {
3086 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
3087 { /* end of list */ }
3090 { /* end of list */ }
3094 .name
= "Cascadelake-Server",
3096 .vendor
= CPUID_VENDOR_INTEL
,
3100 .features
[FEAT_1_EDX
] =
3101 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
3102 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
3103 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
3104 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
3105 CPUID_DE
| CPUID_FP87
,
3106 .features
[FEAT_1_ECX
] =
3107 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
3108 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
3109 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
3110 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
3111 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
3112 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
3113 .features
[FEAT_8000_0001_EDX
] =
3114 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
3115 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
3116 .features
[FEAT_8000_0001_ECX
] =
3117 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
3118 .features
[FEAT_7_0_EBX
] =
3119 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
3120 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
3121 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
3122 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
3123 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
3124 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
3125 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
3126 CPUID_7_0_EBX_AVX512VL
| CPUID_7_0_EBX_CLFLUSHOPT
,
3127 .features
[FEAT_7_0_ECX
] =
3129 CPUID_7_0_ECX_AVX512VNNI
,
3130 .features
[FEAT_7_0_EDX
] =
3131 CPUID_7_0_EDX_SPEC_CTRL
| CPUID_7_0_EDX_SPEC_CTRL_SSBD
,
3132 /* Missing: XSAVES (not supported by some Linux versions,
3133 * including v4.1 to v4.12).
3134 * KVM doesn't yet expose any XSAVES state save component,
3135 * and the only one defined in Skylake (processor tracing)
3136 * probably will block migration anyway.
3138 .features
[FEAT_XSAVE
] =
3139 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3140 CPUID_XSAVE_XGETBV1
,
3141 .features
[FEAT_6_EAX
] =
3143 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3144 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
3145 MSR_VMX_BASIC_TRUE_CTLS
,
3146 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
3147 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
3148 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3149 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
3150 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
3151 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
3152 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3153 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3154 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3155 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
3156 .features
[FEAT_VMX_EXIT_CTLS
] =
3157 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3158 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3159 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
3160 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3161 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3162 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
3163 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
3164 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
3165 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
3166 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
3167 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3168 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3169 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3170 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3171 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3172 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3173 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3174 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3175 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3176 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3177 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3178 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3179 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3180 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3181 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3182 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3183 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3184 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3185 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3186 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3187 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3188 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3189 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
3190 .xlevel
= 0x80000008,
3191 .model_id
= "Intel Xeon Processor (Cascadelake)",
3192 .versions
= (X86CPUVersionDefinition
[]) {
3195 .props
= (PropValue
[]) {
3196 { "arch-capabilities", "on" },
3197 { "rdctl-no", "on" },
3198 { "ibrs-all", "on" },
3199 { "skip-l1dfl-vmentry", "on" },
3201 { /* end of list */ }
3205 .alias
= "Cascadelake-Server-noTSX",
3206 .props
= (PropValue
[]) {
3209 { /* end of list */ }
3212 { /* end of list */ }
3216 .name
= "Cooperlake",
3218 .vendor
= CPUID_VENDOR_INTEL
,
3222 .features
[FEAT_1_EDX
] =
3223 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
3224 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
3225 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
3226 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
3227 CPUID_DE
| CPUID_FP87
,
3228 .features
[FEAT_1_ECX
] =
3229 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
3230 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
3231 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
3232 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
3233 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
3234 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
3235 .features
[FEAT_8000_0001_EDX
] =
3236 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
3237 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
3238 .features
[FEAT_8000_0001_ECX
] =
3239 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
3240 .features
[FEAT_7_0_EBX
] =
3241 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
3242 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
3243 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
3244 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
3245 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
3246 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
3247 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
3248 CPUID_7_0_EBX_AVX512VL
| CPUID_7_0_EBX_CLFLUSHOPT
,
3249 .features
[FEAT_7_0_ECX
] =
3251 CPUID_7_0_ECX_AVX512VNNI
,
3252 .features
[FEAT_7_0_EDX
] =
3253 CPUID_7_0_EDX_SPEC_CTRL
| CPUID_7_0_EDX_STIBP
|
3254 CPUID_7_0_EDX_SPEC_CTRL_SSBD
| CPUID_7_0_EDX_ARCH_CAPABILITIES
,
3255 .features
[FEAT_ARCH_CAPABILITIES
] =
3256 MSR_ARCH_CAP_RDCL_NO
| MSR_ARCH_CAP_IBRS_ALL
|
3257 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY
| MSR_ARCH_CAP_MDS_NO
|
3258 MSR_ARCH_CAP_PSCHANGE_MC_NO
| MSR_ARCH_CAP_TAA_NO
,
3259 .features
[FEAT_7_1_EAX
] =
3260 CPUID_7_1_EAX_AVX512_BF16
,
3262 * Missing: XSAVES (not supported by some Linux versions,
3263 * including v4.1 to v4.12).
3264 * KVM doesn't yet expose any XSAVES state save component,
3265 * and the only one defined in Skylake (processor tracing)
3266 * probably will block migration anyway.
3268 .features
[FEAT_XSAVE
] =
3269 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3270 CPUID_XSAVE_XGETBV1
,
3271 .features
[FEAT_6_EAX
] =
3273 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3274 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
3275 MSR_VMX_BASIC_TRUE_CTLS
,
3276 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
3277 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
3278 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3279 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
3280 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
3281 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
3282 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3283 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3284 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3285 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
3286 .features
[FEAT_VMX_EXIT_CTLS
] =
3287 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3288 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3289 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
3290 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3291 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3292 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
3293 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
3294 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
3295 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
3296 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
3297 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3298 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3299 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3300 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3301 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3302 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3303 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3304 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3305 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3306 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3307 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3308 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3309 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3310 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3311 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3312 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3313 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3314 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3315 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3316 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3317 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3318 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3319 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
3320 .features
[FEAT_VMX_VMFUNC
] = MSR_VMX_VMFUNC_EPT_SWITCHING
,
3321 .xlevel
= 0x80000008,
3322 .model_id
= "Intel Xeon Processor (Cooperlake)",
3325 .name
= "Icelake-Client",
3327 .vendor
= CPUID_VENDOR_INTEL
,
3331 .features
[FEAT_1_EDX
] =
3332 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
3333 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
3334 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
3335 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
3336 CPUID_DE
| CPUID_FP87
,
3337 .features
[FEAT_1_ECX
] =
3338 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
3339 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
3340 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
3341 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
3342 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
3343 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
3344 .features
[FEAT_8000_0001_EDX
] =
3345 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
3347 .features
[FEAT_8000_0001_ECX
] =
3348 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
3349 .features
[FEAT_8000_0008_EBX
] =
3350 CPUID_8000_0008_EBX_WBNOINVD
,
3351 .features
[FEAT_7_0_EBX
] =
3352 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
3353 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
3354 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
3355 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
3357 .features
[FEAT_7_0_ECX
] =
3358 CPUID_7_0_ECX_AVX512_VBMI
| CPUID_7_0_ECX_UMIP
| CPUID_7_0_ECX_PKU
|
3359 CPUID_7_0_ECX_AVX512_VBMI2
| CPUID_7_0_ECX_GFNI
|
3360 CPUID_7_0_ECX_VAES
| CPUID_7_0_ECX_VPCLMULQDQ
|
3361 CPUID_7_0_ECX_AVX512VNNI
| CPUID_7_0_ECX_AVX512BITALG
|
3362 CPUID_7_0_ECX_AVX512_VPOPCNTDQ
,
3363 .features
[FEAT_7_0_EDX
] =
3364 CPUID_7_0_EDX_SPEC_CTRL
| CPUID_7_0_EDX_SPEC_CTRL_SSBD
,
3365 /* Missing: XSAVES (not supported by some Linux versions,
3366 * including v4.1 to v4.12).
3367 * KVM doesn't yet expose any XSAVES state save component,
3368 * and the only one defined in Skylake (processor tracing)
3369 * probably will block migration anyway.
3371 .features
[FEAT_XSAVE
] =
3372 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3373 CPUID_XSAVE_XGETBV1
,
3374 .features
[FEAT_6_EAX
] =
3376 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3377 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
3378 MSR_VMX_BASIC_TRUE_CTLS
,
3379 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
3380 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
3381 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3382 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
3383 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
3384 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
3385 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3386 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3387 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3388 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
3389 .features
[FEAT_VMX_EXIT_CTLS
] =
3390 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3391 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3392 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
3393 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3394 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3395 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
3396 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
3397 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
3398 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
3399 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
,
3400 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3401 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3402 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3403 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3404 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3405 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3406 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3407 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3408 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3409 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3410 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3411 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3412 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3413 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3414 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3415 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3416 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3417 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3418 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3419 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
3420 .features
[FEAT_VMX_VMFUNC
] = MSR_VMX_VMFUNC_EPT_SWITCHING
,
3421 .xlevel
= 0x80000008,
3422 .model_id
= "Intel Core Processor (Icelake)",
3423 .versions
= (X86CPUVersionDefinition
[]) {
3427 .alias
= "Icelake-Client-noTSX",
3428 .props
= (PropValue
[]) {
3431 { /* end of list */ }
3434 { /* end of list */ }
3438 .name
= "Icelake-Server",
3440 .vendor
= CPUID_VENDOR_INTEL
,
3444 .features
[FEAT_1_EDX
] =
3445 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
3446 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
3447 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
3448 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
3449 CPUID_DE
| CPUID_FP87
,
3450 .features
[FEAT_1_ECX
] =
3451 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
3452 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
3453 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
3454 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
3455 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
3456 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
3457 .features
[FEAT_8000_0001_EDX
] =
3458 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
3459 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
3460 .features
[FEAT_8000_0001_ECX
] =
3461 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
3462 .features
[FEAT_8000_0008_EBX
] =
3463 CPUID_8000_0008_EBX_WBNOINVD
,
3464 .features
[FEAT_7_0_EBX
] =
3465 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
3466 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
3467 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
3468 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
3469 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
3470 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
3471 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
3472 CPUID_7_0_EBX_AVX512VL
| CPUID_7_0_EBX_CLFLUSHOPT
,
3473 .features
[FEAT_7_0_ECX
] =
3474 CPUID_7_0_ECX_AVX512_VBMI
| CPUID_7_0_ECX_UMIP
| CPUID_7_0_ECX_PKU
|
3475 CPUID_7_0_ECX_AVX512_VBMI2
| CPUID_7_0_ECX_GFNI
|
3476 CPUID_7_0_ECX_VAES
| CPUID_7_0_ECX_VPCLMULQDQ
|
3477 CPUID_7_0_ECX_AVX512VNNI
| CPUID_7_0_ECX_AVX512BITALG
|
3478 CPUID_7_0_ECX_AVX512_VPOPCNTDQ
| CPUID_7_0_ECX_LA57
,
3479 .features
[FEAT_7_0_EDX
] =
3480 CPUID_7_0_EDX_SPEC_CTRL
| CPUID_7_0_EDX_SPEC_CTRL_SSBD
,
3481 /* Missing: XSAVES (not supported by some Linux versions,
3482 * including v4.1 to v4.12).
3483 * KVM doesn't yet expose any XSAVES state save component,
3484 * and the only one defined in Skylake (processor tracing)
3485 * probably will block migration anyway.
3487 .features
[FEAT_XSAVE
] =
3488 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3489 CPUID_XSAVE_XGETBV1
,
3490 .features
[FEAT_6_EAX
] =
3492 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3493 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
3494 MSR_VMX_BASIC_TRUE_CTLS
,
3495 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
3496 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
3497 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3498 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
3499 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
3500 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
3501 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3502 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3503 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3504 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
3505 .features
[FEAT_VMX_EXIT_CTLS
] =
3506 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3507 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3508 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
3509 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3510 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3511 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
3512 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
3513 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
3514 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
3515 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
3516 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3517 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3518 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3519 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3520 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3521 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3522 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3523 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3524 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3525 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3526 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3527 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3528 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3529 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3530 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3531 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3532 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3533 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3534 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3535 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3536 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3537 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
,
3538 .xlevel
= 0x80000008,
3539 .model_id
= "Intel Xeon Processor (Icelake)",
3540 .versions
= (X86CPUVersionDefinition
[]) {
3544 .alias
= "Icelake-Server-noTSX",
3545 .props
= (PropValue
[]) {
3548 { /* end of list */ }
3551 { /* end of list */ }
3555 .name
= "Denverton",
3557 .vendor
= CPUID_VENDOR_INTEL
,
3561 .features
[FEAT_1_EDX
] =
3562 CPUID_FP87
| CPUID_VME
| CPUID_DE
| CPUID_PSE
| CPUID_TSC
|
3563 CPUID_MSR
| CPUID_PAE
| CPUID_MCE
| CPUID_CX8
| CPUID_APIC
|
3564 CPUID_SEP
| CPUID_MTRR
| CPUID_PGE
| CPUID_MCA
| CPUID_CMOV
|
3565 CPUID_PAT
| CPUID_PSE36
| CPUID_CLFLUSH
| CPUID_MMX
| CPUID_FXSR
|
3566 CPUID_SSE
| CPUID_SSE2
,
3567 .features
[FEAT_1_ECX
] =
3568 CPUID_EXT_SSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_MONITOR
|
3569 CPUID_EXT_SSSE3
| CPUID_EXT_CX16
| CPUID_EXT_SSE41
|
3570 CPUID_EXT_SSE42
| CPUID_EXT_X2APIC
| CPUID_EXT_MOVBE
|
3571 CPUID_EXT_POPCNT
| CPUID_EXT_TSC_DEADLINE_TIMER
|
3572 CPUID_EXT_AES
| CPUID_EXT_XSAVE
| CPUID_EXT_RDRAND
,
3573 .features
[FEAT_8000_0001_EDX
] =
3574 CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
| CPUID_EXT2_PDPE1GB
|
3575 CPUID_EXT2_RDTSCP
| CPUID_EXT2_LM
,
3576 .features
[FEAT_8000_0001_ECX
] =
3577 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
3578 .features
[FEAT_7_0_EBX
] =
3579 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_ERMS
|
3580 CPUID_7_0_EBX_MPX
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_SMAP
|
3581 CPUID_7_0_EBX_CLFLUSHOPT
| CPUID_7_0_EBX_SHA_NI
,
3582 .features
[FEAT_7_0_EDX
] =
3583 CPUID_7_0_EDX_SPEC_CTRL
| CPUID_7_0_EDX_ARCH_CAPABILITIES
|
3584 CPUID_7_0_EDX_SPEC_CTRL_SSBD
,
3586 * Missing: XSAVES (not supported by some Linux versions,
3587 * including v4.1 to v4.12).
3588 * KVM doesn't yet expose any XSAVES state save component,
3589 * and the only one defined in Skylake (processor tracing)
3590 * probably will block migration anyway.
3592 .features
[FEAT_XSAVE
] =
3593 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
| CPUID_XSAVE_XGETBV1
,
3594 .features
[FEAT_6_EAX
] =
3596 .features
[FEAT_ARCH_CAPABILITIES
] =
3597 MSR_ARCH_CAP_RDCL_NO
| MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY
,
3598 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
3599 MSR_VMX_BASIC_TRUE_CTLS
,
3600 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
3601 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
3602 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3603 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
3604 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
3605 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
3606 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3607 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3608 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3609 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
3610 .features
[FEAT_VMX_EXIT_CTLS
] =
3611 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3612 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3613 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
3614 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3615 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3616 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
3617 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
3618 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
3619 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
3620 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
3621 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3622 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3623 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3624 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3625 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3626 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3627 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3628 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3629 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3630 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3631 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3632 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3633 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3634 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3635 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3636 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3637 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3638 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3639 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3640 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3641 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3642 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3643 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
3644 .features
[FEAT_VMX_VMFUNC
] = MSR_VMX_VMFUNC_EPT_SWITCHING
,
3645 .xlevel
= 0x80000008,
3646 .model_id
= "Intel Atom Processor (Denverton)",
3647 .versions
= (X86CPUVersionDefinition
[]) {
3651 .props
= (PropValue
[]) {
3652 { "monitor", "off" },
3654 { /* end of list */ },
3657 { /* end of list */ },
3661 .name
= "Snowridge",
3663 .vendor
= CPUID_VENDOR_INTEL
,
3667 .features
[FEAT_1_EDX
] =
3668 /* missing: CPUID_PN CPUID_IA64 */
3669 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3670 CPUID_FP87
| CPUID_VME
| CPUID_DE
| CPUID_PSE
|
3671 CPUID_TSC
| CPUID_MSR
| CPUID_PAE
| CPUID_MCE
|
3672 CPUID_CX8
| CPUID_APIC
| CPUID_SEP
|
3673 CPUID_MTRR
| CPUID_PGE
| CPUID_MCA
| CPUID_CMOV
|
3674 CPUID_PAT
| CPUID_PSE36
| CPUID_CLFLUSH
|
3676 CPUID_FXSR
| CPUID_SSE
| CPUID_SSE2
,
3677 .features
[FEAT_1_ECX
] =
3678 CPUID_EXT_SSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_MONITOR
|
3682 CPUID_EXT_SSE42
| CPUID_EXT_X2APIC
| CPUID_EXT_MOVBE
|
3684 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_AES
| CPUID_EXT_XSAVE
|
3686 .features
[FEAT_8000_0001_EDX
] =
3687 CPUID_EXT2_SYSCALL
|
3689 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
3691 .features
[FEAT_8000_0001_ECX
] =
3692 CPUID_EXT3_LAHF_LM
|
3693 CPUID_EXT3_3DNOWPREFETCH
,
3694 .features
[FEAT_7_0_EBX
] =
3695 CPUID_7_0_EBX_FSGSBASE
|
3696 CPUID_7_0_EBX_SMEP
|
3697 CPUID_7_0_EBX_ERMS
|
3698 CPUID_7_0_EBX_MPX
| /* missing bits 13, 15 */
3699 CPUID_7_0_EBX_RDSEED
|
3700 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
3701 CPUID_7_0_EBX_CLWB
|
3702 CPUID_7_0_EBX_SHA_NI
,
3703 .features
[FEAT_7_0_ECX
] =
3704 CPUID_7_0_ECX_UMIP
|
3706 CPUID_7_0_ECX_GFNI
|
3707 CPUID_7_0_ECX_MOVDIRI
| CPUID_7_0_ECX_CLDEMOTE
|
3708 CPUID_7_0_ECX_MOVDIR64B
,
3709 .features
[FEAT_7_0_EDX
] =
3710 CPUID_7_0_EDX_SPEC_CTRL
|
3711 CPUID_7_0_EDX_ARCH_CAPABILITIES
| CPUID_7_0_EDX_SPEC_CTRL_SSBD
|
3712 CPUID_7_0_EDX_CORE_CAPABILITY
,
3713 .features
[FEAT_CORE_CAPABILITY
] =
3714 MSR_CORE_CAP_SPLIT_LOCK_DETECT
,
3716 * Missing: XSAVES (not supported by some Linux versions,
3717 * including v4.1 to v4.12).
3718 * KVM doesn't yet expose any XSAVES state save component,
3719 * and the only one defined in Skylake (processor tracing)
3720 * probably will block migration anyway.
3722 .features
[FEAT_XSAVE
] =
3723 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3724 CPUID_XSAVE_XGETBV1
,
3725 .features
[FEAT_6_EAX
] =
3727 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
3728 MSR_VMX_BASIC_TRUE_CTLS
,
3729 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
3730 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
3731 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3732 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
3733 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
3734 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
3735 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3736 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3737 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3738 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
3739 .features
[FEAT_VMX_EXIT_CTLS
] =
3740 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3741 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3742 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
3743 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3744 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3745 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
3746 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
3747 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
3748 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
3749 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
3750 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3751 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3752 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3753 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3754 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3755 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3756 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3757 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3758 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3759 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3760 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3761 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3762 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3763 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3764 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3765 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3766 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3767 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3768 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3769 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3770 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3771 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3772 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
3773 .features
[FEAT_VMX_VMFUNC
] = MSR_VMX_VMFUNC_EPT_SWITCHING
,
3774 .xlevel
= 0x80000008,
3775 .model_id
= "Intel Atom Processor (SnowRidge)",
3776 .versions
= (X86CPUVersionDefinition
[]) {
3780 .props
= (PropValue
[]) {
3782 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
3783 { /* end of list */ },
3786 { /* end of list */ },
3790 .name
= "KnightsMill",
3792 .vendor
= CPUID_VENDOR_INTEL
,
3796 .features
[FEAT_1_EDX
] =
3797 CPUID_VME
| CPUID_SS
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
|
3798 CPUID_MMX
| CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
|
3799 CPUID_MCA
| CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
|
3800 CPUID_CX8
| CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
|
3801 CPUID_PSE
| CPUID_DE
| CPUID_FP87
,
3802 .features
[FEAT_1_ECX
] =
3803 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
3804 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
3805 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
3806 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
3807 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
3808 CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
3809 .features
[FEAT_8000_0001_EDX
] =
3810 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
3811 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
3812 .features
[FEAT_8000_0001_ECX
] =
3813 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
3814 .features
[FEAT_7_0_EBX
] =
3815 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
3816 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
|
3817 CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_AVX512F
|
3818 CPUID_7_0_EBX_AVX512CD
| CPUID_7_0_EBX_AVX512PF
|
3819 CPUID_7_0_EBX_AVX512ER
,
3820 .features
[FEAT_7_0_ECX
] =
3821 CPUID_7_0_ECX_AVX512_VPOPCNTDQ
,
3822 .features
[FEAT_7_0_EDX
] =
3823 CPUID_7_0_EDX_AVX512_4VNNIW
| CPUID_7_0_EDX_AVX512_4FMAPS
,
3824 .features
[FEAT_XSAVE
] =
3825 CPUID_XSAVE_XSAVEOPT
,
3826 .features
[FEAT_6_EAX
] =
3828 .xlevel
= 0x80000008,
3829 .model_id
= "Intel Xeon Phi Processor (Knights Mill)",
3832 .name
= "Opteron_G1",
3834 .vendor
= CPUID_VENDOR_AMD
,
3838 .features
[FEAT_1_EDX
] =
3839 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
3840 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
3841 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
3842 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
3843 CPUID_DE
| CPUID_FP87
,
3844 .features
[FEAT_1_ECX
] =
3846 .features
[FEAT_8000_0001_EDX
] =
3847 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
3848 .xlevel
= 0x80000008,
3849 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
3852 .name
= "Opteron_G2",
3854 .vendor
= CPUID_VENDOR_AMD
,
3858 .features
[FEAT_1_EDX
] =
3859 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
3860 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
3861 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
3862 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
3863 CPUID_DE
| CPUID_FP87
,
3864 .features
[FEAT_1_ECX
] =
3865 CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
3866 .features
[FEAT_8000_0001_EDX
] =
3867 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
3868 .features
[FEAT_8000_0001_ECX
] =
3869 CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
3870 .xlevel
= 0x80000008,
3871 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
3874 .name
= "Opteron_G3",
3876 .vendor
= CPUID_VENDOR_AMD
,
3880 .features
[FEAT_1_EDX
] =
3881 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
3882 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
3883 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
3884 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
3885 CPUID_DE
| CPUID_FP87
,
3886 .features
[FEAT_1_ECX
] =
3887 CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
3889 .features
[FEAT_8000_0001_EDX
] =
3890 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
|
3892 .features
[FEAT_8000_0001_ECX
] =
3893 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
3894 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
3895 .xlevel
= 0x80000008,
3896 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
3899 .name
= "Opteron_G4",
3901 .vendor
= CPUID_VENDOR_AMD
,
3905 .features
[FEAT_1_EDX
] =
3906 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
3907 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
3908 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
3909 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
3910 CPUID_DE
| CPUID_FP87
,
3911 .features
[FEAT_1_ECX
] =
3912 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
3913 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
3914 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
3916 .features
[FEAT_8000_0001_EDX
] =
3917 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_NX
|
3918 CPUID_EXT2_SYSCALL
| CPUID_EXT2_RDTSCP
,
3919 .features
[FEAT_8000_0001_ECX
] =
3920 CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
3921 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
3922 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
3924 .features
[FEAT_SVM
] =
3925 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
3927 .xlevel
= 0x8000001A,
3928 .model_id
= "AMD Opteron 62xx class CPU",
3931 .name
= "Opteron_G5",
3933 .vendor
= CPUID_VENDOR_AMD
,
3937 .features
[FEAT_1_EDX
] =
3938 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
3939 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
3940 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
3941 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
3942 CPUID_DE
| CPUID_FP87
,
3943 .features
[FEAT_1_ECX
] =
3944 CPUID_EXT_F16C
| CPUID_EXT_AVX
| CPUID_EXT_XSAVE
|
3945 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
3946 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_FMA
|
3947 CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
3948 .features
[FEAT_8000_0001_EDX
] =
3949 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_NX
|
3950 CPUID_EXT2_SYSCALL
| CPUID_EXT2_RDTSCP
,
3951 .features
[FEAT_8000_0001_ECX
] =
3952 CPUID_EXT3_TBM
| CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
3953 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
3954 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
3956 .features
[FEAT_SVM
] =
3957 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
3959 .xlevel
= 0x8000001A,
3960 .model_id
= "AMD Opteron 63xx class CPU",
3965 .vendor
= CPUID_VENDOR_AMD
,
3969 .features
[FEAT_1_EDX
] =
3970 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
3971 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
3972 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
3973 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
3974 CPUID_VME
| CPUID_FP87
,
3975 .features
[FEAT_1_ECX
] =
3976 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
3977 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
3978 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
3979 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
3980 CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
3981 .features
[FEAT_8000_0001_EDX
] =
3982 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
3983 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
3985 .features
[FEAT_8000_0001_ECX
] =
3986 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
3987 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
3988 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
|
3990 .features
[FEAT_7_0_EBX
] =
3991 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
3992 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
3993 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
3994 CPUID_7_0_EBX_SHA_NI
,
3995 .features
[FEAT_XSAVE
] =
3996 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3997 CPUID_XSAVE_XGETBV1
,
3998 .features
[FEAT_6_EAX
] =
4000 .features
[FEAT_SVM
] =
4001 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
4002 .xlevel
= 0x8000001E,
4003 .model_id
= "AMD EPYC Processor",
4004 .cache_info
= &epyc_cache_info
,
4005 .versions
= (X86CPUVersionDefinition
[]) {
4009 .alias
= "EPYC-IBPB",
4010 .props
= (PropValue
[]) {
4013 "AMD EPYC Processor (with IBPB)" },
4014 { /* end of list */ }
4019 .props
= (PropValue
[]) {
4021 { "perfctr-core", "on" },
4023 { "xsaveerptr", "on" },
4026 "AMD EPYC Processor" },
4027 { /* end of list */ }
4030 { /* end of list */ }
4036 .vendor
= CPUID_VENDOR_HYGON
,
4040 .features
[FEAT_1_EDX
] =
4041 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
4042 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
4043 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
4044 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
4045 CPUID_VME
| CPUID_FP87
,
4046 .features
[FEAT_1_ECX
] =
4047 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
4048 CPUID_EXT_XSAVE
| CPUID_EXT_POPCNT
|
4049 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
4050 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
4051 CPUID_EXT_MONITOR
| CPUID_EXT_SSE3
,
4052 .features
[FEAT_8000_0001_EDX
] =
4053 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
4054 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
4056 .features
[FEAT_8000_0001_ECX
] =
4057 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
4058 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
4059 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
|
4061 .features
[FEAT_8000_0008_EBX
] =
4062 CPUID_8000_0008_EBX_IBPB
,
4063 .features
[FEAT_7_0_EBX
] =
4064 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
4065 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
4066 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
,
4068 * Missing: XSAVES (not supported by some Linux versions,
4069 * including v4.1 to v4.12).
4070 * KVM doesn't yet expose any XSAVES state save component.
4072 .features
[FEAT_XSAVE
] =
4073 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
4074 CPUID_XSAVE_XGETBV1
,
4075 .features
[FEAT_6_EAX
] =
4077 .features
[FEAT_SVM
] =
4078 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
4079 .xlevel
= 0x8000001E,
4080 .model_id
= "Hygon Dhyana Processor",
4081 .cache_info
= &epyc_cache_info
,
4084 .name
= "EPYC-Rome",
4086 .vendor
= CPUID_VENDOR_AMD
,
4090 .features
[FEAT_1_EDX
] =
4091 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
4092 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
4093 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
4094 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
4095 CPUID_VME
| CPUID_FP87
,
4096 .features
[FEAT_1_ECX
] =
4097 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
4098 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
4099 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
4100 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
4101 CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
4102 .features
[FEAT_8000_0001_EDX
] =
4103 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
4104 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
4106 .features
[FEAT_8000_0001_ECX
] =
4107 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
4108 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
4109 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
|
4110 CPUID_EXT3_TOPOEXT
| CPUID_EXT3_PERFCORE
,
4111 .features
[FEAT_8000_0008_EBX
] =
4112 CPUID_8000_0008_EBX_CLZERO
| CPUID_8000_0008_EBX_XSAVEERPTR
|
4113 CPUID_8000_0008_EBX_WBNOINVD
| CPUID_8000_0008_EBX_IBPB
|
4114 CPUID_8000_0008_EBX_STIBP
,
4115 .features
[FEAT_7_0_EBX
] =
4116 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
4117 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
4118 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
4119 CPUID_7_0_EBX_SHA_NI
| CPUID_7_0_EBX_CLWB
,
4120 .features
[FEAT_7_0_ECX
] =
4121 CPUID_7_0_ECX_UMIP
| CPUID_7_0_ECX_RDPID
,
4122 .features
[FEAT_XSAVE
] =
4123 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
4124 CPUID_XSAVE_XGETBV1
| CPUID_XSAVE_XSAVES
,
4125 .features
[FEAT_6_EAX
] =
4127 .features
[FEAT_SVM
] =
4128 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
4129 .xlevel
= 0x8000001E,
4130 .model_id
= "AMD EPYC-Rome Processor",
4131 .cache_info
= &epyc_rome_cache_info
,
4135 /* KVM-specific features that are automatically added/removed
4136 * from all CPU models when KVM is enabled.
4138 static PropValue kvm_default_props
[] = {
4139 { "kvmclock", "on" },
4140 { "kvm-nopiodelay", "on" },
4141 { "kvm-asyncpf", "on" },
4142 { "kvm-steal-time", "on" },
4143 { "kvm-pv-eoi", "on" },
4144 { "kvmclock-stable-bit", "on" },
4147 { "monitor", "off" },
4152 /* TCG-specific defaults that override all CPU models when using TCG
4154 static PropValue tcg_default_props
[] = {
4161 * We resolve CPU model aliases using -v1 when using "-machine
4162 * none", but this is just for compatibility while libvirt isn't
4163 * adapted to resolve CPU model versions before creating VMs.
4164 * See "Runnability guarantee of CPU models" at * qemu-deprecated.texi.
4166 X86CPUVersion default_cpu_version
= 1;
4168 void x86_cpu_set_default_version(X86CPUVersion version
)
4170 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
4171 assert(version
!= CPU_VERSION_AUTO
);
4172 default_cpu_version
= version
;
4175 static X86CPUVersion
x86_cpu_model_last_version(const X86CPUModel
*model
)
4178 const X86CPUVersionDefinition
*vdef
=
4179 x86_cpu_def_get_versions(model
->cpudef
);
4180 while (vdef
->version
) {
4187 /* Return the actual version being used for a specific CPU model */
4188 static X86CPUVersion
x86_cpu_model_resolve_version(const X86CPUModel
*model
)
4190 X86CPUVersion v
= model
->version
;
4191 if (v
== CPU_VERSION_AUTO
) {
4192 v
= default_cpu_version
;
4194 if (v
== CPU_VERSION_LATEST
) {
4195 return x86_cpu_model_last_version(model
);
4200 void x86_cpu_change_kvm_default(const char *prop
, const char *value
)
4203 for (pv
= kvm_default_props
; pv
->prop
; pv
++) {
4204 if (!strcmp(pv
->prop
, prop
)) {
4210 /* It is valid to call this function only for properties that
4211 * are already present in the kvm_default_props table.
4216 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w
,
4217 bool migratable_only
);
4219 static bool lmce_supported(void)
4221 uint64_t mce_cap
= 0;
4224 if (kvm_ioctl(kvm_state
, KVM_X86_GET_MCE_CAP_SUPPORTED
, &mce_cap
) < 0) {
4229 return !!(mce_cap
& MCG_LMCE_P
);
4232 #define CPUID_MODEL_ID_SZ 48
4235 * cpu_x86_fill_model_id:
4236 * Get CPUID model ID string from host CPU.
4238 * @str should have at least CPUID_MODEL_ID_SZ bytes
4240 * The function does NOT add a null terminator to the string
4243 static int cpu_x86_fill_model_id(char *str
)
4245 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
4248 for (i
= 0; i
< 3; i
++) {
4249 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
4250 memcpy(str
+ i
* 16 + 0, &eax
, 4);
4251 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
4252 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
4253 memcpy(str
+ i
* 16 + 12, &edx
, 4);
4258 static Property max_x86_cpu_properties
[] = {
4259 DEFINE_PROP_BOOL("migratable", X86CPU
, migratable
, true),
4260 DEFINE_PROP_BOOL("host-cache-info", X86CPU
, cache_info_passthrough
, false),
4261 DEFINE_PROP_END_OF_LIST()
4264 static void max_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
4266 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4267 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
4271 xcc
->model_description
=
4272 "Enables all features supported by the accelerator in the current host";
4274 device_class_set_props(dc
, max_x86_cpu_properties
);
4277 static void max_x86_cpu_initfn(Object
*obj
)
4279 X86CPU
*cpu
= X86_CPU(obj
);
4280 CPUX86State
*env
= &cpu
->env
;
4281 KVMState
*s
= kvm_state
;
4283 /* We can't fill the features array here because we don't know yet if
4284 * "migratable" is true or false.
4286 cpu
->max_features
= true;
4288 if (accel_uses_host_cpuid()) {
4289 char vendor
[CPUID_VENDOR_SZ
+ 1] = { 0 };
4290 char model_id
[CPUID_MODEL_ID_SZ
+ 1] = { 0 };
4291 int family
, model
, stepping
;
4293 host_vendor_fms(vendor
, &family
, &model
, &stepping
);
4294 cpu_x86_fill_model_id(model_id
);
4296 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", &error_abort
);
4297 object_property_set_int(OBJECT(cpu
), family
, "family", &error_abort
);
4298 object_property_set_int(OBJECT(cpu
), model
, "model", &error_abort
);
4299 object_property_set_int(OBJECT(cpu
), stepping
, "stepping",
4301 object_property_set_str(OBJECT(cpu
), model_id
, "model-id",
4304 if (kvm_enabled()) {
4305 env
->cpuid_min_level
=
4306 kvm_arch_get_supported_cpuid(s
, 0x0, 0, R_EAX
);
4307 env
->cpuid_min_xlevel
=
4308 kvm_arch_get_supported_cpuid(s
, 0x80000000, 0, R_EAX
);
4309 env
->cpuid_min_xlevel2
=
4310 kvm_arch_get_supported_cpuid(s
, 0xC0000000, 0, R_EAX
);
4312 env
->cpuid_min_level
=
4313 hvf_get_supported_cpuid(0x0, 0, R_EAX
);
4314 env
->cpuid_min_xlevel
=
4315 hvf_get_supported_cpuid(0x80000000, 0, R_EAX
);
4316 env
->cpuid_min_xlevel2
=
4317 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX
);
4320 if (lmce_supported()) {
4321 object_property_set_bool(OBJECT(cpu
), true, "lmce", &error_abort
);
4324 object_property_set_str(OBJECT(cpu
), CPUID_VENDOR_AMD
,
4325 "vendor", &error_abort
);
4326 object_property_set_int(OBJECT(cpu
), 6, "family", &error_abort
);
4327 object_property_set_int(OBJECT(cpu
), 6, "model", &error_abort
);
4328 object_property_set_int(OBJECT(cpu
), 3, "stepping", &error_abort
);
4329 object_property_set_str(OBJECT(cpu
),
4330 "QEMU TCG CPU version " QEMU_HW_VERSION
,
4331 "model-id", &error_abort
);
4334 object_property_set_bool(OBJECT(cpu
), true, "pmu", &error_abort
);
4337 static const TypeInfo max_x86_cpu_type_info
= {
4338 .name
= X86_CPU_TYPE_NAME("max"),
4339 .parent
= TYPE_X86_CPU
,
4340 .instance_init
= max_x86_cpu_initfn
,
4341 .class_init
= max_x86_cpu_class_init
,
4344 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
4345 static void host_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
4347 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
4349 xcc
->host_cpuid_required
= true;
4352 #if defined(CONFIG_KVM)
4353 xcc
->model_description
=
4354 "KVM processor with all supported host features ";
4355 #elif defined(CONFIG_HVF)
4356 xcc
->model_description
=
4357 "HVF processor with all supported host features ";
4361 static const TypeInfo host_x86_cpu_type_info
= {
4362 .name
= X86_CPU_TYPE_NAME("host"),
4363 .parent
= X86_CPU_TYPE_NAME("max"),
4364 .class_init
= host_x86_cpu_class_init
,
4369 static char *feature_word_description(FeatureWordInfo
*f
, uint32_t bit
)
4371 assert(f
->type
== CPUID_FEATURE_WORD
|| f
->type
== MSR_FEATURE_WORD
);
4374 case CPUID_FEATURE_WORD
:
4376 const char *reg
= get_register_name_32(f
->cpuid
.reg
);
4378 return g_strdup_printf("CPUID.%02XH:%s",
4381 case MSR_FEATURE_WORD
:
4382 return g_strdup_printf("MSR(%02XH)",
4389 static bool x86_cpu_have_filtered_features(X86CPU
*cpu
)
4393 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
4394 if (cpu
->filtered_features
[w
]) {
4402 static void mark_unavailable_features(X86CPU
*cpu
, FeatureWord w
, uint64_t mask
,
4403 const char *verbose_prefix
)
4405 CPUX86State
*env
= &cpu
->env
;
4406 FeatureWordInfo
*f
= &feature_word_info
[w
];
4409 if (!cpu
->force_features
) {
4410 env
->features
[w
] &= ~mask
;
4412 cpu
->filtered_features
[w
] |= mask
;
4414 if (!verbose_prefix
) {
4418 for (i
= 0; i
< 64; ++i
) {
4419 if ((1ULL << i
) & mask
) {
4420 g_autofree
char *feat_word_str
= feature_word_description(f
, i
);
4421 warn_report("%s: %s%s%s [bit %d]",
4424 f
->feat_names
[i
] ? "." : "",
4425 f
->feat_names
[i
] ? f
->feat_names
[i
] : "", i
);
4430 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
,
4431 const char *name
, void *opaque
,
4434 X86CPU
*cpu
= X86_CPU(obj
);
4435 CPUX86State
*env
= &cpu
->env
;
4438 value
= (env
->cpuid_version
>> 8) & 0xf;
4440 value
+= (env
->cpuid_version
>> 20) & 0xff;
4442 visit_type_int(v
, name
, &value
, errp
);
4445 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
,
4446 const char *name
, void *opaque
,
4449 X86CPU
*cpu
= X86_CPU(obj
);
4450 CPUX86State
*env
= &cpu
->env
;
4451 const int64_t min
= 0;
4452 const int64_t max
= 0xff + 0xf;
4453 Error
*local_err
= NULL
;
4456 visit_type_int(v
, name
, &value
, &local_err
);
4458 error_propagate(errp
, local_err
);
4461 if (value
< min
|| value
> max
) {
4462 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
4463 name
? name
: "null", value
, min
, max
);
4467 env
->cpuid_version
&= ~0xff00f00;
4469 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
4471 env
->cpuid_version
|= value
<< 8;
4475 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
,
4476 const char *name
, void *opaque
,
4479 X86CPU
*cpu
= X86_CPU(obj
);
4480 CPUX86State
*env
= &cpu
->env
;
4483 value
= (env
->cpuid_version
>> 4) & 0xf;
4484 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
4485 visit_type_int(v
, name
, &value
, errp
);
4488 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
,
4489 const char *name
, void *opaque
,
4492 X86CPU
*cpu
= X86_CPU(obj
);
4493 CPUX86State
*env
= &cpu
->env
;
4494 const int64_t min
= 0;
4495 const int64_t max
= 0xff;
4496 Error
*local_err
= NULL
;
4499 visit_type_int(v
, name
, &value
, &local_err
);
4501 error_propagate(errp
, local_err
);
4504 if (value
< min
|| value
> max
) {
4505 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
4506 name
? name
: "null", value
, min
, max
);
4510 env
->cpuid_version
&= ~0xf00f0;
4511 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
4514 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
4515 const char *name
, void *opaque
,
4518 X86CPU
*cpu
= X86_CPU(obj
);
4519 CPUX86State
*env
= &cpu
->env
;
4522 value
= env
->cpuid_version
& 0xf;
4523 visit_type_int(v
, name
, &value
, errp
);
4526 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
4527 const char *name
, void *opaque
,
4530 X86CPU
*cpu
= X86_CPU(obj
);
4531 CPUX86State
*env
= &cpu
->env
;
4532 const int64_t min
= 0;
4533 const int64_t max
= 0xf;
4534 Error
*local_err
= NULL
;
4537 visit_type_int(v
, name
, &value
, &local_err
);
4539 error_propagate(errp
, local_err
);
4542 if (value
< min
|| value
> max
) {
4543 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
4544 name
? name
: "null", value
, min
, max
);
4548 env
->cpuid_version
&= ~0xf;
4549 env
->cpuid_version
|= value
& 0xf;
4552 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
4554 X86CPU
*cpu
= X86_CPU(obj
);
4555 CPUX86State
*env
= &cpu
->env
;
4558 value
= g_malloc(CPUID_VENDOR_SZ
+ 1);
4559 x86_cpu_vendor_words2str(value
, env
->cpuid_vendor1
, env
->cpuid_vendor2
,
4560 env
->cpuid_vendor3
);
4564 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
4567 X86CPU
*cpu
= X86_CPU(obj
);
4568 CPUX86State
*env
= &cpu
->env
;
4571 if (strlen(value
) != CPUID_VENDOR_SZ
) {
4572 error_setg(errp
, QERR_PROPERTY_VALUE_BAD
, "", "vendor", value
);
4576 env
->cpuid_vendor1
= 0;
4577 env
->cpuid_vendor2
= 0;
4578 env
->cpuid_vendor3
= 0;
4579 for (i
= 0; i
< 4; i
++) {
4580 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
4581 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
4582 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
4586 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
4588 X86CPU
*cpu
= X86_CPU(obj
);
4589 CPUX86State
*env
= &cpu
->env
;
4593 value
= g_malloc(48 + 1);
4594 for (i
= 0; i
< 48; i
++) {
4595 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
4601 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
4604 X86CPU
*cpu
= X86_CPU(obj
);
4605 CPUX86State
*env
= &cpu
->env
;
4608 if (model_id
== NULL
) {
4611 len
= strlen(model_id
);
4612 memset(env
->cpuid_model
, 0, 48);
4613 for (i
= 0; i
< 48; i
++) {
4617 c
= (uint8_t)model_id
[i
];
4619 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
4623 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
4624 void *opaque
, Error
**errp
)
4626 X86CPU
*cpu
= X86_CPU(obj
);
4629 value
= cpu
->env
.tsc_khz
* 1000;
4630 visit_type_int(v
, name
, &value
, errp
);
4633 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
4634 void *opaque
, Error
**errp
)
4636 X86CPU
*cpu
= X86_CPU(obj
);
4637 const int64_t min
= 0;
4638 const int64_t max
= INT64_MAX
;
4639 Error
*local_err
= NULL
;
4642 visit_type_int(v
, name
, &value
, &local_err
);
4644 error_propagate(errp
, local_err
);
4647 if (value
< min
|| value
> max
) {
4648 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
4649 name
? name
: "null", value
, min
, max
);
4653 cpu
->env
.tsc_khz
= cpu
->env
.user_tsc_khz
= value
/ 1000;
4656 /* Generic getter for "feature-words" and "filtered-features" properties */
4657 static void x86_cpu_get_feature_words(Object
*obj
, Visitor
*v
,
4658 const char *name
, void *opaque
,
4661 uint64_t *array
= (uint64_t *)opaque
;
4663 X86CPUFeatureWordInfo word_infos
[FEATURE_WORDS
] = { };
4664 X86CPUFeatureWordInfoList list_entries
[FEATURE_WORDS
] = { };
4665 X86CPUFeatureWordInfoList
*list
= NULL
;
4667 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
4668 FeatureWordInfo
*wi
= &feature_word_info
[w
];
4670 * We didn't have MSR features when "feature-words" was
4671 * introduced. Therefore skipped other type entries.
4673 if (wi
->type
!= CPUID_FEATURE_WORD
) {
4676 X86CPUFeatureWordInfo
*qwi
= &word_infos
[w
];
4677 qwi
->cpuid_input_eax
= wi
->cpuid
.eax
;
4678 qwi
->has_cpuid_input_ecx
= wi
->cpuid
.needs_ecx
;
4679 qwi
->cpuid_input_ecx
= wi
->cpuid
.ecx
;
4680 qwi
->cpuid_register
= x86_reg_info_32
[wi
->cpuid
.reg
].qapi_enum
;
4681 qwi
->features
= array
[w
];
4683 /* List will be in reverse order, but order shouldn't matter */
4684 list_entries
[w
].next
= list
;
4685 list_entries
[w
].value
= &word_infos
[w
];
4686 list
= &list_entries
[w
];
4689 visit_type_X86CPUFeatureWordInfoList(v
, "feature-words", &list
, errp
);
4692 /* Convert all '_' in a feature string option name to '-', to make feature
4693 * name conform to QOM property naming rule, which uses '-' instead of '_'.
4695 static inline void feat2prop(char *s
)
4697 while ((s
= strchr(s
, '_'))) {
4702 /* Return the feature property name for a feature flag bit */
4703 static const char *x86_cpu_feature_name(FeatureWord w
, int bitnr
)
4706 /* XSAVE components are automatically enabled by other features,
4707 * so return the original feature name instead
4709 if (w
== FEAT_XSAVE_COMP_LO
|| w
== FEAT_XSAVE_COMP_HI
) {
4710 int comp
= (w
== FEAT_XSAVE_COMP_HI
) ? bitnr
+ 32 : bitnr
;
4712 if (comp
< ARRAY_SIZE(x86_ext_save_areas
) &&
4713 x86_ext_save_areas
[comp
].bits
) {
4714 w
= x86_ext_save_areas
[comp
].feature
;
4715 bitnr
= ctz32(x86_ext_save_areas
[comp
].bits
);
4720 assert(w
< FEATURE_WORDS
);
4721 name
= feature_word_info
[w
].feat_names
[bitnr
];
4722 assert(bitnr
< 32 || !(name
&& feature_word_info
[w
].type
== CPUID_FEATURE_WORD
));
4726 /* Compatibily hack to maintain legacy +-feat semantic,
4727 * where +-feat overwrites any feature set by
4728 * feat=on|feat even if the later is parsed after +-feat
4729 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
4731 static GList
*plus_features
, *minus_features
;
4733 static gint
compare_string(gconstpointer a
, gconstpointer b
)
4735 return g_strcmp0(a
, b
);
4738 /* Parse "+feature,-feature,feature=foo" CPU feature string
4740 static void x86_cpu_parse_featurestr(const char *typename
, char *features
,
4743 char *featurestr
; /* Single 'key=value" string being parsed */
4744 static bool cpu_globals_initialized
;
4745 bool ambiguous
= false;
4747 if (cpu_globals_initialized
) {
4750 cpu_globals_initialized
= true;
4756 for (featurestr
= strtok(features
, ",");
4758 featurestr
= strtok(NULL
, ",")) {
4760 const char *val
= NULL
;
4763 GlobalProperty
*prop
;
4765 /* Compatibility syntax: */
4766 if (featurestr
[0] == '+') {
4767 plus_features
= g_list_append(plus_features
,
4768 g_strdup(featurestr
+ 1));
4770 } else if (featurestr
[0] == '-') {
4771 minus_features
= g_list_append(minus_features
,
4772 g_strdup(featurestr
+ 1));
4776 eq
= strchr(featurestr
, '=');
4784 feat2prop(featurestr
);
4787 if (g_list_find_custom(plus_features
, name
, compare_string
)) {
4788 warn_report("Ambiguous CPU model string. "
4789 "Don't mix both \"+%s\" and \"%s=%s\"",
4793 if (g_list_find_custom(minus_features
, name
, compare_string
)) {
4794 warn_report("Ambiguous CPU model string. "
4795 "Don't mix both \"-%s\" and \"%s=%s\"",
4801 if (!strcmp(name
, "tsc-freq")) {
4805 ret
= qemu_strtosz_metric(val
, NULL
, &tsc_freq
);
4806 if (ret
< 0 || tsc_freq
> INT64_MAX
) {
4807 error_setg(errp
, "bad numerical value %s", val
);
4810 snprintf(num
, sizeof(num
), "%" PRId64
, tsc_freq
);
4812 name
= "tsc-frequency";
4815 prop
= g_new0(typeof(*prop
), 1);
4816 prop
->driver
= typename
;
4817 prop
->property
= g_strdup(name
);
4818 prop
->value
= g_strdup(val
);
4819 qdev_prop_register_global(prop
);
4823 warn_report("Compatibility of ambiguous CPU model "
4824 "strings won't be kept on future QEMU versions");
4828 static void x86_cpu_expand_features(X86CPU
*cpu
, Error
**errp
);
4829 static void x86_cpu_filter_features(X86CPU
*cpu
, bool verbose
);
4831 /* Build a list with the name of all features on a feature word array */
4832 static void x86_cpu_list_feature_names(FeatureWordArray features
,
4833 strList
**feat_names
)
4836 strList
**next
= feat_names
;
4838 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
4839 uint64_t filtered
= features
[w
];
4841 for (i
= 0; i
< 64; i
++) {
4842 if (filtered
& (1ULL << i
)) {
4843 strList
*new = g_new0(strList
, 1);
4844 new->value
= g_strdup(x86_cpu_feature_name(w
, i
));
4852 static void x86_cpu_get_unavailable_features(Object
*obj
, Visitor
*v
,
4853 const char *name
, void *opaque
,
4856 X86CPU
*xc
= X86_CPU(obj
);
4857 strList
*result
= NULL
;
4859 x86_cpu_list_feature_names(xc
->filtered_features
, &result
);
4860 visit_type_strList(v
, "unavailable-features", &result
, errp
);
4863 /* Check for missing features that may prevent the CPU class from
4864 * running using the current machine and accelerator.
4866 static void x86_cpu_class_check_missing_features(X86CPUClass
*xcc
,
4867 strList
**missing_feats
)
4871 strList
**next
= missing_feats
;
4873 if (xcc
->host_cpuid_required
&& !accel_uses_host_cpuid()) {
4874 strList
*new = g_new0(strList
, 1);
4875 new->value
= g_strdup("kvm");
4876 *missing_feats
= new;
4880 xc
= X86_CPU(object_new_with_class(OBJECT_CLASS(xcc
)));
4882 x86_cpu_expand_features(xc
, &err
);
4884 /* Errors at x86_cpu_expand_features should never happen,
4885 * but in case it does, just report the model as not
4886 * runnable at all using the "type" property.
4888 strList
*new = g_new0(strList
, 1);
4889 new->value
= g_strdup("type");
4894 x86_cpu_filter_features(xc
, false);
4896 x86_cpu_list_feature_names(xc
->filtered_features
, next
);
4898 object_unref(OBJECT(xc
));
4901 /* Print all cpuid feature names in featureset
4903 static void listflags(GList
*features
)
4908 for (tmp
= features
; tmp
; tmp
= tmp
->next
) {
4909 const char *name
= tmp
->data
;
4910 if ((len
+ strlen(name
) + 1) >= 75) {
4914 qemu_printf("%s%s", len
== 0 ? " " : " ", name
);
4915 len
+= strlen(name
) + 1;
4920 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
4921 static gint
x86_cpu_list_compare(gconstpointer a
, gconstpointer b
)
4923 ObjectClass
*class_a
= (ObjectClass
*)a
;
4924 ObjectClass
*class_b
= (ObjectClass
*)b
;
4925 X86CPUClass
*cc_a
= X86_CPU_CLASS(class_a
);
4926 X86CPUClass
*cc_b
= X86_CPU_CLASS(class_b
);
4929 if (cc_a
->ordering
!= cc_b
->ordering
) {
4930 ret
= cc_a
->ordering
- cc_b
->ordering
;
4932 g_autofree
char *name_a
= x86_cpu_class_get_model_name(cc_a
);
4933 g_autofree
char *name_b
= x86_cpu_class_get_model_name(cc_b
);
4934 ret
= strcmp(name_a
, name_b
);
4939 static GSList
*get_sorted_cpu_model_list(void)
4941 GSList
*list
= object_class_get_list(TYPE_X86_CPU
, false);
4942 list
= g_slist_sort(list
, x86_cpu_list_compare
);
4946 static char *x86_cpu_class_get_model_id(X86CPUClass
*xc
)
4948 Object
*obj
= object_new_with_class(OBJECT_CLASS(xc
));
4949 char *r
= object_property_get_str(obj
, "model-id", &error_abort
);
4954 static char *x86_cpu_class_get_alias_of(X86CPUClass
*cc
)
4956 X86CPUVersion version
;
4958 if (!cc
->model
|| !cc
->model
->is_alias
) {
4961 version
= x86_cpu_model_resolve_version(cc
->model
);
4965 return x86_cpu_versioned_model_name(cc
->model
->cpudef
, version
);
4968 static void x86_cpu_list_entry(gpointer data
, gpointer user_data
)
4970 ObjectClass
*oc
= data
;
4971 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
4972 g_autofree
char *name
= x86_cpu_class_get_model_name(cc
);
4973 g_autofree
char *desc
= g_strdup(cc
->model_description
);
4974 g_autofree
char *alias_of
= x86_cpu_class_get_alias_of(cc
);
4975 g_autofree
char *model_id
= x86_cpu_class_get_model_id(cc
);
4977 if (!desc
&& alias_of
) {
4978 if (cc
->model
&& cc
->model
->version
== CPU_VERSION_AUTO
) {
4979 desc
= g_strdup("(alias configured by machine type)");
4981 desc
= g_strdup_printf("(alias of %s)", alias_of
);
4984 if (!desc
&& cc
->model
&& cc
->model
->note
) {
4985 desc
= g_strdup_printf("%s [%s]", model_id
, cc
->model
->note
);
4988 desc
= g_strdup_printf("%s", model_id
);
4991 qemu_printf("x86 %-20s %-58s\n", name
, desc
);
4994 /* list available CPU models and flags */
4995 void x86_cpu_list(void)
4999 GList
*names
= NULL
;
5001 qemu_printf("Available CPUs:\n");
5002 list
= get_sorted_cpu_model_list();
5003 g_slist_foreach(list
, x86_cpu_list_entry
, NULL
);
5007 for (i
= 0; i
< ARRAY_SIZE(feature_word_info
); i
++) {
5008 FeatureWordInfo
*fw
= &feature_word_info
[i
];
5009 for (j
= 0; j
< 64; j
++) {
5010 if (fw
->feat_names
[j
]) {
5011 names
= g_list_append(names
, (gpointer
)fw
->feat_names
[j
]);
5016 names
= g_list_sort(names
, (GCompareFunc
)strcmp
);
5018 qemu_printf("\nRecognized CPUID flags:\n");
5024 static void x86_cpu_definition_entry(gpointer data
, gpointer user_data
)
5026 ObjectClass
*oc
= data
;
5027 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
5028 CpuDefinitionInfoList
**cpu_list
= user_data
;
5029 CpuDefinitionInfoList
*entry
;
5030 CpuDefinitionInfo
*info
;
5032 info
= g_malloc0(sizeof(*info
));
5033 info
->name
= x86_cpu_class_get_model_name(cc
);
5034 x86_cpu_class_check_missing_features(cc
, &info
->unavailable_features
);
5035 info
->has_unavailable_features
= true;
5036 info
->q_typename
= g_strdup(object_class_get_name(oc
));
5037 info
->migration_safe
= cc
->migration_safe
;
5038 info
->has_migration_safe
= true;
5039 info
->q_static
= cc
->static_model
;
5041 * Old machine types won't report aliases, so that alias translation
5042 * doesn't break compatibility with previous QEMU versions.
5044 if (default_cpu_version
!= CPU_VERSION_LEGACY
) {
5045 info
->alias_of
= x86_cpu_class_get_alias_of(cc
);
5046 info
->has_alias_of
= !!info
->alias_of
;
5049 entry
= g_malloc0(sizeof(*entry
));
5050 entry
->value
= info
;
5051 entry
->next
= *cpu_list
;
5055 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
5057 CpuDefinitionInfoList
*cpu_list
= NULL
;
5058 GSList
*list
= get_sorted_cpu_model_list();
5059 g_slist_foreach(list
, x86_cpu_definition_entry
, &cpu_list
);
5064 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w
,
5065 bool migratable_only
)
5067 FeatureWordInfo
*wi
= &feature_word_info
[w
];
5070 if (kvm_enabled()) {
5072 case CPUID_FEATURE_WORD
:
5073 r
= kvm_arch_get_supported_cpuid(kvm_state
, wi
->cpuid
.eax
,
5077 case MSR_FEATURE_WORD
:
5078 r
= kvm_arch_get_supported_msr_feature(kvm_state
,
5082 } else if (hvf_enabled()) {
5083 if (wi
->type
!= CPUID_FEATURE_WORD
) {
5086 r
= hvf_get_supported_cpuid(wi
->cpuid
.eax
,
5089 } else if (tcg_enabled()) {
5090 r
= wi
->tcg_features
;
5094 if (migratable_only
) {
5095 r
&= x86_cpu_get_migratable_flags(w
);
5100 static void x86_cpu_apply_props(X86CPU
*cpu
, PropValue
*props
)
5103 for (pv
= props
; pv
->prop
; pv
++) {
5107 object_property_parse(OBJECT(cpu
), pv
->value
, pv
->prop
,
5112 /* Apply properties for the CPU model version specified in model */
5113 static void x86_cpu_apply_version_props(X86CPU
*cpu
, X86CPUModel
*model
)
5115 const X86CPUVersionDefinition
*vdef
;
5116 X86CPUVersion version
= x86_cpu_model_resolve_version(model
);
5118 if (version
== CPU_VERSION_LEGACY
) {
5122 for (vdef
= x86_cpu_def_get_versions(model
->cpudef
); vdef
->version
; vdef
++) {
5125 for (p
= vdef
->props
; p
&& p
->prop
; p
++) {
5126 object_property_parse(OBJECT(cpu
), p
->value
, p
->prop
,
5130 if (vdef
->version
== version
) {
5136 * If we reached the end of the list, version number was invalid
5138 assert(vdef
->version
== version
);
5141 /* Load data from X86CPUDefinition into a X86CPU object
5143 static void x86_cpu_load_model(X86CPU
*cpu
, X86CPUModel
*model
, Error
**errp
)
5145 X86CPUDefinition
*def
= model
->cpudef
;
5146 CPUX86State
*env
= &cpu
->env
;
5148 char host_vendor
[CPUID_VENDOR_SZ
+ 1];
5151 /*NOTE: any property set by this function should be returned by
5152 * x86_cpu_static_props(), so static expansion of
5153 * query-cpu-model-expansion is always complete.
5156 /* CPU models only set _minimum_ values for level/xlevel: */
5157 object_property_set_uint(OBJECT(cpu
), def
->level
, "min-level", errp
);
5158 object_property_set_uint(OBJECT(cpu
), def
->xlevel
, "min-xlevel", errp
);
5160 object_property_set_int(OBJECT(cpu
), def
->family
, "family", errp
);
5161 object_property_set_int(OBJECT(cpu
), def
->model
, "model", errp
);
5162 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", errp
);
5163 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", errp
);
5164 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
5165 env
->features
[w
] = def
->features
[w
];
5168 /* legacy-cache defaults to 'off' if CPU model provides cache info */
5169 cpu
->legacy_cache
= !def
->cache_info
;
5171 /* Special cases not set in the X86CPUDefinition structs: */
5172 /* TODO: in-kernel irqchip for hvf */
5173 if (kvm_enabled()) {
5174 if (!kvm_irqchip_in_kernel()) {
5175 x86_cpu_change_kvm_default("x2apic", "off");
5178 x86_cpu_apply_props(cpu
, kvm_default_props
);
5179 } else if (tcg_enabled()) {
5180 x86_cpu_apply_props(cpu
, tcg_default_props
);
5183 env
->features
[FEAT_1_ECX
] |= CPUID_EXT_HYPERVISOR
;
5185 /* sysenter isn't supported in compatibility mode on AMD,
5186 * syscall isn't supported in compatibility mode on Intel.
5187 * Normally we advertise the actual CPU vendor, but you can
5188 * override this using the 'vendor' property if you want to use
5189 * KVM's sysenter/syscall emulation in compatibility mode and
5190 * when doing cross vendor migration
5192 vendor
= def
->vendor
;
5193 if (accel_uses_host_cpuid()) {
5194 uint32_t ebx
= 0, ecx
= 0, edx
= 0;
5195 host_cpuid(0, 0, NULL
, &ebx
, &ecx
, &edx
);
5196 x86_cpu_vendor_words2str(host_vendor
, ebx
, edx
, ecx
);
5197 vendor
= host_vendor
;
5200 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", errp
);
5202 x86_cpu_apply_version_props(cpu
, model
);
5205 #ifndef CONFIG_USER_ONLY
5206 /* Return a QDict containing keys for all properties that can be included
5207 * in static expansion of CPU models. All properties set by x86_cpu_load_model()
5208 * must be included in the dictionary.
5210 static QDict
*x86_cpu_static_props(void)
5214 static const char *props
[] = {
5232 for (i
= 0; props
[i
]; i
++) {
5233 qdict_put_null(d
, props
[i
]);
5236 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
5237 FeatureWordInfo
*fi
= &feature_word_info
[w
];
5239 for (bit
= 0; bit
< 64; bit
++) {
5240 if (!fi
->feat_names
[bit
]) {
5243 qdict_put_null(d
, fi
->feat_names
[bit
]);
5250 /* Add an entry to @props dict, with the value for property. */
5251 static void x86_cpu_expand_prop(X86CPU
*cpu
, QDict
*props
, const char *prop
)
5253 QObject
*value
= object_property_get_qobject(OBJECT(cpu
), prop
,
5256 qdict_put_obj(props
, prop
, value
);
5259 /* Convert CPU model data from X86CPU object to a property dictionary
5260 * that can recreate exactly the same CPU model.
5262 static void x86_cpu_to_dict(X86CPU
*cpu
, QDict
*props
)
5264 QDict
*sprops
= x86_cpu_static_props();
5265 const QDictEntry
*e
;
5267 for (e
= qdict_first(sprops
); e
; e
= qdict_next(sprops
, e
)) {
5268 const char *prop
= qdict_entry_key(e
);
5269 x86_cpu_expand_prop(cpu
, props
, prop
);
5273 /* Convert CPU model data from X86CPU object to a property dictionary
5274 * that can recreate exactly the same CPU model, including every
5275 * writeable QOM property.
5277 static void x86_cpu_to_dict_full(X86CPU
*cpu
, QDict
*props
)
5279 ObjectPropertyIterator iter
;
5280 ObjectProperty
*prop
;
5282 object_property_iter_init(&iter
, OBJECT(cpu
));
5283 while ((prop
= object_property_iter_next(&iter
))) {
5284 /* skip read-only or write-only properties */
5285 if (!prop
->get
|| !prop
->set
) {
5289 /* "hotplugged" is the only property that is configurable
5290 * on the command-line but will be set differently on CPUs
5291 * created using "-cpu ... -smp ..." and by CPUs created
5292 * on the fly by x86_cpu_from_model() for querying. Skip it.
5294 if (!strcmp(prop
->name
, "hotplugged")) {
5297 x86_cpu_expand_prop(cpu
, props
, prop
->name
);
5301 static void object_apply_props(Object
*obj
, QDict
*props
, Error
**errp
)
5303 const QDictEntry
*prop
;
5306 for (prop
= qdict_first(props
); prop
; prop
= qdict_next(props
, prop
)) {
5307 object_property_set_qobject(obj
, qdict_entry_value(prop
),
5308 qdict_entry_key(prop
), &err
);
5314 error_propagate(errp
, err
);
5317 /* Create X86CPU object according to model+props specification */
5318 static X86CPU
*x86_cpu_from_model(const char *model
, QDict
*props
, Error
**errp
)
5324 xcc
= X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU
, model
));
5326 error_setg(&err
, "CPU model '%s' not found", model
);
5330 xc
= X86_CPU(object_new_with_class(OBJECT_CLASS(xcc
)));
5332 object_apply_props(OBJECT(xc
), props
, &err
);
5338 x86_cpu_expand_features(xc
, &err
);
5345 error_propagate(errp
, err
);
5346 object_unref(OBJECT(xc
));
5352 CpuModelExpansionInfo
*
5353 qmp_query_cpu_model_expansion(CpuModelExpansionType type
,
5354 CpuModelInfo
*model
,
5359 CpuModelExpansionInfo
*ret
= g_new0(CpuModelExpansionInfo
, 1);
5360 QDict
*props
= NULL
;
5361 const char *base_name
;
5363 xc
= x86_cpu_from_model(model
->name
,
5365 qobject_to(QDict
, model
->props
) :
5371 props
= qdict_new();
5372 ret
->model
= g_new0(CpuModelInfo
, 1);
5373 ret
->model
->props
= QOBJECT(props
);
5374 ret
->model
->has_props
= true;
5377 case CPU_MODEL_EXPANSION_TYPE_STATIC
:
5378 /* Static expansion will be based on "base" only */
5380 x86_cpu_to_dict(xc
, props
);
5382 case CPU_MODEL_EXPANSION_TYPE_FULL
:
5383 /* As we don't return every single property, full expansion needs
5384 * to keep the original model name+props, and add extra
5385 * properties on top of that.
5387 base_name
= model
->name
;
5388 x86_cpu_to_dict_full(xc
, props
);
5391 error_setg(&err
, "Unsupported expansion type");
5395 x86_cpu_to_dict(xc
, props
);
5397 ret
->model
->name
= g_strdup(base_name
);
5400 object_unref(OBJECT(xc
));
5402 error_propagate(errp
, err
);
5403 qapi_free_CpuModelExpansionInfo(ret
);
5408 #endif /* !CONFIG_USER_ONLY */
5410 static gchar
*x86_gdb_arch_name(CPUState
*cs
)
5412 #ifdef TARGET_X86_64
5413 return g_strdup("i386:x86-64");
5415 return g_strdup("i386");
5419 static void x86_cpu_cpudef_class_init(ObjectClass
*oc
, void *data
)
5421 X86CPUModel
*model
= data
;
5422 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
5425 xcc
->migration_safe
= true;
5428 static void x86_register_cpu_model_type(const char *name
, X86CPUModel
*model
)
5430 g_autofree
char *typename
= x86_cpu_type_name(name
);
5433 .parent
= TYPE_X86_CPU
,
5434 .class_init
= x86_cpu_cpudef_class_init
,
5435 .class_data
= model
,
5441 static void x86_register_cpudef_types(X86CPUDefinition
*def
)
5444 const X86CPUVersionDefinition
*vdef
;
5446 /* AMD aliases are handled at runtime based on CPUID vendor, so
5447 * they shouldn't be set on the CPU model table.
5449 assert(!(def
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_AMD_ALIASES
));
5450 /* catch mistakes instead of silently truncating model_id when too long */
5451 assert(def
->model_id
&& strlen(def
->model_id
) <= 48);
5453 /* Unversioned model: */
5454 m
= g_new0(X86CPUModel
, 1);
5456 m
->version
= CPU_VERSION_AUTO
;
5458 x86_register_cpu_model_type(def
->name
, m
);
5460 /* Versioned models: */
5462 for (vdef
= x86_cpu_def_get_versions(def
); vdef
->version
; vdef
++) {
5463 X86CPUModel
*m
= g_new0(X86CPUModel
, 1);
5464 g_autofree
char *name
=
5465 x86_cpu_versioned_model_name(def
, vdef
->version
);
5467 m
->version
= vdef
->version
;
5468 m
->note
= vdef
->note
;
5469 x86_register_cpu_model_type(name
, m
);
5472 X86CPUModel
*am
= g_new0(X86CPUModel
, 1);
5474 am
->version
= vdef
->version
;
5475 am
->is_alias
= true;
5476 x86_register_cpu_model_type(vdef
->alias
, am
);
5482 #if !defined(CONFIG_USER_ONLY)
5484 void cpu_clear_apic_feature(CPUX86State
*env
)
5486 env
->features
[FEAT_1_EDX
] &= ~CPUID_APIC
;
5489 #endif /* !CONFIG_USER_ONLY */
5491 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
5492 uint32_t *eax
, uint32_t *ebx
,
5493 uint32_t *ecx
, uint32_t *edx
)
5495 X86CPU
*cpu
= env_archcpu(env
);
5496 CPUState
*cs
= env_cpu(env
);
5497 uint32_t die_offset
;
5499 uint32_t signature
[3];
5500 X86CPUTopoInfo topo_info
;
5502 topo_info
.dies_per_pkg
= env
->nr_dies
;
5503 topo_info
.cores_per_die
= cs
->nr_cores
;
5504 topo_info
.threads_per_core
= cs
->nr_threads
;
5506 /* Calculate & apply limits for different index ranges */
5507 if (index
>= 0xC0000000) {
5508 limit
= env
->cpuid_xlevel2
;
5509 } else if (index
>= 0x80000000) {
5510 limit
= env
->cpuid_xlevel
;
5511 } else if (index
>= 0x40000000) {
5514 limit
= env
->cpuid_level
;
5517 if (index
> limit
) {
5518 /* Intel documentation states that invalid EAX input will
5519 * return the same information as EAX=cpuid_level
5520 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
5522 index
= env
->cpuid_level
;
5527 *eax
= env
->cpuid_level
;
5528 *ebx
= env
->cpuid_vendor1
;
5529 *edx
= env
->cpuid_vendor2
;
5530 *ecx
= env
->cpuid_vendor3
;
5533 *eax
= env
->cpuid_version
;
5534 *ebx
= (cpu
->apic_id
<< 24) |
5535 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
5536 *ecx
= env
->features
[FEAT_1_ECX
];
5537 if ((*ecx
& CPUID_EXT_XSAVE
) && (env
->cr
[4] & CR4_OSXSAVE_MASK
)) {
5538 *ecx
|= CPUID_EXT_OSXSAVE
;
5540 *edx
= env
->features
[FEAT_1_EDX
];
5541 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
5542 *ebx
|= (cs
->nr_cores
* cs
->nr_threads
) << 16;
5547 /* cache info: needed for Pentium Pro compatibility */
5548 if (cpu
->cache_info_passthrough
) {
5549 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
5552 *eax
= 1; /* Number of CPUID[EAX=2] calls required */
5554 if (!cpu
->enable_l3_cache
) {
5557 *ecx
= cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l3_cache
);
5559 *edx
= (cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l1d_cache
) << 16) |
5560 (cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l1i_cache
) << 8) |
5561 (cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l2_cache
));
5564 /* cache info: needed for Core compatibility */
5565 if (cpu
->cache_info_passthrough
) {
5566 host_cpuid(index
, count
, eax
, ebx
, ecx
, edx
);
5567 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
5568 *eax
&= ~0xFC000000;
5569 if ((*eax
& 31) && cs
->nr_cores
> 1) {
5570 *eax
|= (cs
->nr_cores
- 1) << 26;
5575 case 0: /* L1 dcache info */
5576 encode_cache_cpuid4(env
->cache_info_cpuid4
.l1d_cache
,
5578 eax
, ebx
, ecx
, edx
);
5580 case 1: /* L1 icache info */
5581 encode_cache_cpuid4(env
->cache_info_cpuid4
.l1i_cache
,
5583 eax
, ebx
, ecx
, edx
);
5585 case 2: /* L2 cache info */
5586 encode_cache_cpuid4(env
->cache_info_cpuid4
.l2_cache
,
5587 cs
->nr_threads
, cs
->nr_cores
,
5588 eax
, ebx
, ecx
, edx
);
5590 case 3: /* L3 cache info */
5591 die_offset
= apicid_die_offset(&topo_info
);
5592 if (cpu
->enable_l3_cache
) {
5593 encode_cache_cpuid4(env
->cache_info_cpuid4
.l3_cache
,
5594 (1 << die_offset
), cs
->nr_cores
,
5595 eax
, ebx
, ecx
, edx
);
5599 default: /* end of info */
5600 *eax
= *ebx
= *ecx
= *edx
= 0;
5606 /* MONITOR/MWAIT Leaf */
5607 *eax
= cpu
->mwait
.eax
; /* Smallest monitor-line size in bytes */
5608 *ebx
= cpu
->mwait
.ebx
; /* Largest monitor-line size in bytes */
5609 *ecx
= cpu
->mwait
.ecx
; /* flags */
5610 *edx
= cpu
->mwait
.edx
; /* mwait substates */
5613 /* Thermal and Power Leaf */
5614 *eax
= env
->features
[FEAT_6_EAX
];
5620 /* Structured Extended Feature Flags Enumeration Leaf */
5622 /* Maximum ECX value for sub-leaves */
5623 *eax
= env
->cpuid_level_func7
;
5624 *ebx
= env
->features
[FEAT_7_0_EBX
]; /* Feature flags */
5625 *ecx
= env
->features
[FEAT_7_0_ECX
]; /* Feature flags */
5626 if ((*ecx
& CPUID_7_0_ECX_PKU
) && env
->cr
[4] & CR4_PKE_MASK
) {
5627 *ecx
|= CPUID_7_0_ECX_OSPKE
;
5629 *edx
= env
->features
[FEAT_7_0_EDX
]; /* Feature flags */
5630 } else if (count
== 1) {
5631 *eax
= env
->features
[FEAT_7_1_EAX
];
5643 /* Direct Cache Access Information Leaf */
5644 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
5650 /* Architectural Performance Monitoring Leaf */
5651 if (kvm_enabled() && cpu
->enable_pmu
) {
5652 KVMState
*s
= cs
->kvm_state
;
5654 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
5655 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
5656 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
5657 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
5658 } else if (hvf_enabled() && cpu
->enable_pmu
) {
5659 *eax
= hvf_get_supported_cpuid(0xA, count
, R_EAX
);
5660 *ebx
= hvf_get_supported_cpuid(0xA, count
, R_EBX
);
5661 *ecx
= hvf_get_supported_cpuid(0xA, count
, R_ECX
);
5662 *edx
= hvf_get_supported_cpuid(0xA, count
, R_EDX
);
5671 /* Extended Topology Enumeration Leaf */
5672 if (!cpu
->enable_cpuid_0xb
) {
5673 *eax
= *ebx
= *ecx
= *edx
= 0;
5677 *ecx
= count
& 0xff;
5678 *edx
= cpu
->apic_id
;
5682 *eax
= apicid_core_offset(&topo_info
);
5683 *ebx
= cs
->nr_threads
;
5684 *ecx
|= CPUID_TOPOLOGY_LEVEL_SMT
;
5687 *eax
= apicid_pkg_offset(&topo_info
);
5688 *ebx
= cs
->nr_cores
* cs
->nr_threads
;
5689 *ecx
|= CPUID_TOPOLOGY_LEVEL_CORE
;
5694 *ecx
|= CPUID_TOPOLOGY_LEVEL_INVALID
;
5697 assert(!(*eax
& ~0x1f));
5698 *ebx
&= 0xffff; /* The count doesn't need to be reliable. */
5701 /* V2 Extended Topology Enumeration Leaf */
5702 if (env
->nr_dies
< 2) {
5703 *eax
= *ebx
= *ecx
= *edx
= 0;
5707 *ecx
= count
& 0xff;
5708 *edx
= cpu
->apic_id
;
5711 *eax
= apicid_core_offset(&topo_info
);
5712 *ebx
= cs
->nr_threads
;
5713 *ecx
|= CPUID_TOPOLOGY_LEVEL_SMT
;
5716 *eax
= apicid_die_offset(&topo_info
);
5717 *ebx
= cs
->nr_cores
* cs
->nr_threads
;
5718 *ecx
|= CPUID_TOPOLOGY_LEVEL_CORE
;
5721 *eax
= apicid_pkg_offset(&topo_info
);
5722 *ebx
= env
->nr_dies
* cs
->nr_cores
* cs
->nr_threads
;
5723 *ecx
|= CPUID_TOPOLOGY_LEVEL_DIE
;
5728 *ecx
|= CPUID_TOPOLOGY_LEVEL_INVALID
;
5730 assert(!(*eax
& ~0x1f));
5731 *ebx
&= 0xffff; /* The count doesn't need to be reliable. */
5734 /* Processor Extended State */
5739 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
5744 *ecx
= xsave_area_size(x86_cpu_xsave_components(cpu
));
5745 *eax
= env
->features
[FEAT_XSAVE_COMP_LO
];
5746 *edx
= env
->features
[FEAT_XSAVE_COMP_HI
];
5748 * The initial value of xcr0 and ebx == 0, On host without kvm
5749 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
5750 * even through guest update xcr0, this will crash some legacy guest
5751 * (e.g., CentOS 6), So set ebx == ecx to workaroud it.
5753 *ebx
= kvm_enabled() ? *ecx
: xsave_area_size(env
->xcr0
);
5754 } else if (count
== 1) {
5755 *eax
= env
->features
[FEAT_XSAVE
];
5756 } else if (count
< ARRAY_SIZE(x86_ext_save_areas
)) {
5757 if ((x86_cpu_xsave_components(cpu
) >> count
) & 1) {
5758 const ExtSaveArea
*esa
= &x86_ext_save_areas
[count
];
5766 /* Intel Processor Trace Enumeration */
5771 if (!(env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) ||
5777 *eax
= INTEL_PT_MAX_SUBLEAF
;
5778 *ebx
= INTEL_PT_MINIMAL_EBX
;
5779 *ecx
= INTEL_PT_MINIMAL_ECX
;
5780 } else if (count
== 1) {
5781 *eax
= INTEL_PT_MTC_BITMAP
| INTEL_PT_ADDR_RANGES_NUM
;
5782 *ebx
= INTEL_PT_PSB_BITMAP
| INTEL_PT_CYCLE_BITMAP
;
5788 * CPUID code in kvm_arch_init_vcpu() ignores stuff
5789 * set here, but we restrict to TCG none the less.
5791 if (tcg_enabled() && cpu
->expose_tcg
) {
5792 memcpy(signature
, "TCGTCGTCGTCG", 12);
5794 *ebx
= signature
[0];
5795 *ecx
= signature
[1];
5796 *edx
= signature
[2];
5811 *eax
= env
->cpuid_xlevel
;
5812 *ebx
= env
->cpuid_vendor1
;
5813 *edx
= env
->cpuid_vendor2
;
5814 *ecx
= env
->cpuid_vendor3
;
5817 *eax
= env
->cpuid_version
;
5819 *ecx
= env
->features
[FEAT_8000_0001_ECX
];
5820 *edx
= env
->features
[FEAT_8000_0001_EDX
];
5822 /* The Linux kernel checks for the CMPLegacy bit and
5823 * discards multiple thread information if it is set.
5824 * So don't set it here for Intel to make Linux guests happy.
5826 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
5827 if (env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
||
5828 env
->cpuid_vendor2
!= CPUID_VENDOR_INTEL_2
||
5829 env
->cpuid_vendor3
!= CPUID_VENDOR_INTEL_3
) {
5830 *ecx
|= 1 << 1; /* CmpLegacy bit */
5837 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
5838 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
5839 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
5840 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
5843 /* cache info (L1 cache) */
5844 if (cpu
->cache_info_passthrough
) {
5845 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
5848 *eax
= (L1_DTLB_2M_ASSOC
<< 24) | (L1_DTLB_2M_ENTRIES
<< 16) | \
5849 (L1_ITLB_2M_ASSOC
<< 8) | (L1_ITLB_2M_ENTRIES
);
5850 *ebx
= (L1_DTLB_4K_ASSOC
<< 24) | (L1_DTLB_4K_ENTRIES
<< 16) | \
5851 (L1_ITLB_4K_ASSOC
<< 8) | (L1_ITLB_4K_ENTRIES
);
5852 *ecx
= encode_cache_cpuid80000005(env
->cache_info_amd
.l1d_cache
);
5853 *edx
= encode_cache_cpuid80000005(env
->cache_info_amd
.l1i_cache
);
5856 /* cache info (L2 cache) */
5857 if (cpu
->cache_info_passthrough
) {
5858 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
5861 *eax
= (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC
) << 28) | \
5862 (L2_DTLB_2M_ENTRIES
<< 16) | \
5863 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC
) << 12) | \
5864 (L2_ITLB_2M_ENTRIES
);
5865 *ebx
= (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC
) << 28) | \
5866 (L2_DTLB_4K_ENTRIES
<< 16) | \
5867 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC
) << 12) | \
5868 (L2_ITLB_4K_ENTRIES
);
5869 encode_cache_cpuid80000006(env
->cache_info_amd
.l2_cache
,
5870 cpu
->enable_l3_cache
?
5871 env
->cache_info_amd
.l3_cache
: NULL
,
5878 *edx
= env
->features
[FEAT_8000_0007_EDX
];
5881 /* virtual & phys address size in low 2 bytes. */
5882 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
5883 /* 64 bit processor */
5884 *eax
= cpu
->phys_bits
; /* configurable physical bits */
5885 if (env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_LA57
) {
5886 *eax
|= 0x00003900; /* 57 bits virtual */
5888 *eax
|= 0x00003000; /* 48 bits virtual */
5891 *eax
= cpu
->phys_bits
;
5893 *ebx
= env
->features
[FEAT_8000_0008_EBX
];
5896 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
5897 *ecx
|= (cs
->nr_cores
* cs
->nr_threads
) - 1;
5901 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
5902 *eax
= 0x00000001; /* SVM Revision */
5903 *ebx
= 0x00000010; /* nr of ASIDs */
5905 *edx
= env
->features
[FEAT_SVM
]; /* optional features */
5915 if (cpu
->cache_info_passthrough
) {
5916 host_cpuid(index
, count
, eax
, ebx
, ecx
, edx
);
5920 case 0: /* L1 dcache info */
5921 encode_cache_cpuid8000001d(env
->cache_info_amd
.l1d_cache
, cs
,
5922 eax
, ebx
, ecx
, edx
);
5924 case 1: /* L1 icache info */
5925 encode_cache_cpuid8000001d(env
->cache_info_amd
.l1i_cache
, cs
,
5926 eax
, ebx
, ecx
, edx
);
5928 case 2: /* L2 cache info */
5929 encode_cache_cpuid8000001d(env
->cache_info_amd
.l2_cache
, cs
,
5930 eax
, ebx
, ecx
, edx
);
5932 case 3: /* L3 cache info */
5933 encode_cache_cpuid8000001d(env
->cache_info_amd
.l3_cache
, cs
,
5934 eax
, ebx
, ecx
, edx
);
5936 default: /* end of info */
5937 *eax
= *ebx
= *ecx
= *edx
= 0;
5942 assert(cpu
->core_id
<= 255);
5943 encode_topo_cpuid8000001e(cs
, cpu
,
5944 eax
, ebx
, ecx
, edx
);
5947 *eax
= env
->cpuid_xlevel2
;
5953 /* Support for VIA CPU's CPUID instruction */
5954 *eax
= env
->cpuid_version
;
5957 *edx
= env
->features
[FEAT_C000_0001_EDX
];
5962 /* Reserved for the future, and now filled with zero */
5969 *eax
= sev_enabled() ? 0x2 : 0;
5970 *ebx
= sev_get_cbit_position();
5971 *ebx
|= sev_get_reduced_phys_bits() << 6;
5976 /* reserved values: zero */
5985 static void x86_cpu_reset(DeviceState
*dev
)
5987 CPUState
*s
= CPU(dev
);
5988 X86CPU
*cpu
= X86_CPU(s
);
5989 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
5990 CPUX86State
*env
= &cpu
->env
;
5995 xcc
->parent_reset(dev
);
5997 memset(env
, 0, offsetof(CPUX86State
, end_reset_fields
));
5999 env
->old_exception
= -1;
6001 /* init to reset state */
6003 env
->hflags2
|= HF2_GIF_MASK
;
6005 cpu_x86_update_cr0(env
, 0x60000010);
6006 env
->a20_mask
= ~0x0;
6007 env
->smbase
= 0x30000;
6008 env
->msr_smi_count
= 0;
6010 env
->idt
.limit
= 0xffff;
6011 env
->gdt
.limit
= 0xffff;
6012 env
->ldt
.limit
= 0xffff;
6013 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
6014 env
->tr
.limit
= 0xffff;
6015 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
6017 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
6018 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
6019 DESC_R_MASK
| DESC_A_MASK
);
6020 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
6021 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
6023 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
6024 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
6026 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
6027 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
6029 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
6030 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
6032 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
6033 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
6037 env
->regs
[R_EDX
] = env
->cpuid_version
;
6042 for (i
= 0; i
< 8; i
++) {
6045 cpu_set_fpuc(env
, 0x37f);
6047 env
->mxcsr
= 0x1f80;
6048 /* All units are in INIT state. */
6051 env
->pat
= 0x0007040600070406ULL
;
6052 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
6053 if (env
->features
[FEAT_1_ECX
] & CPUID_EXT_MONITOR
) {
6054 env
->msr_ia32_misc_enable
|= MSR_IA32_MISC_ENABLE_MWAIT
;
6057 memset(env
->dr
, 0, sizeof(env
->dr
));
6058 env
->dr
[6] = DR6_FIXED_1
;
6059 env
->dr
[7] = DR7_FIXED_1
;
6060 cpu_breakpoint_remove_all(s
, BP_CPU
);
6061 cpu_watchpoint_remove_all(s
, BP_CPU
);
6064 xcr0
= XSTATE_FP_MASK
;
6066 #ifdef CONFIG_USER_ONLY
6067 /* Enable all the features for user-mode. */
6068 if (env
->features
[FEAT_1_EDX
] & CPUID_SSE
) {
6069 xcr0
|= XSTATE_SSE_MASK
;
6071 for (i
= 2; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
6072 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
6073 if (env
->features
[esa
->feature
] & esa
->bits
) {
6078 if (env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
) {
6079 cr4
|= CR4_OSFXSR_MASK
| CR4_OSXSAVE_MASK
;
6081 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_FSGSBASE
) {
6082 cr4
|= CR4_FSGSBASE_MASK
;
6087 cpu_x86_update_cr4(env
, cr4
);
6090 * SDM 11.11.5 requires:
6091 * - IA32_MTRR_DEF_TYPE MSR.E = 0
6092 * - IA32_MTRR_PHYSMASKn.V = 0
6093 * All other bits are undefined. For simplification, zero it all.
6095 env
->mtrr_deftype
= 0;
6096 memset(env
->mtrr_var
, 0, sizeof(env
->mtrr_var
));
6097 memset(env
->mtrr_fixed
, 0, sizeof(env
->mtrr_fixed
));
6099 env
->interrupt_injected
= -1;
6100 env
->exception_nr
= -1;
6101 env
->exception_pending
= 0;
6102 env
->exception_injected
= 0;
6103 env
->exception_has_payload
= false;
6104 env
->exception_payload
= 0;
6105 env
->nmi_injected
= false;
6106 #if !defined(CONFIG_USER_ONLY)
6107 /* We hard-wire the BSP to the first CPU. */
6108 apic_designate_bsp(cpu
->apic_state
, s
->cpu_index
== 0);
6110 s
->halted
= !cpu_is_bsp(cpu
);
6112 if (kvm_enabled()) {
6113 kvm_arch_reset_vcpu(cpu
);
6115 else if (hvf_enabled()) {
6121 #ifndef CONFIG_USER_ONLY
6122 bool cpu_is_bsp(X86CPU
*cpu
)
6124 return cpu_get_apic_base(cpu
->apic_state
) & MSR_IA32_APICBASE_BSP
;
6127 /* TODO: remove me, when reset over QOM tree is implemented */
6128 static void x86_cpu_machine_reset_cb(void *opaque
)
6130 X86CPU
*cpu
= opaque
;
6131 cpu_reset(CPU(cpu
));
6135 static void mce_init(X86CPU
*cpu
)
6137 CPUX86State
*cenv
= &cpu
->env
;
6140 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
6141 && (cenv
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
6142 (CPUID_MCE
| CPUID_MCA
)) {
6143 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
|
6144 (cpu
->enable_lmce
? MCG_LMCE_P
: 0);
6145 cenv
->mcg_ctl
= ~(uint64_t)0;
6146 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
6147 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
6152 #ifndef CONFIG_USER_ONLY
6153 APICCommonClass
*apic_get_class(void)
6155 const char *apic_type
= "apic";
6157 /* TODO: in-kernel irqchip for hvf */
6158 if (kvm_apic_in_kernel()) {
6159 apic_type
= "kvm-apic";
6160 } else if (xen_enabled()) {
6161 apic_type
= "xen-apic";
6164 return APIC_COMMON_CLASS(object_class_by_name(apic_type
));
6167 static void x86_cpu_apic_create(X86CPU
*cpu
, Error
**errp
)
6169 APICCommonState
*apic
;
6170 ObjectClass
*apic_class
= OBJECT_CLASS(apic_get_class());
6172 cpu
->apic_state
= DEVICE(object_new_with_class(apic_class
));
6174 object_property_add_child(OBJECT(cpu
), "lapic",
6175 OBJECT(cpu
->apic_state
), &error_abort
);
6176 object_unref(OBJECT(cpu
->apic_state
));
6178 qdev_prop_set_uint32(cpu
->apic_state
, "id", cpu
->apic_id
);
6179 /* TODO: convert to link<> */
6180 apic
= APIC_COMMON(cpu
->apic_state
);
6182 apic
->apicbase
= APIC_DEFAULT_ADDRESS
| MSR_IA32_APICBASE_ENABLE
;
6185 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
6187 APICCommonState
*apic
;
6188 static bool apic_mmio_map_once
;
6190 if (cpu
->apic_state
== NULL
) {
6193 object_property_set_bool(OBJECT(cpu
->apic_state
), true, "realized",
6196 /* Map APIC MMIO area */
6197 apic
= APIC_COMMON(cpu
->apic_state
);
6198 if (!apic_mmio_map_once
) {
6199 memory_region_add_subregion_overlap(get_system_memory(),
6201 MSR_IA32_APICBASE_BASE
,
6204 apic_mmio_map_once
= true;
6208 static void x86_cpu_machine_done(Notifier
*n
, void *unused
)
6210 X86CPU
*cpu
= container_of(n
, X86CPU
, machine_done
);
6211 MemoryRegion
*smram
=
6212 (MemoryRegion
*) object_resolve_path("/machine/smram", NULL
);
6215 cpu
->smram
= g_new(MemoryRegion
, 1);
6216 memory_region_init_alias(cpu
->smram
, OBJECT(cpu
), "smram",
6217 smram
, 0, 1ull << 32);
6218 memory_region_set_enabled(cpu
->smram
, true);
6219 memory_region_add_subregion_overlap(cpu
->cpu_as_root
, 0, cpu
->smram
, 1);
6223 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
6228 /* Note: Only safe for use on x86(-64) hosts */
6229 static uint32_t x86_host_phys_bits(void)
6232 uint32_t host_phys_bits
;
6234 host_cpuid(0x80000000, 0, &eax
, NULL
, NULL
, NULL
);
6235 if (eax
>= 0x80000008) {
6236 host_cpuid(0x80000008, 0, &eax
, NULL
, NULL
, NULL
);
6237 /* Note: According to AMD doc 25481 rev 2.34 they have a field
6238 * at 23:16 that can specify a maximum physical address bits for
6239 * the guest that can override this value; but I've not seen
6240 * anything with that set.
6242 host_phys_bits
= eax
& 0xff;
6244 /* It's an odd 64 bit machine that doesn't have the leaf for
6245 * physical address bits; fall back to 36 that's most older
6248 host_phys_bits
= 36;
6251 return host_phys_bits
;
6254 static void x86_cpu_adjust_level(X86CPU
*cpu
, uint32_t *min
, uint32_t value
)
6261 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
6262 static void x86_cpu_adjust_feat_level(X86CPU
*cpu
, FeatureWord w
)
6264 CPUX86State
*env
= &cpu
->env
;
6265 FeatureWordInfo
*fi
= &feature_word_info
[w
];
6266 uint32_t eax
= fi
->cpuid
.eax
;
6267 uint32_t region
= eax
& 0xF0000000;
6269 assert(feature_word_info
[w
].type
== CPUID_FEATURE_WORD
);
6270 if (!env
->features
[w
]) {
6276 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_level
, eax
);
6279 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, eax
);
6282 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel2
, eax
);
6287 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_level_func7
,
6292 /* Calculate XSAVE components based on the configured CPU feature flags */
6293 static void x86_cpu_enable_xsave_components(X86CPU
*cpu
)
6295 CPUX86State
*env
= &cpu
->env
;
6299 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
6304 for (i
= 0; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
6305 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
6306 if (env
->features
[esa
->feature
] & esa
->bits
) {
6307 mask
|= (1ULL << i
);
6311 env
->features
[FEAT_XSAVE_COMP_LO
] = mask
;
6312 env
->features
[FEAT_XSAVE_COMP_HI
] = mask
>> 32;
6315 /***** Steps involved on loading and filtering CPUID data
6317 * When initializing and realizing a CPU object, the steps
6318 * involved in setting up CPUID data are:
6320 * 1) Loading CPU model definition (X86CPUDefinition). This is
6321 * implemented by x86_cpu_load_model() and should be completely
6322 * transparent, as it is done automatically by instance_init.
6323 * No code should need to look at X86CPUDefinition structs
6324 * outside instance_init.
6326 * 2) CPU expansion. This is done by realize before CPUID
6327 * filtering, and will make sure host/accelerator data is
6328 * loaded for CPU models that depend on host capabilities
6329 * (e.g. "host"). Done by x86_cpu_expand_features().
6331 * 3) CPUID filtering. This initializes extra data related to
6332 * CPUID, and checks if the host supports all capabilities
6333 * required by the CPU. Runnability of a CPU model is
6334 * determined at this step. Done by x86_cpu_filter_features().
6336 * Some operations don't require all steps to be performed.
6339 * - CPU instance creation (instance_init) will run only CPU
6340 * model loading. CPU expansion can't run at instance_init-time
6341 * because host/accelerator data may be not available yet.
6342 * - CPU realization will perform both CPU model expansion and CPUID
6343 * filtering, and return an error in case one of them fails.
6344 * - query-cpu-definitions needs to run all 3 steps. It needs
6345 * to run CPUID filtering, as the 'unavailable-features'
6346 * field is set based on the filtering results.
6347 * - The query-cpu-model-expansion QMP command only needs to run
6348 * CPU model loading and CPU expansion. It should not filter
6349 * any CPUID data based on host capabilities.
6352 /* Expand CPU configuration data, based on configured features
6353 * and host/accelerator capabilities when appropriate.
6355 static void x86_cpu_expand_features(X86CPU
*cpu
, Error
**errp
)
6357 CPUX86State
*env
= &cpu
->env
;
6361 Error
*local_err
= NULL
;
6363 for (l
= plus_features
; l
; l
= l
->next
) {
6364 const char *prop
= l
->data
;
6365 object_property_set_bool(OBJECT(cpu
), true, prop
, &local_err
);
6371 for (l
= minus_features
; l
; l
= l
->next
) {
6372 const char *prop
= l
->data
;
6373 object_property_set_bool(OBJECT(cpu
), false, prop
, &local_err
);
6379 /*TODO: Now cpu->max_features doesn't overwrite features
6380 * set using QOM properties, and we can convert
6381 * plus_features & minus_features to global properties
6382 * inside x86_cpu_parse_featurestr() too.
6384 if (cpu
->max_features
) {
6385 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
6386 /* Override only features that weren't set explicitly
6390 x86_cpu_get_supported_feature_word(w
, cpu
->migratable
) &
6391 ~env
->user_features
[w
] & \
6392 ~feature_word_info
[w
].no_autoenable_flags
;
6396 for (i
= 0; i
< ARRAY_SIZE(feature_dependencies
); i
++) {
6397 FeatureDep
*d
= &feature_dependencies
[i
];
6398 if (!(env
->features
[d
->from
.index
] & d
->from
.mask
)) {
6399 uint64_t unavailable_features
= env
->features
[d
->to
.index
] & d
->to
.mask
;
6401 /* Not an error unless the dependent feature was added explicitly. */
6402 mark_unavailable_features(cpu
, d
->to
.index
,
6403 unavailable_features
& env
->user_features
[d
->to
.index
],
6404 "This feature depends on other features that were not requested");
6406 env
->user_features
[d
->to
.index
] |= unavailable_features
;
6407 env
->features
[d
->to
.index
] &= ~unavailable_features
;
6411 if (!kvm_enabled() || !cpu
->expose_kvm
) {
6412 env
->features
[FEAT_KVM
] = 0;
6415 x86_cpu_enable_xsave_components(cpu
);
6417 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
6418 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_EBX
);
6419 if (cpu
->full_cpuid_auto_level
) {
6420 x86_cpu_adjust_feat_level(cpu
, FEAT_1_EDX
);
6421 x86_cpu_adjust_feat_level(cpu
, FEAT_1_ECX
);
6422 x86_cpu_adjust_feat_level(cpu
, FEAT_6_EAX
);
6423 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_ECX
);
6424 x86_cpu_adjust_feat_level(cpu
, FEAT_7_1_EAX
);
6425 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_EDX
);
6426 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_ECX
);
6427 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0007_EDX
);
6428 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0008_EBX
);
6429 x86_cpu_adjust_feat_level(cpu
, FEAT_C000_0001_EDX
);
6430 x86_cpu_adjust_feat_level(cpu
, FEAT_SVM
);
6431 x86_cpu_adjust_feat_level(cpu
, FEAT_XSAVE
);
6433 /* Intel Processor Trace requires CPUID[0x14] */
6434 if ((env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) &&
6435 kvm_enabled() && cpu
->intel_pt_auto_level
) {
6436 x86_cpu_adjust_level(cpu
, &cpu
->env
.cpuid_min_level
, 0x14);
6439 /* CPU topology with multi-dies support requires CPUID[0x1F] */
6440 if (env
->nr_dies
> 1) {
6441 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_level
, 0x1F);
6444 /* SVM requires CPUID[0x8000000A] */
6445 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
6446 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, 0x8000000A);
6449 /* SEV requires CPUID[0x8000001F] */
6450 if (sev_enabled()) {
6451 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, 0x8000001F);
6455 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
6456 if (env
->cpuid_level_func7
== UINT32_MAX
) {
6457 env
->cpuid_level_func7
= env
->cpuid_min_level_func7
;
6459 if (env
->cpuid_level
== UINT32_MAX
) {
6460 env
->cpuid_level
= env
->cpuid_min_level
;
6462 if (env
->cpuid_xlevel
== UINT32_MAX
) {
6463 env
->cpuid_xlevel
= env
->cpuid_min_xlevel
;
6465 if (env
->cpuid_xlevel2
== UINT32_MAX
) {
6466 env
->cpuid_xlevel2
= env
->cpuid_min_xlevel2
;
6470 if (local_err
!= NULL
) {
6471 error_propagate(errp
, local_err
);
6476 * Finishes initialization of CPUID data, filters CPU feature
6477 * words based on host availability of each feature.
6479 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
6481 static void x86_cpu_filter_features(X86CPU
*cpu
, bool verbose
)
6483 CPUX86State
*env
= &cpu
->env
;
6485 const char *prefix
= NULL
;
6488 prefix
= accel_uses_host_cpuid()
6489 ? "host doesn't support requested feature"
6490 : "TCG doesn't support requested feature";
6493 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
6494 uint64_t host_feat
=
6495 x86_cpu_get_supported_feature_word(w
, false);
6496 uint64_t requested_features
= env
->features
[w
];
6497 uint64_t unavailable_features
= requested_features
& ~host_feat
;
6498 mark_unavailable_features(cpu
, w
, unavailable_features
, prefix
);
6501 if ((env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) &&
6503 KVMState
*s
= CPU(cpu
)->kvm_state
;
6504 uint32_t eax_0
= kvm_arch_get_supported_cpuid(s
, 0x14, 0, R_EAX
);
6505 uint32_t ebx_0
= kvm_arch_get_supported_cpuid(s
, 0x14, 0, R_EBX
);
6506 uint32_t ecx_0
= kvm_arch_get_supported_cpuid(s
, 0x14, 0, R_ECX
);
6507 uint32_t eax_1
= kvm_arch_get_supported_cpuid(s
, 0x14, 1, R_EAX
);
6508 uint32_t ebx_1
= kvm_arch_get_supported_cpuid(s
, 0x14, 1, R_EBX
);
6511 ((ebx_0
& INTEL_PT_MINIMAL_EBX
) != INTEL_PT_MINIMAL_EBX
) ||
6512 ((ecx_0
& INTEL_PT_MINIMAL_ECX
) != INTEL_PT_MINIMAL_ECX
) ||
6513 ((eax_1
& INTEL_PT_MTC_BITMAP
) != INTEL_PT_MTC_BITMAP
) ||
6514 ((eax_1
& INTEL_PT_ADDR_RANGES_NUM_MASK
) <
6515 INTEL_PT_ADDR_RANGES_NUM
) ||
6516 ((ebx_1
& (INTEL_PT_PSB_BITMAP
| INTEL_PT_CYCLE_BITMAP
)) !=
6517 (INTEL_PT_PSB_BITMAP
| INTEL_PT_CYCLE_BITMAP
)) ||
6518 (ecx_0
& INTEL_PT_IP_LIP
)) {
6520 * Processor Trace capabilities aren't configurable, so if the
6521 * host can't emulate the capabilities we report on
6522 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
6524 mark_unavailable_features(cpu
, FEAT_7_0_EBX
, CPUID_7_0_EBX_INTEL_PT
, prefix
);
6529 static void x86_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
6531 CPUState
*cs
= CPU(dev
);
6532 X86CPU
*cpu
= X86_CPU(dev
);
6533 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
6534 CPUX86State
*env
= &cpu
->env
;
6535 Error
*local_err
= NULL
;
6536 static bool ht_warned
;
6538 if (xcc
->host_cpuid_required
) {
6539 if (!accel_uses_host_cpuid()) {
6540 g_autofree
char *name
= x86_cpu_class_get_model_name(xcc
);
6541 error_setg(&local_err
, "CPU model '%s' requires KVM", name
);
6546 if (cpu
->max_features
&& accel_uses_host_cpuid()) {
6547 if (enable_cpu_pm
) {
6548 host_cpuid(5, 0, &cpu
->mwait
.eax
, &cpu
->mwait
.ebx
,
6549 &cpu
->mwait
.ecx
, &cpu
->mwait
.edx
);
6550 env
->features
[FEAT_1_ECX
] |= CPUID_EXT_MONITOR
;
6552 if (kvm_enabled() && cpu
->ucode_rev
== 0) {
6553 cpu
->ucode_rev
= kvm_arch_get_supported_msr_feature(kvm_state
,
6554 MSR_IA32_UCODE_REV
);
6558 if (cpu
->ucode_rev
== 0) {
6559 /* The default is the same as KVM's. */
6560 if (IS_AMD_CPU(env
)) {
6561 cpu
->ucode_rev
= 0x01000065;
6563 cpu
->ucode_rev
= 0x100000000ULL
;
6567 /* mwait extended info: needed for Core compatibility */
6568 /* We always wake on interrupt even if host does not have the capability */
6569 cpu
->mwait
.ecx
|= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
6571 if (cpu
->apic_id
== UNASSIGNED_APIC_ID
) {
6572 error_setg(errp
, "apic-id property was not initialized properly");
6576 x86_cpu_expand_features(cpu
, &local_err
);
6581 x86_cpu_filter_features(cpu
, cpu
->check_cpuid
|| cpu
->enforce_cpuid
);
6583 if (cpu
->enforce_cpuid
&& x86_cpu_have_filtered_features(cpu
)) {
6584 error_setg(&local_err
,
6585 accel_uses_host_cpuid() ?
6586 "Host doesn't support requested features" :
6587 "TCG doesn't support requested features");
6591 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
6594 if (IS_AMD_CPU(env
)) {
6595 env
->features
[FEAT_8000_0001_EDX
] &= ~CPUID_EXT2_AMD_ALIASES
;
6596 env
->features
[FEAT_8000_0001_EDX
] |= (env
->features
[FEAT_1_EDX
]
6597 & CPUID_EXT2_AMD_ALIASES
);
6600 /* For 64bit systems think about the number of physical bits to present.
6601 * ideally this should be the same as the host; anything other than matching
6602 * the host can cause incorrect guest behaviour.
6603 * QEMU used to pick the magic value of 40 bits that corresponds to
6604 * consumer AMD devices but nothing else.
6606 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
6607 if (accel_uses_host_cpuid()) {
6608 uint32_t host_phys_bits
= x86_host_phys_bits();
6611 /* Print a warning if the user set it to a value that's not the
6614 if (cpu
->phys_bits
!= host_phys_bits
&& cpu
->phys_bits
!= 0 &&
6616 warn_report("Host physical bits (%u)"
6617 " does not match phys-bits property (%u)",
6618 host_phys_bits
, cpu
->phys_bits
);
6622 if (cpu
->host_phys_bits
) {
6623 /* The user asked for us to use the host physical bits */
6624 cpu
->phys_bits
= host_phys_bits
;
6625 if (cpu
->host_phys_bits_limit
&&
6626 cpu
->phys_bits
> cpu
->host_phys_bits_limit
) {
6627 cpu
->phys_bits
= cpu
->host_phys_bits_limit
;
6631 if (cpu
->phys_bits
&&
6632 (cpu
->phys_bits
> TARGET_PHYS_ADDR_SPACE_BITS
||
6633 cpu
->phys_bits
< 32)) {
6634 error_setg(errp
, "phys-bits should be between 32 and %u "
6636 TARGET_PHYS_ADDR_SPACE_BITS
, cpu
->phys_bits
);
6640 if (cpu
->phys_bits
&& cpu
->phys_bits
!= TCG_PHYS_ADDR_BITS
) {
6641 error_setg(errp
, "TCG only supports phys-bits=%u",
6642 TCG_PHYS_ADDR_BITS
);
6646 /* 0 means it was not explicitly set by the user (or by machine
6647 * compat_props or by the host code above). In this case, the default
6648 * is the value used by TCG (40).
6650 if (cpu
->phys_bits
== 0) {
6651 cpu
->phys_bits
= TCG_PHYS_ADDR_BITS
;
6654 /* For 32 bit systems don't use the user set value, but keep
6655 * phys_bits consistent with what we tell the guest.
6657 if (cpu
->phys_bits
!= 0) {
6658 error_setg(errp
, "phys-bits is not user-configurable in 32 bit");
6662 if (env
->features
[FEAT_1_EDX
] & CPUID_PSE36
) {
6663 cpu
->phys_bits
= 36;
6665 cpu
->phys_bits
= 32;
6669 /* Cache information initialization */
6670 if (!cpu
->legacy_cache
) {
6671 if (!xcc
->model
|| !xcc
->model
->cpudef
->cache_info
) {
6672 g_autofree
char *name
= x86_cpu_class_get_model_name(xcc
);
6674 "CPU model '%s' doesn't support legacy-cache=off", name
);
6677 env
->cache_info_cpuid2
= env
->cache_info_cpuid4
= env
->cache_info_amd
=
6678 *xcc
->model
->cpudef
->cache_info
;
6680 /* Build legacy cache information */
6681 env
->cache_info_cpuid2
.l1d_cache
= &legacy_l1d_cache
;
6682 env
->cache_info_cpuid2
.l1i_cache
= &legacy_l1i_cache
;
6683 env
->cache_info_cpuid2
.l2_cache
= &legacy_l2_cache_cpuid2
;
6684 env
->cache_info_cpuid2
.l3_cache
= &legacy_l3_cache
;
6686 env
->cache_info_cpuid4
.l1d_cache
= &legacy_l1d_cache
;
6687 env
->cache_info_cpuid4
.l1i_cache
= &legacy_l1i_cache
;
6688 env
->cache_info_cpuid4
.l2_cache
= &legacy_l2_cache
;
6689 env
->cache_info_cpuid4
.l3_cache
= &legacy_l3_cache
;
6691 env
->cache_info_amd
.l1d_cache
= &legacy_l1d_cache_amd
;
6692 env
->cache_info_amd
.l1i_cache
= &legacy_l1i_cache_amd
;
6693 env
->cache_info_amd
.l2_cache
= &legacy_l2_cache_amd
;
6694 env
->cache_info_amd
.l3_cache
= &legacy_l3_cache
;
6698 cpu_exec_realizefn(cs
, &local_err
);
6699 if (local_err
!= NULL
) {
6700 error_propagate(errp
, local_err
);
6704 #ifndef CONFIG_USER_ONLY
6705 MachineState
*ms
= MACHINE(qdev_get_machine());
6706 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
6708 if (cpu
->env
.features
[FEAT_1_EDX
] & CPUID_APIC
|| ms
->smp
.cpus
> 1) {
6709 x86_cpu_apic_create(cpu
, &local_err
);
6710 if (local_err
!= NULL
) {
6718 #ifndef CONFIG_USER_ONLY
6719 if (tcg_enabled()) {
6720 cpu
->cpu_as_mem
= g_new(MemoryRegion
, 1);
6721 cpu
->cpu_as_root
= g_new(MemoryRegion
, 1);
6723 /* Outer container... */
6724 memory_region_init(cpu
->cpu_as_root
, OBJECT(cpu
), "memory", ~0ull);
6725 memory_region_set_enabled(cpu
->cpu_as_root
, true);
6727 /* ... with two regions inside: normal system memory with low
6730 memory_region_init_alias(cpu
->cpu_as_mem
, OBJECT(cpu
), "memory",
6731 get_system_memory(), 0, ~0ull);
6732 memory_region_add_subregion_overlap(cpu
->cpu_as_root
, 0, cpu
->cpu_as_mem
, 0);
6733 memory_region_set_enabled(cpu
->cpu_as_mem
, true);
6736 cpu_address_space_init(cs
, 0, "cpu-memory", cs
->memory
);
6737 cpu_address_space_init(cs
, 1, "cpu-smm", cpu
->cpu_as_root
);
6739 /* ... SMRAM with higher priority, linked from /machine/smram. */
6740 cpu
->machine_done
.notify
= x86_cpu_machine_done
;
6741 qemu_add_machine_init_done_notifier(&cpu
->machine_done
);
6748 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
6749 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
6750 * based on inputs (sockets,cores,threads), it is still better to give
6753 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
6754 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
6756 if (IS_AMD_CPU(env
) &&
6757 !(env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_TOPOEXT
) &&
6758 cs
->nr_threads
> 1 && !ht_warned
) {
6759 warn_report("This family of AMD CPU doesn't support "
6760 "hyperthreading(%d)",
6762 error_printf("Please configure -smp options properly"
6763 " or try enabling topoext feature.\n");
6767 x86_cpu_apic_realize(cpu
, &local_err
);
6768 if (local_err
!= NULL
) {
6773 xcc
->parent_realize(dev
, &local_err
);
6776 if (local_err
!= NULL
) {
6777 error_propagate(errp
, local_err
);
6782 static void x86_cpu_unrealizefn(DeviceState
*dev
, Error
**errp
)
6784 X86CPU
*cpu
= X86_CPU(dev
);
6785 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
6786 Error
*local_err
= NULL
;
6788 #ifndef CONFIG_USER_ONLY
6789 cpu_remove_sync(CPU(dev
));
6790 qemu_unregister_reset(x86_cpu_machine_reset_cb
, dev
);
6793 if (cpu
->apic_state
) {
6794 object_unparent(OBJECT(cpu
->apic_state
));
6795 cpu
->apic_state
= NULL
;
6798 xcc
->parent_unrealize(dev
, &local_err
);
6799 if (local_err
!= NULL
) {
6800 error_propagate(errp
, local_err
);
6805 typedef struct BitProperty
{
6810 static void x86_cpu_get_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
6811 void *opaque
, Error
**errp
)
6813 X86CPU
*cpu
= X86_CPU(obj
);
6814 BitProperty
*fp
= opaque
;
6815 uint64_t f
= cpu
->env
.features
[fp
->w
];
6816 bool value
= (f
& fp
->mask
) == fp
->mask
;
6817 visit_type_bool(v
, name
, &value
, errp
);
6820 static void x86_cpu_set_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
6821 void *opaque
, Error
**errp
)
6823 DeviceState
*dev
= DEVICE(obj
);
6824 X86CPU
*cpu
= X86_CPU(obj
);
6825 BitProperty
*fp
= opaque
;
6826 Error
*local_err
= NULL
;
6829 if (dev
->realized
) {
6830 qdev_prop_set_after_realize(dev
, name
, errp
);
6834 visit_type_bool(v
, name
, &value
, &local_err
);
6836 error_propagate(errp
, local_err
);
6841 cpu
->env
.features
[fp
->w
] |= fp
->mask
;
6843 cpu
->env
.features
[fp
->w
] &= ~fp
->mask
;
6845 cpu
->env
.user_features
[fp
->w
] |= fp
->mask
;
6848 static void x86_cpu_release_bit_prop(Object
*obj
, const char *name
,
6851 BitProperty
*prop
= opaque
;
6855 /* Register a boolean property to get/set a single bit in a uint32_t field.
6857 * The same property name can be registered multiple times to make it affect
6858 * multiple bits in the same FeatureWord. In that case, the getter will return
6859 * true only if all bits are set.
6861 static void x86_cpu_register_bit_prop(X86CPU
*cpu
,
6862 const char *prop_name
,
6868 uint64_t mask
= (1ULL << bitnr
);
6870 op
= object_property_find(OBJECT(cpu
), prop_name
, NULL
);
6876 fp
= g_new0(BitProperty
, 1);
6879 object_property_add(OBJECT(cpu
), prop_name
, "bool",
6880 x86_cpu_get_bit_prop
,
6881 x86_cpu_set_bit_prop
,
6882 x86_cpu_release_bit_prop
, fp
, &error_abort
);
6886 static void x86_cpu_register_feature_bit_props(X86CPU
*cpu
,
6890 FeatureWordInfo
*fi
= &feature_word_info
[w
];
6891 const char *name
= fi
->feat_names
[bitnr
];
6897 /* Property names should use "-" instead of "_".
6898 * Old names containing underscores are registered as aliases
6899 * using object_property_add_alias()
6901 assert(!strchr(name
, '_'));
6902 /* aliases don't use "|" delimiters anymore, they are registered
6903 * manually using object_property_add_alias() */
6904 assert(!strchr(name
, '|'));
6905 x86_cpu_register_bit_prop(cpu
, name
, w
, bitnr
);
6908 static GuestPanicInformation
*x86_cpu_get_crash_info(CPUState
*cs
)
6910 X86CPU
*cpu
= X86_CPU(cs
);
6911 CPUX86State
*env
= &cpu
->env
;
6912 GuestPanicInformation
*panic_info
= NULL
;
6914 if (env
->features
[FEAT_HYPERV_EDX
] & HV_GUEST_CRASH_MSR_AVAILABLE
) {
6915 panic_info
= g_malloc0(sizeof(GuestPanicInformation
));
6917 panic_info
->type
= GUEST_PANIC_INFORMATION_TYPE_HYPER_V
;
6919 assert(HV_CRASH_PARAMS
>= 5);
6920 panic_info
->u
.hyper_v
.arg1
= env
->msr_hv_crash_params
[0];
6921 panic_info
->u
.hyper_v
.arg2
= env
->msr_hv_crash_params
[1];
6922 panic_info
->u
.hyper_v
.arg3
= env
->msr_hv_crash_params
[2];
6923 panic_info
->u
.hyper_v
.arg4
= env
->msr_hv_crash_params
[3];
6924 panic_info
->u
.hyper_v
.arg5
= env
->msr_hv_crash_params
[4];
6929 static void x86_cpu_get_crash_info_qom(Object
*obj
, Visitor
*v
,
6930 const char *name
, void *opaque
,
6933 CPUState
*cs
= CPU(obj
);
6934 GuestPanicInformation
*panic_info
;
6936 if (!cs
->crash_occurred
) {
6937 error_setg(errp
, "No crash occured");
6941 panic_info
= x86_cpu_get_crash_info(cs
);
6942 if (panic_info
== NULL
) {
6943 error_setg(errp
, "No crash information");
6947 visit_type_GuestPanicInformation(v
, "crash-information", &panic_info
,
6949 qapi_free_GuestPanicInformation(panic_info
);
6952 static void x86_cpu_initfn(Object
*obj
)
6954 X86CPU
*cpu
= X86_CPU(obj
);
6955 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(obj
);
6956 CPUX86State
*env
= &cpu
->env
;
6961 cpu_set_cpustate_pointers(cpu
);
6963 object_property_add(obj
, "family", "int",
6964 x86_cpuid_version_get_family
,
6965 x86_cpuid_version_set_family
, NULL
, NULL
, NULL
);
6966 object_property_add(obj
, "model", "int",
6967 x86_cpuid_version_get_model
,
6968 x86_cpuid_version_set_model
, NULL
, NULL
, NULL
);
6969 object_property_add(obj
, "stepping", "int",
6970 x86_cpuid_version_get_stepping
,
6971 x86_cpuid_version_set_stepping
, NULL
, NULL
, NULL
);
6972 object_property_add_str(obj
, "vendor",
6973 x86_cpuid_get_vendor
,
6974 x86_cpuid_set_vendor
, NULL
);
6975 object_property_add_str(obj
, "model-id",
6976 x86_cpuid_get_model_id
,
6977 x86_cpuid_set_model_id
, NULL
);
6978 object_property_add(obj
, "tsc-frequency", "int",
6979 x86_cpuid_get_tsc_freq
,
6980 x86_cpuid_set_tsc_freq
, NULL
, NULL
, NULL
);
6981 object_property_add(obj
, "feature-words", "X86CPUFeatureWordInfo",
6982 x86_cpu_get_feature_words
,
6983 NULL
, NULL
, (void *)env
->features
, NULL
);
6984 object_property_add(obj
, "filtered-features", "X86CPUFeatureWordInfo",
6985 x86_cpu_get_feature_words
,
6986 NULL
, NULL
, (void *)cpu
->filtered_features
, NULL
);
6988 * The "unavailable-features" property has the same semantics as
6989 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
6990 * QMP command: they list the features that would have prevented the
6991 * CPU from running if the "enforce" flag was set.
6993 object_property_add(obj
, "unavailable-features", "strList",
6994 x86_cpu_get_unavailable_features
,
6995 NULL
, NULL
, NULL
, &error_abort
);
6997 object_property_add(obj
, "crash-information", "GuestPanicInformation",
6998 x86_cpu_get_crash_info_qom
, NULL
, NULL
, NULL
, NULL
);
7000 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
7003 for (bitnr
= 0; bitnr
< 64; bitnr
++) {
7004 x86_cpu_register_feature_bit_props(cpu
, w
, bitnr
);
7008 object_property_add_alias(obj
, "sse3", obj
, "pni", &error_abort
);
7009 object_property_add_alias(obj
, "pclmuldq", obj
, "pclmulqdq", &error_abort
);
7010 object_property_add_alias(obj
, "sse4-1", obj
, "sse4.1", &error_abort
);
7011 object_property_add_alias(obj
, "sse4-2", obj
, "sse4.2", &error_abort
);
7012 object_property_add_alias(obj
, "xd", obj
, "nx", &error_abort
);
7013 object_property_add_alias(obj
, "ffxsr", obj
, "fxsr-opt", &error_abort
);
7014 object_property_add_alias(obj
, "i64", obj
, "lm", &error_abort
);
7016 object_property_add_alias(obj
, "ds_cpl", obj
, "ds-cpl", &error_abort
);
7017 object_property_add_alias(obj
, "tsc_adjust", obj
, "tsc-adjust", &error_abort
);
7018 object_property_add_alias(obj
, "fxsr_opt", obj
, "fxsr-opt", &error_abort
);
7019 object_property_add_alias(obj
, "lahf_lm", obj
, "lahf-lm", &error_abort
);
7020 object_property_add_alias(obj
, "cmp_legacy", obj
, "cmp-legacy", &error_abort
);
7021 object_property_add_alias(obj
, "nodeid_msr", obj
, "nodeid-msr", &error_abort
);
7022 object_property_add_alias(obj
, "perfctr_core", obj
, "perfctr-core", &error_abort
);
7023 object_property_add_alias(obj
, "perfctr_nb", obj
, "perfctr-nb", &error_abort
);
7024 object_property_add_alias(obj
, "kvm_nopiodelay", obj
, "kvm-nopiodelay", &error_abort
);
7025 object_property_add_alias(obj
, "kvm_mmu", obj
, "kvm-mmu", &error_abort
);
7026 object_property_add_alias(obj
, "kvm_asyncpf", obj
, "kvm-asyncpf", &error_abort
);
7027 object_property_add_alias(obj
, "kvm_steal_time", obj
, "kvm-steal-time", &error_abort
);
7028 object_property_add_alias(obj
, "kvm_pv_eoi", obj
, "kvm-pv-eoi", &error_abort
);
7029 object_property_add_alias(obj
, "kvm_pv_unhalt", obj
, "kvm-pv-unhalt", &error_abort
);
7030 object_property_add_alias(obj
, "kvm_poll_control", obj
, "kvm-poll-control",
7032 object_property_add_alias(obj
, "svm_lock", obj
, "svm-lock", &error_abort
);
7033 object_property_add_alias(obj
, "nrip_save", obj
, "nrip-save", &error_abort
);
7034 object_property_add_alias(obj
, "tsc_scale", obj
, "tsc-scale", &error_abort
);
7035 object_property_add_alias(obj
, "vmcb_clean", obj
, "vmcb-clean", &error_abort
);
7036 object_property_add_alias(obj
, "pause_filter", obj
, "pause-filter", &error_abort
);
7037 object_property_add_alias(obj
, "sse4_1", obj
, "sse4.1", &error_abort
);
7038 object_property_add_alias(obj
, "sse4_2", obj
, "sse4.2", &error_abort
);
7041 x86_cpu_load_model(cpu
, xcc
->model
, &error_abort
);
7045 static int64_t x86_cpu_get_arch_id(CPUState
*cs
)
7047 X86CPU
*cpu
= X86_CPU(cs
);
7049 return cpu
->apic_id
;
7052 static bool x86_cpu_get_paging_enabled(const CPUState
*cs
)
7054 X86CPU
*cpu
= X86_CPU(cs
);
7056 return cpu
->env
.cr
[0] & CR0_PG_MASK
;
7059 static void x86_cpu_set_pc(CPUState
*cs
, vaddr value
)
7061 X86CPU
*cpu
= X86_CPU(cs
);
7063 cpu
->env
.eip
= value
;
7066 static void x86_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
7068 X86CPU
*cpu
= X86_CPU(cs
);
7070 cpu
->env
.eip
= tb
->pc
- tb
->cs_base
;
7073 int x86_cpu_pending_interrupt(CPUState
*cs
, int interrupt_request
)
7075 X86CPU
*cpu
= X86_CPU(cs
);
7076 CPUX86State
*env
= &cpu
->env
;
7078 #if !defined(CONFIG_USER_ONLY)
7079 if (interrupt_request
& CPU_INTERRUPT_POLL
) {
7080 return CPU_INTERRUPT_POLL
;
7083 if (interrupt_request
& CPU_INTERRUPT_SIPI
) {
7084 return CPU_INTERRUPT_SIPI
;
7087 if (env
->hflags2
& HF2_GIF_MASK
) {
7088 if ((interrupt_request
& CPU_INTERRUPT_SMI
) &&
7089 !(env
->hflags
& HF_SMM_MASK
)) {
7090 return CPU_INTERRUPT_SMI
;
7091 } else if ((interrupt_request
& CPU_INTERRUPT_NMI
) &&
7092 !(env
->hflags2
& HF2_NMI_MASK
)) {
7093 return CPU_INTERRUPT_NMI
;
7094 } else if (interrupt_request
& CPU_INTERRUPT_MCE
) {
7095 return CPU_INTERRUPT_MCE
;
7096 } else if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
7097 (((env
->hflags2
& HF2_VINTR_MASK
) &&
7098 (env
->hflags2
& HF2_HIF_MASK
)) ||
7099 (!(env
->hflags2
& HF2_VINTR_MASK
) &&
7100 (env
->eflags
& IF_MASK
&&
7101 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
))))) {
7102 return CPU_INTERRUPT_HARD
;
7103 #if !defined(CONFIG_USER_ONLY)
7104 } else if ((interrupt_request
& CPU_INTERRUPT_VIRQ
) &&
7105 (env
->eflags
& IF_MASK
) &&
7106 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
)) {
7107 return CPU_INTERRUPT_VIRQ
;
7115 static bool x86_cpu_has_work(CPUState
*cs
)
7117 return x86_cpu_pending_interrupt(cs
, cs
->interrupt_request
) != 0;
7120 static void x86_disas_set_info(CPUState
*cs
, disassemble_info
*info
)
7122 X86CPU
*cpu
= X86_CPU(cs
);
7123 CPUX86State
*env
= &cpu
->env
;
7125 info
->mach
= (env
->hflags
& HF_CS64_MASK
? bfd_mach_x86_64
7126 : env
->hflags
& HF_CS32_MASK
? bfd_mach_i386_i386
7127 : bfd_mach_i386_i8086
);
7128 info
->print_insn
= print_insn_i386
;
7130 info
->cap_arch
= CS_ARCH_X86
;
7131 info
->cap_mode
= (env
->hflags
& HF_CS64_MASK
? CS_MODE_64
7132 : env
->hflags
& HF_CS32_MASK
? CS_MODE_32
7134 info
->cap_insn_unit
= 1;
7135 info
->cap_insn_split
= 8;
7138 void x86_update_hflags(CPUX86State
*env
)
7141 #define HFLAG_COPY_MASK \
7142 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
7143 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
7144 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
7145 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
7147 hflags
= env
->hflags
& HFLAG_COPY_MASK
;
7148 hflags
|= (env
->segs
[R_SS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
7149 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
7150 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
7151 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
7152 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
7154 if (env
->cr
[4] & CR4_OSFXSR_MASK
) {
7155 hflags
|= HF_OSFXSR_MASK
;
7158 if (env
->efer
& MSR_EFER_LMA
) {
7159 hflags
|= HF_LMA_MASK
;
7162 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
7163 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
7165 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
7166 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
7167 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
7168 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
7169 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
) ||
7170 !(hflags
& HF_CS32_MASK
)) {
7171 hflags
|= HF_ADDSEG_MASK
;
7173 hflags
|= ((env
->segs
[R_DS
].base
| env
->segs
[R_ES
].base
|
7174 env
->segs
[R_SS
].base
) != 0) << HF_ADDSEG_SHIFT
;
7177 env
->hflags
= hflags
;
7180 static Property x86_cpu_properties
[] = {
7181 #ifdef CONFIG_USER_ONLY
7182 /* apic_id = 0 by default for *-user, see commit 9886e834 */
7183 DEFINE_PROP_UINT32("apic-id", X86CPU
, apic_id
, 0),
7184 DEFINE_PROP_INT32("thread-id", X86CPU
, thread_id
, 0),
7185 DEFINE_PROP_INT32("core-id", X86CPU
, core_id
, 0),
7186 DEFINE_PROP_INT32("die-id", X86CPU
, die_id
, 0),
7187 DEFINE_PROP_INT32("socket-id", X86CPU
, socket_id
, 0),
7189 DEFINE_PROP_UINT32("apic-id", X86CPU
, apic_id
, UNASSIGNED_APIC_ID
),
7190 DEFINE_PROP_INT32("thread-id", X86CPU
, thread_id
, -1),
7191 DEFINE_PROP_INT32("core-id", X86CPU
, core_id
, -1),
7192 DEFINE_PROP_INT32("die-id", X86CPU
, die_id
, -1),
7193 DEFINE_PROP_INT32("socket-id", X86CPU
, socket_id
, -1),
7195 DEFINE_PROP_INT32("node-id", X86CPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
7196 DEFINE_PROP_BOOL("pmu", X86CPU
, enable_pmu
, false),
7198 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU
, hyperv_spinlock_attempts
,
7199 HYPERV_SPINLOCK_NEVER_RETRY
),
7200 DEFINE_PROP_BIT64("hv-relaxed", X86CPU
, hyperv_features
,
7201 HYPERV_FEAT_RELAXED
, 0),
7202 DEFINE_PROP_BIT64("hv-vapic", X86CPU
, hyperv_features
,
7203 HYPERV_FEAT_VAPIC
, 0),
7204 DEFINE_PROP_BIT64("hv-time", X86CPU
, hyperv_features
,
7205 HYPERV_FEAT_TIME
, 0),
7206 DEFINE_PROP_BIT64("hv-crash", X86CPU
, hyperv_features
,
7207 HYPERV_FEAT_CRASH
, 0),
7208 DEFINE_PROP_BIT64("hv-reset", X86CPU
, hyperv_features
,
7209 HYPERV_FEAT_RESET
, 0),
7210 DEFINE_PROP_BIT64("hv-vpindex", X86CPU
, hyperv_features
,
7211 HYPERV_FEAT_VPINDEX
, 0),
7212 DEFINE_PROP_BIT64("hv-runtime", X86CPU
, hyperv_features
,
7213 HYPERV_FEAT_RUNTIME
, 0),
7214 DEFINE_PROP_BIT64("hv-synic", X86CPU
, hyperv_features
,
7215 HYPERV_FEAT_SYNIC
, 0),
7216 DEFINE_PROP_BIT64("hv-stimer", X86CPU
, hyperv_features
,
7217 HYPERV_FEAT_STIMER
, 0),
7218 DEFINE_PROP_BIT64("hv-frequencies", X86CPU
, hyperv_features
,
7219 HYPERV_FEAT_FREQUENCIES
, 0),
7220 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU
, hyperv_features
,
7221 HYPERV_FEAT_REENLIGHTENMENT
, 0),
7222 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU
, hyperv_features
,
7223 HYPERV_FEAT_TLBFLUSH
, 0),
7224 DEFINE_PROP_BIT64("hv-evmcs", X86CPU
, hyperv_features
,
7225 HYPERV_FEAT_EVMCS
, 0),
7226 DEFINE_PROP_BIT64("hv-ipi", X86CPU
, hyperv_features
,
7227 HYPERV_FEAT_IPI
, 0),
7228 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU
, hyperv_features
,
7229 HYPERV_FEAT_STIMER_DIRECT
, 0),
7230 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU
,
7231 hyperv_no_nonarch_cs
, ON_OFF_AUTO_OFF
),
7232 DEFINE_PROP_BOOL("hv-passthrough", X86CPU
, hyperv_passthrough
, false),
7234 DEFINE_PROP_BOOL("check", X86CPU
, check_cpuid
, true),
7235 DEFINE_PROP_BOOL("enforce", X86CPU
, enforce_cpuid
, false),
7236 DEFINE_PROP_BOOL("x-force-features", X86CPU
, force_features
, false),
7237 DEFINE_PROP_BOOL("kvm", X86CPU
, expose_kvm
, true),
7238 DEFINE_PROP_UINT32("phys-bits", X86CPU
, phys_bits
, 0),
7239 DEFINE_PROP_BOOL("host-phys-bits", X86CPU
, host_phys_bits
, false),
7240 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU
, host_phys_bits_limit
, 0),
7241 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU
, fill_mtrr_mask
, true),
7242 DEFINE_PROP_UINT32("level-func7", X86CPU
, env
.cpuid_level_func7
,
7244 DEFINE_PROP_UINT32("level", X86CPU
, env
.cpuid_level
, UINT32_MAX
),
7245 DEFINE_PROP_UINT32("xlevel", X86CPU
, env
.cpuid_xlevel
, UINT32_MAX
),
7246 DEFINE_PROP_UINT32("xlevel2", X86CPU
, env
.cpuid_xlevel2
, UINT32_MAX
),
7247 DEFINE_PROP_UINT32("min-level", X86CPU
, env
.cpuid_min_level
, 0),
7248 DEFINE_PROP_UINT32("min-xlevel", X86CPU
, env
.cpuid_min_xlevel
, 0),
7249 DEFINE_PROP_UINT32("min-xlevel2", X86CPU
, env
.cpuid_min_xlevel2
, 0),
7250 DEFINE_PROP_UINT64("ucode-rev", X86CPU
, ucode_rev
, 0),
7251 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU
, full_cpuid_auto_level
, true),
7252 DEFINE_PROP_STRING("hv-vendor-id", X86CPU
, hyperv_vendor_id
),
7253 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU
, enable_cpuid_0xb
, true),
7254 DEFINE_PROP_BOOL("lmce", X86CPU
, enable_lmce
, false),
7255 DEFINE_PROP_BOOL("l3-cache", X86CPU
, enable_l3_cache
, true),
7256 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU
, kvm_no_smi_migration
,
7258 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU
, vmware_cpuid_freq
, true),
7259 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU
, expose_tcg
, true),
7260 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU
, migrate_smi_count
,
7263 * lecacy_cache defaults to true unless the CPU model provides its
7264 * own cache information (see x86_cpu_load_def()).
7266 DEFINE_PROP_BOOL("legacy-cache", X86CPU
, legacy_cache
, true),
7269 * From "Requirements for Implementing the Microsoft
7270 * Hypervisor Interface":
7271 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
7273 * "Starting with Windows Server 2012 and Windows 8, if
7274 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
7275 * the hypervisor imposes no specific limit to the number of VPs.
7276 * In this case, Windows Server 2012 guest VMs may use more than
7277 * 64 VPs, up to the maximum supported number of processors applicable
7278 * to the specific Windows version being used."
7280 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU
, hv_max_vps
, -1),
7281 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU
, hyperv_synic_kvm_only
,
7283 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU
, intel_pt_auto_level
,
7285 DEFINE_PROP_END_OF_LIST()
7288 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
7290 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
7291 CPUClass
*cc
= CPU_CLASS(oc
);
7292 DeviceClass
*dc
= DEVICE_CLASS(oc
);
7294 device_class_set_parent_realize(dc
, x86_cpu_realizefn
,
7295 &xcc
->parent_realize
);
7296 device_class_set_parent_unrealize(dc
, x86_cpu_unrealizefn
,
7297 &xcc
->parent_unrealize
);
7298 device_class_set_props(dc
, x86_cpu_properties
);
7300 device_class_set_parent_reset(dc
, x86_cpu_reset
, &xcc
->parent_reset
);
7301 cc
->reset_dump_flags
= CPU_DUMP_FPU
| CPU_DUMP_CCOP
;
7303 cc
->class_by_name
= x86_cpu_class_by_name
;
7304 cc
->parse_features
= x86_cpu_parse_featurestr
;
7305 cc
->has_work
= x86_cpu_has_work
;
7307 cc
->do_interrupt
= x86_cpu_do_interrupt
;
7308 cc
->cpu_exec_interrupt
= x86_cpu_exec_interrupt
;
7310 cc
->dump_state
= x86_cpu_dump_state
;
7311 cc
->get_crash_info
= x86_cpu_get_crash_info
;
7312 cc
->set_pc
= x86_cpu_set_pc
;
7313 cc
->synchronize_from_tb
= x86_cpu_synchronize_from_tb
;
7314 cc
->gdb_read_register
= x86_cpu_gdb_read_register
;
7315 cc
->gdb_write_register
= x86_cpu_gdb_write_register
;
7316 cc
->get_arch_id
= x86_cpu_get_arch_id
;
7317 cc
->get_paging_enabled
= x86_cpu_get_paging_enabled
;
7318 #ifndef CONFIG_USER_ONLY
7319 cc
->asidx_from_attrs
= x86_asidx_from_attrs
;
7320 cc
->get_memory_mapping
= x86_cpu_get_memory_mapping
;
7321 cc
->get_phys_page_attrs_debug
= x86_cpu_get_phys_page_attrs_debug
;
7322 cc
->write_elf64_note
= x86_cpu_write_elf64_note
;
7323 cc
->write_elf64_qemunote
= x86_cpu_write_elf64_qemunote
;
7324 cc
->write_elf32_note
= x86_cpu_write_elf32_note
;
7325 cc
->write_elf32_qemunote
= x86_cpu_write_elf32_qemunote
;
7326 cc
->vmsd
= &vmstate_x86_cpu
;
7328 cc
->gdb_arch_name
= x86_gdb_arch_name
;
7329 #ifdef TARGET_X86_64
7330 cc
->gdb_core_xml_file
= "i386-64bit.xml";
7331 cc
->gdb_num_core_regs
= 66;
7333 cc
->gdb_core_xml_file
= "i386-32bit.xml";
7334 cc
->gdb_num_core_regs
= 50;
7336 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
7337 cc
->debug_excp_handler
= breakpoint_handler
;
7339 cc
->cpu_exec_enter
= x86_cpu_exec_enter
;
7340 cc
->cpu_exec_exit
= x86_cpu_exec_exit
;
7342 cc
->tcg_initialize
= tcg_x86_init
;
7343 cc
->tlb_fill
= x86_cpu_tlb_fill
;
7345 cc
->disas_set_info
= x86_disas_set_info
;
7347 dc
->user_creatable
= true;
7350 static const TypeInfo x86_cpu_type_info
= {
7351 .name
= TYPE_X86_CPU
,
7353 .instance_size
= sizeof(X86CPU
),
7354 .instance_init
= x86_cpu_initfn
,
7356 .class_size
= sizeof(X86CPUClass
),
7357 .class_init
= x86_cpu_common_class_init
,
7361 /* "base" CPU model, used by query-cpu-model-expansion */
7362 static void x86_cpu_base_class_init(ObjectClass
*oc
, void *data
)
7364 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
7366 xcc
->static_model
= true;
7367 xcc
->migration_safe
= true;
7368 xcc
->model_description
= "base CPU model type with no features enabled";
7372 static const TypeInfo x86_base_cpu_type_info
= {
7373 .name
= X86_CPU_TYPE_NAME("base"),
7374 .parent
= TYPE_X86_CPU
,
7375 .class_init
= x86_cpu_base_class_init
,
7378 static void x86_cpu_register_types(void)
7382 type_register_static(&x86_cpu_type_info
);
7383 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
7384 x86_register_cpudef_types(&builtin_x86_defs
[i
]);
7386 type_register_static(&max_x86_cpu_type_info
);
7387 type_register_static(&x86_base_cpu_type_info
);
7388 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
7389 type_register_static(&host_x86_cpu_type_info
);
7393 type_init(x86_cpu_register_types
)