2 * LatticeMico32 main translation routines.
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
32 #include "lm32-decode.h"
33 #include "qemu-common.h"
35 #include "hw/lm32_pic.h"
42 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
44 # define LOG_DIS(...) do { } while (0)
47 #define EXTRACT_FIELD(src, start, end) \
48 (((src) >> start) & ((1 << (end - start + 1)) - 1))
52 static TCGv_ptr cpu_env
;
53 static TCGv cpu_R
[32];
63 static TCGv cpu_bp
[4];
64 static TCGv cpu_wp
[4];
66 #include "gen-icount.h"
75 /* This is the state at translation time. */
76 typedef struct DisasContext
{
84 uint8_t r0
, r1
, r2
, csr
;
89 unsigned int delayed_branch
;
90 unsigned int tb_flags
, synced_flags
; /* tb dependent flags. */
94 struct TranslationBlock
*tb
;
95 int singlestep_enabled
;
98 static const char *regnames
[] = {
99 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
100 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
101 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
102 "r24", "r25", "r26/gp", "r27/fp", "r28/sp", "r29/ra",
103 "r30/ea", "r31/ba", "bp0", "bp1", "bp2", "bp3", "wp0",
107 static inline int zero_extend(unsigned int val
, int width
)
109 return val
& ((1 << width
) - 1);
112 static inline int sign_extend(unsigned int val
, int width
)
125 static inline void t_gen_raise_exception(DisasContext
*dc
, uint32_t index
)
127 TCGv_i32 tmp
= tcg_const_i32(index
);
129 gen_helper_raise_exception(tmp
);
130 tcg_temp_free_i32(tmp
);
133 static void gen_goto_tb(DisasContext
*dc
, int n
, target_ulong dest
)
135 TranslationBlock
*tb
;
138 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
139 likely(!dc
->singlestep_enabled
)) {
141 tcg_gen_movi_tl(cpu_pc
, dest
);
142 tcg_gen_exit_tb((long)tb
+ n
);
144 tcg_gen_movi_tl(cpu_pc
, dest
);
145 if (dc
->singlestep_enabled
) {
146 t_gen_raise_exception(dc
, EXCP_DEBUG
);
152 static void dec_add(DisasContext
*dc
)
154 if (dc
->format
== OP_FMT_RI
) {
155 if (dc
->r0
== R_R0
) {
156 if (dc
->r1
== R_R0
&& dc
->imm16
== 0) {
159 LOG_DIS("mvi r%d, %d\n", dc
->r1
, sign_extend(dc
->imm16
, 16));
162 LOG_DIS("addi r%d, r%d, %d\n", dc
->r1
, dc
->r0
,
163 sign_extend(dc
->imm16
, 16));
166 LOG_DIS("add r%d, r%d, r%d\n", dc
->r2
, dc
->r0
, dc
->r1
);
169 if (dc
->format
== OP_FMT_RI
) {
170 tcg_gen_addi_tl(cpu_R
[dc
->r1
], cpu_R
[dc
->r0
],
171 sign_extend(dc
->imm16
, 16));
173 tcg_gen_add_tl(cpu_R
[dc
->r2
], cpu_R
[dc
->r0
], cpu_R
[dc
->r1
]);
177 static void dec_and(DisasContext
*dc
)
179 if (dc
->format
== OP_FMT_RI
) {
180 LOG_DIS("andi r%d, r%d, %d\n", dc
->r1
, dc
->r0
,
181 zero_extend(dc
->imm16
, 16));
183 LOG_DIS("and r%d, r%d, r%d\n", dc
->r2
, dc
->r0
, dc
->r1
);
186 if (dc
->format
== OP_FMT_RI
) {
187 tcg_gen_andi_tl(cpu_R
[dc
->r1
], cpu_R
[dc
->r0
],
188 zero_extend(dc
->imm16
, 16));
190 if (dc
->r0
== 0 && dc
->r1
== 0 && dc
->r2
== 0) {
191 tcg_gen_movi_tl(cpu_pc
, dc
->pc
+ 4);
194 tcg_gen_and_tl(cpu_R
[dc
->r2
], cpu_R
[dc
->r0
], cpu_R
[dc
->r1
]);
199 static void dec_andhi(DisasContext
*dc
)
201 LOG_DIS("andhi r%d, r%d, %d\n", dc
->r2
, dc
->r0
, dc
->imm16
);
203 tcg_gen_andi_tl(cpu_R
[dc
->r1
], cpu_R
[dc
->r0
], (dc
->imm16
<< 16));
206 static void dec_b(DisasContext
*dc
)
208 if (dc
->r0
== R_RA
) {
210 } else if (dc
->r0
== R_EA
) {
212 } else if (dc
->r0
== R_BA
) {
215 LOG_DIS("b r%d\n", dc
->r0
);
218 /* restore IE.IE in case of an eret */
219 if (dc
->r0
== R_EA
) {
220 TCGv t0
= tcg_temp_new();
221 int l1
= gen_new_label();
222 tcg_gen_andi_tl(t0
, cpu_ie
, IE_EIE
);
223 tcg_gen_ori_tl(cpu_ie
, cpu_ie
, IE_IE
);
224 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, IE_EIE
, l1
);
225 tcg_gen_andi_tl(cpu_ie
, cpu_ie
, ~IE_IE
);
228 } else if (dc
->r0
== R_BA
) {
229 TCGv t0
= tcg_temp_new();
230 int l1
= gen_new_label();
231 tcg_gen_andi_tl(t0
, cpu_ie
, IE_BIE
);
232 tcg_gen_ori_tl(cpu_ie
, cpu_ie
, IE_IE
);
233 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, IE_BIE
, l1
);
234 tcg_gen_andi_tl(cpu_ie
, cpu_ie
, ~IE_IE
);
238 tcg_gen_mov_tl(cpu_pc
, cpu_R
[dc
->r0
]);
240 dc
->is_jmp
= DISAS_JUMP
;
243 static void dec_bi(DisasContext
*dc
)
245 LOG_DIS("bi %d\n", sign_extend(dc
->imm26
<< 2, 26));
247 gen_goto_tb(dc
, 0, dc
->pc
+ (sign_extend(dc
->imm26
<< 2, 26)));
249 dc
->is_jmp
= DISAS_TB_JUMP
;
252 static inline void gen_cond_branch(DisasContext
*dc
, int cond
)
256 l1
= gen_new_label();
257 tcg_gen_brcond_tl(cond
, cpu_R
[dc
->r0
], cpu_R
[dc
->r1
], l1
);
258 gen_goto_tb(dc
, 0, dc
->pc
+ 4);
260 gen_goto_tb(dc
, 1, dc
->pc
+ (sign_extend(dc
->imm16
<< 2, 16)));
261 dc
->is_jmp
= DISAS_TB_JUMP
;
264 static void dec_be(DisasContext
*dc
)
266 LOG_DIS("be r%d, r%d, %d\n", dc
->r0
, dc
->r1
,
267 sign_extend(dc
->imm16
, 16) * 4);
269 gen_cond_branch(dc
, TCG_COND_EQ
);
272 static void dec_bg(DisasContext
*dc
)
274 LOG_DIS("bg r%d, r%d, %d\n", dc
->r0
, dc
->r1
,
275 sign_extend(dc
->imm16
, 16 * 4));
277 gen_cond_branch(dc
, TCG_COND_GT
);
280 static void dec_bge(DisasContext
*dc
)
282 LOG_DIS("bge r%d, r%d, %d\n", dc
->r0
, dc
->r1
,
283 sign_extend(dc
->imm16
, 16) * 4);
285 gen_cond_branch(dc
, TCG_COND_GE
);
288 static void dec_bgeu(DisasContext
*dc
)
290 LOG_DIS("bgeu r%d, r%d, %d\n", dc
->r0
, dc
->r1
,
291 sign_extend(dc
->imm16
, 16) * 4);
293 gen_cond_branch(dc
, TCG_COND_GEU
);
296 static void dec_bgu(DisasContext
*dc
)
298 LOG_DIS("bgu r%d, r%d, %d\n", dc
->r0
, dc
->r1
,
299 sign_extend(dc
->imm16
, 16) * 4);
301 gen_cond_branch(dc
, TCG_COND_GTU
);
304 static void dec_bne(DisasContext
*dc
)
306 LOG_DIS("bne r%d, r%d, %d\n", dc
->r0
, dc
->r1
,
307 sign_extend(dc
->imm16
, 16) * 4);
309 gen_cond_branch(dc
, TCG_COND_NE
);
312 static void dec_call(DisasContext
*dc
)
314 LOG_DIS("call r%d\n", dc
->r0
);
316 tcg_gen_movi_tl(cpu_R
[R_RA
], dc
->pc
+ 4);
317 tcg_gen_mov_tl(cpu_pc
, cpu_R
[dc
->r0
]);
319 dc
->is_jmp
= DISAS_JUMP
;
322 static void dec_calli(DisasContext
*dc
)
324 LOG_DIS("calli %d\n", sign_extend(dc
->imm26
, 26) * 4);
326 tcg_gen_movi_tl(cpu_R
[R_RA
], dc
->pc
+ 4);
327 gen_goto_tb(dc
, 0, dc
->pc
+ (sign_extend(dc
->imm26
<< 2, 26)));
329 dc
->is_jmp
= DISAS_TB_JUMP
;
332 static inline void gen_compare(DisasContext
*dc
, int cond
)
334 int rX
= (dc
->format
== OP_FMT_RR
) ? dc
->r2
: dc
->r1
;
335 int rY
= (dc
->format
== OP_FMT_RR
) ? dc
->r0
: dc
->r0
;
336 int rZ
= (dc
->format
== OP_FMT_RR
) ? dc
->r1
: -1;
338 if (dc
->format
== OP_FMT_RI
) {
339 tcg_gen_setcondi_tl(cond
, cpu_R
[rX
], cpu_R
[rY
],
340 sign_extend(dc
->imm16
, 16));
342 tcg_gen_setcond_tl(cond
, cpu_R
[rX
], cpu_R
[rY
], cpu_R
[rZ
]);
346 static void dec_cmpe(DisasContext
*dc
)
348 if (dc
->format
== OP_FMT_RI
) {
349 LOG_DIS("cmpei r%d, r%d, %d\n", dc
->r0
, dc
->r1
,
350 sign_extend(dc
->imm16
, 16));
352 LOG_DIS("cmpe r%d, r%d, r%d\n", dc
->r2
, dc
->r0
, dc
->r1
);
355 gen_compare(dc
, TCG_COND_EQ
);
358 static void dec_cmpg(DisasContext
*dc
)
360 if (dc
->format
== OP_FMT_RI
) {
361 LOG_DIS("cmpgi r%d, r%d, %d\n", dc
->r0
, dc
->r1
,
362 sign_extend(dc
->imm16
, 16));
364 LOG_DIS("cmpg r%d, r%d, r%d\n", dc
->r2
, dc
->r0
, dc
->r1
);
367 gen_compare(dc
, TCG_COND_GT
);
370 static void dec_cmpge(DisasContext
*dc
)
372 if (dc
->format
== OP_FMT_RI
) {
373 LOG_DIS("cmpgei r%d, r%d, %d\n", dc
->r0
, dc
->r1
,
374 sign_extend(dc
->imm16
, 16));
376 LOG_DIS("cmpge r%d, r%d, r%d\n", dc
->r2
, dc
->r0
, dc
->r1
);
379 gen_compare(dc
, TCG_COND_GE
);
382 static void dec_cmpgeu(DisasContext
*dc
)
384 if (dc
->format
== OP_FMT_RI
) {
385 LOG_DIS("cmpgeui r%d, r%d, %d\n", dc
->r0
, dc
->r1
,
386 sign_extend(dc
->imm16
, 16));
388 LOG_DIS("cmpgeu r%d, r%d, r%d\n", dc
->r2
, dc
->r0
, dc
->r1
);
391 gen_compare(dc
, TCG_COND_GEU
);
394 static void dec_cmpgu(DisasContext
*dc
)
396 if (dc
->format
== OP_FMT_RI
) {
397 LOG_DIS("cmpgui r%d, r%d, %d\n", dc
->r0
, dc
->r1
,
398 sign_extend(dc
->imm16
, 16));
400 LOG_DIS("cmpgu r%d, r%d, r%d\n", dc
->r2
, dc
->r0
, dc
->r1
);
403 gen_compare(dc
, TCG_COND_GTU
);
406 static void dec_cmpne(DisasContext
*dc
)
408 if (dc
->format
== OP_FMT_RI
) {
409 LOG_DIS("cmpnei r%d, r%d, %d\n", dc
->r0
, dc
->r1
,
410 sign_extend(dc
->imm16
, 16));
412 LOG_DIS("cmpne r%d, r%d, r%d\n", dc
->r2
, dc
->r0
, dc
->r1
);
415 gen_compare(dc
, TCG_COND_NE
);
418 static void dec_divu(DisasContext
*dc
)
422 LOG_DIS("divu r%d, r%d, r%d\n", dc
->r2
, dc
->r0
, dc
->r1
);
424 if (!(dc
->env
->features
& LM32_FEATURE_DIVIDE
)) {
425 cpu_abort(dc
->env
, "hardware divider is not available\n");
428 l1
= gen_new_label();
429 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_R
[dc
->r1
], 0, l1
);
430 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
431 t_gen_raise_exception(dc
, EXCP_DIVIDE_BY_ZERO
);
433 tcg_gen_divu_tl(cpu_R
[dc
->r2
], cpu_R
[dc
->r0
], cpu_R
[dc
->r1
]);
436 static void dec_lb(DisasContext
*dc
)
440 LOG_DIS("lb r%d, (r%d+%d)\n", dc
->r1
, dc
->r0
, dc
->imm16
);
443 tcg_gen_addi_tl(t0
, cpu_R
[dc
->r0
], sign_extend(dc
->imm16
, 16));
444 tcg_gen_qemu_ld8s(cpu_R
[dc
->r1
], t0
, MEM_INDEX
);
448 static void dec_lbu(DisasContext
*dc
)
452 LOG_DIS("lbu r%d, (r%d+%d)\n", dc
->r1
, dc
->r0
, dc
->imm16
);
455 tcg_gen_addi_tl(t0
, cpu_R
[dc
->r0
], sign_extend(dc
->imm16
, 16));
456 tcg_gen_qemu_ld8u(cpu_R
[dc
->r1
], t0
, MEM_INDEX
);
460 static void dec_lh(DisasContext
*dc
)
464 LOG_DIS("lh r%d, (r%d+%d)\n", dc
->r1
, dc
->r0
, dc
->imm16
);
467 tcg_gen_addi_tl(t0
, cpu_R
[dc
->r0
], sign_extend(dc
->imm16
, 16));
468 tcg_gen_qemu_ld16s(cpu_R
[dc
->r1
], t0
, MEM_INDEX
);
472 static void dec_lhu(DisasContext
*dc
)
476 LOG_DIS("lhu r%d, (r%d+%d)\n", dc
->r1
, dc
->r0
, dc
->imm16
);
479 tcg_gen_addi_tl(t0
, cpu_R
[dc
->r0
], sign_extend(dc
->imm16
, 16));
480 tcg_gen_qemu_ld16u(cpu_R
[dc
->r1
], t0
, MEM_INDEX
);
484 static void dec_lw(DisasContext
*dc
)
488 LOG_DIS("lw r%d, (r%d+%d)\n", dc
->r1
, dc
->r0
, sign_extend(dc
->imm16
, 16));
491 tcg_gen_addi_tl(t0
, cpu_R
[dc
->r0
], sign_extend(dc
->imm16
, 16));
492 tcg_gen_qemu_ld32s(cpu_R
[dc
->r1
], t0
, MEM_INDEX
);
496 static void dec_modu(DisasContext
*dc
)
500 LOG_DIS("modu r%d, r%d, %d\n", dc
->r2
, dc
->r0
, dc
->r1
);
502 if (!(dc
->env
->features
& LM32_FEATURE_DIVIDE
)) {
503 cpu_abort(dc
->env
, "hardware divider is not available\n");
506 l1
= gen_new_label();
507 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_R
[dc
->r1
], 0, l1
);
508 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
509 t_gen_raise_exception(dc
, EXCP_DIVIDE_BY_ZERO
);
511 tcg_gen_remu_tl(cpu_R
[dc
->r2
], cpu_R
[dc
->r0
], cpu_R
[dc
->r1
]);
514 static void dec_mul(DisasContext
*dc
)
516 if (dc
->format
== OP_FMT_RI
) {
517 LOG_DIS("muli r%d, r%d, %d\n", dc
->r0
, dc
->r1
,
518 sign_extend(dc
->imm16
, 16));
520 LOG_DIS("mul r%d, r%d, r%d\n", dc
->r2
, dc
->r0
, dc
->r1
);
523 if (!(dc
->env
->features
& LM32_FEATURE_MULTIPLY
)) {
524 cpu_abort(dc
->env
, "hardware multiplier is not available\n");
527 if (dc
->format
== OP_FMT_RI
) {
528 tcg_gen_muli_tl(cpu_R
[dc
->r1
], cpu_R
[dc
->r0
],
529 sign_extend(dc
->imm16
, 16));
531 tcg_gen_mul_tl(cpu_R
[dc
->r2
], cpu_R
[dc
->r0
], cpu_R
[dc
->r1
]);
535 static void dec_nor(DisasContext
*dc
)
537 if (dc
->format
== OP_FMT_RI
) {
538 LOG_DIS("nori r%d, r%d, %d\n", dc
->r0
, dc
->r1
,
539 zero_extend(dc
->imm16
, 16));
541 LOG_DIS("nor r%d, r%d, r%d\n", dc
->r2
, dc
->r0
, dc
->r1
);
544 if (dc
->format
== OP_FMT_RI
) {
545 TCGv t0
= tcg_temp_new();
546 tcg_gen_movi_tl(t0
, zero_extend(dc
->imm16
, 16));
547 tcg_gen_nor_tl(cpu_R
[dc
->r1
], cpu_R
[dc
->r0
], t0
);
550 tcg_gen_nor_tl(cpu_R
[dc
->r2
], cpu_R
[dc
->r0
], cpu_R
[dc
->r1
]);
554 static void dec_or(DisasContext
*dc
)
556 if (dc
->format
== OP_FMT_RI
) {
557 LOG_DIS("ori r%d, r%d, %d\n", dc
->r1
, dc
->r0
,
558 zero_extend(dc
->imm16
, 16));
560 if (dc
->r1
== R_R0
) {
561 LOG_DIS("mv r%d, r%d\n", dc
->r2
, dc
->r0
);
563 LOG_DIS("or r%d, r%d, r%d\n", dc
->r2
, dc
->r0
, dc
->r1
);
567 if (dc
->format
== OP_FMT_RI
) {
568 tcg_gen_ori_tl(cpu_R
[dc
->r1
], cpu_R
[dc
->r0
],
569 zero_extend(dc
->imm16
, 16));
571 tcg_gen_or_tl(cpu_R
[dc
->r2
], cpu_R
[dc
->r0
], cpu_R
[dc
->r1
]);
575 static void dec_orhi(DisasContext
*dc
)
577 if (dc
->r0
== R_R0
) {
578 LOG_DIS("mvhi r%d, %d\n", dc
->r1
, dc
->imm16
);
580 LOG_DIS("orhi r%d, r%d, %d\n", dc
->r1
, dc
->r0
, dc
->imm16
);
583 tcg_gen_ori_tl(cpu_R
[dc
->r1
], cpu_R
[dc
->r0
], (dc
->imm16
<< 16));
586 static void dec_raise(DisasContext
*dc
)
593 } else if (dc
->imm5
== 2) {
596 cpu_abort(dc
->env
, "invalid opcode\n");
600 l1
= gen_new_label();
603 tcg_gen_andi_tl(t0
, cpu_ie
, IE_IE
);
606 tcg_gen_andi_tl(cpu_ie
, cpu_ie
, ~IE_IE
);
610 tcg_gen_ori_tl(cpu_ie
, cpu_ie
, IE_EIE
);
611 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, IE_IE
, l1
);
612 tcg_gen_andi_tl(cpu_ie
, cpu_ie
, ~IE_EIE
);
616 tcg_gen_movi_tl(cpu_R
[R_EA
], dc
->pc
);
619 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
620 t_gen_raise_exception(dc
, EXCP_SYSTEMCALL
);
623 tcg_gen_ori_tl(cpu_ie
, cpu_ie
, IE_BIE
);
624 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, IE_IE
, l1
);
625 tcg_gen_andi_tl(cpu_ie
, cpu_ie
, ~IE_BIE
);
629 tcg_gen_movi_tl(cpu_R
[R_BA
], dc
->pc
);
632 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
633 t_gen_raise_exception(dc
, EXCP_BREAKPOINT
);
637 static void dec_rcsr(DisasContext
*dc
)
639 LOG_DIS("rcsr r%d, %d\n", dc
->r2
, dc
->csr
);
643 tcg_gen_mov_tl(cpu_R
[dc
->r2
], cpu_ie
);
646 gen_helper_rcsr_im(cpu_R
[dc
->r2
]);
649 gen_helper_rcsr_ip(cpu_R
[dc
->r2
]);
652 tcg_gen_mov_tl(cpu_R
[dc
->r2
], cpu_cc
);
655 tcg_gen_mov_tl(cpu_R
[dc
->r2
], cpu_cfg
);
658 tcg_gen_mov_tl(cpu_R
[dc
->r2
], cpu_eba
);
661 tcg_gen_mov_tl(cpu_R
[dc
->r2
], cpu_dc
);
664 tcg_gen_mov_tl(cpu_R
[dc
->r2
], cpu_deba
);
667 gen_helper_rcsr_jtx(cpu_R
[dc
->r2
]);
670 gen_helper_rcsr_jrx(cpu_R
[dc
->r2
]);
682 cpu_abort(dc
->env
, "invalid read access csr=%x\n", dc
->csr
);
685 cpu_abort(dc
->env
, "read_csr: unknown csr=%x\n", dc
->csr
);
690 static void dec_sb(DisasContext
*dc
)
694 LOG_DIS("sb (r%d+%d), r%d\n", dc
->r0
, dc
->imm16
, dc
->r1
);
697 tcg_gen_addi_tl(t0
, cpu_R
[dc
->r0
], sign_extend(dc
->imm16
, 16));
698 tcg_gen_qemu_st8(cpu_R
[dc
->r1
], t0
, MEM_INDEX
);
702 static void dec_sextb(DisasContext
*dc
)
704 LOG_DIS("sextb r%d, r%d\n", dc
->r2
, dc
->r0
);
706 if (!(dc
->env
->features
& LM32_FEATURE_SIGN_EXTEND
)) {
707 cpu_abort(dc
->env
, "hardware sign extender is not available\n");
710 tcg_gen_ext8s_tl(cpu_R
[dc
->r2
], cpu_R
[dc
->r0
]);
713 static void dec_sexth(DisasContext
*dc
)
715 LOG_DIS("sexth r%d, r%d\n", dc
->r2
, dc
->r0
);
717 if (!(dc
->env
->features
& LM32_FEATURE_SIGN_EXTEND
)) {
718 cpu_abort(dc
->env
, "hardware sign extender is not available\n");
721 tcg_gen_ext16s_tl(cpu_R
[dc
->r2
], cpu_R
[dc
->r0
]);
724 static void dec_sh(DisasContext
*dc
)
728 LOG_DIS("sh (r%d+%d), r%d\n", dc
->r0
, dc
->imm16
, dc
->r1
);
731 tcg_gen_addi_tl(t0
, cpu_R
[dc
->r0
], sign_extend(dc
->imm16
, 16));
732 tcg_gen_qemu_st16(cpu_R
[dc
->r1
], t0
, MEM_INDEX
);
736 static void dec_sl(DisasContext
*dc
)
738 if (dc
->format
== OP_FMT_RI
) {
739 LOG_DIS("sli r%d, r%d, %d\n", dc
->r1
, dc
->r0
, dc
->imm5
);
741 LOG_DIS("sl r%d, r%d, r%d\n", dc
->r2
, dc
->r0
, dc
->r1
);
744 if (!(dc
->env
->features
& LM32_FEATURE_SHIFT
)) {
745 cpu_abort(dc
->env
, "hardware shifter is not available\n");
748 if (dc
->format
== OP_FMT_RI
) {
749 tcg_gen_shli_tl(cpu_R
[dc
->r1
], cpu_R
[dc
->r0
], dc
->imm5
);
751 TCGv t0
= tcg_temp_new();
752 tcg_gen_andi_tl(t0
, cpu_R
[dc
->r1
], 0x1f);
753 tcg_gen_shl_tl(cpu_R
[dc
->r2
], cpu_R
[dc
->r0
], t0
);
758 static void dec_sr(DisasContext
*dc
)
760 if (dc
->format
== OP_FMT_RI
) {
761 LOG_DIS("sri r%d, r%d, %d\n", dc
->r1
, dc
->r0
, dc
->imm5
);
763 LOG_DIS("sr r%d, r%d, r%d\n", dc
->r2
, dc
->r0
, dc
->r1
);
766 if (!(dc
->env
->features
& LM32_FEATURE_SHIFT
)) {
767 if (dc
->format
== OP_FMT_RI
) {
768 /* TODO: check r1 == 1 during runtime */
771 cpu_abort(dc
->env
, "hardware shifter is not available\n");
776 if (dc
->format
== OP_FMT_RI
) {
777 tcg_gen_sari_tl(cpu_R
[dc
->r1
], cpu_R
[dc
->r0
], dc
->imm5
);
779 TCGv t0
= tcg_temp_new();
780 tcg_gen_andi_tl(t0
, cpu_R
[dc
->r1
], 0x1f);
781 tcg_gen_sar_tl(cpu_R
[dc
->r2
], cpu_R
[dc
->r0
], t0
);
786 static void dec_sru(DisasContext
*dc
)
788 if (dc
->format
== OP_FMT_RI
) {
789 LOG_DIS("srui r%d, r%d, %d\n", dc
->r1
, dc
->r0
, dc
->imm5
);
791 LOG_DIS("sru r%d, r%d, r%d\n", dc
->r2
, dc
->r0
, dc
->r1
);
794 if (!(dc
->env
->features
& LM32_FEATURE_SHIFT
)) {
795 if (dc
->format
== OP_FMT_RI
) {
796 /* TODO: check r1 == 1 during runtime */
799 cpu_abort(dc
->env
, "hardware shifter is not available\n");
804 if (dc
->format
== OP_FMT_RI
) {
805 tcg_gen_shri_tl(cpu_R
[dc
->r1
], cpu_R
[dc
->r0
], dc
->imm5
);
807 TCGv t0
= tcg_temp_new();
808 tcg_gen_andi_tl(t0
, cpu_R
[dc
->r1
], 0x1f);
809 tcg_gen_shr_tl(cpu_R
[dc
->r2
], cpu_R
[dc
->r0
], t0
);
814 static void dec_sub(DisasContext
*dc
)
816 LOG_DIS("sub r%d, r%d, r%d\n", dc
->r2
, dc
->r0
, dc
->r1
);
818 tcg_gen_sub_tl(cpu_R
[dc
->r2
], cpu_R
[dc
->r0
], cpu_R
[dc
->r1
]);
821 static void dec_sw(DisasContext
*dc
)
825 LOG_DIS("sw (r%d+%d), r%d\n", dc
->r0
, sign_extend(dc
->imm16
, 16), dc
->r1
);
828 tcg_gen_addi_tl(t0
, cpu_R
[dc
->r0
], sign_extend(dc
->imm16
, 16));
829 tcg_gen_qemu_st32(cpu_R
[dc
->r1
], t0
, MEM_INDEX
);
833 static void dec_user(DisasContext
*dc
)
837 cpu_abort(dc
->env
, "user insn undefined\n");
840 static void dec_wcsr(DisasContext
*dc
)
844 LOG_DIS("wcsr r%d, %d\n", dc
->r1
, dc
->csr
);
848 tcg_gen_mov_tl(cpu_ie
, cpu_R
[dc
->r1
]);
849 tcg_gen_movi_tl(cpu_pc
, dc
->pc
+ 4);
850 dc
->is_jmp
= DISAS_UPDATE
;
853 /* mark as an io operation because it could cause an interrupt */
857 gen_helper_wcsr_im(cpu_R
[dc
->r1
]);
858 tcg_gen_movi_tl(cpu_pc
, dc
->pc
+ 4);
862 dc
->is_jmp
= DISAS_UPDATE
;
865 /* mark as an io operation because it could cause an interrupt */
869 gen_helper_wcsr_ip(cpu_R
[dc
->r1
]);
870 tcg_gen_movi_tl(cpu_pc
, dc
->pc
+ 4);
874 dc
->is_jmp
= DISAS_UPDATE
;
883 tcg_gen_mov_tl(cpu_eba
, cpu_R
[dc
->r1
]);
886 tcg_gen_mov_tl(cpu_deba
, cpu_R
[dc
->r1
]);
889 gen_helper_wcsr_jtx(cpu_R
[dc
->r1
]);
892 gen_helper_wcsr_jrx(cpu_R
[dc
->r1
]);
895 tcg_gen_mov_tl(cpu_dc
, cpu_R
[dc
->r1
]);
901 no
= dc
->csr
- CSR_BP0
;
902 if (dc
->env
->num_bps
<= no
) {
903 cpu_abort(dc
->env
, "breakpoint #%i is not available\n", no
);
905 tcg_gen_mov_tl(cpu_bp
[no
], cpu_R
[dc
->r1
]);
911 no
= dc
->csr
- CSR_WP0
;
912 if (dc
->env
->num_wps
<= no
) {
913 cpu_abort(dc
->env
, "watchpoint #%i is not available\n", no
);
915 tcg_gen_mov_tl(cpu_wp
[no
], cpu_R
[dc
->r1
]);
919 cpu_abort(dc
->env
, "invalid write access csr=%x\n", dc
->csr
);
922 cpu_abort(dc
->env
, "write_csr unknown csr=%x\n", dc
->csr
);
927 static void dec_xnor(DisasContext
*dc
)
929 if (dc
->format
== OP_FMT_RI
) {
930 LOG_DIS("xnori r%d, r%d, %d\n", dc
->r0
, dc
->r1
,
931 zero_extend(dc
->imm16
, 16));
933 if (dc
->r1
== R_R0
) {
934 LOG_DIS("not r%d, r%d\n", dc
->r2
, dc
->r0
);
936 LOG_DIS("xnor r%d, r%d, r%d\n", dc
->r2
, dc
->r0
, dc
->r1
);
940 if (dc
->format
== OP_FMT_RI
) {
941 tcg_gen_xori_tl(cpu_R
[dc
->r1
], cpu_R
[dc
->r0
],
942 zero_extend(dc
->imm16
, 16));
943 tcg_gen_not_tl(cpu_R
[dc
->r1
], cpu_R
[dc
->r1
]);
945 tcg_gen_eqv_tl(cpu_R
[dc
->r2
], cpu_R
[dc
->r0
], cpu_R
[dc
->r1
]);
949 static void dec_xor(DisasContext
*dc
)
951 if (dc
->format
== OP_FMT_RI
) {
952 LOG_DIS("xori r%d, r%d, %d\n", dc
->r0
, dc
->r1
,
953 zero_extend(dc
->imm16
, 16));
955 LOG_DIS("xor r%d, r%d, r%d\n", dc
->r2
, dc
->r0
, dc
->r1
);
958 if (dc
->format
== OP_FMT_RI
) {
959 tcg_gen_xori_tl(cpu_R
[dc
->r1
], cpu_R
[dc
->r0
],
960 zero_extend(dc
->imm16
, 16));
962 tcg_gen_xor_tl(cpu_R
[dc
->r2
], cpu_R
[dc
->r0
], cpu_R
[dc
->r1
]);
971 void (*dec
)(DisasContext
*dc
);
974 static const DecoderInfo decinfo
[] = {
977 {DEC_ANDHI
, dec_andhi
},
983 {DEC_BGEU
, dec_bgeu
},
986 {DEC_CALL
, dec_call
},
987 {DEC_CALLI
, dec_calli
},
988 {DEC_CMPE
, dec_cmpe
},
989 {DEC_CMPG
, dec_cmpg
},
990 {DEC_CMPGE
, dec_cmpge
},
991 {DEC_CMPGEU
, dec_cmpgeu
},
992 {DEC_CMPGU
, dec_cmpgu
},
993 {DEC_CMPNE
, dec_cmpne
},
994 {DEC_DIVU
, dec_divu
},
1000 {DEC_MODU
, dec_modu
},
1004 {DEC_ORHI
, dec_orhi
},
1005 {DEC_RAISE
, dec_raise
},
1006 {DEC_RCSR
, dec_rcsr
},
1008 {DEC_SEXTB
, dec_sextb
},
1009 {DEC_SEXTH
, dec_sexth
},
1016 {DEC_USER
, dec_user
},
1017 {DEC_WCSR
, dec_wcsr
},
1018 {DEC_XNOR
, dec_xnor
},
1022 static inline void decode(DisasContext
*dc
)
1027 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
))) {
1028 tcg_gen_debug_insn_start(dc
->pc
);
1031 dc
->ir
= ir
= ldl_code(dc
->pc
);
1032 LOG_DIS("%8.8x\t", dc
->ir
);
1034 /* try guessing 'empty' instruction memory, although it may be a valid
1035 * instruction sequence (eg. srui r0, r0, 0) */
1039 LOG_DIS("nr_nops=%d\t", dc
->nr_nops
);
1041 if (dc
->nr_nops
> 4) {
1042 cpu_abort(dc
->env
, "fetching nop sequence\n");
1046 dc
->opcode
= EXTRACT_FIELD(ir
, 26, 31);
1048 dc
->imm5
= EXTRACT_FIELD(ir
, 0, 4);
1049 dc
->imm16
= EXTRACT_FIELD(ir
, 0, 15);
1050 dc
->imm26
= EXTRACT_FIELD(ir
, 0, 25);
1052 dc
->csr
= EXTRACT_FIELD(ir
, 21, 25);
1053 dc
->r0
= EXTRACT_FIELD(ir
, 21, 25);
1054 dc
->r1
= EXTRACT_FIELD(ir
, 16, 20);
1055 dc
->r2
= EXTRACT_FIELD(ir
, 11, 15);
1057 /* bit 31 seems to indicate insn type. */
1058 if (ir
& (1 << 31)) {
1059 dc
->format
= OP_FMT_RR
;
1061 dc
->format
= OP_FMT_RI
;
1064 /* Large switch for all insns. */
1065 for (i
= 0; i
< ARRAY_SIZE(decinfo
); i
++) {
1066 if ((dc
->opcode
& decinfo
[i
].mask
) == decinfo
[i
].bits
) {
1072 cpu_abort(dc
->env
, "unknown opcode 0x%02x\n", dc
->opcode
);
1075 static void check_breakpoint(CPUState
*env
, DisasContext
*dc
)
1079 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
1080 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
1081 if (bp
->pc
== dc
->pc
) {
1082 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
1083 t_gen_raise_exception(dc
, EXCP_DEBUG
);
1084 dc
->is_jmp
= DISAS_UPDATE
;
1090 /* generate intermediate code for basic block 'tb'. */
1091 static void gen_intermediate_code_internal(CPUState
*env
,
1092 TranslationBlock
*tb
, int search_pc
)
1094 struct DisasContext ctx
, *dc
= &ctx
;
1095 uint16_t *gen_opc_end
;
1098 uint32_t next_page_start
;
1102 qemu_log_try_set_file(stderr
);
1108 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
1110 dc
->is_jmp
= DISAS_NEXT
;
1112 dc
->singlestep_enabled
= env
->singlestep_enabled
;
1116 cpu_abort(env
, "LM32: unaligned PC=%x\n", pc_start
);
1119 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1120 qemu_log("-----------------------------------------\n");
1121 log_cpu_state(env
, 0);
1124 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
1127 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
1128 if (max_insns
== 0) {
1129 max_insns
= CF_COUNT_MASK
;
1134 check_breakpoint(env
, dc
);
1137 j
= gen_opc_ptr
- gen_opc_buf
;
1141 gen_opc_instr_start
[lj
++] = 0;
1144 gen_opc_pc
[lj
] = dc
->pc
;
1145 gen_opc_instr_start
[lj
] = 1;
1146 gen_opc_icount
[lj
] = num_insns
;
1150 LOG_DIS("%8.8x:\t", dc
->pc
);
1152 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
1160 } while (!dc
->is_jmp
1161 && gen_opc_ptr
< gen_opc_end
1162 && !env
->singlestep_enabled
1164 && (dc
->pc
< next_page_start
)
1165 && num_insns
< max_insns
);
1167 if (tb
->cflags
& CF_LAST_IO
) {
1171 if (unlikely(env
->singlestep_enabled
)) {
1172 if (dc
->is_jmp
== DISAS_NEXT
) {
1173 tcg_gen_movi_tl(cpu_pc
, dc
->pc
);
1175 t_gen_raise_exception(dc
, EXCP_DEBUG
);
1177 switch (dc
->is_jmp
) {
1179 gen_goto_tb(dc
, 1, dc
->pc
);
1184 /* indicate that the hash table must be used
1185 to find the next TB */
1189 /* nothing more to generate */
1194 gen_icount_end(tb
, num_insns
);
1195 *gen_opc_ptr
= INDEX_op_end
;
1197 j
= gen_opc_ptr
- gen_opc_buf
;
1200 gen_opc_instr_start
[lj
++] = 0;
1203 tb
->size
= dc
->pc
- pc_start
;
1204 tb
->icount
= num_insns
;
1208 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1210 log_target_disas(pc_start
, dc
->pc
- pc_start
, 0);
1211 qemu_log("\nisize=%d osize=%zd\n",
1212 dc
->pc
- pc_start
, gen_opc_ptr
- gen_opc_buf
);
1217 void gen_intermediate_code(CPUState
*env
, struct TranslationBlock
*tb
)
1219 gen_intermediate_code_internal(env
, tb
, 0);
1222 void gen_intermediate_code_pc(CPUState
*env
, struct TranslationBlock
*tb
)
1224 gen_intermediate_code_internal(env
, tb
, 1);
1227 void cpu_dump_state(CPUState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
1236 cpu_fprintf(f
, "IN: PC=%x %s\n",
1237 env
->pc
, lookup_symbol(env
->pc
));
1239 cpu_fprintf(f
, "ie=%8.8x (IE=%x EIE=%x BIE=%x) im=%8.8x ip=%8.8x\n",
1241 (env
->ie
& IE_IE
) ? 1 : 0,
1242 (env
->ie
& IE_EIE
) ? 1 : 0,
1243 (env
->ie
& IE_BIE
) ? 1 : 0,
1244 lm32_pic_get_im(env
->pic_state
),
1245 lm32_pic_get_ip(env
->pic_state
));
1246 cpu_fprintf(f
, "eba=%8.8x deba=%8.8x\n",
1250 for (i
= 0; i
< 32; i
++) {
1251 cpu_fprintf(f
, "r%2.2d=%8.8x ", i
, env
->regs
[i
]);
1252 if ((i
+ 1) % 4 == 0) {
1253 cpu_fprintf(f
, "\n");
1256 cpu_fprintf(f
, "\n\n");
1259 void gen_pc_load(CPUState
*env
, struct TranslationBlock
*tb
,
1260 unsigned long searched_pc
, int pc_pos
, void *puc
)
1262 env
->pc
= gen_opc_pc
[pc_pos
];
1265 void lm32_translate_init(void)
1269 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
1271 for (i
= 0; i
< ARRAY_SIZE(cpu_R
); i
++) {
1272 cpu_R
[i
] = tcg_global_mem_new(TCG_AREG0
,
1273 offsetof(CPUState
, regs
[i
]),
1277 for (i
= 0; i
< ARRAY_SIZE(cpu_bp
); i
++) {
1278 cpu_bp
[i
] = tcg_global_mem_new(TCG_AREG0
,
1279 offsetof(CPUState
, bp
[i
]),
1283 for (i
= 0; i
< ARRAY_SIZE(cpu_wp
); i
++) {
1284 cpu_wp
[i
] = tcg_global_mem_new(TCG_AREG0
,
1285 offsetof(CPUState
, wp
[i
]),
1289 cpu_pc
= tcg_global_mem_new(TCG_AREG0
,
1290 offsetof(CPUState
, pc
),
1292 cpu_ie
= tcg_global_mem_new(TCG_AREG0
,
1293 offsetof(CPUState
, ie
),
1295 cpu_icc
= tcg_global_mem_new(TCG_AREG0
,
1296 offsetof(CPUState
, icc
),
1298 cpu_dcc
= tcg_global_mem_new(TCG_AREG0
,
1299 offsetof(CPUState
, dcc
),
1301 cpu_cc
= tcg_global_mem_new(TCG_AREG0
,
1302 offsetof(CPUState
, cc
),
1304 cpu_cfg
= tcg_global_mem_new(TCG_AREG0
,
1305 offsetof(CPUState
, cfg
),
1307 cpu_eba
= tcg_global_mem_new(TCG_AREG0
,
1308 offsetof(CPUState
, eba
),
1310 cpu_dc
= tcg_global_mem_new(TCG_AREG0
,
1311 offsetof(CPUState
, dc
),
1313 cpu_deba
= tcg_global_mem_new(TCG_AREG0
,
1314 offsetof(CPUState
, deba
),