target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21
  22 #include "qemu-common.h"
  23 #include "sysemu.h"
  24 #include "kvm.h"
  25 #include "cpu.h"
  26 #include "gdbstub.h"
  27 #include "host-utils.h"
  28 #include "hw/pc.h"
  29 #include "hw/apic.h"
  30 #include "ioport.h"
  31
  32 #ifdef CONFIG_KVM_PARA
  33 #include <linux/kvm_para.h>
  34 #endif
  35 //
  36 //#define DEBUG_KVM
  37
  38 #ifdef DEBUG_KVM
  39 #define DPRINTF(fmt, ...) \
  40     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  41 #else
  42 #define DPRINTF(fmt, ...) \
  43     do { } while (0)
  44 #endif
  45
  46 #define MSR_KVM_WALL_CLOCK  0x11
  47 #define MSR_KVM_SYSTEM_TIME 0x12
  48
  49 #ifndef BUS_MCEERR_AR
  50 #define BUS_MCEERR_AR 4
  51 #endif
  52 #ifndef BUS_MCEERR_AO
  53 #define BUS_MCEERR_AO 5
  54 #endif
  55
  56 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  57     KVM_CAP_INFO(SET_TSS_ADDR),
  58     KVM_CAP_INFO(EXT_CPUID),
  59     KVM_CAP_INFO(MP_STATE),
  60     KVM_CAP_LAST_INFO
  61 };
  62
  63 static bool has_msr_star;
  64 static bool has_msr_hsave_pa;
  65 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
  66 static bool has_msr_async_pf_en;
  67 #endif
  68 static int lm_capable_kernel;
  69
  70 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  71 {
  72     struct kvm_cpuid2 *cpuid;
  73     int r, size;
  74
  75     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  76     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  77     cpuid->nent = max;
  78     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  79     if (r == 0 && cpuid->nent >= max) {
  80         r = -E2BIG;
  81     }
  82     if (r < 0) {
  83         if (r == -E2BIG) {
  84             qemu_free(cpuid);
  85             return NULL;
  86         } else {
  87             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  88                     strerror(-r));
  89             exit(1);
  90         }
  91     }
  92     return cpuid;
  93 }
  94
  95 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
  96                                       uint32_t index, int reg)
  97 {
  98     struct kvm_cpuid2 *cpuid;
  99     int i, max;
 100     uint32_t ret = 0;
 101     uint32_t cpuid_1_edx;
 102
 103     max = 1;
 104     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
 105         max *= 2;
 106     }
 107
 108     for (i = 0; i < cpuid->nent; ++i) {
 109         if (cpuid->entries[i].function == function &&
 110             cpuid->entries[i].index == index) {
 111             switch (reg) {
 112             case R_EAX:
 113                 ret = cpuid->entries[i].eax;
 114                 break;
 115             case R_EBX:
 116                 ret = cpuid->entries[i].ebx;
 117                 break;
 118             case R_ECX:
 119                 ret = cpuid->entries[i].ecx;
 120                 break;
 121             case R_EDX:
 122                 ret = cpuid->entries[i].edx;
 123                 switch (function) {
 124                 case 1:
 125                     /* KVM before 2.6.30 misreports the following features */
 126                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 127                     break;
 128                 case 0x80000001:
 129                     /* On Intel, kvm returns cpuid according to the Intel spec,
 130                      * so add missing bits according to the AMD spec:
 131                      */
 132                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 133                     ret |= cpuid_1_edx & 0x183f7ff;
 134                     break;
 135                 }
 136                 break;
 137             }
 138         }
 139     }
 140
 141     qemu_free(cpuid);
 142
 143     return ret;
 144 }
 145
 146 #ifdef CONFIG_KVM_PARA
 147 struct kvm_para_features {
 148     int cap;
 149     int feature;
 150 } para_features[] = {
 151     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 152     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 153     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 154 #ifdef KVM_CAP_ASYNC_PF
 155     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 156 #endif
 157     { -1, -1 }
 158 };
 159
 160 static int get_para_features(CPUState *env)
 161 {
 162     int i, features = 0;
 163
 164     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 165         if (kvm_check_extension(env->kvm_state, para_features[i].cap)) {
 166             features |= (1 << para_features[i].feature);
 167         }
 168     }
 169 #ifdef KVM_CAP_ASYNC_PF
 170     has_msr_async_pf_en = features & (1 << KVM_FEATURE_ASYNC_PF);
 171 #endif
 172     return features;
 173 }
 174 #endif /* CONFIG_KVM_PARA */
 175
 176 #ifdef KVM_CAP_MCE
 177 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 178                                      int *max_banks)
 179 {
 180     int r;
 181
 182     r = kvm_check_extension(s, KVM_CAP_MCE);
 183     if (r > 0) {
 184         *max_banks = r;
 185         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 186     }
 187     return -ENOSYS;
 188 }
 189
 190 static void kvm_mce_inject(CPUState *env, target_phys_addr_t paddr, int code)
 191 {
 192     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 193                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 194     uint64_t mcg_status = MCG_STATUS_MCIP;
 195
 196     if (code == BUS_MCEERR_AR) {
 197         status |= MCI_STATUS_AR | 0x134;
 198         mcg_status |= MCG_STATUS_EIPV;
 199     } else {
 200         status |= 0xc0;
 201         mcg_status |= MCG_STATUS_RIPV;
 202     }
 203     cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr,
 204                        (MCM_ADDR_PHYS << 6) | 0xc,
 205                        cpu_x86_support_mca_broadcast(env) ?
 206                        MCE_INJECT_BROADCAST : 0);
 207 }
 208 #endif /* KVM_CAP_MCE */
 209
 210 static void hardware_memory_error(void)
 211 {
 212     fprintf(stderr, "Hardware memory error!\n");
 213     exit(1);
 214 }
 215
 216 int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr)
 217 {
 218 #ifdef KVM_CAP_MCE
 219     ram_addr_t ram_addr;
 220     target_phys_addr_t paddr;
 221
 222     if ((env->mcg_cap & MCG_SER_P) && addr
 223         && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
 224         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 225             !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr,
 226                                                &paddr)) {
 227             fprintf(stderr, "Hardware memory error for memory used by "
 228                     "QEMU itself instead of guest system!\n");
 229             /* Hope we are lucky for AO MCE */
 230             if (code == BUS_MCEERR_AO) {
 231                 return 0;
 232             } else {
 233                 hardware_memory_error();
 234             }
 235         }
 236         kvm_mce_inject(env, paddr, code);
 237     } else
 238 #endif /* KVM_CAP_MCE */
 239     {
 240         if (code == BUS_MCEERR_AO) {
 241             return 0;
 242         } else if (code == BUS_MCEERR_AR) {
 243             hardware_memory_error();
 244         } else {
 245             return 1;
 246         }
 247     }
 248     return 0;
 249 }
 250
 251 int kvm_arch_on_sigbus(int code, void *addr)
 252 {
 253 #ifdef KVM_CAP_MCE
 254     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
 255         ram_addr_t ram_addr;
 256         target_phys_addr_t paddr;
 257
 258         /* Hope we are lucky for AO MCE */
 259         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 260             !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr,
 261                                                &paddr)) {
 262             fprintf(stderr, "Hardware memory error for memory used by "
 263                     "QEMU itself instead of guest system!: %p\n", addr);
 264             return 0;
 265         }
 266         kvm_mce_inject(first_cpu, paddr, code);
 267     } else
 268 #endif /* KVM_CAP_MCE */
 269     {
 270         if (code == BUS_MCEERR_AO) {
 271             return 0;
 272         } else if (code == BUS_MCEERR_AR) {
 273             hardware_memory_error();
 274         } else {
 275             return 1;
 276         }
 277     }
 278     return 0;
 279 }
 280
 281 static int kvm_inject_mce_oldstyle(CPUState *env)
 282 {
 283 #ifdef KVM_CAP_MCE
 284     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 285         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 286         struct kvm_x86_mce mce;
 287
 288         env->exception_injected = -1;
 289
 290         /*
 291          * There must be at least one bank in use if an MCE is pending.
 292          * Find it and use its values for the event injection.
 293          */
 294         for (bank = 0; bank < bank_num; bank++) {
 295             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 296                 break;
 297             }
 298         }
 299         assert(bank < bank_num);
 300
 301         mce.bank = bank;
 302         mce.status = env->mce_banks[bank * 4 + 1];
 303         mce.mcg_status = env->mcg_status;
 304         mce.addr = env->mce_banks[bank * 4 + 2];
 305         mce.misc = env->mce_banks[bank * 4 + 3];
 306
 307         return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce);
 308     }
 309 #endif /* KVM_CAP_MCE */
 310     return 0;
 311 }
 312
 313 static void cpu_update_state(void *opaque, int running, int reason)
 314 {
 315     CPUState *env = opaque;
 316
 317     if (running) {
 318         env->tsc_valid = false;
 319     }
 320 }
 321
 322 int kvm_arch_init_vcpu(CPUState *env)
 323 {
 324     struct {
 325         struct kvm_cpuid2 cpuid;
 326         struct kvm_cpuid_entry2 entries[100];
 327     } __attribute__((packed)) cpuid_data;
 328     uint32_t limit, i, j, cpuid_i;
 329     uint32_t unused;
 330     struct kvm_cpuid_entry2 *c;
 331 #ifdef CONFIG_KVM_PARA
 332     uint32_t signature[3];
 333 #endif
 334
 335     env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 336
 337     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 338     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
 339     env->cpuid_ext_features |= i;
 340
 341     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 342                                                              0, R_EDX);
 343     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 344                                                              0, R_ECX);
 345     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(env, 0x8000000A,
 346                                                              0, R_EDX);
 347
 348
 349     cpuid_i = 0;
 350
 351 #ifdef CONFIG_KVM_PARA
 352     /* Paravirtualization CPUIDs */
 353     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 354     c = &cpuid_data.entries[cpuid_i++];
 355     memset(c, 0, sizeof(*c));
 356     c->function = KVM_CPUID_SIGNATURE;
 357     c->eax = 0;
 358     c->ebx = signature[0];
 359     c->ecx = signature[1];
 360     c->edx = signature[2];
 361
 362     c = &cpuid_data.entries[cpuid_i++];
 363     memset(c, 0, sizeof(*c));
 364     c->function = KVM_CPUID_FEATURES;
 365     c->eax = env->cpuid_kvm_features & get_para_features(env);
 366 #endif
 367
 368     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 369
 370     for (i = 0; i <= limit; i++) {
 371         c = &cpuid_data.entries[cpuid_i++];
 372
 373         switch (i) {
 374         case 2: {
 375             /* Keep reading function 2 till all the input is received */
 376             int times;
 377
 378             c->function = i;
 379             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 380                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 381             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 382             times = c->eax & 0xff;
 383
 384             for (j = 1; j < times; ++j) {
 385                 c = &cpuid_data.entries[cpuid_i++];
 386                 c->function = i;
 387                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 388                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 389             }
 390             break;
 391         }
 392         case 4:
 393         case 0xb:
 394         case 0xd:
 395             for (j = 0; ; j++) {
 396                 c->function = i;
 397                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 398                 c->index = j;
 399                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 400
 401                 if (i == 4 && c->eax == 0) {
 402                     break;
 403                 }
 404                 if (i == 0xb && !(c->ecx & 0xff00)) {
 405                     break;
 406                 }
 407                 if (i == 0xd && c->eax == 0) {
 408                     break;
 409                 }
 410                 c = &cpuid_data.entries[cpuid_i++];
 411             }
 412             break;
 413         default:
 414             c->function = i;
 415             c->flags = 0;
 416             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 417             break;
 418         }
 419     }
 420     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 421
 422     for (i = 0x80000000; i <= limit; i++) {
 423         c = &cpuid_data.entries[cpuid_i++];
 424
 425         c->function = i;
 426         c->flags = 0;
 427         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 428     }
 429
 430     cpuid_data.cpuid.nent = cpuid_i;
 431
 432 #ifdef KVM_CAP_MCE
 433     if (((env->cpuid_version >> 8)&0xF) >= 6
 434         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 435         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 436         uint64_t mcg_cap;
 437         int banks;
 438         int ret;
 439
 440         ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks);
 441         if (ret < 0) {
 442             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
 443             return ret;
 444         }
 445
 446         if (banks > MCE_BANKS_DEF) {
 447             banks = MCE_BANKS_DEF;
 448         }
 449         mcg_cap &= MCE_CAP_DEF;
 450         mcg_cap |= banks;
 451         ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap);
 452         if (ret < 0) {
 453             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
 454             return ret;
 455         }
 456
 457         env->mcg_cap = mcg_cap;
 458     }
 459 #endif
 460
 461     qemu_add_vm_change_state_handler(cpu_update_state, env);
 462
 463     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 464 }
 465
 466 void kvm_arch_reset_vcpu(CPUState *env)
 467 {
 468     env->exception_injected = -1;
 469     env->interrupt_injected = -1;
 470     env->xcr0 = 1;
 471     if (kvm_irqchip_in_kernel()) {
 472         env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
 473                                           KVM_MP_STATE_UNINITIALIZED;
 474     } else {
 475         env->mp_state = KVM_MP_STATE_RUNNABLE;
 476     }
 477 }
 478
 479 static int kvm_get_supported_msrs(KVMState *s)
 480 {
 481     static int kvm_supported_msrs;
 482     int ret = 0;
 483
 484     /* first time */
 485     if (kvm_supported_msrs == 0) {
 486         struct kvm_msr_list msr_list, *kvm_msr_list;
 487
 488         kvm_supported_msrs = -1;
 489
 490         /* Obtain MSR list from KVM.  These are the MSRs that we must
 491          * save/restore */
 492         msr_list.nmsrs = 0;
 493         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 494         if (ret < 0 && ret != -E2BIG) {
 495             return ret;
 496         }
 497         /* Old kernel modules had a bug and could write beyond the provided
 498            memory. Allocate at least a safe amount of 1K. */
 499         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 500                                               msr_list.nmsrs *
 501                                               sizeof(msr_list.indices[0])));
 502
 503         kvm_msr_list->nmsrs = msr_list.nmsrs;
 504         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 505         if (ret >= 0) {
 506             int i;
 507
 508             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 509                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 510                     has_msr_star = true;
 511                     continue;
 512                 }
 513                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 514                     has_msr_hsave_pa = true;
 515                     continue;
 516                 }
 517             }
 518         }
 519
 520         free(kvm_msr_list);
 521     }
 522
 523     return ret;
 524 }
 525
 526 int kvm_arch_init(KVMState *s)
 527 {
 528     uint64_t identity_base = 0xfffbc000;
 529     int ret;
 530     struct utsname utsname;
 531
 532     ret = kvm_get_supported_msrs(s);
 533     if (ret < 0) {
 534         return ret;
 535     }
 536
 537     uname(&utsname);
 538     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 539
 540     /*
 541      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 542      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 543      * Since these must be part of guest physical memory, we need to allocate
 544      * them, both by setting their start addresses in the kernel and by
 545      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 546      *
 547      * Older KVM versions may not support setting the identity map base. In
 548      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 549      * size.
 550      */
 551 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
 552     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 553         /* Allows up to 16M BIOSes. */
 554         identity_base = 0xfeffc000;
 555
 556         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 557         if (ret < 0) {
 558             return ret;
 559         }
 560     }
 561 #endif
 562     /* Set TSS base one page after EPT identity map. */
 563     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 564     if (ret < 0) {
 565         return ret;
 566     }
 567
 568     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 569     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 570     if (ret < 0) {
 571         fprintf(stderr, "e820_add_entry() table is full\n");
 572         return ret;
 573     }
 574
 575     return 0;
 576 }
 577
 578 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 579 {
 580     lhs->selector = rhs->selector;
 581     lhs->base = rhs->base;
 582     lhs->limit = rhs->limit;
 583     lhs->type = 3;
 584     lhs->present = 1;
 585     lhs->dpl = 3;
 586     lhs->db = 0;
 587     lhs->s = 1;
 588     lhs->l = 0;
 589     lhs->g = 0;
 590     lhs->avl = 0;
 591     lhs->unusable = 0;
 592 }
 593
 594 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 595 {
 596     unsigned flags = rhs->flags;
 597     lhs->selector = rhs->selector;
 598     lhs->base = rhs->base;
 599     lhs->limit = rhs->limit;
 600     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 601     lhs->present = (flags & DESC_P_MASK) != 0;
 602     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 603     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 604     lhs->s = (flags & DESC_S_MASK) != 0;
 605     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 606     lhs->g = (flags & DESC_G_MASK) != 0;
 607     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 608     lhs->unusable = 0;
 609 }
 610
 611 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 612 {
 613     lhs->selector = rhs->selector;
 614     lhs->base = rhs->base;
 615     lhs->limit = rhs->limit;
 616     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 617                  (rhs->present * DESC_P_MASK) |
 618                  (rhs->dpl << DESC_DPL_SHIFT) |
 619                  (rhs->db << DESC_B_SHIFT) |
 620                  (rhs->s * DESC_S_MASK) |
 621                  (rhs->l << DESC_L_SHIFT) |
 622                  (rhs->g * DESC_G_MASK) |
 623                  (rhs->avl * DESC_AVL_MASK);
 624 }
 625
 626 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 627 {
 628     if (set) {
 629         *kvm_reg = *qemu_reg;
 630     } else {
 631         *qemu_reg = *kvm_reg;
 632     }
 633 }
 634
 635 static int kvm_getput_regs(CPUState *env, int set)
 636 {
 637     struct kvm_regs regs;
 638     int ret = 0;
 639
 640     if (!set) {
 641         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 642         if (ret < 0) {
 643             return ret;
 644         }
 645     }
 646
 647     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 648     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 649     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 650     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 651     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 652     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 653     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 654     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 655 #ifdef TARGET_X86_64
 656     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 657     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 658     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 659     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 660     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 661     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 662     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 663     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 664 #endif
 665
 666     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 667     kvm_getput_reg(&regs.rip, &env->eip, set);
 668
 669     if (set) {
 670         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 671     }
 672
 673     return ret;
 674 }
 675
 676 static int kvm_put_fpu(CPUState *env)
 677 {
 678     struct kvm_fpu fpu;
 679     int i;
 680
 681     memset(&fpu, 0, sizeof fpu);
 682     fpu.fsw = env->fpus & ~(7 << 11);
 683     fpu.fsw |= (env->fpstt & 7) << 11;
 684     fpu.fcw = env->fpuc;
 685     for (i = 0; i < 8; ++i) {
 686         fpu.ftwx |= (!env->fptags[i]) << i;
 687     }
 688     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 689     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 690     fpu.mxcsr = env->mxcsr;
 691
 692     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 693 }
 694
 695 #ifdef KVM_CAP_XSAVE
 696 #define XSAVE_CWD_RIP     2
 697 #define XSAVE_CWD_RDP     4
 698 #define XSAVE_MXCSR       6
 699 #define XSAVE_ST_SPACE    8
 700 #define XSAVE_XMM_SPACE   40
 701 #define XSAVE_XSTATE_BV   128
 702 #define XSAVE_YMMH_SPACE  144
 703 #endif
 704
 705 static int kvm_put_xsave(CPUState *env)
 706 {
 707 #ifdef KVM_CAP_XSAVE
 708     int i, r;
 709     struct kvm_xsave* xsave;
 710     uint16_t cwd, swd, twd, fop;
 711
 712     if (!kvm_has_xsave()) {
 713         return kvm_put_fpu(env);
 714     }
 715
 716     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 717     memset(xsave, 0, sizeof(struct kvm_xsave));
 718     cwd = swd = twd = fop = 0;
 719     swd = env->fpus & ~(7 << 11);
 720     swd |= (env->fpstt & 7) << 11;
 721     cwd = env->fpuc;
 722     for (i = 0; i < 8; ++i) {
 723         twd |= (!env->fptags[i]) << i;
 724     }
 725     xsave->region[0] = (uint32_t)(swd << 16) + cwd;
 726     xsave->region[1] = (uint32_t)(fop << 16) + twd;
 727     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 728             sizeof env->fpregs);
 729     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 730             sizeof env->xmm_regs);
 731     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 732     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 733     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 734             sizeof env->ymmh_regs);
 735     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 736     qemu_free(xsave);
 737     return r;
 738 #else
 739     return kvm_put_fpu(env);
 740 #endif
 741 }
 742
 743 static int kvm_put_xcrs(CPUState *env)
 744 {
 745 #ifdef KVM_CAP_XCRS
 746     struct kvm_xcrs xcrs;
 747
 748     if (!kvm_has_xcrs()) {
 749         return 0;
 750     }
 751
 752     xcrs.nr_xcrs = 1;
 753     xcrs.flags = 0;
 754     xcrs.xcrs[0].xcr = 0;
 755     xcrs.xcrs[0].value = env->xcr0;
 756     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 757 #else
 758     return 0;
 759 #endif
 760 }
 761
 762 static int kvm_put_sregs(CPUState *env)
 763 {
 764     struct kvm_sregs sregs;
 765
 766     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 767     if (env->interrupt_injected >= 0) {
 768         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 769                 (uint64_t)1 << (env->interrupt_injected % 64);
 770     }
 771
 772     if ((env->eflags & VM_MASK)) {
 773         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 774         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 775         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 776         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 777         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 778         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 779     } else {
 780         set_seg(&sregs.cs, &env->segs[R_CS]);
 781         set_seg(&sregs.ds, &env->segs[R_DS]);
 782         set_seg(&sregs.es, &env->segs[R_ES]);
 783         set_seg(&sregs.fs, &env->segs[R_FS]);
 784         set_seg(&sregs.gs, &env->segs[R_GS]);
 785         set_seg(&sregs.ss, &env->segs[R_SS]);
 786     }
 787
 788     set_seg(&sregs.tr, &env->tr);
 789     set_seg(&sregs.ldt, &env->ldt);
 790
 791     sregs.idt.limit = env->idt.limit;
 792     sregs.idt.base = env->idt.base;
 793     sregs.gdt.limit = env->gdt.limit;
 794     sregs.gdt.base = env->gdt.base;
 795
 796     sregs.cr0 = env->cr[0];
 797     sregs.cr2 = env->cr[2];
 798     sregs.cr3 = env->cr[3];
 799     sregs.cr4 = env->cr[4];
 800
 801     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 802     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 803
 804     sregs.efer = env->efer;
 805
 806     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 807 }
 808
 809 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 810                               uint32_t index, uint64_t value)
 811 {
 812     entry->index = index;
 813     entry->data = value;
 814 }
 815
 816 static int kvm_put_msrs(CPUState *env, int level)
 817 {
 818     struct {
 819         struct kvm_msrs info;
 820         struct kvm_msr_entry entries[100];
 821     } msr_data;
 822     struct kvm_msr_entry *msrs = msr_data.entries;
 823     int n = 0;
 824
 825     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 826     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 827     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 828     if (has_msr_star) {
 829         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 830     }
 831     if (has_msr_hsave_pa) {
 832         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 833     }
 834 #ifdef TARGET_X86_64
 835     if (lm_capable_kernel) {
 836         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 837         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 838         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 839         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 840     }
 841 #endif
 842     if (level == KVM_PUT_FULL_STATE) {
 843         /*
 844          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
 845          * writeback. Until this is fixed, we only write the offset to SMP
 846          * guests after migration, desynchronizing the VCPUs, but avoiding
 847          * huge jump-backs that would occur without any writeback at all.
 848          */
 849         if (smp_cpus == 1 || env->tsc != 0) {
 850             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 851         }
 852     }
 853     /*
 854      * The following paravirtual MSRs have side effects on the guest or are
 855      * too heavy for normal writeback. Limit them to reset or full state
 856      * updates.
 857      */
 858     if (level >= KVM_PUT_RESET_STATE) {
 859         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 860                           env->system_time_msr);
 861         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 862 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
 863         if (has_msr_async_pf_en) {
 864             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
 865                               env->async_pf_en_msr);
 866         }
 867 #endif
 868     }
 869 #ifdef KVM_CAP_MCE
 870     if (env->mcg_cap) {
 871         int i;
 872
 873         kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 874         kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
 875         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
 876             kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
 877         }
 878     }
 879 #endif
 880
 881     msr_data.info.nmsrs = n;
 882
 883     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 884
 885 }
 886
 887
 888 static int kvm_get_fpu(CPUState *env)
 889 {
 890     struct kvm_fpu fpu;
 891     int i, ret;
 892
 893     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 894     if (ret < 0) {
 895         return ret;
 896     }
 897
 898     env->fpstt = (fpu.fsw >> 11) & 7;
 899     env->fpus = fpu.fsw;
 900     env->fpuc = fpu.fcw;
 901     for (i = 0; i < 8; ++i) {
 902         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 903     }
 904     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 905     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 906     env->mxcsr = fpu.mxcsr;
 907
 908     return 0;
 909 }
 910
 911 static int kvm_get_xsave(CPUState *env)
 912 {
 913 #ifdef KVM_CAP_XSAVE
 914     struct kvm_xsave* xsave;
 915     int ret, i;
 916     uint16_t cwd, swd, twd, fop;
 917
 918     if (!kvm_has_xsave()) {
 919         return kvm_get_fpu(env);
 920     }
 921
 922     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 923     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
 924     if (ret < 0) {
 925         qemu_free(xsave);
 926         return ret;
 927     }
 928
 929     cwd = (uint16_t)xsave->region[0];
 930     swd = (uint16_t)(xsave->region[0] >> 16);
 931     twd = (uint16_t)xsave->region[1];
 932     fop = (uint16_t)(xsave->region[1] >> 16);
 933     env->fpstt = (swd >> 11) & 7;
 934     env->fpus = swd;
 935     env->fpuc = cwd;
 936     for (i = 0; i < 8; ++i) {
 937         env->fptags[i] = !((twd >> i) & 1);
 938     }
 939     env->mxcsr = xsave->region[XSAVE_MXCSR];
 940     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
 941             sizeof env->fpregs);
 942     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
 943             sizeof env->xmm_regs);
 944     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
 945     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
 946             sizeof env->ymmh_regs);
 947     qemu_free(xsave);
 948     return 0;
 949 #else
 950     return kvm_get_fpu(env);
 951 #endif
 952 }
 953
 954 static int kvm_get_xcrs(CPUState *env)
 955 {
 956 #ifdef KVM_CAP_XCRS
 957     int i, ret;
 958     struct kvm_xcrs xcrs;
 959
 960     if (!kvm_has_xcrs()) {
 961         return 0;
 962     }
 963
 964     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
 965     if (ret < 0) {
 966         return ret;
 967     }
 968
 969     for (i = 0; i < xcrs.nr_xcrs; i++) {
 970         /* Only support xcr0 now */
 971         if (xcrs.xcrs[0].xcr == 0) {
 972             env->xcr0 = xcrs.xcrs[0].value;
 973             break;
 974         }
 975     }
 976     return 0;
 977 #else
 978     return 0;
 979 #endif
 980 }
 981
 982 static int kvm_get_sregs(CPUState *env)
 983 {
 984     struct kvm_sregs sregs;
 985     uint32_t hflags;
 986     int bit, i, ret;
 987
 988     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 989     if (ret < 0) {
 990         return ret;
 991     }
 992
 993     /* There can only be one pending IRQ set in the bitmap at a time, so try
 994        to find it and save its number instead (-1 for none). */
 995     env->interrupt_injected = -1;
 996     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 997         if (sregs.interrupt_bitmap[i]) {
 998             bit = ctz64(sregs.interrupt_bitmap[i]);
 999             env->interrupt_injected = i * 64 + bit;
1000             break;
1001         }
1002     }
1003
1004     get_seg(&env->segs[R_CS], &sregs.cs);
1005     get_seg(&env->segs[R_DS], &sregs.ds);
1006     get_seg(&env->segs[R_ES], &sregs.es);
1007     get_seg(&env->segs[R_FS], &sregs.fs);
1008     get_seg(&env->segs[R_GS], &sregs.gs);
1009     get_seg(&env->segs[R_SS], &sregs.ss);
1010
1011     get_seg(&env->tr, &sregs.tr);
1012     get_seg(&env->ldt, &sregs.ldt);
1013
1014     env->idt.limit = sregs.idt.limit;
1015     env->idt.base = sregs.idt.base;
1016     env->gdt.limit = sregs.gdt.limit;
1017     env->gdt.base = sregs.gdt.base;
1018
1019     env->cr[0] = sregs.cr0;
1020     env->cr[2] = sregs.cr2;
1021     env->cr[3] = sregs.cr3;
1022     env->cr[4] = sregs.cr4;
1023
1024     cpu_set_apic_base(env->apic_state, sregs.apic_base);
1025
1026     env->efer = sregs.efer;
1027     //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
1028
1029 #define HFLAG_COPY_MASK \
1030     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1031        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1032        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1033        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1034
1035     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1036     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1037     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1038                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1039     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1040     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1041                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1042
1043     if (env->efer & MSR_EFER_LMA) {
1044         hflags |= HF_LMA_MASK;
1045     }
1046
1047     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1048         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1049     } else {
1050         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1051                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1052         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1053                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1054         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1055             !(hflags & HF_CS32_MASK)) {
1056             hflags |= HF_ADDSEG_MASK;
1057         } else {
1058             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1059                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1060         }
1061     }
1062     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1063
1064     return 0;
1065 }
1066
1067 static int kvm_get_msrs(CPUState *env)
1068 {
1069     struct {
1070         struct kvm_msrs info;
1071         struct kvm_msr_entry entries[100];
1072     } msr_data;
1073     struct kvm_msr_entry *msrs = msr_data.entries;
1074     int ret, i, n;
1075
1076     n = 0;
1077     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1078     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1079     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1080     if (has_msr_star) {
1081         msrs[n++].index = MSR_STAR;
1082     }
1083     if (has_msr_hsave_pa) {
1084         msrs[n++].index = MSR_VM_HSAVE_PA;
1085     }
1086
1087     if (!env->tsc_valid) {
1088         msrs[n++].index = MSR_IA32_TSC;
1089         env->tsc_valid = !vm_running;
1090     }
1091
1092 #ifdef TARGET_X86_64
1093     if (lm_capable_kernel) {
1094         msrs[n++].index = MSR_CSTAR;
1095         msrs[n++].index = MSR_KERNELGSBASE;
1096         msrs[n++].index = MSR_FMASK;
1097         msrs[n++].index = MSR_LSTAR;
1098     }
1099 #endif
1100     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1101     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1102 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
1103     if (has_msr_async_pf_en) {
1104         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1105     }
1106 #endif
1107
1108 #ifdef KVM_CAP_MCE
1109     if (env->mcg_cap) {
1110         msrs[n++].index = MSR_MCG_STATUS;
1111         msrs[n++].index = MSR_MCG_CTL;
1112         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1113             msrs[n++].index = MSR_MC0_CTL + i;
1114         }
1115     }
1116 #endif
1117
1118     msr_data.info.nmsrs = n;
1119     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1120     if (ret < 0) {
1121         return ret;
1122     }
1123
1124     for (i = 0; i < ret; i++) {
1125         switch (msrs[i].index) {
1126         case MSR_IA32_SYSENTER_CS:
1127             env->sysenter_cs = msrs[i].data;
1128             break;
1129         case MSR_IA32_SYSENTER_ESP:
1130             env->sysenter_esp = msrs[i].data;
1131             break;
1132         case MSR_IA32_SYSENTER_EIP:
1133             env->sysenter_eip = msrs[i].data;
1134             break;
1135         case MSR_STAR:
1136             env->star = msrs[i].data;
1137             break;
1138 #ifdef TARGET_X86_64
1139         case MSR_CSTAR:
1140             env->cstar = msrs[i].data;
1141             break;
1142         case MSR_KERNELGSBASE:
1143             env->kernelgsbase = msrs[i].data;
1144             break;
1145         case MSR_FMASK:
1146             env->fmask = msrs[i].data;
1147             break;
1148         case MSR_LSTAR:
1149             env->lstar = msrs[i].data;
1150             break;
1151 #endif
1152         case MSR_IA32_TSC:
1153             env->tsc = msrs[i].data;
1154             break;
1155         case MSR_VM_HSAVE_PA:
1156             env->vm_hsave = msrs[i].data;
1157             break;
1158         case MSR_KVM_SYSTEM_TIME:
1159             env->system_time_msr = msrs[i].data;
1160             break;
1161         case MSR_KVM_WALL_CLOCK:
1162             env->wall_clock_msr = msrs[i].data;
1163             break;
1164 #ifdef KVM_CAP_MCE
1165         case MSR_MCG_STATUS:
1166             env->mcg_status = msrs[i].data;
1167             break;
1168         case MSR_MCG_CTL:
1169             env->mcg_ctl = msrs[i].data;
1170             break;
1171 #endif
1172         default:
1173 #ifdef KVM_CAP_MCE
1174             if (msrs[i].index >= MSR_MC0_CTL &&
1175                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1176                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1177             }
1178 #endif
1179             break;
1180 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
1181         case MSR_KVM_ASYNC_PF_EN:
1182             env->async_pf_en_msr = msrs[i].data;
1183             break;
1184 #endif
1185         }
1186     }
1187
1188     return 0;
1189 }
1190
1191 static int kvm_put_mp_state(CPUState *env)
1192 {
1193     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1194
1195     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1196 }
1197
1198 static int kvm_get_mp_state(CPUState *env)
1199 {
1200     struct kvm_mp_state mp_state;
1201     int ret;
1202
1203     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1204     if (ret < 0) {
1205         return ret;
1206     }
1207     env->mp_state = mp_state.mp_state;
1208     if (kvm_irqchip_in_kernel()) {
1209         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1210     }
1211     return 0;
1212 }
1213
1214 static int kvm_put_vcpu_events(CPUState *env, int level)
1215 {
1216 #ifdef KVM_CAP_VCPU_EVENTS
1217     struct kvm_vcpu_events events;
1218
1219     if (!kvm_has_vcpu_events()) {
1220         return 0;
1221     }
1222
1223     events.exception.injected = (env->exception_injected >= 0);
1224     events.exception.nr = env->exception_injected;
1225     events.exception.has_error_code = env->has_error_code;
1226     events.exception.error_code = env->error_code;
1227
1228     events.interrupt.injected = (env->interrupt_injected >= 0);
1229     events.interrupt.nr = env->interrupt_injected;
1230     events.interrupt.soft = env->soft_interrupt;
1231
1232     events.nmi.injected = env->nmi_injected;
1233     events.nmi.pending = env->nmi_pending;
1234     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1235
1236     events.sipi_vector = env->sipi_vector;
1237
1238     events.flags = 0;
1239     if (level >= KVM_PUT_RESET_STATE) {
1240         events.flags |=
1241             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1242     }
1243
1244     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1245 #else
1246     return 0;
1247 #endif
1248 }
1249
1250 static int kvm_get_vcpu_events(CPUState *env)
1251 {
1252 #ifdef KVM_CAP_VCPU_EVENTS
1253     struct kvm_vcpu_events events;
1254     int ret;
1255
1256     if (!kvm_has_vcpu_events()) {
1257         return 0;
1258     }
1259
1260     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1261     if (ret < 0) {
1262        return ret;
1263     }
1264     env->exception_injected =
1265        events.exception.injected ? events.exception.nr : -1;
1266     env->has_error_code = events.exception.has_error_code;
1267     env->error_code = events.exception.error_code;
1268
1269     env->interrupt_injected =
1270         events.interrupt.injected ? events.interrupt.nr : -1;
1271     env->soft_interrupt = events.interrupt.soft;
1272
1273     env->nmi_injected = events.nmi.injected;
1274     env->nmi_pending = events.nmi.pending;
1275     if (events.nmi.masked) {
1276         env->hflags2 |= HF2_NMI_MASK;
1277     } else {
1278         env->hflags2 &= ~HF2_NMI_MASK;
1279     }
1280
1281     env->sipi_vector = events.sipi_vector;
1282 #endif
1283
1284     return 0;
1285 }
1286
1287 static int kvm_guest_debug_workarounds(CPUState *env)
1288 {
1289     int ret = 0;
1290 #ifdef KVM_CAP_SET_GUEST_DEBUG
1291     unsigned long reinject_trap = 0;
1292
1293     if (!kvm_has_vcpu_events()) {
1294         if (env->exception_injected == 1) {
1295             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1296         } else if (env->exception_injected == 3) {
1297             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1298         }
1299         env->exception_injected = -1;
1300     }
1301
1302     /*
1303      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1304      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1305      * by updating the debug state once again if single-stepping is on.
1306      * Another reason to call kvm_update_guest_debug here is a pending debug
1307      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1308      * reinject them via SET_GUEST_DEBUG.
1309      */
1310     if (reinject_trap ||
1311         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1312         ret = kvm_update_guest_debug(env, reinject_trap);
1313     }
1314 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1315     return ret;
1316 }
1317
1318 static int kvm_put_debugregs(CPUState *env)
1319 {
1320 #ifdef KVM_CAP_DEBUGREGS
1321     struct kvm_debugregs dbgregs;
1322     int i;
1323
1324     if (!kvm_has_debugregs()) {
1325         return 0;
1326     }
1327
1328     for (i = 0; i < 4; i++) {
1329         dbgregs.db[i] = env->dr[i];
1330     }
1331     dbgregs.dr6 = env->dr[6];
1332     dbgregs.dr7 = env->dr[7];
1333     dbgregs.flags = 0;
1334
1335     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1336 #else
1337     return 0;
1338 #endif
1339 }
1340
1341 static int kvm_get_debugregs(CPUState *env)
1342 {
1343 #ifdef KVM_CAP_DEBUGREGS
1344     struct kvm_debugregs dbgregs;
1345     int i, ret;
1346
1347     if (!kvm_has_debugregs()) {
1348         return 0;
1349     }
1350
1351     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1352     if (ret < 0) {
1353         return ret;
1354     }
1355     for (i = 0; i < 4; i++) {
1356         env->dr[i] = dbgregs.db[i];
1357     }
1358     env->dr[4] = env->dr[6] = dbgregs.dr6;
1359     env->dr[5] = env->dr[7] = dbgregs.dr7;
1360 #endif
1361
1362     return 0;
1363 }
1364
1365 int kvm_arch_put_registers(CPUState *env, int level)
1366 {
1367     int ret;
1368
1369     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1370
1371     ret = kvm_getput_regs(env, 1);
1372     if (ret < 0) {
1373         return ret;
1374     }
1375     ret = kvm_put_xsave(env);
1376     if (ret < 0) {
1377         return ret;
1378     }
1379     ret = kvm_put_xcrs(env);
1380     if (ret < 0) {
1381         return ret;
1382     }
1383     ret = kvm_put_sregs(env);
1384     if (ret < 0) {
1385         return ret;
1386     }
1387     /* must be before kvm_put_msrs */
1388     ret = kvm_inject_mce_oldstyle(env);
1389     if (ret < 0) {
1390         return ret;
1391     }
1392     ret = kvm_put_msrs(env, level);
1393     if (ret < 0) {
1394         return ret;
1395     }
1396     if (level >= KVM_PUT_RESET_STATE) {
1397         ret = kvm_put_mp_state(env);
1398         if (ret < 0) {
1399             return ret;
1400         }
1401     }
1402     ret = kvm_put_vcpu_events(env, level);
1403     if (ret < 0) {
1404         return ret;
1405     }
1406     ret = kvm_put_debugregs(env);
1407     if (ret < 0) {
1408         return ret;
1409     }
1410     /* must be last */
1411     ret = kvm_guest_debug_workarounds(env);
1412     if (ret < 0) {
1413         return ret;
1414     }
1415     return 0;
1416 }
1417
1418 int kvm_arch_get_registers(CPUState *env)
1419 {
1420     int ret;
1421
1422     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1423
1424     ret = kvm_getput_regs(env, 0);
1425     if (ret < 0) {
1426         return ret;
1427     }
1428     ret = kvm_get_xsave(env);
1429     if (ret < 0) {
1430         return ret;
1431     }
1432     ret = kvm_get_xcrs(env);
1433     if (ret < 0) {
1434         return ret;
1435     }
1436     ret = kvm_get_sregs(env);
1437     if (ret < 0) {
1438         return ret;
1439     }
1440     ret = kvm_get_msrs(env);
1441     if (ret < 0) {
1442         return ret;
1443     }
1444     ret = kvm_get_mp_state(env);
1445     if (ret < 0) {
1446         return ret;
1447     }
1448     ret = kvm_get_vcpu_events(env);
1449     if (ret < 0) {
1450         return ret;
1451     }
1452     ret = kvm_get_debugregs(env);
1453     if (ret < 0) {
1454         return ret;
1455     }
1456     return 0;
1457 }
1458
1459 void kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1460 {
1461     int ret;
1462
1463     /* Inject NMI */
1464     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1465         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1466         DPRINTF("injected NMI\n");
1467         ret = kvm_vcpu_ioctl(env, KVM_NMI);
1468         if (ret < 0) {
1469             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1470                     strerror(-ret));
1471         }
1472     }
1473
1474     if (!kvm_irqchip_in_kernel()) {
1475         /* Force the VCPU out of its inner loop to process the INIT request */
1476         if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1477             env->exit_request = 1;
1478         }
1479
1480         /* Try to inject an interrupt if the guest can accept it */
1481         if (run->ready_for_interrupt_injection &&
1482             (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1483             (env->eflags & IF_MASK)) {
1484             int irq;
1485
1486             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1487             irq = cpu_get_pic_interrupt(env);
1488             if (irq >= 0) {
1489                 struct kvm_interrupt intr;
1490
1491                 intr.irq = irq;
1492                 DPRINTF("injected interrupt %d\n", irq);
1493                 ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1494                 if (ret < 0) {
1495                     fprintf(stderr,
1496                             "KVM: injection failed, interrupt lost (%s)\n",
1497                             strerror(-ret));
1498                 }
1499             }
1500         }
1501
1502         /* If we have an interrupt but the guest is not ready to receive an
1503          * interrupt, request an interrupt window exit.  This will
1504          * cause a return to userspace as soon as the guest is ready to
1505          * receive interrupts. */
1506         if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1507             run->request_interrupt_window = 1;
1508         } else {
1509             run->request_interrupt_window = 0;
1510         }
1511
1512         DPRINTF("setting tpr\n");
1513         run->cr8 = cpu_get_apic_tpr(env->apic_state);
1514     }
1515 }
1516
1517 void kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1518 {
1519     if (run->if_flag) {
1520         env->eflags |= IF_MASK;
1521     } else {
1522         env->eflags &= ~IF_MASK;
1523     }
1524     cpu_set_apic_tpr(env->apic_state, run->cr8);
1525     cpu_set_apic_base(env->apic_state, run->apic_base);
1526 }
1527
1528 int kvm_arch_process_async_events(CPUState *env)
1529 {
1530     if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1531         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1532         assert(env->mcg_cap);
1533
1534         env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1535
1536         kvm_cpu_synchronize_state(env);
1537
1538         if (env->exception_injected == EXCP08_DBLE) {
1539             /* this means triple fault */
1540             qemu_system_reset_request();
1541             env->exit_request = 1;
1542             return 0;
1543         }
1544         env->exception_injected = EXCP12_MCHK;
1545         env->has_error_code = 0;
1546
1547         env->halted = 0;
1548         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1549             env->mp_state = KVM_MP_STATE_RUNNABLE;
1550         }
1551     }
1552
1553     if (kvm_irqchip_in_kernel()) {
1554         return 0;
1555     }
1556
1557     if (env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI)) {
1558         env->halted = 0;
1559     }
1560     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1561         kvm_cpu_synchronize_state(env);
1562         do_cpu_init(env);
1563     }
1564     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1565         kvm_cpu_synchronize_state(env);
1566         do_cpu_sipi(env);
1567     }
1568
1569     return env->halted;
1570 }
1571
1572 static int kvm_handle_halt(CPUState *env)
1573 {
1574     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1575           (env->eflags & IF_MASK)) &&
1576         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1577         env->halted = 1;
1578         return 0;
1579     }
1580
1581     return 1;
1582 }
1583
1584 static bool host_supports_vmx(void)
1585 {
1586     uint32_t ecx, unused;
1587
1588     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
1589     return ecx & CPUID_EXT_VMX;
1590 }
1591
1592 #define VMX_INVALID_GUEST_STATE 0x80000021
1593
1594 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1595 {
1596     uint64_t code;
1597     int ret = 0;
1598
1599     switch (run->exit_reason) {
1600     case KVM_EXIT_HLT:
1601         DPRINTF("handle_hlt\n");
1602         ret = kvm_handle_halt(env);
1603         break;
1604     case KVM_EXIT_SET_TPR:
1605         ret = 1;
1606         break;
1607     case KVM_EXIT_FAIL_ENTRY:
1608         code = run->fail_entry.hardware_entry_failure_reason;
1609         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
1610                 code);
1611         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
1612             fprintf(stderr,
1613                     "\nIf you're runnning a guest on an Intel machine without "
1614                         "unrestricted mode\n"
1615                     "support, the failure can be most likely due to the guest "
1616                         "entering an invalid\n"
1617                     "state for Intel VT. For example, the guest maybe running "
1618                         "in big real mode\n"
1619                     "which is not supported on less recent Intel processors."
1620                         "\n\n");
1621         }
1622         ret = -1;
1623         break;
1624     case KVM_EXIT_EXCEPTION:
1625         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
1626                 run->ex.exception, run->ex.error_code);
1627         ret = -1;
1628         break;
1629     default:
1630         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1631         ret = -1;
1632         break;
1633     }
1634
1635     return ret;
1636 }
1637
1638 #ifdef KVM_CAP_SET_GUEST_DEBUG
1639 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1640 {
1641     static const uint8_t int3 = 0xcc;
1642
1643     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1644         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1645         return -EINVAL;
1646     }
1647     return 0;
1648 }
1649
1650 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1651 {
1652     uint8_t int3;
1653
1654     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1655         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1656         return -EINVAL;
1657     }
1658     return 0;
1659 }
1660
1661 static struct {
1662     target_ulong addr;
1663     int len;
1664     int type;
1665 } hw_breakpoint[4];
1666
1667 static int nb_hw_breakpoint;
1668
1669 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1670 {
1671     int n;
1672
1673     for (n = 0; n < nb_hw_breakpoint; n++) {
1674         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1675             (hw_breakpoint[n].len == len || len == -1)) {
1676             return n;
1677         }
1678     }
1679     return -1;
1680 }
1681
1682 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1683                                   target_ulong len, int type)
1684 {
1685     switch (type) {
1686     case GDB_BREAKPOINT_HW:
1687         len = 1;
1688         break;
1689     case GDB_WATCHPOINT_WRITE:
1690     case GDB_WATCHPOINT_ACCESS:
1691         switch (len) {
1692         case 1:
1693             break;
1694         case 2:
1695         case 4:
1696         case 8:
1697             if (addr & (len - 1)) {
1698                 return -EINVAL;
1699             }
1700             break;
1701         default:
1702             return -EINVAL;
1703         }
1704         break;
1705     default:
1706         return -ENOSYS;
1707     }
1708
1709     if (nb_hw_breakpoint == 4) {
1710         return -ENOBUFS;
1711     }
1712     if (find_hw_breakpoint(addr, len, type) >= 0) {
1713         return -EEXIST;
1714     }
1715     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1716     hw_breakpoint[nb_hw_breakpoint].len = len;
1717     hw_breakpoint[nb_hw_breakpoint].type = type;
1718     nb_hw_breakpoint++;
1719
1720     return 0;
1721 }
1722
1723 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1724                                   target_ulong len, int type)
1725 {
1726     int n;
1727
1728     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1729     if (n < 0) {
1730         return -ENOENT;
1731     }
1732     nb_hw_breakpoint--;
1733     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1734
1735     return 0;
1736 }
1737
1738 void kvm_arch_remove_all_hw_breakpoints(void)
1739 {
1740     nb_hw_breakpoint = 0;
1741 }
1742
1743 static CPUWatchpoint hw_watchpoint;
1744
1745 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1746 {
1747     int handle = 0;
1748     int n;
1749
1750     if (arch_info->exception == 1) {
1751         if (arch_info->dr6 & (1 << 14)) {
1752             if (cpu_single_env->singlestep_enabled) {
1753                 handle = 1;
1754             }
1755         } else {
1756             for (n = 0; n < 4; n++) {
1757                 if (arch_info->dr6 & (1 << n)) {
1758                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1759                     case 0x0:
1760                         handle = 1;
1761                         break;
1762                     case 0x1:
1763                         handle = 1;
1764                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1765                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1766                         hw_watchpoint.flags = BP_MEM_WRITE;
1767                         break;
1768                     case 0x3:
1769                         handle = 1;
1770                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1771                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1772                         hw_watchpoint.flags = BP_MEM_ACCESS;
1773                         break;
1774                     }
1775                 }
1776             }
1777         }
1778     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1779         handle = 1;
1780     }
1781     if (!handle) {
1782         cpu_synchronize_state(cpu_single_env);
1783         assert(cpu_single_env->exception_injected == -1);
1784
1785         cpu_single_env->exception_injected = arch_info->exception;
1786         cpu_single_env->has_error_code = 0;
1787     }
1788
1789     return handle;
1790 }
1791
1792 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1793 {
1794     const uint8_t type_code[] = {
1795         [GDB_BREAKPOINT_HW] = 0x0,
1796         [GDB_WATCHPOINT_WRITE] = 0x1,
1797         [GDB_WATCHPOINT_ACCESS] = 0x3
1798     };
1799     const uint8_t len_code[] = {
1800         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1801     };
1802     int n;
1803
1804     if (kvm_sw_breakpoints_active(env)) {
1805         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1806     }
1807     if (nb_hw_breakpoint > 0) {
1808         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1809         dbg->arch.debugreg[7] = 0x0600;
1810         for (n = 0; n < nb_hw_breakpoint; n++) {
1811             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1812             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1813                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1814                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
1815         }
1816     }
1817 }
1818 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1819
1820 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1821 {
1822     return !(env->cr[0] & CR0_PE_MASK) ||
1823            ((env->segs[R_CS].selector  & 3) != 3);
1824 }