hw/mc146818rtc.c

   1 /*
   2  * QEMU MC146818 RTC emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "qemu-timer.h"
  26 #include "sysemu.h"
  27 #include "pc.h"
  28 #include "apic.h"
  29 #include "isa.h"
  30 #include "mc146818rtc.h"
  31
  32 //#define DEBUG_CMOS
  33 //#define DEBUG_COALESCED
  34
  35 #ifdef DEBUG_CMOS
  36 # define CMOS_DPRINTF(format, ...)      printf(format, ## __VA_ARGS__)
  37 #else
  38 # define CMOS_DPRINTF(format, ...)      do { } while (0)
  39 #endif
  40
  41 #ifdef DEBUG_COALESCED
  42 # define DPRINTF_C(format, ...)      printf(format, ## __VA_ARGS__)
  43 #else
  44 # define DPRINTF_C(format, ...)      do { } while (0)
  45 #endif
  46
  47 #define RTC_REINJECT_ON_ACK_COUNT 20
  48
  49 #define RTC_SECONDS             0
  50 #define RTC_SECONDS_ALARM       1
  51 #define RTC_MINUTES             2
  52 #define RTC_MINUTES_ALARM       3
  53 #define RTC_HOURS               4
  54 #define RTC_HOURS_ALARM         5
  55 #define RTC_ALARM_DONT_CARE    0xC0
  56
  57 #define RTC_DAY_OF_WEEK         6
  58 #define RTC_DAY_OF_MONTH        7
  59 #define RTC_MONTH               8
  60 #define RTC_YEAR                9
  61
  62 #define RTC_REG_A               10
  63 #define RTC_REG_B               11
  64 #define RTC_REG_C               12
  65 #define RTC_REG_D               13
  66
  67 #define REG_A_UIP 0x80
  68
  69 #define REG_B_SET  0x80
  70 #define REG_B_PIE  0x40
  71 #define REG_B_AIE  0x20
  72 #define REG_B_UIE  0x10
  73 #define REG_B_SQWE 0x08
  74 #define REG_B_DM   0x04
  75
  76 #define REG_C_UF   0x10
  77 #define REG_C_IRQF 0x80
  78 #define REG_C_PF   0x40
  79 #define REG_C_AF   0x20
  80
  81 typedef struct RTCState {
  82     ISADevice dev;
  83     uint8_t cmos_data[128];
  84     uint8_t cmos_index;
  85     struct tm current_tm;
  86     int32_t base_year;
  87     qemu_irq irq;
  88     qemu_irq sqw_irq;
  89     int it_shift;
  90     /* periodic timer */
  91     QEMUTimer *periodic_timer;
  92     int64_t next_periodic_time;
  93     /* second update */
  94     int64_t next_second_time;
  95     uint16_t irq_reinject_on_ack_count;
  96     uint32_t irq_coalesced;
  97     uint32_t period;
  98     QEMUTimer *coalesced_timer;
  99     QEMUTimer *second_timer;
 100     QEMUTimer *second_timer2;
 101 } RTCState;
 102
 103 static void rtc_set_time(RTCState *s);
 104 static void rtc_copy_date(RTCState *s);
 105
 106 #ifdef TARGET_I386
 107 static void rtc_coalesced_timer_update(RTCState *s)
 108 {
 109     if (s->irq_coalesced == 0) {
 110         qemu_del_timer(s->coalesced_timer);
 111     } else {
 112         /* divide each RTC interval to 2 - 8 smaller intervals */
 113         int c = MIN(s->irq_coalesced, 7) + 1;
 114         int64_t next_clock = qemu_get_clock(rtc_clock) +
 115             muldiv64(s->period / c, get_ticks_per_sec(), 32768);
 116         qemu_mod_timer(s->coalesced_timer, next_clock);
 117     }
 118 }
 119
 120 static void rtc_coalesced_timer(void *opaque)
 121 {
 122     RTCState *s = opaque;
 123
 124     if (s->irq_coalesced != 0) {
 125         apic_reset_irq_delivered();
 126         s->cmos_data[RTC_REG_C] |= 0xc0;
 127         DPRINTF_C("cmos: injecting from timer\n");
 128         qemu_irq_raise(s->irq);
 129         if (apic_get_irq_delivered()) {
 130             s->irq_coalesced--;
 131             DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 132                       s->irq_coalesced);
 133         }
 134     }
 135
 136     rtc_coalesced_timer_update(s);
 137 }
 138 #endif
 139
 140 static void rtc_timer_update(RTCState *s, int64_t current_time)
 141 {
 142     int period_code, period;
 143     int64_t cur_clock, next_irq_clock;
 144
 145     period_code = s->cmos_data[RTC_REG_A] & 0x0f;
 146     if (period_code != 0
 147         && ((s->cmos_data[RTC_REG_B] & REG_B_PIE)
 148             || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
 149         if (period_code <= 2)
 150             period_code += 7;
 151         /* period in 32 Khz cycles */
 152         period = 1 << (period_code - 1);
 153 #ifdef TARGET_I386
 154         if (period != s->period) {
 155             s->irq_coalesced = (s->irq_coalesced * s->period) / period;
 156             DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
 157         }
 158         s->period = period;
 159 #endif
 160         /* compute 32 khz clock */
 161         cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
 162         next_irq_clock = (cur_clock & ~(period - 1)) + period;
 163         s->next_periodic_time =
 164             muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1;
 165         qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
 166     } else {
 167 #ifdef TARGET_I386
 168         s->irq_coalesced = 0;
 169 #endif
 170         qemu_del_timer(s->periodic_timer);
 171     }
 172 }
 173
 174 static void rtc_periodic_timer(void *opaque)
 175 {
 176     RTCState *s = opaque;
 177
 178     rtc_timer_update(s, s->next_periodic_time);
 179     if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
 180         s->cmos_data[RTC_REG_C] |= 0xc0;
 181 #ifdef TARGET_I386
 182         if(rtc_td_hack) {
 183             if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
 184                 s->irq_reinject_on_ack_count = 0;
 185             apic_reset_irq_delivered();
 186             qemu_irq_raise(s->irq);
 187             if (!apic_get_irq_delivered()) {
 188                 s->irq_coalesced++;
 189                 rtc_coalesced_timer_update(s);
 190                 DPRINTF_C("cmos: coalesced irqs increased to %d\n",
 191                           s->irq_coalesced);
 192             }
 193         } else
 194 #endif
 195         qemu_irq_raise(s->irq);
 196     }
 197     if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
 198         /* Not square wave at all but we don't want 2048Hz interrupts!
 199            Must be seen as a pulse.  */
 200         qemu_irq_raise(s->sqw_irq);
 201     }
 202 }
 203
 204 static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
 205 {
 206     RTCState *s = opaque;
 207
 208     if ((addr & 1) == 0) {
 209         s->cmos_index = data & 0x7f;
 210     } else {
 211         CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
 212                      s->cmos_index, data);
 213         switch(s->cmos_index) {
 214         case RTC_SECONDS_ALARM:
 215         case RTC_MINUTES_ALARM:
 216         case RTC_HOURS_ALARM:
 217             /* XXX: not supported */
 218             s->cmos_data[s->cmos_index] = data;
 219             break;
 220         case RTC_SECONDS:
 221         case RTC_MINUTES:
 222         case RTC_HOURS:
 223         case RTC_DAY_OF_WEEK:
 224         case RTC_DAY_OF_MONTH:
 225         case RTC_MONTH:
 226         case RTC_YEAR:
 227             s->cmos_data[s->cmos_index] = data;
 228             /* if in set mode, do not update the time */
 229             if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 230                 rtc_set_time(s);
 231             }
 232             break;
 233         case RTC_REG_A:
 234             /* UIP bit is read only */
 235             s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
 236                 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
 237             rtc_timer_update(s, qemu_get_clock(rtc_clock));
 238             break;
 239         case RTC_REG_B:
 240             if (data & REG_B_SET) {
 241                 /* set mode: reset UIP mode */
 242                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 243                 data &= ~REG_B_UIE;
 244             } else {
 245                 /* if disabling set mode, update the time */
 246                 if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
 247                     rtc_set_time(s);
 248                 }
 249             }
 250             s->cmos_data[RTC_REG_B] = data;
 251             rtc_timer_update(s, qemu_get_clock(rtc_clock));
 252             break;
 253         case RTC_REG_C:
 254         case RTC_REG_D:
 255             /* cannot write to them */
 256             break;
 257         default:
 258             s->cmos_data[s->cmos_index] = data;
 259             break;
 260         }
 261     }
 262 }
 263
 264 static inline int rtc_to_bcd(RTCState *s, int a)
 265 {
 266     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 267         return a;
 268     } else {
 269         return ((a / 10) << 4) | (a % 10);
 270     }
 271 }
 272
 273 static inline int rtc_from_bcd(RTCState *s, int a)
 274 {
 275     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 276         return a;
 277     } else {
 278         return ((a >> 4) * 10) + (a & 0x0f);
 279     }
 280 }
 281
 282 static void rtc_set_time(RTCState *s)
 283 {
 284     struct tm *tm = &s->current_tm;
 285
 286     tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 287     tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 288     tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
 289     if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
 290         (s->cmos_data[RTC_HOURS] & 0x80)) {
 291         tm->tm_hour += 12;
 292     }
 293     tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
 294     tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
 295     tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
 296     tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
 297
 298     rtc_change_mon_event(tm);
 299 }
 300
 301 static void rtc_copy_date(RTCState *s)
 302 {
 303     const struct tm *tm = &s->current_tm;
 304     int year;
 305
 306     s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
 307     s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
 308     if (s->cmos_data[RTC_REG_B] & 0x02) {
 309         /* 24 hour format */
 310         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
 311     } else {
 312         /* 12 hour format */
 313         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour % 12);
 314         if (tm->tm_hour >= 12)
 315             s->cmos_data[RTC_HOURS] |= 0x80;
 316     }
 317     s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
 318     s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
 319     s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
 320     year = (tm->tm_year - s->base_year) % 100;
 321     if (year < 0)
 322         year += 100;
 323     s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year);
 324 }
 325
 326 /* month is between 0 and 11. */
 327 static int get_days_in_month(int month, int year)
 328 {
 329     static const int days_tab[12] = {
 330         31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
 331     };
 332     int d;
 333     if ((unsigned )month >= 12)
 334         return 31;
 335     d = days_tab[month];
 336     if (month == 1) {
 337         if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
 338             d++;
 339     }
 340     return d;
 341 }
 342
 343 /* update 'tm' to the next second */
 344 static void rtc_next_second(struct tm *tm)
 345 {
 346     int days_in_month;
 347
 348     tm->tm_sec++;
 349     if ((unsigned)tm->tm_sec >= 60) {
 350         tm->tm_sec = 0;
 351         tm->tm_min++;
 352         if ((unsigned)tm->tm_min >= 60) {
 353             tm->tm_min = 0;
 354             tm->tm_hour++;
 355             if ((unsigned)tm->tm_hour >= 24) {
 356                 tm->tm_hour = 0;
 357                 /* next day */
 358                 tm->tm_wday++;
 359                 if ((unsigned)tm->tm_wday >= 7)
 360                     tm->tm_wday = 0;
 361                 days_in_month = get_days_in_month(tm->tm_mon,
 362                                                   tm->tm_year + 1900);
 363                 tm->tm_mday++;
 364                 if (tm->tm_mday < 1) {
 365                     tm->tm_mday = 1;
 366                 } else if (tm->tm_mday > days_in_month) {
 367                     tm->tm_mday = 1;
 368                     tm->tm_mon++;
 369                     if (tm->tm_mon >= 12) {
 370                         tm->tm_mon = 0;
 371                         tm->tm_year++;
 372                     }
 373                 }
 374             }
 375         }
 376     }
 377 }
 378
 379
 380 static void rtc_update_second(void *opaque)
 381 {
 382     RTCState *s = opaque;
 383     int64_t delay;
 384
 385     /* if the oscillator is not in normal operation, we do not update */
 386     if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
 387         s->next_second_time += get_ticks_per_sec();
 388         qemu_mod_timer(s->second_timer, s->next_second_time);
 389     } else {
 390         rtc_next_second(&s->current_tm);
 391
 392         if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 393             /* update in progress bit */
 394             s->cmos_data[RTC_REG_A] |= REG_A_UIP;
 395         }
 396         /* should be 244 us = 8 / 32768 seconds, but currently the
 397            timers do not have the necessary resolution. */
 398         delay = (get_ticks_per_sec() * 1) / 100;
 399         if (delay < 1)
 400             delay = 1;
 401         qemu_mod_timer(s->second_timer2,
 402                        s->next_second_time + delay);
 403     }
 404 }
 405
 406 static void rtc_update_second2(void *opaque)
 407 {
 408     RTCState *s = opaque;
 409
 410     if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 411         rtc_copy_date(s);
 412     }
 413
 414     /* check alarm */
 415     if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
 416         if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
 417              s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) &&
 418             ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
 419              s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) &&
 420             ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
 421              s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
 422
 423             s->cmos_data[RTC_REG_C] |= 0xa0;
 424             qemu_irq_raise(s->irq);
 425         }
 426     }
 427
 428     /* update ended interrupt */
 429     s->cmos_data[RTC_REG_C] |= REG_C_UF;
 430     if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
 431         s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 432         qemu_irq_raise(s->irq);
 433     }
 434
 435     /* clear update in progress bit */
 436     s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 437
 438     s->next_second_time += get_ticks_per_sec();
 439     qemu_mod_timer(s->second_timer, s->next_second_time);
 440 }
 441
 442 static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
 443 {
 444     RTCState *s = opaque;
 445     int ret;
 446     if ((addr & 1) == 0) {
 447         return 0xff;
 448     } else {
 449         switch(s->cmos_index) {
 450         case RTC_SECONDS:
 451         case RTC_MINUTES:
 452         case RTC_HOURS:
 453         case RTC_DAY_OF_WEEK:
 454         case RTC_DAY_OF_MONTH:
 455         case RTC_MONTH:
 456         case RTC_YEAR:
 457             ret = s->cmos_data[s->cmos_index];
 458             break;
 459         case RTC_REG_A:
 460             ret = s->cmos_data[s->cmos_index];
 461             break;
 462         case RTC_REG_C:
 463             ret = s->cmos_data[s->cmos_index];
 464             qemu_irq_lower(s->irq);
 465 #ifdef TARGET_I386
 466             if(s->irq_coalesced &&
 467                     s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
 468                 s->irq_reinject_on_ack_count++;
 469                 apic_reset_irq_delivered();
 470                 DPRINTF_C("cmos: injecting on ack\n");
 471                 qemu_irq_raise(s->irq);
 472                 if (apic_get_irq_delivered()) {
 473                     s->irq_coalesced--;
 474                     DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 475                               s->irq_coalesced);
 476                 }
 477                 break;
 478             }
 479 #endif
 480
 481             s->cmos_data[RTC_REG_C] = 0x00;
 482             break;
 483         default:
 484             ret = s->cmos_data[s->cmos_index];
 485             break;
 486         }
 487         CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
 488                      s->cmos_index, ret);
 489         return ret;
 490     }
 491 }
 492
 493 void rtc_set_memory(ISADevice *dev, int addr, int val)
 494 {
 495     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 496     if (addr >= 0 && addr <= 127)
 497         s->cmos_data[addr] = val;
 498 }
 499
 500 void rtc_set_date(ISADevice *dev, const struct tm *tm)
 501 {
 502     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 503     s->current_tm = *tm;
 504     rtc_copy_date(s);
 505 }
 506
 507 /* PC cmos mappings */
 508 #define REG_IBM_CENTURY_BYTE        0x32
 509 #define REG_IBM_PS2_CENTURY_BYTE    0x37
 510
 511 static void rtc_set_date_from_host(ISADevice *dev)
 512 {
 513     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 514     struct tm tm;
 515     int val;
 516
 517     /* set the CMOS date */
 518     qemu_get_timedate(&tm, 0);
 519     rtc_set_date(dev, &tm);
 520
 521     val = rtc_to_bcd(s, (tm.tm_year / 100) + 19);
 522     rtc_set_memory(dev, REG_IBM_CENTURY_BYTE, val);
 523     rtc_set_memory(dev, REG_IBM_PS2_CENTURY_BYTE, val);
 524 }
 525
 526 static int rtc_post_load(void *opaque, int version_id)
 527 {
 528 #ifdef TARGET_I386
 529     RTCState *s = opaque;
 530
 531     if (version_id >= 2) {
 532         if (rtc_td_hack) {
 533             rtc_coalesced_timer_update(s);
 534         }
 535     }
 536 #endif
 537     return 0;
 538 }
 539
 540 static const VMStateDescription vmstate_rtc = {
 541     .name = "mc146818rtc",
 542     .version_id = 2,
 543     .minimum_version_id = 1,
 544     .minimum_version_id_old = 1,
 545     .post_load = rtc_post_load,
 546     .fields      = (VMStateField []) {
 547         VMSTATE_BUFFER(cmos_data, RTCState),
 548         VMSTATE_UINT8(cmos_index, RTCState),
 549         VMSTATE_INT32(current_tm.tm_sec, RTCState),
 550         VMSTATE_INT32(current_tm.tm_min, RTCState),
 551         VMSTATE_INT32(current_tm.tm_hour, RTCState),
 552         VMSTATE_INT32(current_tm.tm_wday, RTCState),
 553         VMSTATE_INT32(current_tm.tm_mday, RTCState),
 554         VMSTATE_INT32(current_tm.tm_mon, RTCState),
 555         VMSTATE_INT32(current_tm.tm_year, RTCState),
 556         VMSTATE_TIMER(periodic_timer, RTCState),
 557         VMSTATE_INT64(next_periodic_time, RTCState),
 558         VMSTATE_INT64(next_second_time, RTCState),
 559         VMSTATE_TIMER(second_timer, RTCState),
 560         VMSTATE_TIMER(second_timer2, RTCState),
 561         VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
 562         VMSTATE_UINT32_V(period, RTCState, 2),
 563         VMSTATE_END_OF_LIST()
 564     }
 565 };
 566
 567 static void rtc_reset(void *opaque)
 568 {
 569     RTCState *s = opaque;
 570
 571     s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
 572     s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
 573
 574     qemu_irq_lower(s->irq);
 575
 576 #ifdef TARGET_I386
 577     if (rtc_td_hack)
 578             s->irq_coalesced = 0;
 579 #endif
 580 }
 581
 582 static int rtc_initfn(ISADevice *dev)
 583 {
 584     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 585     int base = 0x70;
 586
 587     s->cmos_data[RTC_REG_A] = 0x26;
 588     s->cmos_data[RTC_REG_B] = 0x02;
 589     s->cmos_data[RTC_REG_C] = 0x00;
 590     s->cmos_data[RTC_REG_D] = 0x80;
 591
 592     rtc_set_date_from_host(dev);
 593
 594     s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s);
 595 #ifdef TARGET_I386
 596     if (rtc_td_hack)
 597         s->coalesced_timer =
 598             qemu_new_timer(rtc_clock, rtc_coalesced_timer, s);
 599 #endif
 600     s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s);
 601     s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s);
 602
 603     s->next_second_time =
 604         qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
 605     qemu_mod_timer(s->second_timer2, s->next_second_time);
 606
 607     register_ioport_write(base, 2, 1, cmos_ioport_write, s);
 608     register_ioport_read(base, 2, 1, cmos_ioport_read, s);
 609
 610     qdev_set_legacy_instance_id(&dev->qdev, base, 2);
 611     qemu_register_reset(rtc_reset, s);
 612     return 0;
 613 }
 614
 615 ISADevice *rtc_init(int base_year, qemu_irq intercept_irq)
 616 {
 617     ISADevice *dev;
 618     RTCState *s;
 619
 620     dev = isa_create("mc146818rtc");
 621     s = DO_UPCAST(RTCState, dev, dev);
 622     qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
 623     qdev_init_nofail(&dev->qdev);
 624     if (intercept_irq) {
 625         s->irq = intercept_irq;
 626     } else {
 627         isa_init_irq(dev, &s->irq, RTC_ISA_IRQ);
 628     }
 629     return dev;
 630 }
 631
 632 static ISADeviceInfo mc146818rtc_info = {
 633     .qdev.name     = "mc146818rtc",
 634     .qdev.size     = sizeof(RTCState),
 635     .qdev.no_user  = 1,
 636     .qdev.vmsd     = &vmstate_rtc,
 637     .init          = rtc_initfn,
 638     .qdev.props    = (Property[]) {
 639         DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
 640         DEFINE_PROP_END_OF_LIST(),
 641     }
 642 };
 643
 644 static void mc146818rtc_register(void)
 645 {
 646     isa_qdev_register(&mc146818rtc_info);
 647 }
 648 device_init(mc146818rtc_register)