2 * QEMU PowerPC PowerNV machine model
4 * Copyright (c) 2016, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "sysemu/sysemu.h"
23 #include "sysemu/numa.h"
24 #include "sysemu/cpus.h"
26 #include "target/ppc/cpu.h"
28 #include "hw/ppc/fdt.h"
29 #include "hw/ppc/ppc.h"
30 #include "hw/ppc/pnv.h"
31 #include "hw/ppc/pnv_core.h"
32 #include "hw/loader.h"
33 #include "exec/address-spaces.h"
34 #include "qemu/cutils.h"
35 #include "qapi/visitor.h"
36 #include "monitor/monitor.h"
37 #include "hw/intc/intc.h"
38 #include "hw/ipmi/ipmi.h"
40 #include "hw/ppc/xics.h"
41 #include "hw/ppc/pnv_xscom.h"
43 #include "hw/isa/isa.h"
44 #include "hw/char/serial.h"
45 #include "hw/timer/mc146818rtc.h"
49 #define FDT_MAX_SIZE 0x00100000
51 #define FW_FILE_NAME "skiboot.lid"
52 #define FW_LOAD_ADDR 0x0
53 #define FW_MAX_SIZE 0x00400000
55 #define KERNEL_LOAD_ADDR 0x20000000
56 #define INITRD_LOAD_ADDR 0x40000000
58 static const char *pnv_chip_core_typename(const PnvChip
*o
)
60 const char *chip_type
= object_class_get_name(object_get_class(OBJECT(o
)));
61 int len
= strlen(chip_type
) - strlen(PNV_CHIP_TYPE_SUFFIX
);
62 char *s
= g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len
, chip_type
);
63 const char *core_type
= object_class_get_name(object_class_by_name(s
));
69 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
70 * 4 * 4 sockets * 12 cores * 8 threads = 1536
76 * Memory nodes are created by hostboot, one for each range of memory
77 * that has a different "affinity". In practice, it means one range
80 static void powernv_populate_memory_node(void *fdt
, int chip_id
, hwaddr start
,
84 uint64_t mem_reg_property
[2];
87 mem_reg_property
[0] = cpu_to_be64(start
);
88 mem_reg_property
[1] = cpu_to_be64(size
);
90 mem_name
= g_strdup_printf("memory@%"HWADDR_PRIx
, start
);
91 off
= fdt_add_subnode(fdt
, 0, mem_name
);
94 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
95 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
96 sizeof(mem_reg_property
))));
97 _FDT((fdt_setprop_cell(fdt
, off
, "ibm,chip-id", chip_id
)));
100 static int get_cpus_node(void *fdt
)
102 int cpus_offset
= fdt_path_offset(fdt
, "/cpus");
104 if (cpus_offset
< 0) {
105 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
107 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
108 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
116 * The PowerNV cores (and threads) need to use real HW ids and not an
117 * incremental index like it has been done on other platforms. This HW
118 * id is stored in the CPU PIR, it is used to create cpu nodes in the
119 * device tree, used in XSCOM to address cores and in interrupt
122 static void powernv_create_core_node(PnvChip
*chip
, PnvCore
*pc
, void *fdt
)
124 CPUState
*cs
= CPU(DEVICE(pc
->threads
));
125 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
126 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
127 int smt_threads
= CPU_CORE(pc
)->nr_threads
;
128 CPUPPCState
*env
= &cpu
->env
;
129 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
130 uint32_t servers_prop
[smt_threads
];
132 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
133 0xffffffff, 0xffffffff};
134 uint32_t tbfreq
= PNV_TIMEBASE_FREQ
;
135 uint32_t cpufreq
= 1000000000;
136 uint32_t page_sizes_prop
[64];
137 size_t page_sizes_prop_size
;
138 const uint8_t pa_features
[] = { 24, 0,
139 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
140 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
141 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
142 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
145 int cpus_offset
= get_cpus_node(fdt
);
147 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, pc
->pir
);
148 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
152 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id", chip
->chip_id
)));
154 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", pc
->pir
)));
155 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,pir", pc
->pir
)));
156 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
158 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
159 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
160 env
->dcache_line_size
)));
161 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
162 env
->dcache_line_size
)));
163 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
164 env
->icache_line_size
)));
165 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
166 env
->icache_line_size
)));
168 if (pcc
->l1_dcache_size
) {
169 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
170 pcc
->l1_dcache_size
)));
172 warn_report("Unknown L1 dcache size for cpu");
174 if (pcc
->l1_icache_size
) {
175 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
176 pcc
->l1_icache_size
)));
178 warn_report("Unknown L1 icache size for cpu");
181 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
182 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
183 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", env
->slb_nr
)));
184 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
185 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
187 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
188 _FDT((fdt_setprop(fdt
, offset
, "ibm,purr", NULL
, 0)));
191 if (env
->mmu_model
& POWERPC_MMU_1TSEG
) {
192 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
193 segs
, sizeof(segs
))));
196 /* Advertise VMX/VSX (vector extensions) if available
197 * 0 / no property == no vector extensions
198 * 1 == VMX / Altivec available
199 * 2 == VSX available */
200 if (env
->insns_flags
& PPC_ALTIVEC
) {
201 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
203 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", vmx
)));
206 /* Advertise DFP (Decimal Floating Point) if available
207 * 0 / no property == no DFP
208 * 1 == DFP available */
209 if (env
->insns_flags2
& PPC2_DFP
) {
210 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
213 page_sizes_prop_size
= ppc_create_page_sizes_prop(env
, page_sizes_prop
,
214 sizeof(page_sizes_prop
));
215 if (page_sizes_prop_size
) {
216 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
217 page_sizes_prop
, page_sizes_prop_size
)));
220 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features",
221 pa_features
, sizeof(pa_features
))));
223 /* Build interrupt servers properties */
224 for (i
= 0; i
< smt_threads
; i
++) {
225 servers_prop
[i
] = cpu_to_be32(pc
->pir
+ i
);
227 _FDT((fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
228 servers_prop
, sizeof(servers_prop
))));
231 static void powernv_populate_icp(PnvChip
*chip
, void *fdt
, uint32_t pir
,
234 uint64_t addr
= PNV_ICP_BASE(chip
) | (pir
<< 12);
236 const char compat
[] = "IBM,power8-icp\0IBM,ppc-xicp";
237 uint32_t irange
[2], i
, rsize
;
241 irange
[0] = cpu_to_be32(pir
);
242 irange
[1] = cpu_to_be32(nr_threads
);
244 rsize
= sizeof(uint64_t) * 2 * nr_threads
;
245 reg
= g_malloc(rsize
);
246 for (i
= 0; i
< nr_threads
; i
++) {
247 reg
[i
* 2] = cpu_to_be64(addr
| ((pir
+ i
) * 0x1000));
248 reg
[i
* 2 + 1] = cpu_to_be64(0x1000);
251 name
= g_strdup_printf("interrupt-controller@%"PRIX64
, addr
);
252 offset
= fdt_add_subnode(fdt
, 0, name
);
256 _FDT((fdt_setprop(fdt
, offset
, "compatible", compat
, sizeof(compat
))));
257 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, rsize
)));
258 _FDT((fdt_setprop_string(fdt
, offset
, "device_type",
259 "PowerPC-External-Interrupt-Presentation")));
260 _FDT((fdt_setprop(fdt
, offset
, "interrupt-controller", NULL
, 0)));
261 _FDT((fdt_setprop(fdt
, offset
, "ibm,interrupt-server-ranges",
262 irange
, sizeof(irange
))));
263 _FDT((fdt_setprop_cell(fdt
, offset
, "#interrupt-cells", 1)));
264 _FDT((fdt_setprop_cell(fdt
, offset
, "#address-cells", 0)));
268 static int pnv_chip_lpc_offset(PnvChip
*chip
, void *fdt
)
273 name
= g_strdup_printf("/xscom@%" PRIx64
"/isa@%x",
274 (uint64_t) PNV_XSCOM_BASE(chip
), PNV_XSCOM_LPC_BASE
);
275 offset
= fdt_path_offset(fdt
, name
);
280 static void powernv_populate_chip(PnvChip
*chip
, void *fdt
)
282 const char *typename
= pnv_chip_core_typename(chip
);
283 size_t typesize
= object_type_get_instance_size(typename
);
286 pnv_xscom_populate(chip
, fdt
, 0);
288 /* The default LPC bus of a multichip system is on chip 0. It's
289 * recognized by the firmware (skiboot) using a "primary"
292 if (chip
->chip_id
== 0x0) {
293 int lpc_offset
= pnv_chip_lpc_offset(chip
, fdt
);
295 _FDT((fdt_setprop(fdt
, lpc_offset
, "primary", NULL
, 0)));
298 for (i
= 0; i
< chip
->nr_cores
; i
++) {
299 PnvCore
*pnv_core
= PNV_CORE(chip
->cores
+ i
* typesize
);
301 powernv_create_core_node(chip
, pnv_core
, fdt
);
303 /* Interrupt Control Presenters (ICP). One per core. */
304 powernv_populate_icp(chip
, fdt
, pnv_core
->pir
,
305 CPU_CORE(pnv_core
)->nr_threads
);
308 if (chip
->ram_size
) {
309 powernv_populate_memory_node(fdt
, chip
->chip_id
, chip
->ram_start
,
314 static void powernv_populate_rtc(ISADevice
*d
, void *fdt
, int lpc_off
)
316 uint32_t io_base
= d
->ioport_id
;
317 uint32_t io_regs
[] = {
319 cpu_to_be32(io_base
),
325 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
326 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
330 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
331 _FDT((fdt_setprop_string(fdt
, node
, "compatible", "pnpPNP,b00")));
334 static void powernv_populate_serial(ISADevice
*d
, void *fdt
, int lpc_off
)
336 const char compatible
[] = "ns16550\0pnpPNP,501";
337 uint32_t io_base
= d
->ioport_id
;
338 uint32_t io_regs
[] = {
340 cpu_to_be32(io_base
),
346 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
347 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
351 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
352 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
353 sizeof(compatible
))));
355 _FDT((fdt_setprop_cell(fdt
, node
, "clock-frequency", 1843200)));
356 _FDT((fdt_setprop_cell(fdt
, node
, "current-speed", 115200)));
357 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", d
->isairq
[0])));
358 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
359 fdt_get_phandle(fdt
, lpc_off
))));
361 /* This is needed by Linux */
362 _FDT((fdt_setprop_string(fdt
, node
, "device_type", "serial")));
365 static void powernv_populate_ipmi_bt(ISADevice
*d
, void *fdt
, int lpc_off
)
367 const char compatible
[] = "bt\0ipmi-bt";
369 uint32_t io_regs
[] = {
371 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
378 io_base
= object_property_get_int(OBJECT(d
), "ioport", &error_fatal
);
379 io_regs
[1] = cpu_to_be32(io_base
);
381 irq
= object_property_get_int(OBJECT(d
), "irq", &error_fatal
);
383 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
384 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
388 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
389 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
390 sizeof(compatible
))));
392 /* Mark it as reserved to avoid Linux trying to claim it */
393 _FDT((fdt_setprop_string(fdt
, node
, "status", "reserved")));
394 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", irq
)));
395 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
396 fdt_get_phandle(fdt
, lpc_off
))));
399 typedef struct ForeachPopulateArgs
{
402 } ForeachPopulateArgs
;
404 static int powernv_populate_isa_device(DeviceState
*dev
, void *opaque
)
406 ForeachPopulateArgs
*args
= opaque
;
407 ISADevice
*d
= ISA_DEVICE(dev
);
409 if (object_dynamic_cast(OBJECT(dev
), TYPE_MC146818_RTC
)) {
410 powernv_populate_rtc(d
, args
->fdt
, args
->offset
);
411 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_ISA_SERIAL
)) {
412 powernv_populate_serial(d
, args
->fdt
, args
->offset
);
413 } else if (object_dynamic_cast(OBJECT(dev
), "isa-ipmi-bt")) {
414 powernv_populate_ipmi_bt(d
, args
->fdt
, args
->offset
);
416 error_report("unknown isa device %s@i%x", qdev_fw_name(dev
),
423 static void powernv_populate_isa(ISABus
*bus
, void *fdt
, int lpc_offset
)
425 ForeachPopulateArgs args
= {
427 .offset
= lpc_offset
,
430 /* ISA devices are not necessarily parented to the ISA bus so we
431 * can not use object_child_foreach() */
432 qbus_walk_children(BUS(bus
), powernv_populate_isa_device
,
433 NULL
, NULL
, NULL
, &args
);
436 static void *powernv_create_fdt(MachineState
*machine
)
438 const char plat_compat
[] = "qemu,powernv\0ibm,powernv";
439 PnvMachineState
*pnv
= POWERNV_MACHINE(machine
);
446 fdt
= g_malloc0(FDT_MAX_SIZE
);
447 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
450 _FDT((fdt_setprop_cell(fdt
, 0, "#address-cells", 0x2)));
451 _FDT((fdt_setprop_cell(fdt
, 0, "#size-cells", 0x2)));
452 _FDT((fdt_setprop_string(fdt
, 0, "model",
453 "IBM PowerNV (emulated by qemu)")));
454 _FDT((fdt_setprop(fdt
, 0, "compatible", plat_compat
,
455 sizeof(plat_compat
))));
457 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
458 _FDT((fdt_setprop_string(fdt
, 0, "vm,uuid", buf
)));
460 _FDT((fdt_property_string(fdt
, "system-id", buf
)));
464 off
= fdt_add_subnode(fdt
, 0, "chosen");
465 if (machine
->kernel_cmdline
) {
466 _FDT((fdt_setprop_string(fdt
, off
, "bootargs",
467 machine
->kernel_cmdline
)));
470 if (pnv
->initrd_size
) {
471 uint32_t start_prop
= cpu_to_be32(pnv
->initrd_base
);
472 uint32_t end_prop
= cpu_to_be32(pnv
->initrd_base
+ pnv
->initrd_size
);
474 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-start",
475 &start_prop
, sizeof(start_prop
))));
476 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-end",
477 &end_prop
, sizeof(end_prop
))));
480 /* Populate device tree for each chip */
481 for (i
= 0; i
< pnv
->num_chips
; i
++) {
482 powernv_populate_chip(pnv
->chips
[i
], fdt
);
485 /* Populate ISA devices on chip 0 */
486 lpc_offset
= pnv_chip_lpc_offset(pnv
->chips
[0], fdt
);
487 powernv_populate_isa(pnv
->isa_bus
, fdt
, lpc_offset
);
490 pnv_bmc_populate_sensors(pnv
->bmc
, fdt
);
496 static void pnv_powerdown_notify(Notifier
*n
, void *opaque
)
498 PnvMachineState
*pnv
= POWERNV_MACHINE(qdev_get_machine());
501 pnv_bmc_powerdown(pnv
->bmc
);
505 static void ppc_powernv_reset(void)
507 MachineState
*machine
= MACHINE(qdev_get_machine());
508 PnvMachineState
*pnv
= POWERNV_MACHINE(machine
);
512 qemu_devices_reset();
514 /* OpenPOWER systems have a BMC, which can be defined on the
517 * -device ipmi-bmc-sim,id=bmc0
519 * This is the internal simulator but it could also be an external
522 obj
= object_resolve_path_type("", "ipmi-bmc-sim", NULL
);
524 pnv
->bmc
= IPMI_BMC(obj
);
527 fdt
= powernv_create_fdt(machine
);
529 /* Pack resulting tree */
530 _FDT((fdt_pack(fdt
)));
532 cpu_physical_memory_write(PNV_FDT_ADDR
, fdt
, fdt_totalsize(fdt
));
535 static ISABus
*pnv_isa_create(PnvChip
*chip
)
537 PnvLpcController
*lpc
= &chip
->lpc
;
540 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
542 /* let isa_bus_new() create its own bridge on SysBus otherwise
543 * devices speficied on the command line won't find the bus and
544 * will fail to create.
546 isa_bus
= isa_bus_new(NULL
, &lpc
->isa_mem
, &lpc
->isa_io
,
549 irqs
= pnv_lpc_isa_irq_create(lpc
, pcc
->chip_type
, ISA_NUM_IRQS
);
551 isa_bus_irqs(isa_bus
, irqs
);
555 static void ppc_powernv_init(MachineState
*machine
)
557 PnvMachineState
*pnv
= POWERNV_MACHINE(machine
);
565 if (machine
->ram_size
< (1 * G_BYTE
)) {
566 warn_report("skiboot may not work with < 1GB of RAM");
569 ram
= g_new(MemoryRegion
, 1);
570 memory_region_allocate_system_memory(ram
, NULL
, "ppc_powernv.ram",
572 memory_region_add_subregion(get_system_memory(), 0, ram
);
574 /* load skiboot firmware */
575 if (bios_name
== NULL
) {
576 bios_name
= FW_FILE_NAME
;
579 fw_filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
581 error_report("Could not find OPAL firmware '%s'", bios_name
);
585 fw_size
= load_image_targphys(fw_filename
, FW_LOAD_ADDR
, FW_MAX_SIZE
);
587 error_report("Could not load OPAL firmware '%s'", fw_filename
);
593 if (machine
->kernel_filename
) {
596 kernel_size
= load_image_targphys(machine
->kernel_filename
,
597 KERNEL_LOAD_ADDR
, 0x2000000);
598 if (kernel_size
< 0) {
599 error_report("Could not load kernel '%s'",
600 machine
->kernel_filename
);
606 if (machine
->initrd_filename
) {
607 pnv
->initrd_base
= INITRD_LOAD_ADDR
;
608 pnv
->initrd_size
= load_image_targphys(machine
->initrd_filename
,
609 pnv
->initrd_base
, 0x10000000); /* 128MB max */
610 if (pnv
->initrd_size
< 0) {
611 error_report("Could not load initial ram disk '%s'",
612 machine
->initrd_filename
);
617 /* Create the processor chips */
618 i
= strlen(machine
->cpu_type
) - strlen(POWERPC_CPU_TYPE_SUFFIX
);
619 chip_typename
= g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
620 i
, machine
->cpu_type
);
621 if (!object_class_by_name(chip_typename
)) {
622 error_report("invalid CPU model '%.*s' for %s machine",
623 i
, machine
->cpu_type
, MACHINE_GET_CLASS(machine
)->name
);
627 pnv
->chips
= g_new0(PnvChip
*, pnv
->num_chips
);
628 for (i
= 0; i
< pnv
->num_chips
; i
++) {
630 Object
*chip
= object_new(chip_typename
);
632 pnv
->chips
[i
] = PNV_CHIP(chip
);
634 /* TODO: put all the memory in one node on chip 0 until we find a
635 * way to specify different ranges for each chip
638 object_property_set_int(chip
, machine
->ram_size
, "ram-size",
642 snprintf(chip_name
, sizeof(chip_name
), "chip[%d]", PNV_CHIP_HWID(i
));
643 object_property_add_child(OBJECT(pnv
), chip_name
, chip
, &error_fatal
);
644 object_property_set_int(chip
, PNV_CHIP_HWID(i
), "chip-id",
646 object_property_set_int(chip
, smp_cores
, "nr-cores", &error_fatal
);
647 object_property_set_bool(chip
, true, "realized", &error_fatal
);
649 g_free(chip_typename
);
651 /* Instantiate ISA bus on chip 0 */
652 pnv
->isa_bus
= pnv_isa_create(pnv
->chips
[0]);
654 /* Create serial port */
655 serial_hds_isa_init(pnv
->isa_bus
, 0, MAX_SERIAL_PORTS
);
657 /* Create an RTC ISA device too */
658 mc146818_rtc_init(pnv
->isa_bus
, 2000, NULL
);
660 /* OpenPOWER systems use a IPMI SEL Event message to notify the
661 * host to powerdown */
662 pnv
->powerdown_notifier
.notify
= pnv_powerdown_notify
;
663 qemu_register_powerdown_notifier(&pnv
->powerdown_notifier
);
667 * 0:21 Reserved - Read as zeros
672 static uint32_t pnv_chip_core_pir_p8(PnvChip
*chip
, uint32_t core_id
)
674 return (chip
->chip_id
<< 7) | (core_id
<< 3);
678 * 0:48 Reserved - Read as zeroes
681 * 56 Reserved - Read as zero
685 * We only care about the lower bits. uint32_t is fine for the moment.
687 static uint32_t pnv_chip_core_pir_p9(PnvChip
*chip
, uint32_t core_id
)
689 return (chip
->chip_id
<< 8) | (core_id
<< 2);
692 /* Allowed core identifiers on a POWER8 Processor Chip :
701 * <EX7,8 reserved> <reserved>
710 #define POWER8E_CORE_MASK (0x7070ull)
711 #define POWER8_CORE_MASK (0x7e7eull)
714 * POWER9 has 24 cores, ids starting at 0x20
716 #define POWER9_CORE_MASK (0xffffff00000000ull)
718 static void pnv_chip_power8e_class_init(ObjectClass
*klass
, void *data
)
720 DeviceClass
*dc
= DEVICE_CLASS(klass
);
721 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
723 k
->chip_type
= PNV_CHIP_POWER8E
;
724 k
->chip_cfam_id
= 0x221ef04980000000ull
; /* P8 Murano DD2.1 */
725 k
->cores_mask
= POWER8E_CORE_MASK
;
726 k
->core_pir
= pnv_chip_core_pir_p8
;
727 k
->xscom_base
= 0x003fc0000000000ull
;
728 k
->xscom_core_base
= 0x10000000ull
;
729 dc
->desc
= "PowerNV Chip POWER8E";
732 static void pnv_chip_power8_class_init(ObjectClass
*klass
, void *data
)
734 DeviceClass
*dc
= DEVICE_CLASS(klass
);
735 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
737 k
->chip_type
= PNV_CHIP_POWER8
;
738 k
->chip_cfam_id
= 0x220ea04980000000ull
; /* P8 Venice DD2.0 */
739 k
->cores_mask
= POWER8_CORE_MASK
;
740 k
->core_pir
= pnv_chip_core_pir_p8
;
741 k
->xscom_base
= 0x003fc0000000000ull
;
742 k
->xscom_core_base
= 0x10000000ull
;
743 dc
->desc
= "PowerNV Chip POWER8";
746 static void pnv_chip_power8nvl_class_init(ObjectClass
*klass
, void *data
)
748 DeviceClass
*dc
= DEVICE_CLASS(klass
);
749 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
751 k
->chip_type
= PNV_CHIP_POWER8NVL
;
752 k
->chip_cfam_id
= 0x120d304980000000ull
; /* P8 Naples DD1.0 */
753 k
->cores_mask
= POWER8_CORE_MASK
;
754 k
->core_pir
= pnv_chip_core_pir_p8
;
755 k
->xscom_base
= 0x003fc0000000000ull
;
756 k
->xscom_core_base
= 0x10000000ull
;
757 dc
->desc
= "PowerNV Chip POWER8NVL";
760 static void pnv_chip_power9_class_init(ObjectClass
*klass
, void *data
)
762 DeviceClass
*dc
= DEVICE_CLASS(klass
);
763 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
765 k
->chip_type
= PNV_CHIP_POWER9
;
766 k
->chip_cfam_id
= 0x100d104980000000ull
; /* P9 Nimbus DD1.0 */
767 k
->cores_mask
= POWER9_CORE_MASK
;
768 k
->core_pir
= pnv_chip_core_pir_p9
;
769 k
->xscom_base
= 0x00603fc00000000ull
;
770 k
->xscom_core_base
= 0x0ull
;
771 dc
->desc
= "PowerNV Chip POWER9";
774 static void pnv_chip_core_sanitize(PnvChip
*chip
, Error
**errp
)
776 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
780 * No custom mask for this chip, let's use the default one from *
783 if (!chip
->cores_mask
) {
784 chip
->cores_mask
= pcc
->cores_mask
;
787 /* filter alien core ids ! some are reserved */
788 if ((chip
->cores_mask
& pcc
->cores_mask
) != chip
->cores_mask
) {
789 error_setg(errp
, "warning: invalid core mask for chip Ox%"PRIx64
" !",
793 chip
->cores_mask
&= pcc
->cores_mask
;
795 /* now that we have a sane layout, let check the number of cores */
796 cores_max
= ctpop64(chip
->cores_mask
);
797 if (chip
->nr_cores
> cores_max
) {
798 error_setg(errp
, "warning: too many cores for chip ! Limit is %d",
804 static void pnv_chip_init(Object
*obj
)
806 PnvChip
*chip
= PNV_CHIP(obj
);
807 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
809 chip
->xscom_base
= pcc
->xscom_base
;
811 object_initialize(&chip
->lpc
, sizeof(chip
->lpc
), TYPE_PNV_LPC
);
812 object_property_add_child(obj
, "lpc", OBJECT(&chip
->lpc
), NULL
);
814 object_initialize(&chip
->psi
, sizeof(chip
->psi
), TYPE_PNV_PSI
);
815 object_property_add_child(obj
, "psi", OBJECT(&chip
->psi
), NULL
);
816 object_property_add_const_link(OBJECT(&chip
->psi
), "xics",
817 OBJECT(qdev_get_machine()), &error_abort
);
819 object_initialize(&chip
->occ
, sizeof(chip
->occ
), TYPE_PNV_OCC
);
820 object_property_add_child(obj
, "occ", OBJECT(&chip
->occ
), NULL
);
821 object_property_add_const_link(OBJECT(&chip
->occ
), "psi",
822 OBJECT(&chip
->psi
), &error_abort
);
824 /* The LPC controller needs PSI to generate interrupts */
825 object_property_add_const_link(OBJECT(&chip
->lpc
), "psi",
826 OBJECT(&chip
->psi
), &error_abort
);
829 static void pnv_chip_icp_realize(PnvChip
*chip
, Error
**errp
)
831 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
832 const char *typename
= pnv_chip_core_typename(chip
);
833 size_t typesize
= object_type_get_instance_size(typename
);
836 XICSFabric
*xi
= XICS_FABRIC(qdev_get_machine());
838 name
= g_strdup_printf("icp-%x", chip
->chip_id
);
839 memory_region_init(&chip
->icp_mmio
, OBJECT(chip
), name
, PNV_ICP_SIZE
);
840 sysbus_init_mmio(SYS_BUS_DEVICE(chip
), &chip
->icp_mmio
);
843 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 1, PNV_ICP_BASE(chip
));
845 /* Map the ICP registers for each thread */
846 for (i
= 0; i
< chip
->nr_cores
; i
++) {
847 PnvCore
*pnv_core
= PNV_CORE(chip
->cores
+ i
* typesize
);
848 int core_hwid
= CPU_CORE(pnv_core
)->core_id
;
850 for (j
= 0; j
< CPU_CORE(pnv_core
)->nr_threads
; j
++) {
851 uint32_t pir
= pcc
->core_pir(chip
, core_hwid
) + j
;
852 PnvICPState
*icp
= PNV_ICP(xics_icp_get(xi
, pir
));
854 memory_region_add_subregion(&chip
->icp_mmio
, pir
<< 12, &icp
->mmio
);
859 static void pnv_chip_realize(DeviceState
*dev
, Error
**errp
)
861 PnvChip
*chip
= PNV_CHIP(dev
);
863 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
864 const char *typename
= pnv_chip_core_typename(chip
);
865 size_t typesize
= object_type_get_instance_size(typename
);
868 if (!object_class_by_name(typename
)) {
869 error_setg(errp
, "Unable to find PowerNV CPU Core '%s'", typename
);
874 pnv_xscom_realize(chip
, &error
);
876 error_propagate(errp
, error
);
879 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV_XSCOM_BASE(chip
));
882 pnv_chip_core_sanitize(chip
, &error
);
884 error_propagate(errp
, error
);
888 chip
->cores
= g_malloc0(typesize
* chip
->nr_cores
);
890 for (i
= 0, core_hwid
= 0; (core_hwid
< sizeof(chip
->cores_mask
) * 8)
891 && (i
< chip
->nr_cores
); core_hwid
++) {
893 void *pnv_core
= chip
->cores
+ i
* typesize
;
895 if (!(chip
->cores_mask
& (1ull << core_hwid
))) {
899 object_initialize(pnv_core
, typesize
, typename
);
900 snprintf(core_name
, sizeof(core_name
), "core[%d]", core_hwid
);
901 object_property_add_child(OBJECT(chip
), core_name
, OBJECT(pnv_core
),
903 object_property_set_int(OBJECT(pnv_core
), smp_threads
, "nr-threads",
905 object_property_set_int(OBJECT(pnv_core
), core_hwid
,
906 CPU_CORE_PROP_CORE_ID
, &error_fatal
);
907 object_property_set_int(OBJECT(pnv_core
),
908 pcc
->core_pir(chip
, core_hwid
),
909 "pir", &error_fatal
);
910 object_property_add_const_link(OBJECT(pnv_core
), "xics",
911 qdev_get_machine(), &error_fatal
);
912 object_property_set_bool(OBJECT(pnv_core
), true, "realized",
914 object_unref(OBJECT(pnv_core
));
916 /* Each core has an XSCOM MMIO region */
917 pnv_xscom_add_subregion(chip
,
918 PNV_XSCOM_EX_CORE_BASE(pcc
->xscom_core_base
,
920 &PNV_CORE(pnv_core
)->xscom_regs
);
924 /* Create LPC controller */
925 object_property_set_bool(OBJECT(&chip
->lpc
), true, "realized",
927 pnv_xscom_add_subregion(chip
, PNV_XSCOM_LPC_BASE
, &chip
->lpc
.xscom_regs
);
929 /* Interrupt Management Area. This is the memory region holding
930 * all the Interrupt Control Presenter (ICP) registers */
931 pnv_chip_icp_realize(chip
, &error
);
933 error_propagate(errp
, error
);
937 /* Processor Service Interface (PSI) Host Bridge */
938 object_property_set_int(OBJECT(&chip
->psi
), PNV_PSIHB_BASE(chip
),
939 "bar", &error_fatal
);
940 object_property_set_bool(OBJECT(&chip
->psi
), true, "realized", &error
);
942 error_propagate(errp
, error
);
945 pnv_xscom_add_subregion(chip
, PNV_XSCOM_PSIHB_BASE
, &chip
->psi
.xscom_regs
);
947 /* Create the simplified OCC model */
948 object_property_set_bool(OBJECT(&chip
->occ
), true, "realized", &error
);
950 error_propagate(errp
, error
);
953 pnv_xscom_add_subregion(chip
, PNV_XSCOM_OCC_BASE
, &chip
->occ
.xscom_regs
);
956 static Property pnv_chip_properties
[] = {
957 DEFINE_PROP_UINT32("chip-id", PnvChip
, chip_id
, 0),
958 DEFINE_PROP_UINT64("ram-start", PnvChip
, ram_start
, 0),
959 DEFINE_PROP_UINT64("ram-size", PnvChip
, ram_size
, 0),
960 DEFINE_PROP_UINT32("nr-cores", PnvChip
, nr_cores
, 1),
961 DEFINE_PROP_UINT64("cores-mask", PnvChip
, cores_mask
, 0x0),
962 DEFINE_PROP_END_OF_LIST(),
965 static void pnv_chip_class_init(ObjectClass
*klass
, void *data
)
967 DeviceClass
*dc
= DEVICE_CLASS(klass
);
969 set_bit(DEVICE_CATEGORY_CPU
, dc
->categories
);
970 dc
->realize
= pnv_chip_realize
;
971 dc
->props
= pnv_chip_properties
;
972 dc
->desc
= "PowerNV Chip";
975 static ICSState
*pnv_ics_get(XICSFabric
*xi
, int irq
)
977 PnvMachineState
*pnv
= POWERNV_MACHINE(xi
);
980 for (i
= 0; i
< pnv
->num_chips
; i
++) {
981 if (ics_valid_irq(&pnv
->chips
[i
]->psi
.ics
, irq
)) {
982 return &pnv
->chips
[i
]->psi
.ics
;
988 static void pnv_ics_resend(XICSFabric
*xi
)
990 PnvMachineState
*pnv
= POWERNV_MACHINE(xi
);
993 for (i
= 0; i
< pnv
->num_chips
; i
++) {
994 ics_resend(&pnv
->chips
[i
]->psi
.ics
);
998 static PowerPCCPU
*ppc_get_vcpu_by_pir(int pir
)
1003 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1004 CPUPPCState
*env
= &cpu
->env
;
1006 if (env
->spr_cb
[SPR_PIR
].default_value
== pir
) {
1014 static ICPState
*pnv_icp_get(XICSFabric
*xi
, int pir
)
1016 PowerPCCPU
*cpu
= ppc_get_vcpu_by_pir(pir
);
1018 return cpu
? ICP(cpu
->intc
) : NULL
;
1021 static void pnv_pic_print_info(InterruptStatsProvider
*obj
,
1024 PnvMachineState
*pnv
= POWERNV_MACHINE(obj
);
1029 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1031 icp_pic_print_info(ICP(cpu
->intc
), mon
);
1034 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1035 ics_pic_print_info(&pnv
->chips
[i
]->psi
.ics
, mon
);
1039 static void pnv_get_num_chips(Object
*obj
, Visitor
*v
, const char *name
,
1040 void *opaque
, Error
**errp
)
1042 visit_type_uint32(v
, name
, &POWERNV_MACHINE(obj
)->num_chips
, errp
);
1045 static void pnv_set_num_chips(Object
*obj
, Visitor
*v
, const char *name
,
1046 void *opaque
, Error
**errp
)
1048 PnvMachineState
*pnv
= POWERNV_MACHINE(obj
);
1050 Error
*local_err
= NULL
;
1052 visit_type_uint32(v
, name
, &num_chips
, &local_err
);
1054 error_propagate(errp
, local_err
);
1059 * TODO: should we decide on how many chips we can create based
1060 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
1062 if (!is_power_of_2(num_chips
) || num_chips
> 4) {
1063 error_setg(errp
, "invalid number of chips: '%d'", num_chips
);
1067 pnv
->num_chips
= num_chips
;
1070 static void powernv_machine_initfn(Object
*obj
)
1072 PnvMachineState
*pnv
= POWERNV_MACHINE(obj
);
1076 static void powernv_machine_class_props_init(ObjectClass
*oc
)
1078 object_class_property_add(oc
, "num-chips", "uint32",
1079 pnv_get_num_chips
, pnv_set_num_chips
,
1081 object_class_property_set_description(oc
, "num-chips",
1082 "Specifies the number of processor chips",
1086 static void powernv_machine_class_init(ObjectClass
*oc
, void *data
)
1088 MachineClass
*mc
= MACHINE_CLASS(oc
);
1089 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
1090 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
1092 mc
->desc
= "IBM PowerNV (Non-Virtualized)";
1093 mc
->init
= ppc_powernv_init
;
1094 mc
->reset
= ppc_powernv_reset
;
1095 mc
->max_cpus
= MAX_CPUS
;
1096 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
1097 mc
->block_default_type
= IF_IDE
; /* Pnv provides a AHCI device for
1099 mc
->no_parallel
= 1;
1100 mc
->default_boot_order
= NULL
;
1101 mc
->default_ram_size
= 1 * G_BYTE
;
1102 xic
->icp_get
= pnv_icp_get
;
1103 xic
->ics_get
= pnv_ics_get
;
1104 xic
->ics_resend
= pnv_ics_resend
;
1105 ispc
->print_info
= pnv_pic_print_info
;
1107 powernv_machine_class_props_init(oc
);
1110 #define DEFINE_PNV_CHIP_TYPE(type, class_initfn) \
1113 .class_init = class_initfn, \
1114 .parent = TYPE_PNV_CHIP, \
1117 static const TypeInfo types
[] = {
1119 .name
= TYPE_POWERNV_MACHINE
,
1120 .parent
= TYPE_MACHINE
,
1121 .instance_size
= sizeof(PnvMachineState
),
1122 .instance_init
= powernv_machine_initfn
,
1123 .class_init
= powernv_machine_class_init
,
1124 .interfaces
= (InterfaceInfo
[]) {
1125 { TYPE_XICS_FABRIC
},
1126 { TYPE_INTERRUPT_STATS_PROVIDER
},
1131 .name
= TYPE_PNV_CHIP
,
1132 .parent
= TYPE_SYS_BUS_DEVICE
,
1133 .class_init
= pnv_chip_class_init
,
1134 .instance_init
= pnv_chip_init
,
1135 .instance_size
= sizeof(PnvChip
),
1136 .class_size
= sizeof(PnvChipClass
),
1139 DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER9
, pnv_chip_power9_class_init
),
1140 DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8
, pnv_chip_power8_class_init
),
1141 DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E
, pnv_chip_power8e_class_init
),
1142 DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL
,
1143 pnv_chip_power8nvl_class_init
),