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hw/arm/aspeed: fix AST2500/AST2600 EVB fmc model
[qemu.git] / hw / arm / aspeed.c
bloba74c13ab0fbc00cfb903fe3840d091b28222a5a7
1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "hw/arm/boot.h"
15 #include "hw/arm/aspeed.h"
16 #include "hw/arm/aspeed_soc.h"
17 #include "hw/i2c/i2c_mux_pca954x.h"
18 #include "hw/i2c/smbus_eeprom.h"
19 #include "hw/misc/pca9552.h"
20 #include "hw/sensor/tmp105.h"
21 #include "hw/misc/led.h"
22 #include "hw/qdev-properties.h"
23 #include "sysemu/block-backend.h"
24 #include "hw/loader.h"
25 #include "qemu/error-report.h"
26 #include "qemu/units.h"
27 #include "hw/qdev-clock.h"
28
29 static struct arm_boot_info aspeed_board_binfo = {
30 .board_id = -1, /* device-tree-only board */
31 };
32
33 struct AspeedMachineState {
34 /* Private */
35 MachineState parent_obj;
36 /* Public */
37
38 AspeedSoCState soc;
39 MemoryRegion ram_container;
40 MemoryRegion max_ram;
41 bool mmio_exec;
42 char *fmc_model;
43 char *spi_model;
44 };
45
46 /* Palmetto hardware value: 0x120CE416 */
47 #define PALMETTO_BMC_HW_STRAP1 ( \
48 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
49 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
50 SCU_AST2400_HW_STRAP_ACPI_DIS | \
51 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
52 SCU_HW_STRAP_VGA_CLASS_CODE | \
53 SCU_HW_STRAP_LPC_RESET_PIN | \
54 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
55 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
56 SCU_HW_STRAP_SPI_WIDTH | \
57 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
58 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
59
60 /* TODO: Find the actual hardware value */
61 #define SUPERMICROX11_BMC_HW_STRAP1 ( \
62 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
63 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
64 SCU_AST2400_HW_STRAP_ACPI_DIS | \
65 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
66 SCU_HW_STRAP_VGA_CLASS_CODE | \
67 SCU_HW_STRAP_LPC_RESET_PIN | \
68 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
69 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
70 SCU_HW_STRAP_SPI_WIDTH | \
71 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
72 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
73
74 /* AST2500 evb hardware value: 0xF100C2E6 */
75 #define AST2500_EVB_HW_STRAP1 (( \
76 AST2500_HW_STRAP1_DEFAULTS | \
77 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
78 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
79 SCU_AST2500_HW_STRAP_UART_DEBUG | \
80 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
81 SCU_HW_STRAP_MAC1_RGMII | \
82 SCU_HW_STRAP_MAC0_RGMII) & \
83 ~SCU_HW_STRAP_2ND_BOOT_WDT)
84
85 /* Romulus hardware value: 0xF10AD206 */
86 #define ROMULUS_BMC_HW_STRAP1 ( \
87 AST2500_HW_STRAP1_DEFAULTS | \
88 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
89 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
90 SCU_AST2500_HW_STRAP_UART_DEBUG | \
91 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
92 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
93 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
94
95 /* Sonorapass hardware value: 0xF100D216 */
96 #define SONORAPASS_BMC_HW_STRAP1 ( \
97 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
98 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
99 SCU_AST2500_HW_STRAP_UART_DEBUG | \
100 SCU_AST2500_HW_STRAP_RESERVED28 | \
101 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
102 SCU_HW_STRAP_VGA_CLASS_CODE | \
103 SCU_HW_STRAP_LPC_RESET_PIN | \
104 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
105 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
106 SCU_HW_STRAP_VGA_BIOS_ROM | \
107 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
108 SCU_AST2500_HW_STRAP_RESERVED1)
109
110 #define G220A_BMC_HW_STRAP1 ( \
111 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
112 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
113 SCU_AST2500_HW_STRAP_UART_DEBUG | \
114 SCU_AST2500_HW_STRAP_RESERVED28 | \
115 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
116 SCU_HW_STRAP_2ND_BOOT_WDT | \
117 SCU_HW_STRAP_VGA_CLASS_CODE | \
118 SCU_HW_STRAP_LPC_RESET_PIN | \
119 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
120 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
121 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
122 SCU_AST2500_HW_STRAP_RESERVED1)
123
124 /* FP5280G2 hardware value: 0XF100D286 */
125 #define FP5280G2_BMC_HW_STRAP1 ( \
126 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
127 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
128 SCU_AST2500_HW_STRAP_UART_DEBUG | \
129 SCU_AST2500_HW_STRAP_RESERVED28 | \
130 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
131 SCU_HW_STRAP_VGA_CLASS_CODE | \
132 SCU_HW_STRAP_LPC_RESET_PIN | \
133 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
134 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
135 SCU_HW_STRAP_MAC1_RGMII | \
136 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
137 SCU_AST2500_HW_STRAP_RESERVED1)
138
139 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
140 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
141
142 /* Quanta-Q71l hardware value */
143 #define QUANTA_Q71L_BMC_HW_STRAP1 ( \
144 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
145 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
146 SCU_AST2400_HW_STRAP_ACPI_DIS | \
147 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
148 SCU_HW_STRAP_VGA_CLASS_CODE | \
149 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
150 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
151 SCU_HW_STRAP_SPI_WIDTH | \
152 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
153 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
154
155 /* AST2600 evb hardware value */
156 #define AST2600_EVB_HW_STRAP1 0x000000C0
157 #define AST2600_EVB_HW_STRAP2 0x00000003
158
159 /* Tacoma hardware value */
160 #define TACOMA_BMC_HW_STRAP1 0x00000000
161 #define TACOMA_BMC_HW_STRAP2 0x00000040
162
163 /* Rainier hardware value: (QEMU prototype) */
164 #define RAINIER_BMC_HW_STRAP1 0x00422016
165 #define RAINIER_BMC_HW_STRAP2 0x80000848
166
167 /* Fuji hardware value */
168 #define FUJI_BMC_HW_STRAP1 0x00000000
169 #define FUJI_BMC_HW_STRAP2 0x00000000
170
171 /* Bletchley hardware value */
172 /* TODO: Leave same as EVB for now. */
173 #define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
174 #define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
175
176 /*
177 * The max ram region is for firmwares that scan the address space
178 * with load/store to guess how much RAM the SoC has.
179 */
180 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
181 {
182 return 0;
183 }
184
185 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
186 unsigned size)
187 {
188 /* Discard writes */
189 }
190
191 static const MemoryRegionOps max_ram_ops = {
192 .read = max_ram_read,
193 .write = max_ram_write,
194 .endianness = DEVICE_NATIVE_ENDIAN,
195 };
196
197 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
198 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
199 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
200 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
201 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
202 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
203 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
204
205 static void aspeed_write_smpboot(ARMCPU *cpu,
206 const struct arm_boot_info *info)
207 {
208 static const uint32_t poll_mailbox_ready[] = {
209 /*
210 * r2 = per-cpu go sign value
211 * r1 = AST_SMP_MBOX_FIELD_ENTRY
212 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
213 */
214 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
215 0xe21000ff, /* ands r0, r0, #255 */
216 0xe59f201c, /* ldr r2, [pc, #28] */
217 0xe1822000, /* orr r2, r2, r0 */
218
219 0xe59f1018, /* ldr r1, [pc, #24] */
220 0xe59f0018, /* ldr r0, [pc, #24] */
221
222 0xe320f002, /* wfe */
223 0xe5904000, /* ldr r4, [r0] */
224 0xe1520004, /* cmp r2, r4 */
225 0x1afffffb, /* bne <wfe> */
226 0xe591f000, /* ldr pc, [r1] */
227 AST_SMP_MBOX_GOSIGN,
228 AST_SMP_MBOX_FIELD_ENTRY,
229 AST_SMP_MBOX_FIELD_GOSIGN,
230 };
231
232 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
233 sizeof(poll_mailbox_ready),
234 info->smp_loader_start);
235 }
236
237 static void aspeed_reset_secondary(ARMCPU *cpu,
238 const struct arm_boot_info *info)
239 {
240 AddressSpace *as = arm_boot_address_space(cpu, info);
241 CPUState *cs = CPU(cpu);
242
243 /* info->smp_bootreg_addr */
244 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
245 MEMTXATTRS_UNSPECIFIED, NULL);
246 cpu_set_pc(cs, info->smp_loader_start);
247 }
248
249 #define FIRMWARE_ADDR 0x0
250
251 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
252 Error **errp)
253 {
254 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
255 g_autofree void *storage = NULL;
256 int64_t size;
257
258 /* The block backend size should have already been 'validated' by
259 * the creation of the m25p80 object.
260 */
261 size = blk_getlength(blk);
262 if (size <= 0) {
263 error_setg(errp, "failed to get flash size");
264 return;
265 }
266
267 if (rom_size > size) {
268 rom_size = size;
269 }
270
271 storage = g_malloc0(rom_size);
272 if (blk_pread(blk, 0, storage, rom_size) < 0) {
273 error_setg(errp, "failed to read the initial flash content");
274 return;
275 }
276
277 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
278 }
279
280 static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
281 unsigned int count, int unit0)
282 {
283 int i;
284
285 if (!flashtype) {
286 return;
287 }
288
289 for (i = 0; i < count; ++i) {
290 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
291 qemu_irq cs_line;
292 DeviceState *dev;
293
294 dev = qdev_new(flashtype);
295 if (dinfo) {
296 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
297 }
298 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
299
300 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
301 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
302 }
303 }
304
305 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
306 {
307 DeviceState *card;
308
309 if (!dinfo) {
310 return;
311 }
312 card = qdev_new(TYPE_SD_CARD);
313 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
314 &error_fatal);
315 qdev_realize_and_unref(card,
316 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
317 &error_fatal);
318 }
319
320 static void aspeed_machine_init(MachineState *machine)
321 {
322 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
323 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
324 AspeedSoCClass *sc;
325 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
326 ram_addr_t max_ram_size;
327 int i;
328 NICInfo *nd = &nd_table[0];
329
330 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container",
331 4 * GiB);
332 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram);
333
334 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
335
336 sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
337
338 /*
339 * This will error out if isize is not supported by memory controller.
340 */
341 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
342 &error_fatal);
343
344 for (i = 0; i < sc->macs_num; i++) {
345 if ((amc->macs_mask & (1 << i)) && nd->used) {
346 qemu_check_nic_model(nd, TYPE_FTGMAC100);
347 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
348 nd++;
349 }
350 }
351
352 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
353 &error_abort);
354 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
355 &error_abort);
356 object_property_set_link(OBJECT(&bmc->soc), "dram",
357 OBJECT(machine->ram), &error_abort);
358 if (machine->kernel_filename) {
359 /*
360 * When booting with a -kernel command line there is no u-boot
361 * that runs to unlock the SCU. In this case set the default to
362 * be unlocked as the kernel expects
363 */
364 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
365 ASPEED_SCU_PROT_KEY, &error_abort);
366 }
367 qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default",
368 amc->uart_default);
369 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
370
371 memory_region_add_subregion(get_system_memory(),
372 sc->memmap[ASPEED_DEV_SDRAM],
373 &bmc->ram_container);
374
375 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
376 &error_abort);
377 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
378 "max_ram", max_ram_size - machine->ram_size);
379 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram);
380
381 aspeed_board_init_flashes(&bmc->soc.fmc,
382 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
383 amc->num_cs, 0);
384 aspeed_board_init_flashes(&bmc->soc.spi[0],
385 bmc->spi_model ? bmc->spi_model : amc->spi_model,
386 1, amc->num_cs);
387
388 /* Install first FMC flash content as a boot rom. */
389 if (drive0) {
390 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
391 MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
392 uint64_t size = memory_region_size(&fl->mmio);
393
394 /*
395 * create a ROM region using the default mapping window size of
396 * the flash module. The window size is 64MB for the AST2400
397 * SoC and 128MB for the AST2500 SoC, which is twice as big as
398 * needed by the flash modules of the Aspeed machines.
399 */
400 if (ASPEED_MACHINE(machine)->mmio_exec) {
401 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
402 &fl->mmio, 0, size);
403 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
404 boot_rom);
405 } else {
406 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
407 size, &error_abort);
408 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
409 boot_rom);
410 write_boot_rom(drive0, FIRMWARE_ADDR, size, &error_abort);
411 }
412 }
413
414 if (machine->kernel_filename && sc->num_cpus > 1) {
415 /* With no u-boot we must set up a boot stub for the secondary CPU */
416 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
417 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
418 0x80, &error_abort);
419 memory_region_add_subregion(get_system_memory(),
420 AST_SMP_MAILBOX_BASE, smpboot);
421
422 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
423 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
424 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
425 }
426
427 aspeed_board_binfo.ram_size = machine->ram_size;
428 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
429
430 if (amc->i2c_init) {
431 amc->i2c_init(bmc);
432 }
433
434 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
435 sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
436 drive_get(IF_SD, 0, i));
437 }
438
439 if (bmc->soc.emmc.num_slots) {
440 sdhci_attach_drive(&bmc->soc.emmc.slots[0],
441 drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
442 }
443
444 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
445 }
446
447 static void at24c_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
448 {
449 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
450 DeviceState *dev = DEVICE(i2c_dev);
451
452 qdev_prop_set_uint32(dev, "rom-size", rsize);
453 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
454 }
455
456 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
457 {
458 AspeedSoCState *soc = &bmc->soc;
459 DeviceState *dev;
460 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
461
462 /* The palmetto platform expects a ds3231 RTC but a ds1338 is
463 * enough to provide basic RTC features. Alarms will be missing */
464 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
465
466 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
467 eeprom_buf);
468
469 /* add a TMP423 temperature sensor */
470 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
471 "tmp423", 0x4c));
472 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
473 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
474 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
475 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
476 }
477
478 static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
479 {
480 AspeedSoCState *soc = &bmc->soc;
481
482 /*
483 * The quanta-q71l platform expects tmp75s which are compatible with
484 * tmp105s.
485 */
486 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
487 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
488 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
489
490 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
491 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
492 /* TODO: Add Memory Riser i2c mux and eeproms. */
493
494 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
495 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
496
497 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
498
499 /* i2c-7 */
500 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
501 /* - i2c@0: pmbus@59 */
502 /* - i2c@1: pmbus@58 */
503 /* - i2c@2: pmbus@58 */
504 /* - i2c@3: pmbus@59 */
505
506 /* TODO: i2c-7: Add PDB FRU eeprom@52 */
507 /* TODO: i2c-8: Add BMC FRU eeprom@50 */
508 }
509
510 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
511 {
512 AspeedSoCState *soc = &bmc->soc;
513 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
514
515 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
516 eeprom_buf);
517
518 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
519 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
520 TYPE_TMP105, 0x4d);
521
522 /* The AST2500 EVB does not have an RTC. Let's pretend that one is
523 * plugged on the I2C bus header */
524 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
525 }
526
527 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
528 {
529 /* Start with some devices on our I2C busses */
530 ast2500_evb_i2c_init(bmc);
531 }
532
533 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
534 {
535 AspeedSoCState *soc = &bmc->soc;
536
537 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
538 * good enough */
539 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
540 }
541
542 static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
543 {
544 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
545 TYPE_PCA9552, addr);
546 }
547
548 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
549 {
550 AspeedSoCState *soc = &bmc->soc;
551
552 /* bus 2 : */
553 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
554 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
555 /* bus 2 : pca9546 @ 0x73 */
556
557 /* bus 3 : pca9548 @ 0x70 */
558
559 /* bus 4 : */
560 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
561 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
562 eeprom4_54);
563 /* PCA9539 @ 0x76, but PCA9552 is compatible */
564 create_pca9552(soc, 4, 0x76);
565 /* PCA9539 @ 0x77, but PCA9552 is compatible */
566 create_pca9552(soc, 4, 0x77);
567
568 /* bus 6 : */
569 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
570 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
571 /* bus 6 : pca9546 @ 0x73 */
572
573 /* bus 8 : */
574 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
575 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
576 eeprom8_56);
577 create_pca9552(soc, 8, 0x60);
578 create_pca9552(soc, 8, 0x61);
579 /* bus 8 : adc128d818 @ 0x1d */
580 /* bus 8 : adc128d818 @ 0x1f */
581
582 /*
583 * bus 13 : pca9548 @ 0x71
584 * - channel 3:
585 * - tmm421 @ 0x4c
586 * - tmp421 @ 0x4e
587 * - tmp421 @ 0x4f
588 */
589
590 }
591
592 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
593 {
594 static const struct {
595 unsigned gpio_id;
596 LEDColor color;
597 const char *description;
598 bool gpio_polarity;
599 } pca1_leds[] = {
600 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
601 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
602 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
603 };
604 AspeedSoCState *soc = &bmc->soc;
605 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
606 DeviceState *dev;
607 LEDState *led;
608
609 /* Bus 3: TODO bmp280@77 */
610 /* Bus 3: TODO max31785@52 */
611 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
612 qdev_prop_set_string(dev, "description", "pca1");
613 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
614 aspeed_i2c_get_bus(&soc->i2c, 3),
615 &error_fatal);
616
617 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
618 led = led_create_simple(OBJECT(bmc),
619 pca1_leds[i].gpio_polarity,
620 pca1_leds[i].color,
621 pca1_leds[i].description);
622 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
623 qdev_get_gpio_in(DEVICE(led), 0));
624 }
625 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
626 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
627 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
628
629 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
630 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
631 0x4a);
632
633 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
634 * good enough */
635 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
636
637 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
638 eeprom_buf);
639 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
640 qdev_prop_set_string(dev, "description", "pca0");
641 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
642 aspeed_i2c_get_bus(&soc->i2c, 11),
643 &error_fatal);
644 /* Bus 11: TODO ucd90160@64 */
645 }
646
647 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
648 {
649 AspeedSoCState *soc = &bmc->soc;
650 DeviceState *dev;
651
652 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
653 "emc1413", 0x4c));
654 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
655 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
656 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
657
658 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
659 "emc1413", 0x4c));
660 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
661 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
662 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
663
664 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
665 "emc1413", 0x4c));
666 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
667 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
668 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
669
670 static uint8_t eeprom_buf[2 * 1024] = {
671 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
672 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
673 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
674 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
675 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
676 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
677 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
678 };
679 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
680 eeprom_buf);
681 }
682
683 static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
684 {
685 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
686 DeviceState *dev = DEVICE(i2c_dev);
687
688 qdev_prop_set_uint32(dev, "rom-size", rsize);
689 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
690 }
691
692 static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
693 {
694 AspeedSoCState *soc = &bmc->soc;
695 I2CSlave *i2c_mux;
696
697 /* The at24c256 */
698 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
699
700 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
701 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
702 0x48);
703 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
704 0x49);
705
706 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
707 "pca9546", 0x70);
708 /* It expects a TMP112 but a TMP105 is compatible */
709 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
710 0x4a);
711
712 /* It expects a ds3232 but a ds1338 is good enough */
713 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
714
715 /* It expects a pca9555 but a pca9552 is compatible */
716 create_pca9552(soc, 8, 0x30);
717 }
718
719 static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
720 {
721 AspeedSoCState *soc = &bmc->soc;
722 I2CSlave *i2c_mux;
723
724 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
725
726 create_pca9552(soc, 3, 0x61);
727
728 /* The rainier expects a TMP275 but a TMP105 is compatible */
729 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
730 0x48);
731 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
732 0x49);
733 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
734 0x4a);
735 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
736 "pca9546", 0x70);
737 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
738 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
739 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
740 create_pca9552(soc, 4, 0x60);
741
742 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
743 0x48);
744 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
745 0x49);
746 create_pca9552(soc, 5, 0x60);
747 create_pca9552(soc, 5, 0x61);
748 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
749 "pca9546", 0x70);
750 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
751 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
752
753 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
754 0x48);
755 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
756 0x4a);
757 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
758 0x4b);
759 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
760 "pca9546", 0x70);
761 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
762 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
763 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
764 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
765
766 create_pca9552(soc, 7, 0x30);
767 create_pca9552(soc, 7, 0x31);
768 create_pca9552(soc, 7, 0x32);
769 create_pca9552(soc, 7, 0x33);
770 /* Bus 7: TODO max31785@52 */
771 create_pca9552(soc, 7, 0x60);
772 create_pca9552(soc, 7, 0x61);
773 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
774 /* Bus 7: TODO si7021-a20@20 */
775 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
776 0x48);
777 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
778 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
779
780 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
781 0x48);
782 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
783 0x4a);
784 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
785 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
786 create_pca9552(soc, 8, 0x60);
787 create_pca9552(soc, 8, 0x61);
788 /* Bus 8: ucd90320@11 */
789 /* Bus 8: ucd90320@b */
790 /* Bus 8: ucd90320@c */
791
792 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
793 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
794 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
795
796 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
797 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
798 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
799
800 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
801 0x48);
802 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
803 0x49);
804 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
805 "pca9546", 0x70);
806 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
807 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
808 create_pca9552(soc, 11, 0x60);
809
810
811 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
812 create_pca9552(soc, 13, 0x60);
813
814 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
815 create_pca9552(soc, 14, 0x60);
816
817 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
818 create_pca9552(soc, 15, 0x60);
819 }
820
821 static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
822 I2CBus **channels)
823 {
824 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
825 for (int i = 0; i < 8; i++) {
826 channels[i] = pca954x_i2c_get_bus(mux, i);
827 }
828 }
829
830 #define TYPE_LM75 TYPE_TMP105
831 #define TYPE_TMP75 TYPE_TMP105
832 #define TYPE_TMP422 "tmp422"
833
834 static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
835 {
836 AspeedSoCState *soc = &bmc->soc;
837 I2CBus *i2c[144] = {};
838
839 for (int i = 0; i < 16; i++) {
840 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
841 }
842 I2CBus *i2c180 = i2c[2];
843 I2CBus *i2c480 = i2c[8];
844 I2CBus *i2c600 = i2c[11];
845
846 get_pca9548_channels(i2c180, 0x70, &i2c[16]);
847 get_pca9548_channels(i2c480, 0x70, &i2c[24]);
848 /* NOTE: The device tree skips [32, 40) in the alias numbering */
849 get_pca9548_channels(i2c600, 0x77, &i2c[40]);
850 get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
851 get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
852 get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
853 get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
854 for (int i = 0; i < 8; i++) {
855 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
856 }
857
858 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
859 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
860
861 aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB);
862 aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB);
863 aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB);
864
865 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
866 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
867 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
868 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
869
870 aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB);
871 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
872
873 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
874 aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB);
875 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
876 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
877
878 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
879 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
880
881 aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB);
882 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
883 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
884 aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB);
885 aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB);
886 aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB);
887 aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB);
888
889 aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB);
890 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
891 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
892 aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB);
893 aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB);
894 aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB);
895 aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB);
896 aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB);
897
898 for (int i = 0; i < 8; i++) {
899 aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
900 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
901 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
902 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
903 }
904 }
905
906 #define TYPE_TMP421 "tmp421"
907
908 static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
909 {
910 AspeedSoCState *soc = &bmc->soc;
911 I2CBus *i2c[13] = {};
912 for (int i = 0; i < 13; i++) {
913 if ((i == 8) || (i == 11)) {
914 continue;
915 }
916 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
917 }
918
919 /* Bus 0 - 5 all have the same config. */
920 for (int i = 0; i < 6; i++) {
921 /* Missing model: ti,ina230 @ 0x45 */
922 /* Missing model: mps,mp5023 @ 0x40 */
923 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
924 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
925 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
926 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
927 /* Missing model: fsc,fusb302 @ 0x22 */
928 }
929
930 /* Bus 6 */
931 at24c_eeprom_init(i2c[6], 0x56, 65536);
932 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
933 i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
934
935
936 /* Bus 7 */
937 at24c_eeprom_init(i2c[7], 0x54, 65536);
938
939 /* Bus 9 */
940 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
941
942 /* Bus 10 */
943 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
944 /* Missing model: ti,hdc1080 @ 0x40 */
945 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
946
947 /* Bus 12 */
948 /* Missing model: adi,adm1278 @ 0x11 */
949 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
950 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
951 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
952 }
953
954 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
955 {
956 return ASPEED_MACHINE(obj)->mmio_exec;
957 }
958
959 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
960 {
961 ASPEED_MACHINE(obj)->mmio_exec = value;
962 }
963
964 static void aspeed_machine_instance_init(Object *obj)
965 {
966 ASPEED_MACHINE(obj)->mmio_exec = false;
967 }
968
969 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
970 {
971 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
972 return g_strdup(bmc->fmc_model);
973 }
974
975 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
976 {
977 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
978
979 g_free(bmc->fmc_model);
980 bmc->fmc_model = g_strdup(value);
981 }
982
983 static char *aspeed_get_spi_model(Object *obj, Error **errp)
984 {
985 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
986 return g_strdup(bmc->spi_model);
987 }
988
989 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
990 {
991 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
992
993 g_free(bmc->spi_model);
994 bmc->spi_model = g_strdup(value);
995 }
996
997 static void aspeed_machine_class_props_init(ObjectClass *oc)
998 {
999 object_class_property_add_bool(oc, "execute-in-place",
1000 aspeed_get_mmio_exec,
1001 aspeed_set_mmio_exec);
1002 object_class_property_set_description(oc, "execute-in-place",
1003 "boot directly from CE0 flash device");
1004
1005 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1006 aspeed_set_fmc_model);
1007 object_class_property_set_description(oc, "fmc-model",
1008 "Change the FMC Flash model");
1009 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1010 aspeed_set_spi_model);
1011 object_class_property_set_description(oc, "spi-model",
1012 "Change the SPI Flash model");
1013 }
1014
1015 static int aspeed_soc_num_cpus(const char *soc_name)
1016 {
1017 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
1018 return sc->num_cpus;
1019 }
1020
1021 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
1022 {
1023 MachineClass *mc = MACHINE_CLASS(oc);
1024 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1025
1026 mc->init = aspeed_machine_init;
1027 mc->no_floppy = 1;
1028 mc->no_cdrom = 1;
1029 mc->no_parallel = 1;
1030 mc->default_ram_id = "ram";
1031 amc->macs_mask = ASPEED_MAC0_ON;
1032 amc->uart_default = ASPEED_DEV_UART5;
1033
1034 aspeed_machine_class_props_init(oc);
1035 }
1036
1037 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
1038 {
1039 MachineClass *mc = MACHINE_CLASS(oc);
1040 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1041
1042 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1043 amc->soc_name = "ast2400-a1";
1044 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1045 amc->fmc_model = "n25q256a";
1046 amc->spi_model = "mx25l25635e";
1047 amc->num_cs = 1;
1048 amc->i2c_init = palmetto_bmc_i2c_init;
1049 mc->default_ram_size = 256 * MiB;
1050 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1051 aspeed_soc_num_cpus(amc->soc_name);
1052 };
1053
1054 static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
1055 {
1056 MachineClass *mc = MACHINE_CLASS(oc);
1057 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1058
1059 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
1060 amc->soc_name = "ast2400-a1";
1061 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1062 amc->fmc_model = "n25q256a";
1063 amc->spi_model = "mx25l25635e";
1064 amc->num_cs = 1;
1065 amc->i2c_init = quanta_q71l_bmc_i2c_init;
1066 mc->default_ram_size = 128 * MiB;
1067 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1068 aspeed_soc_num_cpus(amc->soc_name);
1069 }
1070
1071 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1072 void *data)
1073 {
1074 MachineClass *mc = MACHINE_CLASS(oc);
1075 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1076
1077 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
1078 amc->soc_name = "ast2400-a1";
1079 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1080 amc->fmc_model = "mx25l25635e";
1081 amc->spi_model = "mx25l25635e";
1082 amc->num_cs = 1;
1083 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1084 amc->i2c_init = palmetto_bmc_i2c_init;
1085 mc->default_ram_size = 256 * MiB;
1086 }
1087
1088 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1089 {
1090 MachineClass *mc = MACHINE_CLASS(oc);
1091 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1092
1093 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
1094 amc->soc_name = "ast2500-a1";
1095 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
1096 amc->fmc_model = "mx25l25635e";
1097 amc->spi_model = "mx25l25635e";
1098 amc->num_cs = 1;
1099 amc->i2c_init = ast2500_evb_i2c_init;
1100 mc->default_ram_size = 512 * MiB;
1101 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1102 aspeed_soc_num_cpus(amc->soc_name);
1103 };
1104
1105 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1106 {
1107 MachineClass *mc = MACHINE_CLASS(oc);
1108 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1109
1110 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
1111 amc->soc_name = "ast2500-a1";
1112 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1113 amc->fmc_model = "n25q256a";
1114 amc->spi_model = "mx66l1g45g";
1115 amc->num_cs = 2;
1116 amc->i2c_init = romulus_bmc_i2c_init;
1117 mc->default_ram_size = 512 * MiB;
1118 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1119 aspeed_soc_num_cpus(amc->soc_name);
1120 };
1121
1122 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1123 {
1124 MachineClass *mc = MACHINE_CLASS(oc);
1125 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1126
1127 mc->desc = "OCP SonoraPass BMC (ARM1176)";
1128 amc->soc_name = "ast2500-a1";
1129 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1130 amc->fmc_model = "mx66l1g45g";
1131 amc->spi_model = "mx66l1g45g";
1132 amc->num_cs = 2;
1133 amc->i2c_init = sonorapass_bmc_i2c_init;
1134 mc->default_ram_size = 512 * MiB;
1135 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1136 aspeed_soc_num_cpus(amc->soc_name);
1137 };
1138
1139 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1140 {
1141 MachineClass *mc = MACHINE_CLASS(oc);
1142 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1143
1144 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
1145 amc->soc_name = "ast2500-a1";
1146 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1147 amc->fmc_model = "mx25l25635e";
1148 amc->spi_model = "mx66l1g45g";
1149 amc->num_cs = 2;
1150 amc->i2c_init = witherspoon_bmc_i2c_init;
1151 mc->default_ram_size = 512 * MiB;
1152 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1153 aspeed_soc_num_cpus(amc->soc_name);
1154 };
1155
1156 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1157 {
1158 MachineClass *mc = MACHINE_CLASS(oc);
1159 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1160
1161 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
1162 amc->soc_name = "ast2600-a3";
1163 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1164 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
1165 amc->fmc_model = "mx66u51235f";
1166 amc->spi_model = "mx66u51235f";
1167 amc->num_cs = 1;
1168 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1169 ASPEED_MAC3_ON;
1170 amc->i2c_init = ast2600_evb_i2c_init;
1171 mc->default_ram_size = 1 * GiB;
1172 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1173 aspeed_soc_num_cpus(amc->soc_name);
1174 };
1175
1176 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1177 {
1178 MachineClass *mc = MACHINE_CLASS(oc);
1179 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1180
1181 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)";
1182 amc->soc_name = "ast2600-a3";
1183 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1184 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1185 amc->fmc_model = "mx66l1g45g";
1186 amc->spi_model = "mx66l1g45g";
1187 amc->num_cs = 2;
1188 amc->macs_mask = ASPEED_MAC2_ON;
1189 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
1190 mc->default_ram_size = 1 * GiB;
1191 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1192 aspeed_soc_num_cpus(amc->soc_name);
1193 };
1194
1195 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1196 {
1197 MachineClass *mc = MACHINE_CLASS(oc);
1198 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1199
1200 mc->desc = "Bytedance G220A BMC (ARM1176)";
1201 amc->soc_name = "ast2500-a1";
1202 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1203 amc->fmc_model = "n25q512a";
1204 amc->spi_model = "mx25l25635e";
1205 amc->num_cs = 2;
1206 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1207 amc->i2c_init = g220a_bmc_i2c_init;
1208 mc->default_ram_size = 1024 * MiB;
1209 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1210 aspeed_soc_num_cpus(amc->soc_name);
1211 };
1212
1213 static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1214 {
1215 MachineClass *mc = MACHINE_CLASS(oc);
1216 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1217
1218 mc->desc = "Inspur FP5280G2 BMC (ARM1176)";
1219 amc->soc_name = "ast2500-a1";
1220 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1221 amc->fmc_model = "n25q512a";
1222 amc->spi_model = "mx25l25635e";
1223 amc->num_cs = 2;
1224 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1225 amc->i2c_init = fp5280g2_bmc_i2c_init;
1226 mc->default_ram_size = 512 * MiB;
1227 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1228 aspeed_soc_num_cpus(amc->soc_name);
1229 };
1230
1231 static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1232 {
1233 MachineClass *mc = MACHINE_CLASS(oc);
1234 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1235
1236 mc->desc = "IBM Rainier BMC (Cortex-A7)";
1237 amc->soc_name = "ast2600-a3";
1238 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1239 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1240 amc->fmc_model = "mx66l1g45g";
1241 amc->spi_model = "mx66l1g45g";
1242 amc->num_cs = 2;
1243 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1244 amc->i2c_init = rainier_bmc_i2c_init;
1245 mc->default_ram_size = 1 * GiB;
1246 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1247 aspeed_soc_num_cpus(amc->soc_name);
1248 };
1249
1250 /* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1251 #if HOST_LONG_BITS == 32
1252 #define FUJI_BMC_RAM_SIZE (1 * GiB)
1253 #else
1254 #define FUJI_BMC_RAM_SIZE (2 * GiB)
1255 #endif
1256
1257 static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1258 {
1259 MachineClass *mc = MACHINE_CLASS(oc);
1260 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1261
1262 mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1263 amc->soc_name = "ast2600-a3";
1264 amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1265 amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1266 amc->fmc_model = "mx66l1g45g";
1267 amc->spi_model = "mx66l1g45g";
1268 amc->num_cs = 2;
1269 amc->macs_mask = ASPEED_MAC3_ON;
1270 amc->i2c_init = fuji_bmc_i2c_init;
1271 amc->uart_default = ASPEED_DEV_UART1;
1272 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1273 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1274 aspeed_soc_num_cpus(amc->soc_name);
1275 };
1276
1277 static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
1278 {
1279 MachineClass *mc = MACHINE_CLASS(oc);
1280 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1281
1282 mc->desc = "Facebook Bletchley BMC (Cortex-A7)";
1283 amc->soc_name = "ast2600-a3";
1284 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1285 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1286 amc->fmc_model = "w25q01jvq";
1287 amc->spi_model = NULL;
1288 amc->num_cs = 2;
1289 amc->macs_mask = ASPEED_MAC2_ON;
1290 amc->i2c_init = bletchley_bmc_i2c_init;
1291 mc->default_ram_size = 512 * MiB;
1292 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1293 aspeed_soc_num_cpus(amc->soc_name);
1294 }
1295
1296 #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1297 /* Main SYSCLK frequency in Hz (200MHz) */
1298 #define SYSCLK_FRQ 200000000ULL
1299
1300 static void aspeed_minibmc_machine_init(MachineState *machine)
1301 {
1302 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1303 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1304 Clock *sysclk;
1305
1306 sysclk = clock_new(OBJECT(machine), "SYSCLK");
1307 clock_set_hz(sysclk, SYSCLK_FRQ);
1308
1309 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
1310 qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
1311
1312 qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default",
1313 amc->uart_default);
1314 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
1315
1316 aspeed_board_init_flashes(&bmc->soc.fmc,
1317 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1318 amc->num_cs,
1319 0);
1320
1321 aspeed_board_init_flashes(&bmc->soc.spi[0],
1322 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1323 amc->num_cs, amc->num_cs);
1324
1325 aspeed_board_init_flashes(&bmc->soc.spi[1],
1326 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1327 amc->num_cs, (amc->num_cs * 2));
1328
1329 if (amc->i2c_init) {
1330 amc->i2c_init(bmc);
1331 }
1332
1333 armv7m_load_kernel(ARM_CPU(first_cpu),
1334 machine->kernel_filename,
1335 AST1030_INTERNAL_FLASH_SIZE);
1336 }
1337
1338 static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1339 void *data)
1340 {
1341 MachineClass *mc = MACHINE_CLASS(oc);
1342 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1343
1344 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
1345 amc->soc_name = "ast1030-a1";
1346 amc->hw_strap1 = 0;
1347 amc->hw_strap2 = 0;
1348 mc->init = aspeed_minibmc_machine_init;
1349 mc->default_ram_size = 0;
1350 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
1351 amc->fmc_model = "sst25vf032b";
1352 amc->spi_model = "sst25vf032b";
1353 amc->num_cs = 2;
1354 amc->macs_mask = 0;
1355 }
1356
1357 static const TypeInfo aspeed_machine_types[] = {
1358 {
1359 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
1360 .parent = TYPE_ASPEED_MACHINE,
1361 .class_init = aspeed_machine_palmetto_class_init,
1362 }, {
1363 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1364 .parent = TYPE_ASPEED_MACHINE,
1365 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
1366 }, {
1367 .name = MACHINE_TYPE_NAME("ast2500-evb"),
1368 .parent = TYPE_ASPEED_MACHINE,
1369 .class_init = aspeed_machine_ast2500_evb_class_init,
1370 }, {
1371 .name = MACHINE_TYPE_NAME("romulus-bmc"),
1372 .parent = TYPE_ASPEED_MACHINE,
1373 .class_init = aspeed_machine_romulus_class_init,
1374 }, {
1375 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
1376 .parent = TYPE_ASPEED_MACHINE,
1377 .class_init = aspeed_machine_sonorapass_class_init,
1378 }, {
1379 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
1380 .parent = TYPE_ASPEED_MACHINE,
1381 .class_init = aspeed_machine_witherspoon_class_init,
1382 }, {
1383 .name = MACHINE_TYPE_NAME("ast2600-evb"),
1384 .parent = TYPE_ASPEED_MACHINE,
1385 .class_init = aspeed_machine_ast2600_evb_class_init,
1386 }, {
1387 .name = MACHINE_TYPE_NAME("tacoma-bmc"),
1388 .parent = TYPE_ASPEED_MACHINE,
1389 .class_init = aspeed_machine_tacoma_class_init,
1390 }, {
1391 .name = MACHINE_TYPE_NAME("g220a-bmc"),
1392 .parent = TYPE_ASPEED_MACHINE,
1393 .class_init = aspeed_machine_g220a_class_init,
1394 }, {
1395 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1396 .parent = TYPE_ASPEED_MACHINE,
1397 .class_init = aspeed_machine_fp5280g2_class_init,
1398 }, {
1399 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1400 .parent = TYPE_ASPEED_MACHINE,
1401 .class_init = aspeed_machine_quanta_q71l_class_init,
1402 }, {
1403 .name = MACHINE_TYPE_NAME("rainier-bmc"),
1404 .parent = TYPE_ASPEED_MACHINE,
1405 .class_init = aspeed_machine_rainier_class_init,
1406 }, {
1407 .name = MACHINE_TYPE_NAME("fuji-bmc"),
1408 .parent = TYPE_ASPEED_MACHINE,
1409 .class_init = aspeed_machine_fuji_class_init,
1410 }, {
1411 .name = MACHINE_TYPE_NAME("bletchley-bmc"),
1412 .parent = TYPE_ASPEED_MACHINE,
1413 .class_init = aspeed_machine_bletchley_class_init,
1414 }, {
1415 .name = MACHINE_TYPE_NAME("ast1030-evb"),
1416 .parent = TYPE_ASPEED_MACHINE,
1417 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
1418 }, {
1419 .name = TYPE_ASPEED_MACHINE,
1420 .parent = TYPE_MACHINE,
1421 .instance_size = sizeof(AspeedMachineState),
1422 .instance_init = aspeed_machine_instance_init,
1423 .class_size = sizeof(AspeedMachineClass),
1424 .class_init = aspeed_machine_class_init,
1425 .abstract = true,
1426 }
1427 };
1428
1429 DEFINE_TYPES(aspeed_machine_types)
QEmu