2 * QEMU PowerPC 405 evaluation boards emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
36 #define BIOS_FILENAME "ppc405_rom.bin"
37 #define BIOS_SIZE (2048 * 1024)
39 #define KERNEL_LOAD_ADDR 0x00000000
40 #define INITRD_LOAD_ADDR 0x01800000
42 #define USE_FLASH_BIOS
44 #define DEBUG_BOARD_INIT
46 /*****************************************************************************/
47 /* PPC405EP reference board (IBM) */
48 /* Standalone board with:
50 * - SDRAM (0x00000000)
51 * - Flash (0xFFF80000)
53 * - NVRAM (0xF0000000)
56 typedef struct ref405ep_fpga_t ref405ep_fpga_t
;
57 struct ref405ep_fpga_t
{
62 static uint32_t ref405ep_fpga_readb (void *opaque
, target_phys_addr_t addr
)
64 ref405ep_fpga_t
*fpga
;
83 static void ref405ep_fpga_writeb (void *opaque
,
84 target_phys_addr_t addr
, uint32_t value
)
86 ref405ep_fpga_t
*fpga
;
101 static uint32_t ref405ep_fpga_readw (void *opaque
, target_phys_addr_t addr
)
105 ret
= ref405ep_fpga_readb(opaque
, addr
) << 8;
106 ret
|= ref405ep_fpga_readb(opaque
, addr
+ 1);
111 static void ref405ep_fpga_writew (void *opaque
,
112 target_phys_addr_t addr
, uint32_t value
)
114 ref405ep_fpga_writeb(opaque
, addr
, (value
>> 8) & 0xFF);
115 ref405ep_fpga_writeb(opaque
, addr
+ 1, value
& 0xFF);
118 static uint32_t ref405ep_fpga_readl (void *opaque
, target_phys_addr_t addr
)
122 ret
= ref405ep_fpga_readb(opaque
, addr
) << 24;
123 ret
|= ref405ep_fpga_readb(opaque
, addr
+ 1) << 16;
124 ret
|= ref405ep_fpga_readb(opaque
, addr
+ 2) << 8;
125 ret
|= ref405ep_fpga_readb(opaque
, addr
+ 3);
130 static void ref405ep_fpga_writel (void *opaque
,
131 target_phys_addr_t addr
, uint32_t value
)
133 ref405ep_fpga_writeb(opaque
, addr
, (value
>> 24) & 0xFF);
134 ref405ep_fpga_writeb(opaque
, addr
+ 1, (value
>> 16) & 0xFF);
135 ref405ep_fpga_writeb(opaque
, addr
+ 2, (value
>> 8) & 0xFF);
136 ref405ep_fpga_writeb(opaque
, addr
+ 3, value
& 0xFF);
139 static CPUReadMemoryFunc
* const ref405ep_fpga_read
[] = {
140 &ref405ep_fpga_readb
,
141 &ref405ep_fpga_readw
,
142 &ref405ep_fpga_readl
,
145 static CPUWriteMemoryFunc
* const ref405ep_fpga_write
[] = {
146 &ref405ep_fpga_writeb
,
147 &ref405ep_fpga_writew
,
148 &ref405ep_fpga_writel
,
151 static void ref405ep_fpga_reset (void *opaque
)
153 ref405ep_fpga_t
*fpga
;
160 static void ref405ep_fpga_init (uint32_t base
)
162 ref405ep_fpga_t
*fpga
;
165 fpga
= g_malloc0(sizeof(ref405ep_fpga_t
));
166 fpga_memory
= cpu_register_io_memory(ref405ep_fpga_read
,
167 ref405ep_fpga_write
, fpga
,
168 DEVICE_NATIVE_ENDIAN
);
169 cpu_register_physical_memory(base
, 0x00000100, fpga_memory
);
170 qemu_register_reset(&ref405ep_fpga_reset
, fpga
);
173 static void ref405ep_init (ram_addr_t ram_size
,
174 const char *boot_device
,
175 const char *kernel_filename
,
176 const char *kernel_cmdline
,
177 const char *initrd_filename
,
178 const char *cpu_model
)
184 ram_addr_t sram_offset
, bios_offset
, bdloc
;
185 MemoryRegion
*ram_memories
= g_malloc(2 * sizeof(*ram_memories
));
186 target_phys_addr_t ram_bases
[2], ram_sizes
[2];
187 target_ulong sram_size
;
190 //static int phy_addr = 1;
191 target_ulong kernel_base
, initrd_base
;
192 long kernel_size
, initrd_size
;
194 int fl_idx
, fl_sectors
, len
;
198 memory_region_init_ram(&ram_memories
[0], NULL
, "ef405ep.ram", 0x08000000);
200 ram_sizes
[0] = 0x08000000;
201 memory_region_init(&ram_memories
[1], "ef405ep.ram1", 0);
202 ram_bases
[1] = 0x00000000;
203 ram_sizes
[1] = 0x00000000;
204 ram_size
= 128 * 1024 * 1024;
205 #ifdef DEBUG_BOARD_INIT
206 printf("%s: register cpu\n", __func__
);
208 env
= ppc405ep_init(ram_memories
, ram_bases
, ram_sizes
, 33333333, &pic
,
209 kernel_filename
== NULL
? 0 : 1);
211 sram_size
= 512 * 1024;
212 sram_offset
= qemu_ram_alloc(NULL
, "ef405ep.sram", sram_size
);
213 #ifdef DEBUG_BOARD_INIT
214 printf("%s: register SRAM at offset %08lx\n", __func__
, sram_offset
);
216 cpu_register_physical_memory(0xFFF00000, sram_size
,
217 sram_offset
| IO_MEM_RAM
);
218 /* allocate and load BIOS */
219 #ifdef DEBUG_BOARD_INIT
220 printf("%s: register BIOS\n", __func__
);
223 #ifdef USE_FLASH_BIOS
224 dinfo
= drive_get(IF_PFLASH
, 0, fl_idx
);
226 bios_size
= bdrv_getlength(dinfo
->bdrv
);
227 bios_offset
= qemu_ram_alloc(NULL
, "ef405ep.bios", bios_size
);
228 fl_sectors
= (bios_size
+ 65535) >> 16;
229 #ifdef DEBUG_BOARD_INIT
230 printf("Register parallel flash %d size %lx"
231 " at offset %08lx addr %lx '%s' %d\n",
232 fl_idx
, bios_size
, bios_offset
, -bios_size
,
233 bdrv_get_device_name(dinfo
->bdrv
), fl_sectors
);
235 pflash_cfi02_register((uint32_t)(-bios_size
), bios_offset
,
236 dinfo
->bdrv
, 65536, fl_sectors
, 1,
237 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
243 #ifdef DEBUG_BOARD_INIT
244 printf("Load BIOS from file\n");
246 bios_offset
= qemu_ram_alloc(NULL
, "ef405ep.bios", BIOS_SIZE
);
247 if (bios_name
== NULL
)
248 bios_name
= BIOS_FILENAME
;
249 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
251 bios_size
= load_image(filename
, qemu_get_ram_ptr(bios_offset
));
256 if (bios_size
< 0 || bios_size
> BIOS_SIZE
) {
257 fprintf(stderr
, "qemu: could not load PowerPC bios '%s'\n",
261 bios_size
= (bios_size
+ 0xfff) & ~0xfff;
262 cpu_register_physical_memory((uint32_t)(-bios_size
),
263 bios_size
, bios_offset
| IO_MEM_ROM
);
266 #ifdef DEBUG_BOARD_INIT
267 printf("%s: register FPGA\n", __func__
);
269 ref405ep_fpga_init(0xF0300000);
271 #ifdef DEBUG_BOARD_INIT
272 printf("%s: register NVRAM\n", __func__
);
274 m48t59_init(NULL
, 0xF0000000, 0, 8192, 8);
276 linux_boot
= (kernel_filename
!= NULL
);
278 #ifdef DEBUG_BOARD_INIT
279 printf("%s: load kernel\n", __func__
);
281 memset(&bd
, 0, sizeof(bd
));
282 bd
.bi_memstart
= 0x00000000;
283 bd
.bi_memsize
= ram_size
;
284 bd
.bi_flashstart
= -bios_size
;
285 bd
.bi_flashsize
= -bios_size
;
286 bd
.bi_flashoffset
= 0;
287 bd
.bi_sramstart
= 0xFFF00000;
288 bd
.bi_sramsize
= sram_size
;
290 bd
.bi_intfreq
= 133333333;
291 bd
.bi_busfreq
= 33333333;
292 bd
.bi_baudrate
= 115200;
293 bd
.bi_s_version
[0] = 'Q';
294 bd
.bi_s_version
[1] = 'M';
295 bd
.bi_s_version
[2] = 'U';
296 bd
.bi_s_version
[3] = '\0';
297 bd
.bi_r_version
[0] = 'Q';
298 bd
.bi_r_version
[1] = 'E';
299 bd
.bi_r_version
[2] = 'M';
300 bd
.bi_r_version
[3] = 'U';
301 bd
.bi_r_version
[4] = '\0';
302 bd
.bi_procfreq
= 133333333;
303 bd
.bi_plb_busfreq
= 33333333;
304 bd
.bi_pci_busfreq
= 33333333;
305 bd
.bi_opbfreq
= 33333333;
306 bdloc
= ppc405_set_bootinfo(env
, &bd
, 0x00000001);
308 kernel_base
= KERNEL_LOAD_ADDR
;
309 /* now we can load the kernel */
310 kernel_size
= load_image_targphys(kernel_filename
, kernel_base
,
311 ram_size
- kernel_base
);
312 if (kernel_size
< 0) {
313 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
317 printf("Load kernel size %ld at " TARGET_FMT_lx
,
318 kernel_size
, kernel_base
);
320 if (initrd_filename
) {
321 initrd_base
= INITRD_LOAD_ADDR
;
322 initrd_size
= load_image_targphys(initrd_filename
, initrd_base
,
323 ram_size
- initrd_base
);
324 if (initrd_size
< 0) {
325 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
333 env
->gpr
[4] = initrd_base
;
334 env
->gpr
[5] = initrd_size
;
335 if (kernel_cmdline
!= NULL
) {
336 len
= strlen(kernel_cmdline
);
337 bdloc
-= ((len
+ 255) & ~255);
338 cpu_physical_memory_write(bdloc
, (void *)kernel_cmdline
, len
+ 1);
340 env
->gpr
[7] = bdloc
+ len
;
345 env
->nip
= KERNEL_LOAD_ADDR
;
353 #ifdef DEBUG_BOARD_INIT
354 printf("%s: Done\n", __func__
);
356 printf("bdloc %016lx\n", (unsigned long)bdloc
);
359 static QEMUMachine ref405ep_machine
= {
362 .init
= ref405ep_init
,
365 /*****************************************************************************/
366 /* AMCC Taihu evaluation board */
367 /* - PowerPC 405EP processor
368 * - SDRAM 128 MB at 0x00000000
369 * - Boot flash 2 MB at 0xFFE00000
370 * - Application flash 32 MB at 0xFC000000
373 * - 1 USB 1.1 device 0x50000000
374 * - 1 LCD display 0x50100000
375 * - 1 CPLD 0x50100000
377 * - 1 I2C thermal sensor
379 * - bit-bang SPI port using GPIOs
380 * - 1 EBC interface connector 0 0x50200000
381 * - 1 cardbus controller + expansion slot.
382 * - 1 PCI expansion slot.
384 typedef struct taihu_cpld_t taihu_cpld_t
;
385 struct taihu_cpld_t
{
390 static uint32_t taihu_cpld_readb (void *opaque
, target_phys_addr_t addr
)
411 static void taihu_cpld_writeb (void *opaque
,
412 target_phys_addr_t addr
, uint32_t value
)
429 static uint32_t taihu_cpld_readw (void *opaque
, target_phys_addr_t addr
)
433 ret
= taihu_cpld_readb(opaque
, addr
) << 8;
434 ret
|= taihu_cpld_readb(opaque
, addr
+ 1);
439 static void taihu_cpld_writew (void *opaque
,
440 target_phys_addr_t addr
, uint32_t value
)
442 taihu_cpld_writeb(opaque
, addr
, (value
>> 8) & 0xFF);
443 taihu_cpld_writeb(opaque
, addr
+ 1, value
& 0xFF);
446 static uint32_t taihu_cpld_readl (void *opaque
, target_phys_addr_t addr
)
450 ret
= taihu_cpld_readb(opaque
, addr
) << 24;
451 ret
|= taihu_cpld_readb(opaque
, addr
+ 1) << 16;
452 ret
|= taihu_cpld_readb(opaque
, addr
+ 2) << 8;
453 ret
|= taihu_cpld_readb(opaque
, addr
+ 3);
458 static void taihu_cpld_writel (void *opaque
,
459 target_phys_addr_t addr
, uint32_t value
)
461 taihu_cpld_writel(opaque
, addr
, (value
>> 24) & 0xFF);
462 taihu_cpld_writel(opaque
, addr
+ 1, (value
>> 16) & 0xFF);
463 taihu_cpld_writel(opaque
, addr
+ 2, (value
>> 8) & 0xFF);
464 taihu_cpld_writeb(opaque
, addr
+ 3, value
& 0xFF);
467 static CPUReadMemoryFunc
* const taihu_cpld_read
[] = {
473 static CPUWriteMemoryFunc
* const taihu_cpld_write
[] = {
479 static void taihu_cpld_reset (void *opaque
)
488 static void taihu_cpld_init (uint32_t base
)
493 cpld
= g_malloc0(sizeof(taihu_cpld_t
));
494 cpld_memory
= cpu_register_io_memory(taihu_cpld_read
,
495 taihu_cpld_write
, cpld
,
496 DEVICE_NATIVE_ENDIAN
);
497 cpu_register_physical_memory(base
, 0x00000100, cpld_memory
);
498 qemu_register_reset(&taihu_cpld_reset
, cpld
);
501 static void taihu_405ep_init(ram_addr_t ram_size
,
502 const char *boot_device
,
503 const char *kernel_filename
,
504 const char *kernel_cmdline
,
505 const char *initrd_filename
,
506 const char *cpu_model
)
510 ram_addr_t bios_offset
;
511 MemoryRegion
*ram_memories
= g_malloc(2 * sizeof(*ram_memories
));
512 target_phys_addr_t ram_bases
[2], ram_sizes
[2];
514 target_ulong kernel_base
, initrd_base
;
515 long kernel_size
, initrd_size
;
517 int fl_idx
, fl_sectors
;
520 /* RAM is soldered to the board so the size cannot be changed */
521 memory_region_init_ram(&ram_memories
[0], NULL
,
522 "taihu_405ep.ram-0", 0x04000000);
524 ram_sizes
[0] = 0x04000000;
525 memory_region_init_ram(&ram_memories
[1], NULL
,
526 "taihu_405ep.ram-1", 0x04000000);
527 ram_bases
[1] = 0x04000000;
528 ram_sizes
[1] = 0x04000000;
529 ram_size
= 0x08000000;
530 #ifdef DEBUG_BOARD_INIT
531 printf("%s: register cpu\n", __func__
);
533 ppc405ep_init(ram_memories
, ram_bases
, ram_sizes
, 33333333, &pic
,
534 kernel_filename
== NULL
? 0 : 1);
535 /* allocate and load BIOS */
536 #ifdef DEBUG_BOARD_INIT
537 printf("%s: register BIOS\n", __func__
);
540 #if defined(USE_FLASH_BIOS)
541 dinfo
= drive_get(IF_PFLASH
, 0, fl_idx
);
543 bios_size
= bdrv_getlength(dinfo
->bdrv
);
544 /* XXX: should check that size is 2MB */
545 // bios_size = 2 * 1024 * 1024;
546 fl_sectors
= (bios_size
+ 65535) >> 16;
547 bios_offset
= qemu_ram_alloc(NULL
, "taihu_405ep.bios", bios_size
);
548 #ifdef DEBUG_BOARD_INIT
549 printf("Register parallel flash %d size %lx"
550 " at offset %08lx addr %lx '%s' %d\n",
551 fl_idx
, bios_size
, bios_offset
, -bios_size
,
552 bdrv_get_device_name(dinfo
->bdrv
), fl_sectors
);
554 pflash_cfi02_register((uint32_t)(-bios_size
), bios_offset
,
555 dinfo
->bdrv
, 65536, fl_sectors
, 1,
556 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
562 #ifdef DEBUG_BOARD_INIT
563 printf("Load BIOS from file\n");
565 if (bios_name
== NULL
)
566 bios_name
= BIOS_FILENAME
;
567 bios_offset
= qemu_ram_alloc(NULL
, "taihu_405ep.bios", BIOS_SIZE
);
568 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
570 bios_size
= load_image(filename
, qemu_get_ram_ptr(bios_offset
));
575 if (bios_size
< 0 || bios_size
> BIOS_SIZE
) {
576 fprintf(stderr
, "qemu: could not load PowerPC bios '%s'\n",
580 bios_size
= (bios_size
+ 0xfff) & ~0xfff;
581 cpu_register_physical_memory((uint32_t)(-bios_size
),
582 bios_size
, bios_offset
| IO_MEM_ROM
);
584 /* Register Linux flash */
585 dinfo
= drive_get(IF_PFLASH
, 0, fl_idx
);
587 bios_size
= bdrv_getlength(dinfo
->bdrv
);
588 /* XXX: should check that size is 32MB */
589 bios_size
= 32 * 1024 * 1024;
590 fl_sectors
= (bios_size
+ 65535) >> 16;
591 #ifdef DEBUG_BOARD_INIT
592 printf("Register parallel flash %d size %lx"
593 " at offset %08lx addr " TARGET_FMT_lx
" '%s'\n",
594 fl_idx
, bios_size
, bios_offset
, (target_ulong
)0xfc000000,
595 bdrv_get_device_name(dinfo
->bdrv
));
597 bios_offset
= qemu_ram_alloc(NULL
, "taihu_405ep.flash", bios_size
);
598 pflash_cfi02_register(0xfc000000, bios_offset
,
599 dinfo
->bdrv
, 65536, fl_sectors
, 1,
600 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
604 /* Register CLPD & LCD display */
605 #ifdef DEBUG_BOARD_INIT
606 printf("%s: register CPLD\n", __func__
);
608 taihu_cpld_init(0x50100000);
610 linux_boot
= (kernel_filename
!= NULL
);
612 #ifdef DEBUG_BOARD_INIT
613 printf("%s: load kernel\n", __func__
);
615 kernel_base
= KERNEL_LOAD_ADDR
;
616 /* now we can load the kernel */
617 kernel_size
= load_image_targphys(kernel_filename
, kernel_base
,
618 ram_size
- kernel_base
);
619 if (kernel_size
< 0) {
620 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
625 if (initrd_filename
) {
626 initrd_base
= INITRD_LOAD_ADDR
;
627 initrd_size
= load_image_targphys(initrd_filename
, initrd_base
,
628 ram_size
- initrd_base
);
629 if (initrd_size
< 0) {
631 "qemu: could not load initial ram disk '%s'\n",
645 #ifdef DEBUG_BOARD_INIT
646 printf("%s: Done\n", __func__
);
650 static QEMUMachine taihu_machine
= {
653 .init
= taihu_405ep_init
,
656 static void ppc405_machine_init(void)
658 qemu_register_machine(&ref405ep_machine
);
659 qemu_register_machine(&taihu_machine
);
662 machine_init(ppc405_machine_init
);