| blob | 5469ce041434fc3036d32044711533b93ad13ce0 |
1 # AArch64 SVE instruction descriptions
2 #
3 # Copyright (c) 2017 Linaro, Ltd
4 #
5 # This library is free software; you can redistribute it and/or
6 # modify it under the terms of the GNU Lesser General Public
7 # License as published by the Free Software Foundation; either
8 # version 2.1 of the License, or (at your option) any later version.
9 #
10 # This library is distributed in the hope that it will be useful,
11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 # Lesser General Public License for more details.
14 #
15 # You should have received a copy of the GNU Lesser General Public
16 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 #
19 # This file is processed by scripts/decodetree.py
20 #
22 ###########################################################################
23 # Named fields. These are primarily for disjoint fields.
25 %imm4_16_p1 16:4 !function=plus1
26 %imm6_22_5 22:1 5:5
27 %imm7_22_16 22:2 16:5
28 %imm8_16_10 16:5 10:3
29 %imm9_16_10 16:s6 10:3
30 %size_23 23:2
31 %dtype_23_13 23:2 13:2
32 %index3_22_19 22:1 19:2
33 %index3_19_11 19:2 11:1
34 %index2_20_11 20:1 11:1
36 # A combination of tsz:imm3 -- extract esize.
37 %tszimm_esz 22:2 5:5 !function=tszimm_esz
38 # A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3)
39 %tszimm_shr 22:2 5:5 !function=tszimm_shr
40 # A combination of tsz:imm3 -- extract (tsz:imm3) - esize
41 %tszimm_shl 22:2 5:5 !function=tszimm_shl
43 # Similarly for the tszh/tszl pair at 22/16 for zzi
44 %tszimm16_esz 22:2 16:5 !function=tszimm_esz
45 %tszimm16_shr 22:2 16:5 !function=tszimm_shr
46 %tszimm16_shl 22:2 16:5 !function=tszimm_shl
48 # Signed 8-bit immediate, optionally shifted left by 8.
49 %sh8_i8s 5:9 !function=expand_imm_sh8s
50 # Unsigned 8-bit immediate, optionally shifted left by 8.
51 %sh8_i8u 5:9 !function=expand_imm_sh8u
53 # Unsigned load of msz into esz=2, represented as a dtype.
54 %msz_dtype 23:2 !function=msz_dtype
56 # Either a copy of rd (at bit 0), or a different source
57 # as propagated via the MOVPRFX instruction.
58 %reg_movprfx 0:5
60 ###########################################################################
61 # Named attribute sets. These are used to make nice(er) names
62 # when creating helpers common to those for the individual
63 # instruction patterns.
65 &rr_esz rd rn esz
66 &rri rd rn imm
67 &rr_dbm rd rn dbm
68 &rrri rd rn rm imm
69 &rri_esz rd rn imm esz
70 &rrri_esz rd rn rm imm esz
71 &rrr_esz rd rn rm esz
72 &rrx_esz rd rn rm index esz
73 &rpr_esz rd pg rn esz
74 &rpr_s rd pg rn s
75 &rprr_s rd pg rn rm s
76 &rprr_esz rd pg rn rm esz
77 &rrrr_esz rd ra rn rm esz
78 &rrxr_esz rd rn rm ra index esz
79 &rprrr_esz rd pg rn rm ra esz
80 &rpri_esz rd pg rn imm esz
81 &ptrue rd esz pat s
82 &incdec_cnt rd pat esz imm d u
83 &incdec2_cnt rd rn pat esz imm d u
84 &incdec_pred rd pg esz d u
85 &incdec2_pred rd rn pg esz d u
86 &rprr_load rd pg rn rm dtype nreg
87 &rpri_load rd pg rn imm dtype nreg
88 &rprr_store rd pg rn rm msz esz nreg
89 &rpri_store rd pg rn imm msz esz nreg
90 &rprr_gather_load rd pg rn rm esz msz u ff xs scale
91 &rpri_gather_load rd pg rn imm esz msz u ff
92 &rprr_scatter_store rd pg rn rm esz msz xs scale
93 &rpri_scatter_store rd pg rn imm esz msz
95 ###########################################################################
96 # Named instruction formats. These are generally used to
97 # reduce the amount of duplication between instruction patterns.
99 # Two operand with unused vector element size
100 @pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
102 # Two operand
103 @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
104 @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz
106 # Two operand with governing predicate, flags setting
107 @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s
108 @pd_pg_pn_s0 ........ . . ...... .. pg:4 . rn:4 . rd:4 &rpr_s s=0
110 # Three operand with unused vector element size
111 @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
113 # Three predicate operand, with governing predicate, flag setting
114 @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s
116 # Three operand, vector element size
117 @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz
118 @pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz
119 @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \
120 &rrr_esz rn=%reg_movprfx
121 @rdn_rm_e0 ........ .. ...... ...... rm:5 rd:5 \
122 &rrr_esz rn=%reg_movprfx esz=0
123 @rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \
124 &rri_esz rn=%reg_movprfx imm=%sh8_i8u
125 @rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \
126 &rri_esz rn=%reg_movprfx
127 @rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \
128 &rri_esz rn=%reg_movprfx
130 # Four operand, vector element size
131 @rda_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 \
132 &rrrr_esz ra=%reg_movprfx
134 # Four operand with unused vector element size
135 @rdn_ra_rm_e0 ........ ... rm:5 ... ... ra:5 rd:5 \
136 &rrrr_esz esz=0 rn=%reg_movprfx
138 # Three operand with "memory" size, aka immediate left shift
139 @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri
141 # Two register operand, with governing predicate, vector element size
142 @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
143 &rprr_esz rn=%reg_movprfx
144 @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
145 &rprr_esz rm=%reg_movprfx
146 @rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz
147 @pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz
149 # Three register operand, with governing predicate, vector element size
150 @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \
151 &rprrr_esz ra=%reg_movprfx
152 @rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \
153 &rprrr_esz rn=%reg_movprfx
154 @rdn_pg_rm_ra ........ esz:2 . ra:5 ... pg:3 rm:5 rd:5 \
155 &rprrr_esz rn=%reg_movprfx
156 @rd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 &rprr_esz
158 # One register operand, with governing predicate, vector element size
159 @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz
160 @rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz
161 @pd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 . rd:4 &rpr_esz
163 # One register operand, with governing predicate, no vector element size
164 @rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0
166 # Two register operands with a 6-bit signed immediate.
167 @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
169 # Two register operand, one immediate operand, with predicate,
170 # element size encoded as TSZHL.
171 @rdn_pg_tszimm_shl ........ .. ... ... ... pg:3 ..... rd:5 \
172 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shl
173 @rdn_pg_tszimm_shr ........ .. ... ... ... pg:3 ..... rd:5 \
174 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shr
176 # Similarly without predicate.
177 @rd_rn_tszimm_shl ........ .. ... ... ...... rn:5 rd:5 \
178 &rri_esz esz=%tszimm16_esz imm=%tszimm16_shl
179 @rd_rn_tszimm_shr ........ .. ... ... ...... rn:5 rd:5 \
180 &rri_esz esz=%tszimm16_esz imm=%tszimm16_shr
182 # Two register operand, one immediate operand, with 4-bit predicate.
183 # User must fill in imm.
184 @rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \
185 &rpri_esz rn=%reg_movprfx
187 # Two register operand, one one-bit floating-point operand.
188 @rdn_i1 ........ esz:2 ......... pg:3 .... imm:1 rd:5 \
189 &rpri_esz rn=%reg_movprfx
191 # Two register operand, one encoded bitmask.
192 @rdn_dbm ........ .. .... dbm:13 rd:5 \
193 &rr_dbm rn=%reg_movprfx
195 # Predicate output, vector and immediate input,
196 # controlling predicate, element size.
197 @pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz
198 @pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz
200 # Basic Load/Store with 9-bit immediate offset
201 @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \
202 &rri imm=%imm9_16_10
203 @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \
204 &rri imm=%imm9_16_10
206 # One register, pattern, and uint4+1.
207 # User must fill in U and D.
208 @incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
209 &incdec_cnt imm=%imm4_16_p1
210 @incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
211 &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx
213 # One register, predicate.
214 # User must fill in U and D.
215 @incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred
216 @incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \
217 &incdec2_pred rn=%reg_movprfx
219 # Loads; user must fill in NREG.
220 @rprr_load_dt ....... dtype:4 rm:5 ... pg:3 rn:5 rd:5 &rprr_load
221 @rpri_load_dt ....... dtype:4 . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load
223 @rprr_load_msz ....... .... rm:5 ... pg:3 rn:5 rd:5 \
224 &rprr_load dtype=%msz_dtype
225 @rpri_load_msz ....... .... . imm:s4 ... pg:3 rn:5 rd:5 \
226 &rpri_load dtype=%msz_dtype
228 # Gather Loads.
229 @rprr_g_load_u ....... .. . . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
230 &rprr_gather_load xs=2
231 @rprr_g_load_xs_u ....... .. xs:1 . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
232 &rprr_gather_load
233 @rprr_g_load_xs_u_sc ....... .. xs:1 scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
234 &rprr_gather_load
235 @rprr_g_load_xs_sc ....... .. xs:1 scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \
236 &rprr_gather_load
237 @rprr_g_load_u_sc ....... .. . scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
238 &rprr_gather_load xs=2
239 @rprr_g_load_sc ....... .. . scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \
240 &rprr_gather_load xs=2
241 @rpri_g_load ....... msz:2 .. imm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
242 &rpri_gather_load
244 # Stores; user must fill in ESZ, MSZ, NREG as needed.
245 @rprr_store ....... .. .. rm:5 ... pg:3 rn:5 rd:5 &rprr_store
246 @rpri_store_msz ....... msz:2 .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store
247 @rprr_store_esz_n0 ....... .. esz:2 rm:5 ... pg:3 rn:5 rd:5 \
248 &rprr_store nreg=0
249 @rprr_scatter_store ....... msz:2 .. rm:5 ... pg:3 rn:5 rd:5 \
250 &rprr_scatter_store
251 @rpri_scatter_store ....... msz:2 .. imm:5 ... pg:3 rn:5 rd:5 \
252 &rpri_scatter_store
254 # Two registers and a scalar by N-bit index
255 @rrx_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \
256 &rrx_esz index=%index3_22_19
257 @rrx_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 &rrx_esz
258 @rrx_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 &rrx_esz
260 # Two registers and a scalar by N-bit index, alternate
261 @rrx_3a ........ .. . .. rm:3 ...... rn:5 rd:5 \
262 &rrx_esz index=%index3_19_11
263 @rrx_2a ........ .. . . rm:4 ...... rn:5 rd:5 \
264 &rrx_esz index=%index2_20_11
266 # Three registers and a scalar by N-bit index
267 @rrxr_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \
268 &rrxr_esz ra=%reg_movprfx index=%index3_22_19
269 @rrxr_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 \
270 &rrxr_esz ra=%reg_movprfx
271 @rrxr_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 \
272 &rrxr_esz ra=%reg_movprfx
274 # Three registers and a scalar by N-bit index, alternate
275 @rrxr_3a ........ .. ... rm:3 ...... rn:5 rd:5 \
276 &rrxr_esz ra=%reg_movprfx index=%index3_19_11
277 @rrxr_2a ........ .. .. rm:4 ...... rn:5 rd:5 \
278 &rrxr_esz ra=%reg_movprfx index=%index2_20_11
280 ###########################################################################
281 # Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
283 ### SVE Integer Arithmetic - Binary Predicated Group
285 # SVE bitwise logical vector operations (predicated)
286 ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm
287 EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm
288 AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm
289 BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm
291 # SVE integer add/subtract vectors (predicated)
292 ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm
293 SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm
294 SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR
296 # SVE integer min/max/difference (predicated)
297 SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm
298 UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm
299 SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm
300 UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm
301 SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm
302 UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm
304 # SVE integer multiply/divide (predicated)
305 MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm
306 SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm
307 UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm
308 # Note that divide requires size >= 2; below 2 is unallocated.
309 SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm
310 UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm
311 SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR
312 UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR
314 ### SVE Integer Reduction Group
316 # SVE bitwise logical reduction (predicated)
317 ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn
318 EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn
319 ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn
321 # SVE constructive prefix (predicated)
322 MOVPRFX_z 00000100 .. 010 000 001 ... ..... ..... @rd_pg_rn
323 MOVPRFX_m 00000100 .. 010 001 001 ... ..... ..... @rd_pg_rn
325 # SVE integer add reduction (predicated)
326 # Note that saddv requires size != 3.
327 UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn
328 SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn
330 # SVE integer min/max reduction (predicated)
331 SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn
332 UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn
333 SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn
334 UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
336 ### SVE Shift by Immediate - Predicated Group
338 # SVE bitwise shift by immediate (predicated)
339 ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... @rdn_pg_tszimm_shr
340 LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... @rdn_pg_tszimm_shr
341 LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... @rdn_pg_tszimm_shl
342 ASRD 00000100 .. 000 100 100 ... .. ... ..... @rdn_pg_tszimm_shr
344 # SVE bitwise shift by vector (predicated)
345 ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
346 LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm
347 LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm
348 ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR
349 LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR
350 LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR
352 # SVE bitwise shift by wide elements (predicated)
353 # Note these require size != 3.
354 ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm
355 LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm
356 LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm
358 ### SVE Integer Arithmetic - Unary Predicated Group
360 # SVE unary bit operations (predicated)
361 # Note esz != 0 for FABS and FNEG.
362 CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn
363 CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn
364 CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn
365 CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn
366 NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn
367 FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn
368 FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn
370 # SVE integer unary operations (predicated)
371 # Note esz > original size for extensions.
372 ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn
373 NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn
374 SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn
375 UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn
376 SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn
377 UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn
378 SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn
379 UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn
381 ### SVE Floating Point Compare - Vectors Group
383 # SVE floating-point compare vectors
384 FCMGE_ppzz 01100101 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm
385 FCMGT_ppzz 01100101 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm
386 FCMEQ_ppzz 01100101 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm
387 FCMNE_ppzz 01100101 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm
388 FCMUO_ppzz 01100101 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm
389 FACGE_ppzz 01100101 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm
390 FACGT_ppzz 01100101 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm
392 ### SVE Integer Multiply-Add Group
394 # SVE integer multiply-add writing addend (predicated)
395 MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm
396 MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm
398 # SVE integer multiply-add writing multiplicand (predicated)
399 MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD
400 MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB
402 ### SVE Integer Arithmetic - Unpredicated Group
404 # SVE integer add/subtract vectors (unpredicated)
405 ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm
406 SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm
407 SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm
408 UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm
409 SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm
410 UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm
412 ### SVE Logical - Unpredicated Group
414 # SVE bitwise logical operations (unpredicated)
415 AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
416 ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
417 EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
418 BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
420 XAR 00000100 .. 1 ..... 001 101 rm:5 rd:5 &rrri_esz \
421 rn=%reg_movprfx esz=%tszimm16_esz imm=%tszimm16_shr
423 # SVE2 bitwise ternary operations
424 EOR3 00000100 00 1 ..... 001 110 ..... ..... @rdn_ra_rm_e0
425 BSL 00000100 00 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0
426 BCAX 00000100 01 1 ..... 001 110 ..... ..... @rdn_ra_rm_e0
427 BSL1N 00000100 01 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0
428 BSL2N 00000100 10 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0
429 NBSL 00000100 11 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0
431 ### SVE Index Generation Group
433 # SVE index generation (immediate start, immediate increment)
434 INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5
436 # SVE index generation (immediate start, register increment)
437 INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5
439 # SVE index generation (register start, immediate increment)
440 INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5
442 # SVE index generation (register start, register increment)
443 INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm
445 ### SVE Stack Allocation Group
447 # SVE stack frame adjustment
448 ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6
449 ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6
451 # SVE stack frame size
452 RDVL 00000100 101 11111 01010 imm:s6 rd:5
454 ### SVE Bitwise Shift - Unpredicated Group
456 # SVE bitwise shift by immediate (unpredicated)
457 ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... @rd_rn_tszimm_shr
458 LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... @rd_rn_tszimm_shr
459 LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... @rd_rn_tszimm_shl
461 # SVE bitwise shift by wide elements (unpredicated)
462 # Note esz != 3
463 ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm
464 LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm
465 LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm
467 ### SVE Compute Vector Address Group
469 # SVE vector address generation
470 ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
471 ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
472 ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
473 ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
475 ### SVE Integer Misc - Unpredicated Group
477 # SVE constructive prefix (unpredicated)
478 MOVPRFX 00000100 00 1 00000 101111 rn:5 rd:5
480 # SVE floating-point exponential accelerator
481 # Note esz != 0
482 FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn
484 # SVE floating-point trig select coefficient
485 # Note esz != 0
486 FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm
488 ### SVE Element Count Group
490 # SVE element count
491 CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1
493 # SVE inc/dec register by element count
494 INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1
496 # SVE saturating inc/dec register by element count
497 SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
498 SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
500 # SVE inc/dec vector by element count
501 # Note this requires esz != 0.
502 INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1
504 # SVE saturating inc/dec vector by element count
505 # Note these require esz != 0.
506 SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt
508 ### SVE Bitwise Immediate Group
510 # SVE bitwise logical with immediate (unpredicated)
511 ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm
512 EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm
513 AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm
515 # SVE broadcast bitmask immediate
516 DUPM 00000101 11 0000 dbm:13 rd:5
518 ### SVE Integer Wide Immediate - Predicated Group
520 # SVE copy floating-point immediate (predicated)
521 FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4
523 # SVE copy integer immediate (predicated)
524 CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
525 CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
527 ### SVE Permute - Extract Group
529 # SVE extract vector (destructive)
530 EXT 00000101 001 ..... 000 ... rm:5 rd:5 \
531 &rrri rn=%reg_movprfx imm=%imm8_16_10
533 # SVE2 extract vector (constructive)
534 EXT_sve2 00000101 011 ..... 000 ... rn:5 rd:5 \
535 &rri imm=%imm8_16_10
537 ### SVE Permute - Unpredicated Group
539 # SVE broadcast general register
540 DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn
542 # SVE broadcast indexed element
543 DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \
544 &rri imm=%imm7_22_16
546 # SVE insert SIMD&FP scalar register
547 INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm
549 # SVE insert general register
550 INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm
552 # SVE reverse vector elements
553 REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn
555 # SVE vector table lookup
556 TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm
558 # SVE unpack vector elements
559 UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5
561 # SVE2 Table Lookup (three sources)
563 TBL_sve2 00000101 .. 1 ..... 001010 ..... ..... @rd_rn_rm
564 TBX 00000101 .. 1 ..... 001011 ..... ..... @rd_rn_rm
566 ### SVE Permute - Predicates Group
568 # SVE permute predicate elements
569 ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm
570 ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm
571 UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm
572 UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm
573 TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm
574 TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm
576 # SVE reverse predicate elements
577 REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn
579 # SVE unpack predicate elements
580 PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0
581 PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0
583 ### SVE Permute - Interleaving Group
585 # SVE permute vector elements
586 ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm
587 ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm
588 UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm
589 UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm
590 TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm
591 TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm
593 # SVE2 permute vector segments
594 ZIP1_q 00000101 10 1 ..... 000 000 ..... ..... @rd_rn_rm_e0
595 ZIP2_q 00000101 10 1 ..... 000 001 ..... ..... @rd_rn_rm_e0
596 UZP1_q 00000101 10 1 ..... 000 010 ..... ..... @rd_rn_rm_e0
597 UZP2_q 00000101 10 1 ..... 000 011 ..... ..... @rd_rn_rm_e0
598 TRN1_q 00000101 10 1 ..... 000 110 ..... ..... @rd_rn_rm_e0
599 TRN2_q 00000101 10 1 ..... 000 111 ..... ..... @rd_rn_rm_e0
601 ### SVE Permute - Predicated Group
603 # SVE compress active elements
604 # Note esz >= 2
605 COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn
607 # SVE conditionally broadcast element to vector
608 CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm
609 CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm
611 # SVE conditionally copy element to SIMD&FP scalar
612 CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn
613 CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn
615 # SVE conditionally copy element to general register
616 CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn
617 CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn
619 # SVE copy element to SIMD&FP scalar register
620 LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn
621 LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn
623 # SVE copy element to general register
624 LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn
625 LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn
627 # SVE copy element from SIMD&FP scalar register
628 CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn
630 # SVE copy element from general register to vector (predicated)
631 CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn
633 # SVE reverse within elements
634 # Note esz >= operation size
635 REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn
636 REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn
637 REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn
638 RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn
640 # SVE vector splice (predicated, destructive)
641 SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm
643 # SVE2 vector splice (predicated, constructive)
644 SPLICE_sve2 00000101 .. 101 101 100 ... ..... ..... @rd_pg_rn
646 ### SVE Select Vectors Group
648 # SVE select vector elements (predicated)
649 SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm
651 ### SVE Integer Compare - Vectors Group
653 # SVE integer compare_vectors
654 CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm
655 CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm
656 CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm
657 CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm
658 CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm
659 CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm
661 # SVE integer compare with wide elements
662 # Note these require esz != 3.
663 CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm
664 CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm
665 CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm
666 CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm
667 CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm
668 CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm
669 CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm
670 CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm
671 CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm
672 CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm
674 ### SVE Integer Compare - Unsigned Immediate Group
676 # SVE integer compare with unsigned immediate
677 CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7
678 CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7
679 CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7
680 CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7
682 ### SVE Integer Compare - Signed Immediate Group
684 # SVE integer compare with signed immediate
685 CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5
686 CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5
687 CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5
688 CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5
689 CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5
690 CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5
692 ### SVE Predicate Logical Operations Group
694 # SVE predicate logical operations
695 AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
696 BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
697 EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
698 SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
699 ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
700 ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
701 NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
702 NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
704 ### SVE Predicate Misc Group
706 # SVE predicate test
707 PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000
709 # SVE predicate initialize
710 PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4
712 # SVE initialize FFR
713 SETFFR 00100101 0010 1100 1001 0000 0000 0000
715 # SVE zero predicate register
716 PFALSE 00100101 0001 1000 1110 0100 0000 rd:4
718 # SVE predicate read from FFR (predicated)
719 RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4
721 # SVE predicate read from FFR (unpredicated)
722 RDFFR 00100101 0001 1001 1111 0000 0000 rd:4
724 # SVE FFR write from predicate (WRFFR)
725 WRFFR 00100101 0010 1000 1001 000 rn:4 00000
727 # SVE predicate first active
728 PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0
730 # SVE predicate next active
731 PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn
733 ### SVE Partition Break Group
735 # SVE propagate break from previous partition
736 BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s
737 BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s
739 # SVE partition break condition
740 BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s
741 BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s
742 BRKA_m 00100101 00 01000001 .... 0 .... 1 .... @pd_pg_pn_s0
743 BRKB_m 00100101 10 01000001 .... 0 .... 1 .... @pd_pg_pn_s0
745 # SVE propagate break to next partition
746 BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s
748 ### SVE Predicate Count Group
750 # SVE predicate count
751 CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn
753 # SVE inc/dec register by predicate count
754 INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1
756 # SVE inc/dec vector by predicate count
757 INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1
759 # SVE saturating inc/dec register by predicate count
760 SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred
761 SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred
763 # SVE saturating inc/dec vector by predicate count
764 SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred
766 ### SVE Integer Compare - Scalars Group
768 # SVE conditionally terminate scalars
769 CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000
771 # SVE integer compare scalar count and limit
772 WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 lt:1 rn:5 eq:1 rd:4
774 # SVE2 pointer conflict compare
775 WHILE_ptr 00100101 esz:2 1 rm:5 001 100 rn:5 rw:1 rd:4
777 ### SVE Integer Wide Immediate - Unpredicated Group
779 # SVE broadcast floating-point immediate (unpredicated)
780 FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
782 # SVE broadcast integer immediate (unpredicated)
783 DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
785 # SVE integer add/subtract immediate (unpredicated)
786 ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
787 SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
788 SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
789 SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
790 UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
791 SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
792 UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
794 # SVE integer min/max immediate (unpredicated)
795 SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s
796 UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u
797 SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s
798 UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u
800 # SVE integer multiply immediate (unpredicated)
801 MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s
803 # SVE integer dot product (unpredicated)
804 DOT_zzzz 01000100 1 sz:1 0 rm:5 00000 u:1 rn:5 rd:5 \
805 ra=%reg_movprfx
807 # SVE2 complex dot product (vectors)
808 CDOT_zzzz 01000100 esz:2 0 rm:5 0001 rot:2 rn:5 rd:5 ra=%reg_movprfx
810 #### SVE Multiply - Indexed
812 # SVE integer dot product (indexed)
813 SDOT_zzxw_s 01000100 10 1 ..... 000000 ..... ..... @rrxr_2 esz=2
814 SDOT_zzxw_d 01000100 11 1 ..... 000000 ..... ..... @rrxr_1 esz=3
815 UDOT_zzxw_s 01000100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2
816 UDOT_zzxw_d 01000100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3
818 # SVE2 integer multiply-add (indexed)
819 MLA_zzxz_h 01000100 0. 1 ..... 000010 ..... ..... @rrxr_3 esz=1
820 MLA_zzxz_s 01000100 10 1 ..... 000010 ..... ..... @rrxr_2 esz=2
821 MLA_zzxz_d 01000100 11 1 ..... 000010 ..... ..... @rrxr_1 esz=3
822 MLS_zzxz_h 01000100 0. 1 ..... 000011 ..... ..... @rrxr_3 esz=1
823 MLS_zzxz_s 01000100 10 1 ..... 000011 ..... ..... @rrxr_2 esz=2
824 MLS_zzxz_d 01000100 11 1 ..... 000011 ..... ..... @rrxr_1 esz=3
826 # SVE2 saturating multiply-add high (indexed)
827 SQRDMLAH_zzxz_h 01000100 0. 1 ..... 000100 ..... ..... @rrxr_3 esz=1
828 SQRDMLAH_zzxz_s 01000100 10 1 ..... 000100 ..... ..... @rrxr_2 esz=2
829 SQRDMLAH_zzxz_d 01000100 11 1 ..... 000100 ..... ..... @rrxr_1 esz=3
830 SQRDMLSH_zzxz_h 01000100 0. 1 ..... 000101 ..... ..... @rrxr_3 esz=1
831 SQRDMLSH_zzxz_s 01000100 10 1 ..... 000101 ..... ..... @rrxr_2 esz=2
832 SQRDMLSH_zzxz_d 01000100 11 1 ..... 000101 ..... ..... @rrxr_1 esz=3
834 # SVE mixed sign dot product (indexed)
835 USDOT_zzxw_s 01000100 10 1 ..... 000110 ..... ..... @rrxr_2 esz=2
836 SUDOT_zzxw_s 01000100 10 1 ..... 000111 ..... ..... @rrxr_2 esz=2
838 # SVE2 saturating multiply-add (indexed)
839 SQDMLALB_zzxw_s 01000100 10 1 ..... 0010.0 ..... ..... @rrxr_3a esz=2
840 SQDMLALB_zzxw_d 01000100 11 1 ..... 0010.0 ..... ..... @rrxr_2a esz=3
841 SQDMLALT_zzxw_s 01000100 10 1 ..... 0010.1 ..... ..... @rrxr_3a esz=2
842 SQDMLALT_zzxw_d 01000100 11 1 ..... 0010.1 ..... ..... @rrxr_2a esz=3
843 SQDMLSLB_zzxw_s 01000100 10 1 ..... 0011.0 ..... ..... @rrxr_3a esz=2
844 SQDMLSLB_zzxw_d 01000100 11 1 ..... 0011.0 ..... ..... @rrxr_2a esz=3
845 SQDMLSLT_zzxw_s 01000100 10 1 ..... 0011.1 ..... ..... @rrxr_3a esz=2
846 SQDMLSLT_zzxw_d 01000100 11 1 ..... 0011.1 ..... ..... @rrxr_2a esz=3
848 # SVE2 complex integer dot product (indexed)
849 CDOT_zzxw_s 01000100 10 1 index:2 rm:3 0100 rot:2 rn:5 rd:5 \
850 ra=%reg_movprfx
851 CDOT_zzxw_d 01000100 11 1 index:1 rm:4 0100 rot:2 rn:5 rd:5 \
852 ra=%reg_movprfx
854 # SVE2 complex integer multiply-add (indexed)
855 CMLA_zzxz_h 01000100 10 1 index:2 rm:3 0110 rot:2 rn:5 rd:5 \
856 ra=%reg_movprfx
857 CMLA_zzxz_s 01000100 11 1 index:1 rm:4 0110 rot:2 rn:5 rd:5 \
858 ra=%reg_movprfx
860 # SVE2 complex saturating integer multiply-add (indexed)
861 SQRDCMLAH_zzxz_h 01000100 10 1 index:2 rm:3 0111 rot:2 rn:5 rd:5 \
862 ra=%reg_movprfx
863 SQRDCMLAH_zzxz_s 01000100 11 1 index:1 rm:4 0111 rot:2 rn:5 rd:5 \
864 ra=%reg_movprfx
866 # SVE2 multiply-add long (indexed)
867 SMLALB_zzxw_s 01000100 10 1 ..... 1000.0 ..... ..... @rrxr_3a esz=2
868 SMLALB_zzxw_d 01000100 11 1 ..... 1000.0 ..... ..... @rrxr_2a esz=3
869 SMLALT_zzxw_s 01000100 10 1 ..... 1000.1 ..... ..... @rrxr_3a esz=2
870 SMLALT_zzxw_d 01000100 11 1 ..... 1000.1 ..... ..... @rrxr_2a esz=3
871 UMLALB_zzxw_s 01000100 10 1 ..... 1001.0 ..... ..... @rrxr_3a esz=2
872 UMLALB_zzxw_d 01000100 11 1 ..... 1001.0 ..... ..... @rrxr_2a esz=3
873 UMLALT_zzxw_s 01000100 10 1 ..... 1001.1 ..... ..... @rrxr_3a esz=2
874 UMLALT_zzxw_d 01000100 11 1 ..... 1001.1 ..... ..... @rrxr_2a esz=3
875 SMLSLB_zzxw_s 01000100 10 1 ..... 1010.0 ..... ..... @rrxr_3a esz=2
876 SMLSLB_zzxw_d 01000100 11 1 ..... 1010.0 ..... ..... @rrxr_2a esz=3
877 SMLSLT_zzxw_s 01000100 10 1 ..... 1010.1 ..... ..... @rrxr_3a esz=2
878 SMLSLT_zzxw_d 01000100 11 1 ..... 1010.1 ..... ..... @rrxr_2a esz=3
879 UMLSLB_zzxw_s 01000100 10 1 ..... 1011.0 ..... ..... @rrxr_3a esz=2
880 UMLSLB_zzxw_d 01000100 11 1 ..... 1011.0 ..... ..... @rrxr_2a esz=3
881 UMLSLT_zzxw_s 01000100 10 1 ..... 1011.1 ..... ..... @rrxr_3a esz=2
882 UMLSLT_zzxw_d 01000100 11 1 ..... 1011.1 ..... ..... @rrxr_2a esz=3
884 # SVE2 integer multiply long (indexed)
885 SMULLB_zzx_s 01000100 10 1 ..... 1100.0 ..... ..... @rrx_3a esz=2
886 SMULLB_zzx_d 01000100 11 1 ..... 1100.0 ..... ..... @rrx_2a esz=3
887 SMULLT_zzx_s 01000100 10 1 ..... 1100.1 ..... ..... @rrx_3a esz=2
888 SMULLT_zzx_d 01000100 11 1 ..... 1100.1 ..... ..... @rrx_2a esz=3
889 UMULLB_zzx_s 01000100 10 1 ..... 1101.0 ..... ..... @rrx_3a esz=2
890 UMULLB_zzx_d 01000100 11 1 ..... 1101.0 ..... ..... @rrx_2a esz=3
891 UMULLT_zzx_s 01000100 10 1 ..... 1101.1 ..... ..... @rrx_3a esz=2
892 UMULLT_zzx_d 01000100 11 1 ..... 1101.1 ..... ..... @rrx_2a esz=3
894 # SVE2 saturating multiply (indexed)
895 SQDMULLB_zzx_s 01000100 10 1 ..... 1110.0 ..... ..... @rrx_3a esz=2
896 SQDMULLB_zzx_d 01000100 11 1 ..... 1110.0 ..... ..... @rrx_2a esz=3
897 SQDMULLT_zzx_s 01000100 10 1 ..... 1110.1 ..... ..... @rrx_3a esz=2
898 SQDMULLT_zzx_d 01000100 11 1 ..... 1110.1 ..... ..... @rrx_2a esz=3
900 # SVE2 saturating multiply high (indexed)
901 SQDMULH_zzx_h 01000100 0. 1 ..... 111100 ..... ..... @rrx_3 esz=1
902 SQDMULH_zzx_s 01000100 10 1 ..... 111100 ..... ..... @rrx_2 esz=2
903 SQDMULH_zzx_d 01000100 11 1 ..... 111100 ..... ..... @rrx_1 esz=3
904 SQRDMULH_zzx_h 01000100 0. 1 ..... 111101 ..... ..... @rrx_3 esz=1
905 SQRDMULH_zzx_s 01000100 10 1 ..... 111101 ..... ..... @rrx_2 esz=2
906 SQRDMULH_zzx_d 01000100 11 1 ..... 111101 ..... ..... @rrx_1 esz=3
908 # SVE2 integer multiply (indexed)
909 MUL_zzx_h 01000100 0. 1 ..... 111110 ..... ..... @rrx_3 esz=1
910 MUL_zzx_s 01000100 10 1 ..... 111110 ..... ..... @rrx_2 esz=2
911 MUL_zzx_d 01000100 11 1 ..... 111110 ..... ..... @rrx_1 esz=3
913 # SVE floating-point complex add (predicated)
914 FCADD 01100100 esz:2 00000 rot:1 100 pg:3 rm:5 rd:5 \
915 rn=%reg_movprfx
917 # SVE floating-point complex multiply-add (predicated)
918 FCMLA_zpzzz 01100100 esz:2 0 rm:5 0 rot:2 pg:3 rn:5 rd:5 \
919 ra=%reg_movprfx
921 # SVE floating-point complex multiply-add (indexed)
922 FCMLA_zzxz 01100100 10 1 index:2 rm:3 0001 rot:2 rn:5 rd:5 \
923 ra=%reg_movprfx esz=1
924 FCMLA_zzxz 01100100 11 1 index:1 rm:4 0001 rot:2 rn:5 rd:5 \
925 ra=%reg_movprfx esz=2
927 ### SVE FP Multiply-Add Indexed Group
929 # SVE floating-point multiply-add (indexed)
930 FMLA_zzxz 01100100 0. 1 ..... 000000 ..... ..... @rrxr_3 esz=1
931 FMLA_zzxz 01100100 10 1 ..... 000000 ..... ..... @rrxr_2 esz=2
932 FMLA_zzxz 01100100 11 1 ..... 000000 ..... ..... @rrxr_1 esz=3
933 FMLS_zzxz 01100100 0. 1 ..... 000001 ..... ..... @rrxr_3 esz=1
934 FMLS_zzxz 01100100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2
935 FMLS_zzxz 01100100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3
937 ### SVE FP Multiply Indexed Group
939 # SVE floating-point multiply (indexed)
940 FMUL_zzx 01100100 0. 1 ..... 001000 ..... ..... @rrx_3 esz=1
941 FMUL_zzx 01100100 10 1 ..... 001000 ..... ..... @rrx_2 esz=2
942 FMUL_zzx 01100100 11 1 ..... 001000 ..... ..... @rrx_1 esz=3
944 ### SVE FP Fast Reduction Group
946 FADDV 01100101 .. 000 000 001 ... ..... ..... @rd_pg_rn
947 FMAXNMV 01100101 .. 000 100 001 ... ..... ..... @rd_pg_rn
948 FMINNMV 01100101 .. 000 101 001 ... ..... ..... @rd_pg_rn
949 FMAXV 01100101 .. 000 110 001 ... ..... ..... @rd_pg_rn
950 FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn
952 ## SVE Floating Point Unary Operations - Unpredicated Group
954 FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn
955 FRSQRTE 01100101 .. 001 111 001100 ..... ..... @rd_rn
957 ### SVE FP Compare with Zero Group
959 FCMGE_ppz0 01100101 .. 0100 00 001 ... ..... 0 .... @pd_pg_rn
960 FCMGT_ppz0 01100101 .. 0100 00 001 ... ..... 1 .... @pd_pg_rn
961 FCMLT_ppz0 01100101 .. 0100 01 001 ... ..... 0 .... @pd_pg_rn
962 FCMLE_ppz0 01100101 .. 0100 01 001 ... ..... 1 .... @pd_pg_rn
963 FCMEQ_ppz0 01100101 .. 0100 10 001 ... ..... 0 .... @pd_pg_rn
964 FCMNE_ppz0 01100101 .. 0100 11 001 ... ..... 0 .... @pd_pg_rn
966 ### SVE FP Accumulating Reduction Group
968 # SVE floating-point serial reduction (predicated)
969 FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm
971 ### SVE Floating Point Arithmetic - Unpredicated Group
973 # SVE floating-point arithmetic (unpredicated)
974 FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm
975 FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm
976 FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm
977 FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm
978 FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm
979 FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm
981 ### SVE FP Arithmetic Predicated Group
983 # SVE floating-point arithmetic (predicated)
984 FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm
985 FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm
986 FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm
987 FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR
988 FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm
989 FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm
990 FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm
991 FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm
992 FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm
993 FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm
994 FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm
995 FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR
996 FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm
998 # SVE floating-point arithmetic with immediate (predicated)
999 FADD_zpzi 01100101 .. 011 000 100 ... 0000 . ..... @rdn_i1
1000 FSUB_zpzi 01100101 .. 011 001 100 ... 0000 . ..... @rdn_i1
1001 FMUL_zpzi 01100101 .. 011 010 100 ... 0000 . ..... @rdn_i1
1002 FSUBR_zpzi 01100101 .. 011 011 100 ... 0000 . ..... @rdn_i1
1003 FMAXNM_zpzi 01100101 .. 011 100 100 ... 0000 . ..... @rdn_i1
1004 FMINNM_zpzi 01100101 .. 011 101 100 ... 0000 . ..... @rdn_i1
1005 FMAX_zpzi 01100101 .. 011 110 100 ... 0000 . ..... @rdn_i1
1006 FMIN_zpzi 01100101 .. 011 111 100 ... 0000 . ..... @rdn_i1
1008 # SVE floating-point trig multiply-add coefficient
1009 FTMAD 01100101 esz:2 010 imm:3 100000 rm:5 rd:5 rn=%reg_movprfx
1011 ### SVE FP Multiply-Add Group
1013 # SVE floating-point multiply-accumulate writing addend
1014 FMLA_zpzzz 01100101 .. 1 ..... 000 ... ..... ..... @rda_pg_rn_rm
1015 FMLS_zpzzz 01100101 .. 1 ..... 001 ... ..... ..... @rda_pg_rn_rm
1016 FNMLA_zpzzz 01100101 .. 1 ..... 010 ... ..... ..... @rda_pg_rn_rm
1017 FNMLS_zpzzz 01100101 .. 1 ..... 011 ... ..... ..... @rda_pg_rn_rm
1019 # SVE floating-point multiply-accumulate writing multiplicand
1020 # Alter the operand extraction order and reuse the helpers from above.
1021 # FMAD, FMSB, FNMAD, FNMS
1022 FMLA_zpzzz 01100101 .. 1 ..... 100 ... ..... ..... @rdn_pg_rm_ra
1023 FMLS_zpzzz 01100101 .. 1 ..... 101 ... ..... ..... @rdn_pg_rm_ra
1024 FNMLA_zpzzz 01100101 .. 1 ..... 110 ... ..... ..... @rdn_pg_rm_ra
1025 FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ..... @rdn_pg_rm_ra
1027 ### SVE FP Unary Operations Predicated Group
1029 # SVE floating-point convert precision
1030 FCVT_sh 01100101 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0
1031 FCVT_hs 01100101 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0
1032 FCVT_dh 01100101 11 0010 00 101 ... ..... ..... @rd_pg_rn_e0
1033 FCVT_hd 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_e0
1034 FCVT_ds 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0
1035 FCVT_sd 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0
1037 # SVE floating-point convert to integer
1038 FCVTZS_hh 01100101 01 011 01 0 101 ... ..... ..... @rd_pg_rn_e0
1039 FCVTZU_hh 01100101 01 011 01 1 101 ... ..... ..... @rd_pg_rn_e0
1040 FCVTZS_hs 01100101 01 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
1041 FCVTZU_hs 01100101 01 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
1042 FCVTZS_hd 01100101 01 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
1043 FCVTZU_hd 01100101 01 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
1044 FCVTZS_ss 01100101 10 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
1045 FCVTZU_ss 01100101 10 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
1046 FCVTZS_ds 01100101 11 011 00 0 101 ... ..... ..... @rd_pg_rn_e0
1047 FCVTZU_ds 01100101 11 011 00 1 101 ... ..... ..... @rd_pg_rn_e0
1048 FCVTZS_sd 01100101 11 011 10 0 101 ... ..... ..... @rd_pg_rn_e0
1049 FCVTZU_sd 01100101 11 011 10 1 101 ... ..... ..... @rd_pg_rn_e0
1050 FCVTZS_dd 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0
1051 FCVTZU_dd 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0
1053 # SVE floating-point round to integral value
1054 FRINTN 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn
1055 FRINTP 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn
1056 FRINTM 01100101 .. 000 010 101 ... ..... ..... @rd_pg_rn
1057 FRINTZ 01100101 .. 000 011 101 ... ..... ..... @rd_pg_rn
1058 FRINTA 01100101 .. 000 100 101 ... ..... ..... @rd_pg_rn
1059 FRINTX 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn
1060 FRINTI 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn
1062 # SVE floating-point unary operations
1063 FRECPX 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn
1064 FSQRT 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn
1066 # SVE integer convert to floating-point
1067 SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0
1068 SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
1069 SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
1070 SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
1071 SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0
1072 SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
1073 SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
1075 UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0
1076 UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
1077 UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
1078 UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
1079 UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0
1080 UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
1081 UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
1083 ### SVE Memory - 32-bit Gather and Unsized Contiguous Group
1085 # SVE load predicate register
1086 LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9
1088 # SVE load vector register
1089 LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9
1091 # SVE load and broadcast element
1092 LD1R_zpri 1000010 .. 1 imm:6 1.. pg:3 rn:5 rd:5 \
1093 &rpri_load dtype=%dtype_23_13 nreg=0
1095 # SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)
1096 # SVE 32-bit gather load (scalar plus 32-bit scaled offsets)
1097 LD1_zprz 1000010 00 .0 ..... 0.. ... ..... ..... \
1098 @rprr_g_load_xs_u esz=2 msz=0 scale=0
1099 LD1_zprz 1000010 01 .. ..... 0.. ... ..... ..... \
1100 @rprr_g_load_xs_u_sc esz=2 msz=1
1101 LD1_zprz 1000010 10 .. ..... 01. ... ..... ..... \
1102 @rprr_g_load_xs_sc esz=2 msz=2 u=1
1104 # SVE 32-bit gather load (vector plus immediate)
1105 LD1_zpiz 1000010 .. 01 ..... 1.. ... ..... ..... \
1106 @rpri_g_load esz=2
1108 ### SVE Memory Contiguous Load Group
1110 # SVE contiguous load (scalar plus scalar)
1111 LD_zprr 1010010 .... ..... 010 ... ..... ..... @rprr_load_dt nreg=0
1113 # SVE contiguous first-fault load (scalar plus scalar)
1114 LDFF1_zprr 1010010 .... ..... 011 ... ..... ..... @rprr_load_dt nreg=0
1116 # SVE contiguous load (scalar plus immediate)
1117 LD_zpri 1010010 .... 0.... 101 ... ..... ..... @rpri_load_dt nreg=0
1119 # SVE contiguous non-fault load (scalar plus immediate)
1120 LDNF1_zpri 1010010 .... 1.... 101 ... ..... ..... @rpri_load_dt nreg=0
1122 # SVE contiguous non-temporal load (scalar plus scalar)
1123 # LDNT1B, LDNT1H, LDNT1W, LDNT1D
1124 # SVE load multiple structures (scalar plus scalar)
1125 # LD2B, LD2H, LD2W, LD2D; etc.
1126 LD_zprr 1010010 .. nreg:2 ..... 110 ... ..... ..... @rprr_load_msz
1128 # SVE contiguous non-temporal load (scalar plus immediate)
1129 # LDNT1B, LDNT1H, LDNT1W, LDNT1D
1130 # SVE load multiple structures (scalar plus immediate)
1131 # LD2B, LD2H, LD2W, LD2D; etc.
1132 LD_zpri 1010010 .. nreg:2 0.... 111 ... ..... ..... @rpri_load_msz
1134 # SVE load and broadcast quadword (scalar plus scalar)
1135 LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \
1136 @rprr_load_msz nreg=0
1137 LD1RO_zprr 1010010 .. 01 ..... 000 ... ..... ..... \
1138 @rprr_load_msz nreg=0
1140 # SVE load and broadcast quadword (scalar plus immediate)
1141 # LD1RQB, LD1RQH, LD1RQS, LD1RQD
1142 LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \
1143 @rpri_load_msz nreg=0
1144 LD1RO_zpri 1010010 .. 01 0.... 001 ... ..... ..... \
1145 @rpri_load_msz nreg=0
1147 # SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)
1148 PRF 1000010 00 -1 ----- 0-- --- ----- 0 ----
1150 # SVE 32-bit gather prefetch (vector plus immediate)
1151 PRF 1000010 -- 00 ----- 111 --- ----- 0 ----
1153 # SVE contiguous prefetch (scalar plus immediate)
1154 PRF 1000010 11 1- ----- 0-- --- ----- 0 ----
1156 # SVE contiguous prefetch (scalar plus scalar)
1157 PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ----
1159 ### SVE Memory 64-bit Gather Group
1161 # SVE 64-bit gather load (scalar plus 32-bit unpacked unscaled offsets)
1162 # SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)
1163 LD1_zprz 1100010 00 .0 ..... 0.. ... ..... ..... \
1164 @rprr_g_load_xs_u esz=3 msz=0 scale=0
1165 LD1_zprz 1100010 01 .. ..... 0.. ... ..... ..... \
1166 @rprr_g_load_xs_u_sc esz=3 msz=1
1167 LD1_zprz 1100010 10 .. ..... 0.. ... ..... ..... \
1168 @rprr_g_load_xs_u_sc esz=3 msz=2
1169 LD1_zprz 1100010 11 .. ..... 01. ... ..... ..... \
1170 @rprr_g_load_xs_sc esz=3 msz=3 u=1
1172 # SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)
1173 # SVE 64-bit gather load (scalar plus 64-bit scaled offsets)
1174 LD1_zprz 1100010 00 10 ..... 1.. ... ..... ..... \
1175 @rprr_g_load_u esz=3 msz=0 scale=0
1176 LD1_zprz 1100010 01 1. ..... 1.. ... ..... ..... \
1177 @rprr_g_load_u_sc esz=3 msz=1
1178 LD1_zprz 1100010 10 1. ..... 1.. ... ..... ..... \
1179 @rprr_g_load_u_sc esz=3 msz=2
1180 LD1_zprz 1100010 11 1. ..... 11. ... ..... ..... \
1181 @rprr_g_load_sc esz=3 msz=3 u=1
1183 # SVE 64-bit gather load (vector plus immediate)
1184 LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \
1185 @rpri_g_load esz=3
1187 # SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)
1188 PRF 1100010 00 11 ----- 1-- --- ----- 0 ----
1190 # SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)
1191 PRF 1100010 00 -1 ----- 0-- --- ----- 0 ----
1193 # SVE 64-bit gather prefetch (vector plus immediate)
1194 PRF 1100010 -- 00 ----- 111 --- ----- 0 ----
1196 ### SVE Memory Store Group
1198 # SVE store predicate register
1199 STR_pri 1110010 11 0. ..... 000 ... ..... 0 .... @pd_rn_i9
1201 # SVE store vector register
1202 STR_zri 1110010 11 0. ..... 010 ... ..... ..... @rd_rn_i9
1204 # SVE contiguous store (scalar plus immediate)
1205 # ST1B, ST1H, ST1W, ST1D; require msz <= esz
1206 ST_zpri 1110010 .. esz:2 0.... 111 ... ..... ..... \
1207 @rpri_store_msz nreg=0
1209 # SVE contiguous store (scalar plus scalar)
1210 # ST1B, ST1H, ST1W, ST1D; require msz <= esz
1211 # Enumerate msz lest we conflict with STR_zri.
1212 ST_zprr 1110010 00 .. ..... 010 ... ..... ..... \
1213 @rprr_store_esz_n0 msz=0
1214 ST_zprr 1110010 01 .. ..... 010 ... ..... ..... \
1215 @rprr_store_esz_n0 msz=1
1216 ST_zprr 1110010 10 .. ..... 010 ... ..... ..... \
1217 @rprr_store_esz_n0 msz=2
1218 ST_zprr 1110010 11 11 ..... 010 ... ..... ..... \
1219 @rprr_store msz=3 esz=3 nreg=0
1221 # SVE contiguous non-temporal store (scalar plus immediate) (nreg == 0)
1222 # SVE store multiple structures (scalar plus immediate) (nreg != 0)
1223 ST_zpri 1110010 .. nreg:2 1.... 111 ... ..... ..... \
1224 @rpri_store_msz esz=%size_23
1226 # SVE contiguous non-temporal store (scalar plus scalar) (nreg == 0)
1227 # SVE store multiple structures (scalar plus scalar) (nreg != 0)
1228 ST_zprr 1110010 msz:2 nreg:2 ..... 011 ... ..... ..... \
1229 @rprr_store esz=%size_23
1231 # SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)
1232 # Require msz > 0 && msz <= esz.
1233 ST1_zprz 1110010 .. 11 ..... 100 ... ..... ..... \
1234 @rprr_scatter_store xs=0 esz=2 scale=1
1235 ST1_zprz 1110010 .. 11 ..... 110 ... ..... ..... \
1236 @rprr_scatter_store xs=1 esz=2 scale=1
1238 # SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)
1239 # Require msz <= esz.
1240 ST1_zprz 1110010 .. 10 ..... 100 ... ..... ..... \
1241 @rprr_scatter_store xs=0 esz=2 scale=0
1242 ST1_zprz 1110010 .. 10 ..... 110 ... ..... ..... \
1243 @rprr_scatter_store xs=1 esz=2 scale=0
1245 # SVE 64-bit scatter store (scalar plus 64-bit scaled offset)
1246 # Require msz > 0
1247 ST1_zprz 1110010 .. 01 ..... 101 ... ..... ..... \
1248 @rprr_scatter_store xs=2 esz=3 scale=1
1250 # SVE 64-bit scatter store (scalar plus 64-bit unscaled offset)
1251 ST1_zprz 1110010 .. 00 ..... 101 ... ..... ..... \
1252 @rprr_scatter_store xs=2 esz=3 scale=0
1254 # SVE 64-bit scatter store (vector plus immediate)
1255 ST1_zpiz 1110010 .. 10 ..... 101 ... ..... ..... \
1256 @rpri_scatter_store esz=3
1258 # SVE 32-bit scatter store (vector plus immediate)
1259 ST1_zpiz 1110010 .. 11 ..... 101 ... ..... ..... \
1260 @rpri_scatter_store esz=2
1262 # SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offset)
1263 # Require msz > 0
1264 ST1_zprz 1110010 .. 01 ..... 100 ... ..... ..... \
1265 @rprr_scatter_store xs=0 esz=3 scale=1
1266 ST1_zprz 1110010 .. 01 ..... 110 ... ..... ..... \
1267 @rprr_scatter_store xs=1 esz=3 scale=1
1269 # SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offset)
1270 ST1_zprz 1110010 .. 00 ..... 100 ... ..... ..... \
1271 @rprr_scatter_store xs=0 esz=3 scale=0
1272 ST1_zprz 1110010 .. 00 ..... 110 ... ..... ..... \
1273 @rprr_scatter_store xs=1 esz=3 scale=0
1275 #### SVE2 Support
1277 ### SVE2 Integer Multiply - Unpredicated
1279 # SVE2 integer multiply vectors (unpredicated)
1280 MUL_zzz 00000100 .. 1 ..... 0110 00 ..... ..... @rd_rn_rm
1281 SMULH_zzz 00000100 .. 1 ..... 0110 10 ..... ..... @rd_rn_rm
1282 UMULH_zzz 00000100 .. 1 ..... 0110 11 ..... ..... @rd_rn_rm
1283 PMUL_zzz 00000100 00 1 ..... 0110 01 ..... ..... @rd_rn_rm_e0
1285 # SVE2 signed saturating doubling multiply high (unpredicated)
1286 SQDMULH_zzz 00000100 .. 1 ..... 0111 00 ..... ..... @rd_rn_rm
1287 SQRDMULH_zzz 00000100 .. 1 ..... 0111 01 ..... ..... @rd_rn_rm
1289 ### SVE2 Integer - Predicated
1291 SADALP_zpzz 01000100 .. 000 100 101 ... ..... ..... @rdm_pg_rn
1292 UADALP_zpzz 01000100 .. 000 101 101 ... ..... ..... @rdm_pg_rn
1294 ### SVE2 integer unary operations (predicated)
1296 URECPE 01000100 .. 000 000 101 ... ..... ..... @rd_pg_rn
1297 URSQRTE 01000100 .. 000 001 101 ... ..... ..... @rd_pg_rn
1298 SQABS 01000100 .. 001 000 101 ... ..... ..... @rd_pg_rn
1299 SQNEG 01000100 .. 001 001 101 ... ..... ..... @rd_pg_rn
1301 ### SVE2 saturating/rounding bitwise shift left (predicated)
1303 SRSHL 01000100 .. 000 010 100 ... ..... ..... @rdn_pg_rm
1304 URSHL 01000100 .. 000 011 100 ... ..... ..... @rdn_pg_rm
1305 SRSHL 01000100 .. 000 110 100 ... ..... ..... @rdm_pg_rn # SRSHLR
1306 URSHL 01000100 .. 000 111 100 ... ..... ..... @rdm_pg_rn # URSHLR
1308 SQSHL 01000100 .. 001 000 100 ... ..... ..... @rdn_pg_rm
1309 UQSHL 01000100 .. 001 001 100 ... ..... ..... @rdn_pg_rm
1310 SQSHL 01000100 .. 001 100 100 ... ..... ..... @rdm_pg_rn # SQSHLR
1311 UQSHL 01000100 .. 001 101 100 ... ..... ..... @rdm_pg_rn # UQSHLR
1313 SQRSHL 01000100 .. 001 010 100 ... ..... ..... @rdn_pg_rm
1314 UQRSHL 01000100 .. 001 011 100 ... ..... ..... @rdn_pg_rm
1315 SQRSHL 01000100 .. 001 110 100 ... ..... ..... @rdm_pg_rn # SQRSHLR
1316 UQRSHL 01000100 .. 001 111 100 ... ..... ..... @rdm_pg_rn # UQRSHLR
1318 ### SVE2 integer halving add/subtract (predicated)
1320 SHADD 01000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
1321 UHADD 01000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm
1322 SHSUB 01000100 .. 010 010 100 ... ..... ..... @rdn_pg_rm
1323 UHSUB 01000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm
1324 SRHADD 01000100 .. 010 100 100 ... ..... ..... @rdn_pg_rm
1325 URHADD 01000100 .. 010 101 100 ... ..... ..... @rdn_pg_rm
1326 SHSUB 01000100 .. 010 110 100 ... ..... ..... @rdm_pg_rn # SHSUBR
1327 UHSUB 01000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # UHSUBR
1329 ### SVE2 integer pairwise arithmetic
1331 ADDP 01000100 .. 010 001 101 ... ..... ..... @rdn_pg_rm
1332 SMAXP 01000100 .. 010 100 101 ... ..... ..... @rdn_pg_rm
1333 UMAXP 01000100 .. 010 101 101 ... ..... ..... @rdn_pg_rm
1334 SMINP 01000100 .. 010 110 101 ... ..... ..... @rdn_pg_rm
1335 UMINP 01000100 .. 010 111 101 ... ..... ..... @rdn_pg_rm
1337 ### SVE2 saturating add/subtract (predicated)
1339 SQADD_zpzz 01000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm
1340 UQADD_zpzz 01000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm
1341 SQSUB_zpzz 01000100 .. 011 010 100 ... ..... ..... @rdn_pg_rm
1342 UQSUB_zpzz 01000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm
1343 SUQADD 01000100 .. 011 100 100 ... ..... ..... @rdn_pg_rm
1344 USQADD 01000100 .. 011 101 100 ... ..... ..... @rdn_pg_rm
1345 SQSUB_zpzz 01000100 .. 011 110 100 ... ..... ..... @rdm_pg_rn # SQSUBR
1346 UQSUB_zpzz 01000100 .. 011 111 100 ... ..... ..... @rdm_pg_rn # UQSUBR
1348 #### SVE2 Widening Integer Arithmetic
1350 ## SVE2 integer add/subtract long
1352 SADDLB 01000101 .. 0 ..... 00 0000 ..... ..... @rd_rn_rm
1353 SADDLT 01000101 .. 0 ..... 00 0001 ..... ..... @rd_rn_rm
1354 UADDLB 01000101 .. 0 ..... 00 0010 ..... ..... @rd_rn_rm
1355 UADDLT 01000101 .. 0 ..... 00 0011 ..... ..... @rd_rn_rm
1357 SSUBLB 01000101 .. 0 ..... 00 0100 ..... ..... @rd_rn_rm
1358 SSUBLT 01000101 .. 0 ..... 00 0101 ..... ..... @rd_rn_rm
1359 USUBLB 01000101 .. 0 ..... 00 0110 ..... ..... @rd_rn_rm
1360 USUBLT 01000101 .. 0 ..... 00 0111 ..... ..... @rd_rn_rm
1362 SABDLB 01000101 .. 0 ..... 00 1100 ..... ..... @rd_rn_rm
1363 SABDLT 01000101 .. 0 ..... 00 1101 ..... ..... @rd_rn_rm
1364 UABDLB 01000101 .. 0 ..... 00 1110 ..... ..... @rd_rn_rm
1365 UABDLT 01000101 .. 0 ..... 00 1111 ..... ..... @rd_rn_rm
1367 ## SVE2 integer add/subtract interleaved long
1369 SADDLBT 01000101 .. 0 ..... 1000 00 ..... ..... @rd_rn_rm
1370 SSUBLBT 01000101 .. 0 ..... 1000 10 ..... ..... @rd_rn_rm
1371 SSUBLTB 01000101 .. 0 ..... 1000 11 ..... ..... @rd_rn_rm
1373 ## SVE2 integer add/subtract wide
1375 SADDWB 01000101 .. 0 ..... 010 000 ..... ..... @rd_rn_rm
1376 SADDWT 01000101 .. 0 ..... 010 001 ..... ..... @rd_rn_rm
1377 UADDWB 01000101 .. 0 ..... 010 010 ..... ..... @rd_rn_rm
1378 UADDWT 01000101 .. 0 ..... 010 011 ..... ..... @rd_rn_rm
1380 SSUBWB 01000101 .. 0 ..... 010 100 ..... ..... @rd_rn_rm
1381 SSUBWT 01000101 .. 0 ..... 010 101 ..... ..... @rd_rn_rm
1382 USUBWB 01000101 .. 0 ..... 010 110 ..... ..... @rd_rn_rm
1383 USUBWT 01000101 .. 0 ..... 010 111 ..... ..... @rd_rn_rm
1385 ## SVE2 integer multiply long
1387 SQDMULLB_zzz 01000101 .. 0 ..... 011 000 ..... ..... @rd_rn_rm
1388 SQDMULLT_zzz 01000101 .. 0 ..... 011 001 ..... ..... @rd_rn_rm
1389 PMULLB 01000101 .. 0 ..... 011 010 ..... ..... @rd_rn_rm
1390 PMULLT 01000101 .. 0 ..... 011 011 ..... ..... @rd_rn_rm
1391 SMULLB_zzz 01000101 .. 0 ..... 011 100 ..... ..... @rd_rn_rm
1392 SMULLT_zzz 01000101 .. 0 ..... 011 101 ..... ..... @rd_rn_rm
1393 UMULLB_zzz 01000101 .. 0 ..... 011 110 ..... ..... @rd_rn_rm
1394 UMULLT_zzz 01000101 .. 0 ..... 011 111 ..... ..... @rd_rn_rm
1396 ## SVE2 bitwise shift left long
1398 # Note bit23 == 0 is handled by esz > 0 in do_sve2_shll_tb.
1399 SSHLLB 01000101 .. 0 ..... 1010 00 ..... ..... @rd_rn_tszimm_shl
1400 SSHLLT 01000101 .. 0 ..... 1010 01 ..... ..... @rd_rn_tszimm_shl
1401 USHLLB 01000101 .. 0 ..... 1010 10 ..... ..... @rd_rn_tszimm_shl
1402 USHLLT 01000101 .. 0 ..... 1010 11 ..... ..... @rd_rn_tszimm_shl
1404 ## SVE2 bitwise exclusive-or interleaved
1406 EORBT 01000101 .. 0 ..... 10010 0 ..... ..... @rd_rn_rm
1407 EORTB 01000101 .. 0 ..... 10010 1 ..... ..... @rd_rn_rm
1409 ## SVE2 bitwise permute
1411 BEXT 01000101 .. 0 ..... 1011 00 ..... ..... @rd_rn_rm
1412 BDEP 01000101 .. 0 ..... 1011 01 ..... ..... @rd_rn_rm
1413 BGRP 01000101 .. 0 ..... 1011 10 ..... ..... @rd_rn_rm
1415 #### SVE2 Accumulate
1417 ## SVE2 complex integer add
1419 CADD_rot90 01000101 .. 00000 0 11011 0 ..... ..... @rdn_rm
1420 CADD_rot270 01000101 .. 00000 0 11011 1 ..... ..... @rdn_rm
1421 SQCADD_rot90 01000101 .. 00000 1 11011 0 ..... ..... @rdn_rm
1422 SQCADD_rot270 01000101 .. 00000 1 11011 1 ..... ..... @rdn_rm
1424 ## SVE2 integer absolute difference and accumulate long
1426 SABALB 01000101 .. 0 ..... 1100 00 ..... ..... @rda_rn_rm
1427 SABALT 01000101 .. 0 ..... 1100 01 ..... ..... @rda_rn_rm
1428 UABALB 01000101 .. 0 ..... 1100 10 ..... ..... @rda_rn_rm
1429 UABALT 01000101 .. 0 ..... 1100 11 ..... ..... @rda_rn_rm
1431 ## SVE2 integer add/subtract long with carry
1433 # ADC and SBC decoded via size in helper dispatch.
1434 ADCLB 01000101 .. 0 ..... 11010 0 ..... ..... @rda_rn_rm
1435 ADCLT 01000101 .. 0 ..... 11010 1 ..... ..... @rda_rn_rm
1437 ## SVE2 bitwise shift right and accumulate
1439 # TODO: Use @rda and %reg_movprfx here.
1440 SSRA 01000101 .. 0 ..... 1110 00 ..... ..... @rd_rn_tszimm_shr
1441 USRA 01000101 .. 0 ..... 1110 01 ..... ..... @rd_rn_tszimm_shr
1442 SRSRA 01000101 .. 0 ..... 1110 10 ..... ..... @rd_rn_tszimm_shr
1443 URSRA 01000101 .. 0 ..... 1110 11 ..... ..... @rd_rn_tszimm_shr
1445 ## SVE2 bitwise shift and insert
1447 SRI 01000101 .. 0 ..... 11110 0 ..... ..... @rd_rn_tszimm_shr
1448 SLI 01000101 .. 0 ..... 11110 1 ..... ..... @rd_rn_tszimm_shl
1450 ## SVE2 integer absolute difference and accumulate
1452 # TODO: Use @rda and %reg_movprfx here.
1453 SABA 01000101 .. 0 ..... 11111 0 ..... ..... @rd_rn_rm
1454 UABA 01000101 .. 0 ..... 11111 1 ..... ..... @rd_rn_rm
1456 #### SVE2 Narrowing
1458 ## SVE2 saturating extract narrow
1460 # Bits 23, 18-16 are zero, limited in the translator via esz < 3 & imm == 0.
1461 SQXTNB 01000101 .. 1 ..... 010 000 ..... ..... @rd_rn_tszimm_shl
1462 SQXTNT 01000101 .. 1 ..... 010 001 ..... ..... @rd_rn_tszimm_shl
1463 UQXTNB 01000101 .. 1 ..... 010 010 ..... ..... @rd_rn_tszimm_shl
1464 UQXTNT 01000101 .. 1 ..... 010 011 ..... ..... @rd_rn_tszimm_shl
1465 SQXTUNB 01000101 .. 1 ..... 010 100 ..... ..... @rd_rn_tszimm_shl
1466 SQXTUNT 01000101 .. 1 ..... 010 101 ..... ..... @rd_rn_tszimm_shl
1468 ## SVE2 bitwise shift right narrow
1470 # Bit 23 == 0 is handled by esz > 0 in the translator.
1471 SQSHRUNB 01000101 .. 1 ..... 00 0000 ..... ..... @rd_rn_tszimm_shr
1472 SQSHRUNT 01000101 .. 1 ..... 00 0001 ..... ..... @rd_rn_tszimm_shr
1473 SQRSHRUNB 01000101 .. 1 ..... 00 0010 ..... ..... @rd_rn_tszimm_shr
1474 SQRSHRUNT 01000101 .. 1 ..... 00 0011 ..... ..... @rd_rn_tszimm_shr
1475 SHRNB 01000101 .. 1 ..... 00 0100 ..... ..... @rd_rn_tszimm_shr
1476 SHRNT 01000101 .. 1 ..... 00 0101 ..... ..... @rd_rn_tszimm_shr
1477 RSHRNB 01000101 .. 1 ..... 00 0110 ..... ..... @rd_rn_tszimm_shr
1478 RSHRNT 01000101 .. 1 ..... 00 0111 ..... ..... @rd_rn_tszimm_shr
1479 SQSHRNB 01000101 .. 1 ..... 00 1000 ..... ..... @rd_rn_tszimm_shr
1480 SQSHRNT 01000101 .. 1 ..... 00 1001 ..... ..... @rd_rn_tszimm_shr
1481 SQRSHRNB 01000101 .. 1 ..... 00 1010 ..... ..... @rd_rn_tszimm_shr
1482 SQRSHRNT 01000101 .. 1 ..... 00 1011 ..... ..... @rd_rn_tszimm_shr
1483 UQSHRNB 01000101 .. 1 ..... 00 1100 ..... ..... @rd_rn_tszimm_shr
1484 UQSHRNT 01000101 .. 1 ..... 00 1101 ..... ..... @rd_rn_tszimm_shr
1485 UQRSHRNB 01000101 .. 1 ..... 00 1110 ..... ..... @rd_rn_tszimm_shr
1486 UQRSHRNT 01000101 .. 1 ..... 00 1111 ..... ..... @rd_rn_tszimm_shr
1488 ## SVE2 integer add/subtract narrow high part
1490 ADDHNB 01000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm
1491 ADDHNT 01000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm
1492 RADDHNB 01000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm
1493 RADDHNT 01000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm
1494 SUBHNB 01000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm
1495 SUBHNT 01000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm
1496 RSUBHNB 01000101 .. 1 ..... 011 110 ..... ..... @rd_rn_rm
1497 RSUBHNT 01000101 .. 1 ..... 011 111 ..... ..... @rd_rn_rm
1499 ### SVE2 Character Match
1501 MATCH 01000101 .. 1 ..... 100 ... ..... 0 .... @pd_pg_rn_rm
1502 NMATCH 01000101 .. 1 ..... 100 ... ..... 1 .... @pd_pg_rn_rm
1504 ### SVE2 Histogram Computation
1506 HISTCNT 01000101 .. 1 ..... 110 ... ..... ..... @rd_pg_rn_rm
1507 HISTSEG 01000101 .. 1 ..... 101 000 ..... ..... @rd_rn_rm
1509 ## SVE2 floating-point pairwise operations
1511 FADDP 01100100 .. 010 00 0 100 ... ..... ..... @rdn_pg_rm
1512 FMAXNMP 01100100 .. 010 10 0 100 ... ..... ..... @rdn_pg_rm
1513 FMINNMP 01100100 .. 010 10 1 100 ... ..... ..... @rdn_pg_rm
1514 FMAXP 01100100 .. 010 11 0 100 ... ..... ..... @rdn_pg_rm
1515 FMINP 01100100 .. 010 11 1 100 ... ..... ..... @rdn_pg_rm
1517 #### SVE Integer Multiply-Add (unpredicated)
1519 ## SVE2 saturating multiply-add long
1521 SQDMLALB_zzzw 01000100 .. 0 ..... 0110 00 ..... ..... @rda_rn_rm
1522 SQDMLALT_zzzw 01000100 .. 0 ..... 0110 01 ..... ..... @rda_rn_rm
1523 SQDMLSLB_zzzw 01000100 .. 0 ..... 0110 10 ..... ..... @rda_rn_rm
1524 SQDMLSLT_zzzw 01000100 .. 0 ..... 0110 11 ..... ..... @rda_rn_rm
1526 ## SVE2 saturating multiply-add interleaved long
1528 SQDMLALBT 01000100 .. 0 ..... 00001 0 ..... ..... @rda_rn_rm
1529 SQDMLSLBT 01000100 .. 0 ..... 00001 1 ..... ..... @rda_rn_rm
1531 ## SVE2 saturating multiply-add high
1533 SQRDMLAH_zzzz 01000100 .. 0 ..... 01110 0 ..... ..... @rda_rn_rm
1534 SQRDMLSH_zzzz 01000100 .. 0 ..... 01110 1 ..... ..... @rda_rn_rm
1536 ## SVE2 integer multiply-add long
1538 SMLALB_zzzw 01000100 .. 0 ..... 010 000 ..... ..... @rda_rn_rm
1539 SMLALT_zzzw 01000100 .. 0 ..... 010 001 ..... ..... @rda_rn_rm
1540 UMLALB_zzzw 01000100 .. 0 ..... 010 010 ..... ..... @rda_rn_rm
1541 UMLALT_zzzw 01000100 .. 0 ..... 010 011 ..... ..... @rda_rn_rm
1542 SMLSLB_zzzw 01000100 .. 0 ..... 010 100 ..... ..... @rda_rn_rm
1543 SMLSLT_zzzw 01000100 .. 0 ..... 010 101 ..... ..... @rda_rn_rm
1544 UMLSLB_zzzw 01000100 .. 0 ..... 010 110 ..... ..... @rda_rn_rm
1545 UMLSLT_zzzw 01000100 .. 0 ..... 010 111 ..... ..... @rda_rn_rm
1547 ## SVE2 complex integer multiply-add
1549 CMLA_zzzz 01000100 esz:2 0 rm:5 0010 rot:2 rn:5 rd:5 ra=%reg_movprfx
1550 SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx
1552 ## SVE mixed sign dot product
1554 USDOT_zzzz 01000100 .. 0 ..... 011 110 ..... ..... @rda_rn_rm
1556 ### SVE2 floating point matrix multiply accumulate
1558 FMMLA 01100100 .. 1 ..... 111001 ..... ..... @rda_rn_rm
1560 ### SVE2 Memory Gather Load Group
1562 # SVE2 64-bit gather non-temporal load
1563 # (scalar plus unpacked 32-bit unscaled offsets)
1564 LDNT1_zprz 1100010 msz:2 00 rm:5 1 u:1 0 pg:3 rn:5 rd:5 \
1565 &rprr_gather_load xs=0 esz=3 scale=0 ff=0
1567 # SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets)
1568 LDNT1_zprz 1000010 msz:2 00 rm:5 10 u:1 pg:3 rn:5 rd:5 \
1569 &rprr_gather_load xs=0 esz=2 scale=0 ff=0
1571 ### SVE2 Memory Store Group
1573 # SVE2 64-bit scatter non-temporal store (vector plus scalar)
1574 STNT1_zprz 1110010 .. 00 ..... 001 ... ..... ..... \
1575 @rprr_scatter_store xs=2 esz=3 scale=0
1577 # SVE2 32-bit scatter non-temporal store (vector plus scalar)
1578 STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \
1579 @rprr_scatter_store xs=0 esz=2 scale=0
1581 ### SVE2 Crypto Extensions
1583 # SVE2 crypto unary operations
1584 # AESMC and AESIMC
1585 AESMC 01000101 00 10000011100 decrypt:1 00000 rd:5
1587 # SVE2 crypto destructive binary operations
1588 AESE 01000101 00 10001 0 11100 0 ..... ..... @rdn_rm_e0
1589 AESD 01000101 00 10001 0 11100 1 ..... ..... @rdn_rm_e0
1590 SM4E 01000101 00 10001 1 11100 0 ..... ..... @rdn_rm_e0
1592 # SVE2 crypto constructive binary operations
1593 SM4EKEY 01000101 00 1 ..... 11110 0 ..... ..... @rd_rn_rm_e0
1594 RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0
1596 ### SVE2 floating-point convert precision odd elements
1597 FCVTXNT_ds 01100100 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0
1598 FCVTX_ds 01100101 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0
1599 FCVTNT_sh 01100100 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0
1600 FCVTLT_hs 01100100 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0
1601 FCVTNT_ds 01100100 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0
1602 FCVTLT_sd 01100100 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0
1604 ### SVE2 floating-point convert to integer
1605 FLOGB 01100101 00 011 esz:2 0101 pg:3 rn:5 rd:5 &rpr_esz