2 * Cluster Power Controller emulation
4 * Copyright (c) 2016 Imagination Technologies
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "hw/sysbus.h"
24 #include "hw/misc/mips_cpc.h"
26 static inline uint64_t cpc_vp_run_mask(MIPSCPCState
*cpc
)
28 return (1ULL << cpc
->num_vp
) - 1;
31 static void cpc_run_vp(MIPSCPCState
*cpc
, uint64_t vp_run
)
33 CPUState
*cs
= first_cpu
;
36 uint64_t i
= 1ULL << cs
->cpu_index
;
37 if (i
& vp_run
& ~cpc
->vp_running
) {
38 cpu_interrupt(cs
, CPU_INTERRUPT_WAKE
);
44 static void cpc_stop_vp(MIPSCPCState
*cpc
, uint64_t vp_stop
)
46 CPUState
*cs
= first_cpu
;
49 uint64_t i
= 1ULL << cs
->cpu_index
;
50 if (i
& vp_stop
& cpc
->vp_running
) {
52 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
53 cpc
->vp_running
&= ~i
;
58 static void cpc_write(void *opaque
, hwaddr offset
, uint64_t data
,
61 MIPSCPCState
*s
= opaque
;
64 case CPC_CL_BASE_OFS
+ CPC_VP_RUN_OFS
:
65 case CPC_CO_BASE_OFS
+ CPC_VP_RUN_OFS
:
66 cpc_run_vp(s
, data
& cpc_vp_run_mask(s
));
68 case CPC_CL_BASE_OFS
+ CPC_VP_STOP_OFS
:
69 case CPC_CO_BASE_OFS
+ CPC_VP_STOP_OFS
:
70 cpc_stop_vp(s
, data
& cpc_vp_run_mask(s
));
73 qemu_log_mask(LOG_UNIMP
,
74 "%s: Bad offset 0x%x\n", __func__
, (int)offset
);
81 static uint64_t cpc_read(void *opaque
, hwaddr offset
, unsigned size
)
83 MIPSCPCState
*s
= opaque
;
86 case CPC_CL_BASE_OFS
+ CPC_VP_RUNNING_OFS
:
87 case CPC_CO_BASE_OFS
+ CPC_VP_RUNNING_OFS
:
90 qemu_log_mask(LOG_UNIMP
,
91 "%s: Bad offset 0x%x\n", __func__
, (int)offset
);
96 static const MemoryRegionOps cpc_ops
= {
99 .endianness
= DEVICE_NATIVE_ENDIAN
,
101 .max_access_size
= 8,
105 static void mips_cpc_init(Object
*obj
)
107 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
108 MIPSCPCState
*s
= MIPS_CPC(obj
);
110 memory_region_init_io(&s
->mr
, OBJECT(s
), &cpc_ops
, s
, "mips-cpc",
112 sysbus_init_mmio(sbd
, &s
->mr
);
115 static void mips_cpc_realize(DeviceState
*dev
, Error
**errp
)
117 MIPSCPCState
*s
= MIPS_CPC(dev
);
119 if (s
->vp_start_running
> cpc_vp_run_mask(s
)) {
121 "incorrect vp_start_running 0x%" PRIx64
" for num_vp = %d",
122 s
->vp_running
, s
->num_vp
);
127 static void mips_cpc_reset(DeviceState
*dev
)
129 MIPSCPCState
*s
= MIPS_CPC(dev
);
131 /* Reflect the fact that all VPs are halted on reset */
134 /* Put selected VPs into run state */
135 cpc_run_vp(s
, s
->vp_start_running
);
138 static const VMStateDescription vmstate_mips_cpc
= {
141 .minimum_version_id
= 0,
142 .fields
= (VMStateField
[]) {
143 VMSTATE_UINT64(vp_running
, MIPSCPCState
),
144 VMSTATE_END_OF_LIST()
148 static Property mips_cpc_properties
[] = {
149 DEFINE_PROP_UINT32("num-vp", MIPSCPCState
, num_vp
, 0x1),
150 DEFINE_PROP_UINT64("vp-start-running", MIPSCPCState
, vp_start_running
, 0x1),
151 DEFINE_PROP_END_OF_LIST(),
154 static void mips_cpc_class_init(ObjectClass
*klass
, void *data
)
156 DeviceClass
*dc
= DEVICE_CLASS(klass
);
158 dc
->realize
= mips_cpc_realize
;
159 dc
->reset
= mips_cpc_reset
;
160 dc
->vmsd
= &vmstate_mips_cpc
;
161 dc
->props
= mips_cpc_properties
;
164 static const TypeInfo mips_cpc_info
= {
165 .name
= TYPE_MIPS_CPC
,
166 .parent
= TYPE_SYS_BUS_DEVICE
,
167 .instance_size
= sizeof(MIPSCPCState
),
168 .instance_init
= mips_cpc_init
,
169 .class_init
= mips_cpc_class_init
,
172 static void mips_cpc_register_types(void)
174 type_register_static(&mips_cpc_info
);
177 type_init(mips_cpc_register_types
)