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target/ppc: Update do_frsp for new flags
[qemu.git] / target / ppc / fpu_helper.c
blob65acf605b78f3ce47e7c61c661d637d9779e1c5e
1 /*
2 * PowerPC floating point and SPE emulation helpers for QEMU.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "exec/helper-proto.h"
22 #include "exec/exec-all.h"
23 #include "internal.h"
24 #include "fpu/softfloat.h"
25
26 static inline float128 float128_snan_to_qnan(float128 x)
27 {
28 float128 r;
29
30 r.high = x.high | 0x0000800000000000;
31 r.low = x.low;
32 return r;
33 }
34
35 #define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
36 #define float32_snan_to_qnan(x) ((x) | 0x00400000)
37 #define float16_snan_to_qnan(x) ((x) | 0x0200)
38
39 static inline bool fp_exceptions_enabled(CPUPPCState *env)
40 {
41 #ifdef CONFIG_USER_ONLY
42 return true;
43 #else
44 return (env->msr & ((1U << MSR_FE0) | (1U << MSR_FE1))) != 0;
45 #endif
46 }
47
48 /*****************************************************************************/
49 /* Floating point operations helpers */
50
51 /*
52 * This is the non-arithmatic conversion that happens e.g. on loads.
53 * In the Power ISA pseudocode, this is called DOUBLE.
54 */
55 uint64_t helper_todouble(uint32_t arg)
56 {
57 uint32_t abs_arg = arg & 0x7fffffff;
58 uint64_t ret;
59
60 if (likely(abs_arg >= 0x00800000)) {
61 if (unlikely(extract32(arg, 23, 8) == 0xff)) {
62 /* Inf or NAN. */
63 ret = (uint64_t)extract32(arg, 31, 1) << 63;
64 ret |= (uint64_t)0x7ff << 52;
65 ret |= (uint64_t)extract32(arg, 0, 23) << 29;
66 } else {
67 /* Normalized operand. */
68 ret = (uint64_t)extract32(arg, 30, 2) << 62;
69 ret |= ((extract32(arg, 30, 1) ^ 1) * (uint64_t)7) << 59;
70 ret |= (uint64_t)extract32(arg, 0, 30) << 29;
71 }
72 } else {
73 /* Zero or Denormalized operand. */
74 ret = (uint64_t)extract32(arg, 31, 1) << 63;
75 if (unlikely(abs_arg != 0)) {
76 /*
77 * Denormalized operand.
78 * Shift fraction so that the msb is in the implicit bit position.
79 * Thus, shift is in the range [1:23].
80 */
81 int shift = clz32(abs_arg) - 8;
82 /*
83 * The first 3 terms compute the float64 exponent. We then bias
84 * this result by -1 so that we can swallow the implicit bit below.
85 */
86 int exp = -126 - shift + 1023 - 1;
87
88 ret |= (uint64_t)exp << 52;
89 ret += (uint64_t)abs_arg << (52 - 23 + shift);
90 }
91 }
92 return ret;
93 }
94
95 /*
96 * This is the non-arithmatic conversion that happens e.g. on stores.
97 * In the Power ISA pseudocode, this is called SINGLE.
98 */
99 uint32_t helper_tosingle(uint64_t arg)
100 {
101 int exp = extract64(arg, 52, 11);
102 uint32_t ret;
103
104 if (likely(exp > 896)) {
105 /* No denormalization required (includes Inf, NaN). */
106 ret = extract64(arg, 62, 2) << 30;
107 ret |= extract64(arg, 29, 30);
108 } else {
109 /*
110 * Zero or Denormal result. If the exponent is in bounds for
111 * a single-precision denormal result, extract the proper
112 * bits. If the input is not zero, and the exponent is out of
113 * bounds, then the result is undefined; this underflows to
114 * zero.
115 */
116 ret = extract64(arg, 63, 1) << 31;
117 if (unlikely(exp >= 874)) {
118 /* Denormal result. */
119 ret |= ((1ULL << 52) | extract64(arg, 0, 52)) >> (896 + 30 - exp);
120 }
121 }
122 return ret;
123 }
124
125 static inline int ppc_float32_get_unbiased_exp(float32 f)
126 {
127 return ((f >> 23) & 0xFF) - 127;
128 }
129
130 static inline int ppc_float64_get_unbiased_exp(float64 f)
131 {
132 return ((f >> 52) & 0x7FF) - 1023;
133 }
134
135 /* Classify a floating-point number. */
136 enum {
137 is_normal = 1,
138 is_zero = 2,
139 is_denormal = 4,
140 is_inf = 8,
141 is_qnan = 16,
142 is_snan = 32,
143 is_neg = 64,
144 };
145
146 #define COMPUTE_CLASS(tp) \
147 static int tp##_classify(tp arg) \
148 { \
149 int ret = tp##_is_neg(arg) * is_neg; \
150 if (unlikely(tp##_is_any_nan(arg))) { \
151 float_status dummy = { }; /* snan_bit_is_one = 0 */ \
152 ret |= (tp##_is_signaling_nan(arg, &dummy) \
153 ? is_snan : is_qnan); \
154 } else if (unlikely(tp##_is_infinity(arg))) { \
155 ret |= is_inf; \
156 } else if (tp##_is_zero(arg)) { \
157 ret |= is_zero; \
158 } else if (tp##_is_zero_or_denormal(arg)) { \
159 ret |= is_denormal; \
160 } else { \
161 ret |= is_normal; \
162 } \
163 return ret; \
164 }
165
166 COMPUTE_CLASS(float16)
167 COMPUTE_CLASS(float32)
168 COMPUTE_CLASS(float64)
169 COMPUTE_CLASS(float128)
170
171 static void set_fprf_from_class(CPUPPCState *env, int class)
172 {
173 static const uint8_t fprf[6][2] = {
174 { 0x04, 0x08 }, /* normalized */
175 { 0x02, 0x12 }, /* zero */
176 { 0x14, 0x18 }, /* denormalized */
177 { 0x05, 0x09 }, /* infinity */
178 { 0x11, 0x11 }, /* qnan */
179 { 0x00, 0x00 }, /* snan -- flags are undefined */
180 };
181 bool isneg = class & is_neg;
182
183 env->fpscr &= ~FP_FPRF;
184 env->fpscr |= fprf[ctz32(class)][isneg] << FPSCR_FPRF;
185 }
186
187 #define COMPUTE_FPRF(tp) \
188 void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
189 { \
190 set_fprf_from_class(env, tp##_classify(arg)); \
191 }
192
193 COMPUTE_FPRF(float16)
194 COMPUTE_FPRF(float32)
195 COMPUTE_FPRF(float64)
196 COMPUTE_FPRF(float128)
197
198 /* Floating-point invalid operations exception */
199 static void finish_invalid_op_excp(CPUPPCState *env, int op, uintptr_t retaddr)
200 {
201 /* Update the floating-point invalid operation summary */
202 env->fpscr |= FP_VX;
203 /* Update the floating-point exception summary */
204 env->fpscr |= FP_FX;
205 if (fpscr_ve != 0) {
206 /* Update the floating-point enabled exception summary */
207 env->fpscr |= FP_FEX;
208 if (fp_exceptions_enabled(env)) {
209 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
210 POWERPC_EXCP_FP | op, retaddr);
211 }
212 }
213 }
214
215 static void finish_invalid_op_arith(CPUPPCState *env, int op,
216 bool set_fpcc, uintptr_t retaddr)
217 {
218 env->fpscr &= ~(FP_FR | FP_FI);
219 if (fpscr_ve == 0) {
220 if (set_fpcc) {
221 env->fpscr &= ~FP_FPCC;
222 env->fpscr |= (FP_C | FP_FU);
223 }
224 }
225 finish_invalid_op_excp(env, op, retaddr);
226 }
227
228 /* Signalling NaN */
229 static void float_invalid_op_vxsnan(CPUPPCState *env, uintptr_t retaddr)
230 {
231 env->fpscr |= FP_VXSNAN;
232 finish_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, retaddr);
233 }
234
235 /* Magnitude subtraction of infinities */
236 static void float_invalid_op_vxisi(CPUPPCState *env, bool set_fpcc,
237 uintptr_t retaddr)
238 {
239 env->fpscr |= FP_VXISI;
240 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXISI, set_fpcc, retaddr);
241 }
242
243 /* Division of infinity by infinity */
244 static void float_invalid_op_vxidi(CPUPPCState *env, bool set_fpcc,
245 uintptr_t retaddr)
246 {
247 env->fpscr |= FP_VXIDI;
248 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXIDI, set_fpcc, retaddr);
249 }
250
251 /* Division of zero by zero */
252 static void float_invalid_op_vxzdz(CPUPPCState *env, bool set_fpcc,
253 uintptr_t retaddr)
254 {
255 env->fpscr |= FP_VXZDZ;
256 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXZDZ, set_fpcc, retaddr);
257 }
258
259 /* Multiplication of zero by infinity */
260 static void float_invalid_op_vximz(CPUPPCState *env, bool set_fpcc,
261 uintptr_t retaddr)
262 {
263 env->fpscr |= FP_VXIMZ;
264 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXIMZ, set_fpcc, retaddr);
265 }
266
267 /* Square root of a negative number */
268 static void float_invalid_op_vxsqrt(CPUPPCState *env, bool set_fpcc,
269 uintptr_t retaddr)
270 {
271 env->fpscr |= FP_VXSQRT;
272 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXSQRT, set_fpcc, retaddr);
273 }
274
275 /* Ordered comparison of NaN */
276 static void float_invalid_op_vxvc(CPUPPCState *env, bool set_fpcc,
277 uintptr_t retaddr)
278 {
279 env->fpscr |= FP_VXVC;
280 if (set_fpcc) {
281 env->fpscr &= ~FP_FPCC;
282 env->fpscr |= (FP_C | FP_FU);
283 }
284 /* Update the floating-point invalid operation summary */
285 env->fpscr |= FP_VX;
286 /* Update the floating-point exception summary */
287 env->fpscr |= FP_FX;
288 /* We must update the target FPR before raising the exception */
289 if (fpscr_ve != 0) {
290 CPUState *cs = env_cpu(env);
291
292 cs->exception_index = POWERPC_EXCP_PROGRAM;
293 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
294 /* Update the floating-point enabled exception summary */
295 env->fpscr |= FP_FEX;
296 /* Exception is deferred */
297 }
298 }
299
300 /* Invalid conversion */
301 static void float_invalid_op_vxcvi(CPUPPCState *env, bool set_fpcc,
302 uintptr_t retaddr)
303 {
304 env->fpscr |= FP_VXCVI;
305 env->fpscr &= ~(FP_FR | FP_FI);
306 if (fpscr_ve == 0) {
307 if (set_fpcc) {
308 env->fpscr &= ~FP_FPCC;
309 env->fpscr |= (FP_C | FP_FU);
310 }
311 }
312 finish_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, retaddr);
313 }
314
315 static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr)
316 {
317 env->fpscr |= FP_ZX;
318 env->fpscr &= ~(FP_FR | FP_FI);
319 /* Update the floating-point exception summary */
320 env->fpscr |= FP_FX;
321 if (fpscr_ze != 0) {
322 /* Update the floating-point enabled exception summary */
323 env->fpscr |= FP_FEX;
324 if (fp_exceptions_enabled(env)) {
325 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
326 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX,
327 raddr);
328 }
329 }
330 }
331
332 static inline void float_overflow_excp(CPUPPCState *env)
333 {
334 CPUState *cs = env_cpu(env);
335
336 env->fpscr |= FP_OX;
337 /* Update the floating-point exception summary */
338 env->fpscr |= FP_FX;
339 if (fpscr_oe != 0) {
340 /* XXX: should adjust the result */
341 /* Update the floating-point enabled exception summary */
342 env->fpscr |= FP_FEX;
343 /* We must update the target FPR before raising the exception */
344 cs->exception_index = POWERPC_EXCP_PROGRAM;
345 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
346 } else {
347 env->fpscr |= FP_XX;
348 env->fpscr |= FP_FI;
349 }
350 }
351
352 static inline void float_underflow_excp(CPUPPCState *env)
353 {
354 CPUState *cs = env_cpu(env);
355
356 env->fpscr |= FP_UX;
357 /* Update the floating-point exception summary */
358 env->fpscr |= FP_FX;
359 if (fpscr_ue != 0) {
360 /* XXX: should adjust the result */
361 /* Update the floating-point enabled exception summary */
362 env->fpscr |= FP_FEX;
363 /* We must update the target FPR before raising the exception */
364 cs->exception_index = POWERPC_EXCP_PROGRAM;
365 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
366 }
367 }
368
369 static inline void float_inexact_excp(CPUPPCState *env)
370 {
371 CPUState *cs = env_cpu(env);
372
373 env->fpscr |= FP_FI;
374 env->fpscr |= FP_XX;
375 /* Update the floating-point exception summary */
376 env->fpscr |= FP_FX;
377 if (fpscr_xe != 0) {
378 /* Update the floating-point enabled exception summary */
379 env->fpscr |= FP_FEX;
380 /* We must update the target FPR before raising the exception */
381 cs->exception_index = POWERPC_EXCP_PROGRAM;
382 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
383 }
384 }
385
386 void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)
387 {
388 uint32_t mask = 1u << bit;
389 if (env->fpscr & mask) {
390 ppc_store_fpscr(env, env->fpscr & ~(target_ulong)mask);
391 }
392 }
393
394 void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
395 {
396 uint32_t mask = 1u << bit;
397 if (!(env->fpscr & mask)) {
398 ppc_store_fpscr(env, env->fpscr | mask);
399 }
400 }
401
402 void helper_store_fpscr(CPUPPCState *env, uint64_t val, uint32_t nibbles)
403 {
404 target_ulong mask = 0;
405 int i;
406
407 /* TODO: push this extension back to translation time */
408 for (i = 0; i < sizeof(target_ulong) * 2; i++) {
409 if (nibbles & (1 << i)) {
410 mask |= (target_ulong) 0xf << (4 * i);
411 }
412 }
413 val = (val & mask) | (env->fpscr & ~mask);
414 ppc_store_fpscr(env, val);
415 }
416
417 void helper_fpscr_check_status(CPUPPCState *env)
418 {
419 CPUState *cs = env_cpu(env);
420 target_ulong fpscr = env->fpscr;
421 int error = 0;
422
423 if ((fpscr & FP_OX) && (fpscr & FP_OE)) {
424 error = POWERPC_EXCP_FP_OX;
425 } else if ((fpscr & FP_UX) && (fpscr & FP_UE)) {
426 error = POWERPC_EXCP_FP_UX;
427 } else if ((fpscr & FP_XX) && (fpscr & FP_XE)) {
428 error = POWERPC_EXCP_FP_XX;
429 } else if ((fpscr & FP_ZX) && (fpscr & FP_ZE)) {
430 error = POWERPC_EXCP_FP_ZX;
431 } else if (fpscr & FP_VE) {
432 if (fpscr & FP_VXSOFT) {
433 error = POWERPC_EXCP_FP_VXSOFT;
434 } else if (fpscr & FP_VXSNAN) {
435 error = POWERPC_EXCP_FP_VXSNAN;
436 } else if (fpscr & FP_VXISI) {
437 error = POWERPC_EXCP_FP_VXISI;
438 } else if (fpscr & FP_VXIDI) {
439 error = POWERPC_EXCP_FP_VXIDI;
440 } else if (fpscr & FP_VXZDZ) {
441 error = POWERPC_EXCP_FP_VXZDZ;
442 } else if (fpscr & FP_VXIMZ) {
443 error = POWERPC_EXCP_FP_VXIMZ;
444 } else if (fpscr & FP_VXVC) {
445 error = POWERPC_EXCP_FP_VXVC;
446 } else if (fpscr & FP_VXSQRT) {
447 error = POWERPC_EXCP_FP_VXSQRT;
448 } else if (fpscr & FP_VXCVI) {
449 error = POWERPC_EXCP_FP_VXCVI;
450 } else {
451 return;
452 }
453 } else {
454 return;
455 }
456 cs->exception_index = POWERPC_EXCP_PROGRAM;
457 env->error_code = error | POWERPC_EXCP_FP;
458 /* Deferred floating-point exception after target FPSCR update */
459 if (fp_exceptions_enabled(env)) {
460 raise_exception_err_ra(env, cs->exception_index,
461 env->error_code, GETPC());
462 }
463 }
464
465 static void do_float_check_status(CPUPPCState *env, uintptr_t raddr)
466 {
467 CPUState *cs = env_cpu(env);
468 int status = get_float_exception_flags(&env->fp_status);
469
470 if (status & float_flag_overflow) {
471 float_overflow_excp(env);
472 } else if (status & float_flag_underflow) {
473 float_underflow_excp(env);
474 }
475 if (status & float_flag_inexact) {
476 float_inexact_excp(env);
477 } else {
478 env->fpscr &= ~FP_FI; /* clear the FPSCR[FI] bit */
479 }
480
481 if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
482 (env->error_code & POWERPC_EXCP_FP)) {
483 /* Deferred floating-point exception after target FPR update */
484 if (fp_exceptions_enabled(env)) {
485 raise_exception_err_ra(env, cs->exception_index,
486 env->error_code, raddr);
487 }
488 }
489 }
490
491 void helper_float_check_status(CPUPPCState *env)
492 {
493 do_float_check_status(env, GETPC());
494 }
495
496 void helper_reset_fpstatus(CPUPPCState *env)
497 {
498 set_float_exception_flags(0, &env->fp_status);
499 }
500
501 static void float_invalid_op_addsub(CPUPPCState *env, int flags,
502 bool set_fpcc, uintptr_t retaddr)
503 {
504 if (flags & float_flag_invalid_isi) {
505 float_invalid_op_vxisi(env, set_fpcc, retaddr);
506 } else if (flags & float_flag_invalid_snan) {
507 float_invalid_op_vxsnan(env, retaddr);
508 }
509 }
510
511 /* fadd - fadd. */
512 float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2)
513 {
514 float64 ret = float64_add(arg1, arg2, &env->fp_status);
515 int flags = get_float_exception_flags(&env->fp_status);
516
517 if (unlikely(flags & float_flag_invalid)) {
518 float_invalid_op_addsub(env, flags, 1, GETPC());
519 }
520
521 return ret;
522 }
523
524 /* fsub - fsub. */
525 float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2)
526 {
527 float64 ret = float64_sub(arg1, arg2, &env->fp_status);
528 int flags = get_float_exception_flags(&env->fp_status);
529
530 if (unlikely(flags & float_flag_invalid)) {
531 float_invalid_op_addsub(env, flags, 1, GETPC());
532 }
533
534 return ret;
535 }
536
537 static void float_invalid_op_mul(CPUPPCState *env, int flags,
538 bool set_fprc, uintptr_t retaddr)
539 {
540 if (flags & float_flag_invalid_imz) {
541 float_invalid_op_vximz(env, set_fprc, retaddr);
542 } else if (flags & float_flag_invalid_snan) {
543 float_invalid_op_vxsnan(env, retaddr);
544 }
545 }
546
547 /* fmul - fmul. */
548 float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2)
549 {
550 float64 ret = float64_mul(arg1, arg2, &env->fp_status);
551 int flags = get_float_exception_flags(&env->fp_status);
552
553 if (unlikely(flags & float_flag_invalid)) {
554 float_invalid_op_mul(env, flags, 1, GETPC());
555 }
556
557 return ret;
558 }
559
560 static void float_invalid_op_div(CPUPPCState *env, int flags,
561 bool set_fprc, uintptr_t retaddr)
562 {
563 if (flags & float_flag_invalid_idi) {
564 float_invalid_op_vxidi(env, set_fprc, retaddr);
565 } else if (flags & float_flag_invalid_zdz) {
566 float_invalid_op_vxzdz(env, set_fprc, retaddr);
567 } else if (flags & float_flag_invalid_snan) {
568 float_invalid_op_vxsnan(env, retaddr);
569 }
570 }
571
572 /* fdiv - fdiv. */
573 float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2)
574 {
575 float64 ret = float64_div(arg1, arg2, &env->fp_status);
576 int flags = get_float_exception_flags(&env->fp_status);
577
578 if (unlikely(flags & float_flag_invalid)) {
579 float_invalid_op_div(env, flags, 1, GETPC());
580 }
581 if (unlikely(flags & float_flag_divbyzero)) {
582 float_zero_divide_excp(env, GETPC());
583 }
584
585 return ret;
586 }
587
588 static uint64_t float_invalid_cvt(CPUPPCState *env, int flags,
589 uint64_t ret, uint64_t ret_nan,
590 bool set_fprc, uintptr_t retaddr)
591 {
592 /*
593 * VXCVI is different from most in that it sets two exception bits,
594 * VXCVI and VXSNAN for an SNaN input.
595 */
596 if (flags & float_flag_invalid_snan) {
597 env->fpscr |= FP_VXSNAN;
598 }
599 float_invalid_op_vxcvi(env, set_fprc, retaddr);
600
601 return flags & float_flag_invalid_cvti ? ret : ret_nan;
602 }
603
604 #define FPU_FCTI(op, cvt, nanval) \
605 uint64_t helper_##op(CPUPPCState *env, float64 arg) \
606 { \
607 uint64_t ret = float64_to_##cvt(arg, &env->fp_status); \
608 int flags = get_float_exception_flags(&env->fp_status); \
609 if (unlikely(flags & float_flag_invalid)) { \
610 ret = float_invalid_cvt(env, flags, ret, nanval, 1, GETPC()); \
611 } \
612 return ret; \
613 }
614
615 FPU_FCTI(fctiw, int32, 0x80000000U)
616 FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000U)
617 FPU_FCTI(fctiwu, uint32, 0x00000000U)
618 FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000U)
619 FPU_FCTI(fctid, int64, 0x8000000000000000ULL)
620 FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000ULL)
621 FPU_FCTI(fctidu, uint64, 0x0000000000000000ULL)
622 FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000ULL)
623
624 #define FPU_FCFI(op, cvtr, is_single) \
625 uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
626 { \
627 CPU_DoubleU farg; \
628 \
629 if (is_single) { \
630 float32 tmp = cvtr(arg, &env->fp_status); \
631 farg.d = float32_to_float64(tmp, &env->fp_status); \
632 } else { \
633 farg.d = cvtr(arg, &env->fp_status); \
634 } \
635 do_float_check_status(env, GETPC()); \
636 return farg.ll; \
637 }
638
639 FPU_FCFI(fcfid, int64_to_float64, 0)
640 FPU_FCFI(fcfids, int64_to_float32, 1)
641 FPU_FCFI(fcfidu, uint64_to_float64, 0)
642 FPU_FCFI(fcfidus, uint64_to_float32, 1)
643
644 static uint64_t do_fri(CPUPPCState *env, uint64_t arg,
645 FloatRoundMode rounding_mode)
646 {
647 FloatRoundMode old_rounding_mode = get_float_rounding_mode(&env->fp_status);
648 int flags;
649
650 set_float_rounding_mode(rounding_mode, &env->fp_status);
651 arg = float64_round_to_int(arg, &env->fp_status);
652 set_float_rounding_mode(old_rounding_mode, &env->fp_status);
653
654 flags = get_float_exception_flags(&env->fp_status);
655 if (flags & float_flag_invalid_snan) {
656 float_invalid_op_vxsnan(env, GETPC());
657 }
658
659 /* fri* does not set FPSCR[XX] */
660 set_float_exception_flags(flags & ~float_flag_inexact, &env->fp_status);
661 do_float_check_status(env, GETPC());
662
663 return arg;
664 }
665
666 uint64_t helper_frin(CPUPPCState *env, uint64_t arg)
667 {
668 return do_fri(env, arg, float_round_ties_away);
669 }
670
671 uint64_t helper_friz(CPUPPCState *env, uint64_t arg)
672 {
673 return do_fri(env, arg, float_round_to_zero);
674 }
675
676 uint64_t helper_frip(CPUPPCState *env, uint64_t arg)
677 {
678 return do_fri(env, arg, float_round_up);
679 }
680
681 uint64_t helper_frim(CPUPPCState *env, uint64_t arg)
682 {
683 return do_fri(env, arg, float_round_down);
684 }
685
686 static void float_invalid_op_madd(CPUPPCState *env, int flags,
687 bool set_fpcc, uintptr_t retaddr)
688 {
689 if (flags & float_flag_invalid_imz) {
690 float_invalid_op_vximz(env, set_fpcc, retaddr);
691 } else {
692 float_invalid_op_addsub(env, flags, set_fpcc, retaddr);
693 }
694 }
695
696 static float64 do_fmadd(CPUPPCState *env, float64 a, float64 b,
697 float64 c, int madd_flags, uintptr_t retaddr)
698 {
699 float64 ret = float64_muladd(a, b, c, madd_flags, &env->fp_status);
700 int flags = get_float_exception_flags(&env->fp_status);
701
702 if (unlikely(flags & float_flag_invalid)) {
703 float_invalid_op_madd(env, flags, 1, retaddr);
704 }
705 return ret;
706 }
707
708 #define FPU_FMADD(op, madd_flags) \
709 uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \
710 uint64_t arg2, uint64_t arg3) \
711 { return do_fmadd(env, arg1, arg2, arg3, madd_flags, GETPC()); }
712
713 #define MADD_FLGS 0
714 #define MSUB_FLGS float_muladd_negate_c
715 #define NMADD_FLGS float_muladd_negate_result
716 #define NMSUB_FLGS (float_muladd_negate_c | float_muladd_negate_result)
717
718 FPU_FMADD(fmadd, MADD_FLGS)
719 FPU_FMADD(fnmadd, NMADD_FLGS)
720 FPU_FMADD(fmsub, MSUB_FLGS)
721 FPU_FMADD(fnmsub, NMSUB_FLGS)
722
723 /* frsp - frsp. */
724 static uint64_t do_frsp(CPUPPCState *env, uint64_t arg, uintptr_t retaddr)
725 {
726 float32 f32 = float64_to_float32(arg, &env->fp_status);
727 int flags = get_float_exception_flags(&env->fp_status);
728
729 if (unlikely(flags & float_flag_invalid_snan)) {
730 float_invalid_op_vxsnan(env, retaddr);
731 }
732 return float32_to_float64(f32, &env->fp_status);
733 }
734
735 uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
736 {
737 return do_frsp(env, arg, GETPC());
738 }
739
740 /* fsqrt - fsqrt. */
741 float64 helper_fsqrt(CPUPPCState *env, float64 arg)
742 {
743 float64 ret = float64_sqrt(arg, &env->fp_status);
744 int status = get_float_exception_flags(&env->fp_status);
745
746 if (unlikely(status & float_flag_invalid)) {
747 if (unlikely(float64_is_any_nan(arg))) {
748 if (unlikely(float64_is_signaling_nan(arg, &env->fp_status))) {
749 /* sNaN square root */
750 float_invalid_op_vxsnan(env, GETPC());
751 }
752 } else {
753 /* Square root of a negative nonzero number */
754 float_invalid_op_vxsqrt(env, 1, GETPC());
755 }
756 }
757
758 return ret;
759 }
760
761 /* fre - fre. */
762 float64 helper_fre(CPUPPCState *env, float64 arg)
763 {
764 /* "Estimate" the reciprocal with actual division. */
765 float64 ret = float64_div(float64_one, arg, &env->fp_status);
766 int status = get_float_exception_flags(&env->fp_status);
767
768 if (unlikely(status)) {
769 if (status & float_flag_invalid) {
770 if (float64_is_signaling_nan(arg, &env->fp_status)) {
771 /* sNaN reciprocal */
772 float_invalid_op_vxsnan(env, GETPC());
773 }
774 }
775 if (status & float_flag_divbyzero) {
776 float_zero_divide_excp(env, GETPC());
777 /* For FPSCR.ZE == 0, the result is 1/2. */
778 ret = float64_set_sign(float64_half, float64_is_neg(arg));
779 }
780 }
781
782 return ret;
783 }
784
785 /* fres - fres. */
786 uint64_t helper_fres(CPUPPCState *env, uint64_t arg)
787 {
788 CPU_DoubleU farg;
789 float32 f32;
790
791 farg.ll = arg;
792
793 if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
794 /* sNaN reciprocal */
795 float_invalid_op_vxsnan(env, GETPC());
796 }
797 farg.d = float64_div(float64_one, farg.d, &env->fp_status);
798 f32 = float64_to_float32(farg.d, &env->fp_status);
799 farg.d = float32_to_float64(f32, &env->fp_status);
800
801 return farg.ll;
802 }
803
804 /* frsqrte - frsqrte. */
805 float64 helper_frsqrte(CPUPPCState *env, float64 arg)
806 {
807 /* "Estimate" the reciprocal with actual division. */
808 float64 rets = float64_sqrt(arg, &env->fp_status);
809 float64 retd = float64_div(float64_one, rets, &env->fp_status);
810 int status = get_float_exception_flags(&env->fp_status);
811
812 if (unlikely(status)) {
813 if (status & float_flag_invalid) {
814 if (float64_is_signaling_nan(arg, &env->fp_status)) {
815 /* sNaN reciprocal */
816 float_invalid_op_vxsnan(env, GETPC());
817 } else {
818 /* Square root of a negative nonzero number */
819 float_invalid_op_vxsqrt(env, 1, GETPC());
820 }
821 }
822 if (status & float_flag_divbyzero) {
823 /* Reciprocal of (square root of) zero. */
824 float_zero_divide_excp(env, GETPC());
825 }
826 }
827
828 return retd;
829 }
830
831 /* fsel - fsel. */
832 uint64_t helper_fsel(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
833 uint64_t arg3)
834 {
835 CPU_DoubleU farg1;
836
837 farg1.ll = arg1;
838
839 if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) &&
840 !float64_is_any_nan(farg1.d)) {
841 return arg2;
842 } else {
843 return arg3;
844 }
845 }
846
847 uint32_t helper_ftdiv(uint64_t fra, uint64_t frb)
848 {
849 int fe_flag = 0;
850 int fg_flag = 0;
851
852 if (unlikely(float64_is_infinity(fra) ||
853 float64_is_infinity(frb) ||
854 float64_is_zero(frb))) {
855 fe_flag = 1;
856 fg_flag = 1;
857 } else {
858 int e_a = ppc_float64_get_unbiased_exp(fra);
859 int e_b = ppc_float64_get_unbiased_exp(frb);
860
861 if (unlikely(float64_is_any_nan(fra) ||
862 float64_is_any_nan(frb))) {
863 fe_flag = 1;
864 } else if ((e_b <= -1022) || (e_b >= 1021)) {
865 fe_flag = 1;
866 } else if (!float64_is_zero(fra) &&
867 (((e_a - e_b) >= 1023) ||
868 ((e_a - e_b) <= -1021) ||
869 (e_a <= -970))) {
870 fe_flag = 1;
871 }
872
873 if (unlikely(float64_is_zero_or_denormal(frb))) {
874 /* XB is not zero because of the above check and */
875 /* so must be denormalized. */
876 fg_flag = 1;
877 }
878 }
879
880 return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
881 }
882
883 uint32_t helper_ftsqrt(uint64_t frb)
884 {
885 int fe_flag = 0;
886 int fg_flag = 0;
887
888 if (unlikely(float64_is_infinity(frb) || float64_is_zero(frb))) {
889 fe_flag = 1;
890 fg_flag = 1;
891 } else {
892 int e_b = ppc_float64_get_unbiased_exp(frb);
893
894 if (unlikely(float64_is_any_nan(frb))) {
895 fe_flag = 1;
896 } else if (unlikely(float64_is_zero(frb))) {
897 fe_flag = 1;
898 } else if (unlikely(float64_is_neg(frb))) {
899 fe_flag = 1;
900 } else if (!float64_is_zero(frb) && (e_b <= (-1022 + 52))) {
901 fe_flag = 1;
902 }
903
904 if (unlikely(float64_is_zero_or_denormal(frb))) {
905 /* XB is not zero because of the above check and */
906 /* therefore must be denormalized. */
907 fg_flag = 1;
908 }
909 }
910
911 return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
912 }
913
914 void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
915 uint32_t crfD)
916 {
917 CPU_DoubleU farg1, farg2;
918 uint32_t ret = 0;
919
920 farg1.ll = arg1;
921 farg2.ll = arg2;
922
923 if (unlikely(float64_is_any_nan(farg1.d) ||
924 float64_is_any_nan(farg2.d))) {
925 ret = 0x01UL;
926 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
927 ret = 0x08UL;
928 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
929 ret = 0x04UL;
930 } else {
931 ret = 0x02UL;
932 }
933
934 env->fpscr &= ~FP_FPCC;
935 env->fpscr |= ret << FPSCR_FPCC;
936 env->crf[crfD] = ret;
937 if (unlikely(ret == 0x01UL
938 && (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
939 float64_is_signaling_nan(farg2.d, &env->fp_status)))) {
940 /* sNaN comparison */
941 float_invalid_op_vxsnan(env, GETPC());
942 }
943 }
944
945 void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
946 uint32_t crfD)
947 {
948 CPU_DoubleU farg1, farg2;
949 uint32_t ret = 0;
950
951 farg1.ll = arg1;
952 farg2.ll = arg2;
953
954 if (unlikely(float64_is_any_nan(farg1.d) ||
955 float64_is_any_nan(farg2.d))) {
956 ret = 0x01UL;
957 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
958 ret = 0x08UL;
959 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
960 ret = 0x04UL;
961 } else {
962 ret = 0x02UL;
963 }
964
965 env->fpscr &= ~FP_FPCC;
966 env->fpscr |= ret << FPSCR_FPCC;
967 env->crf[crfD] = (uint32_t) ret;
968 if (unlikely(ret == 0x01UL)) {
969 float_invalid_op_vxvc(env, 1, GETPC());
970 if (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
971 float64_is_signaling_nan(farg2.d, &env->fp_status)) {
972 /* sNaN comparison */
973 float_invalid_op_vxsnan(env, GETPC());
974 }
975 }
976 }
977
978 /* Single-precision floating-point conversions */
979 static inline uint32_t efscfsi(CPUPPCState *env, uint32_t val)
980 {
981 CPU_FloatU u;
982
983 u.f = int32_to_float32(val, &env->vec_status);
984
985 return u.l;
986 }
987
988 static inline uint32_t efscfui(CPUPPCState *env, uint32_t val)
989 {
990 CPU_FloatU u;
991
992 u.f = uint32_to_float32(val, &env->vec_status);
993
994 return u.l;
995 }
996
997 static inline int32_t efsctsi(CPUPPCState *env, uint32_t val)
998 {
999 CPU_FloatU u;
1000
1001 u.l = val;
1002 /* NaN are not treated the same way IEEE 754 does */
1003 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1004 return 0;
1005 }
1006
1007 return float32_to_int32(u.f, &env->vec_status);
1008 }
1009
1010 static inline uint32_t efsctui(CPUPPCState *env, uint32_t val)
1011 {
1012 CPU_FloatU u;
1013
1014 u.l = val;
1015 /* NaN are not treated the same way IEEE 754 does */
1016 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1017 return 0;
1018 }
1019
1020 return float32_to_uint32(u.f, &env->vec_status);
1021 }
1022
1023 static inline uint32_t efsctsiz(CPUPPCState *env, uint32_t val)
1024 {
1025 CPU_FloatU u;
1026
1027 u.l = val;
1028 /* NaN are not treated the same way IEEE 754 does */
1029 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1030 return 0;
1031 }
1032
1033 return float32_to_int32_round_to_zero(u.f, &env->vec_status);
1034 }
1035
1036 static inline uint32_t efsctuiz(CPUPPCState *env, uint32_t val)
1037 {
1038 CPU_FloatU u;
1039
1040 u.l = val;
1041 /* NaN are not treated the same way IEEE 754 does */
1042 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1043 return 0;
1044 }
1045
1046 return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
1047 }
1048
1049 static inline uint32_t efscfsf(CPUPPCState *env, uint32_t val)
1050 {
1051 CPU_FloatU u;
1052 float32 tmp;
1053
1054 u.f = int32_to_float32(val, &env->vec_status);
1055 tmp = int64_to_float32(1ULL << 32, &env->vec_status);
1056 u.f = float32_div(u.f, tmp, &env->vec_status);
1057
1058 return u.l;
1059 }
1060
1061 static inline uint32_t efscfuf(CPUPPCState *env, uint32_t val)
1062 {
1063 CPU_FloatU u;
1064 float32 tmp;
1065
1066 u.f = uint32_to_float32(val, &env->vec_status);
1067 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1068 u.f = float32_div(u.f, tmp, &env->vec_status);
1069
1070 return u.l;
1071 }
1072
1073 static inline uint32_t efsctsf(CPUPPCState *env, uint32_t val)
1074 {
1075 CPU_FloatU u;
1076 float32 tmp;
1077
1078 u.l = val;
1079 /* NaN are not treated the same way IEEE 754 does */
1080 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1081 return 0;
1082 }
1083 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1084 u.f = float32_mul(u.f, tmp, &env->vec_status);
1085
1086 return float32_to_int32(u.f, &env->vec_status);
1087 }
1088
1089 static inline uint32_t efsctuf(CPUPPCState *env, uint32_t val)
1090 {
1091 CPU_FloatU u;
1092 float32 tmp;
1093
1094 u.l = val;
1095 /* NaN are not treated the same way IEEE 754 does */
1096 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1097 return 0;
1098 }
1099 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1100 u.f = float32_mul(u.f, tmp, &env->vec_status);
1101
1102 return float32_to_uint32(u.f, &env->vec_status);
1103 }
1104
1105 #define HELPER_SPE_SINGLE_CONV(name) \
1106 uint32_t helper_e##name(CPUPPCState *env, uint32_t val) \
1107 { \
1108 return e##name(env, val); \
1109 }
1110 /* efscfsi */
1111 HELPER_SPE_SINGLE_CONV(fscfsi);
1112 /* efscfui */
1113 HELPER_SPE_SINGLE_CONV(fscfui);
1114 /* efscfuf */
1115 HELPER_SPE_SINGLE_CONV(fscfuf);
1116 /* efscfsf */
1117 HELPER_SPE_SINGLE_CONV(fscfsf);
1118 /* efsctsi */
1119 HELPER_SPE_SINGLE_CONV(fsctsi);
1120 /* efsctui */
1121 HELPER_SPE_SINGLE_CONV(fsctui);
1122 /* efsctsiz */
1123 HELPER_SPE_SINGLE_CONV(fsctsiz);
1124 /* efsctuiz */
1125 HELPER_SPE_SINGLE_CONV(fsctuiz);
1126 /* efsctsf */
1127 HELPER_SPE_SINGLE_CONV(fsctsf);
1128 /* efsctuf */
1129 HELPER_SPE_SINGLE_CONV(fsctuf);
1130
1131 #define HELPER_SPE_VECTOR_CONV(name) \
1132 uint64_t helper_ev##name(CPUPPCState *env, uint64_t val) \
1133 { \
1134 return ((uint64_t)e##name(env, val >> 32) << 32) | \
1135 (uint64_t)e##name(env, val); \
1136 }
1137 /* evfscfsi */
1138 HELPER_SPE_VECTOR_CONV(fscfsi);
1139 /* evfscfui */
1140 HELPER_SPE_VECTOR_CONV(fscfui);
1141 /* evfscfuf */
1142 HELPER_SPE_VECTOR_CONV(fscfuf);
1143 /* evfscfsf */
1144 HELPER_SPE_VECTOR_CONV(fscfsf);
1145 /* evfsctsi */
1146 HELPER_SPE_VECTOR_CONV(fsctsi);
1147 /* evfsctui */
1148 HELPER_SPE_VECTOR_CONV(fsctui);
1149 /* evfsctsiz */
1150 HELPER_SPE_VECTOR_CONV(fsctsiz);
1151 /* evfsctuiz */
1152 HELPER_SPE_VECTOR_CONV(fsctuiz);
1153 /* evfsctsf */
1154 HELPER_SPE_VECTOR_CONV(fsctsf);
1155 /* evfsctuf */
1156 HELPER_SPE_VECTOR_CONV(fsctuf);
1157
1158 /* Single-precision floating-point arithmetic */
1159 static inline uint32_t efsadd(CPUPPCState *env, uint32_t op1, uint32_t op2)
1160 {
1161 CPU_FloatU u1, u2;
1162
1163 u1.l = op1;
1164 u2.l = op2;
1165 u1.f = float32_add(u1.f, u2.f, &env->vec_status);
1166 return u1.l;
1167 }
1168
1169 static inline uint32_t efssub(CPUPPCState *env, uint32_t op1, uint32_t op2)
1170 {
1171 CPU_FloatU u1, u2;
1172
1173 u1.l = op1;
1174 u2.l = op2;
1175 u1.f = float32_sub(u1.f, u2.f, &env->vec_status);
1176 return u1.l;
1177 }
1178
1179 static inline uint32_t efsmul(CPUPPCState *env, uint32_t op1, uint32_t op2)
1180 {
1181 CPU_FloatU u1, u2;
1182
1183 u1.l = op1;
1184 u2.l = op2;
1185 u1.f = float32_mul(u1.f, u2.f, &env->vec_status);
1186 return u1.l;
1187 }
1188
1189 static inline uint32_t efsdiv(CPUPPCState *env, uint32_t op1, uint32_t op2)
1190 {
1191 CPU_FloatU u1, u2;
1192
1193 u1.l = op1;
1194 u2.l = op2;
1195 u1.f = float32_div(u1.f, u2.f, &env->vec_status);
1196 return u1.l;
1197 }
1198
1199 #define HELPER_SPE_SINGLE_ARITH(name) \
1200 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1201 { \
1202 return e##name(env, op1, op2); \
1203 }
1204 /* efsadd */
1205 HELPER_SPE_SINGLE_ARITH(fsadd);
1206 /* efssub */
1207 HELPER_SPE_SINGLE_ARITH(fssub);
1208 /* efsmul */
1209 HELPER_SPE_SINGLE_ARITH(fsmul);
1210 /* efsdiv */
1211 HELPER_SPE_SINGLE_ARITH(fsdiv);
1212
1213 #define HELPER_SPE_VECTOR_ARITH(name) \
1214 uint64_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1215 { \
1216 return ((uint64_t)e##name(env, op1 >> 32, op2 >> 32) << 32) | \
1217 (uint64_t)e##name(env, op1, op2); \
1218 }
1219 /* evfsadd */
1220 HELPER_SPE_VECTOR_ARITH(fsadd);
1221 /* evfssub */
1222 HELPER_SPE_VECTOR_ARITH(fssub);
1223 /* evfsmul */
1224 HELPER_SPE_VECTOR_ARITH(fsmul);
1225 /* evfsdiv */
1226 HELPER_SPE_VECTOR_ARITH(fsdiv);
1227
1228 /* Single-precision floating-point comparisons */
1229 static inline uint32_t efscmplt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1230 {
1231 CPU_FloatU u1, u2;
1232
1233 u1.l = op1;
1234 u2.l = op2;
1235 return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1236 }
1237
1238 static inline uint32_t efscmpgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1239 {
1240 CPU_FloatU u1, u2;
1241
1242 u1.l = op1;
1243 u2.l = op2;
1244 return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
1245 }
1246
1247 static inline uint32_t efscmpeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1248 {
1249 CPU_FloatU u1, u2;
1250
1251 u1.l = op1;
1252 u2.l = op2;
1253 return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1254 }
1255
1256 static inline uint32_t efststlt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1257 {
1258 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1259 return efscmplt(env, op1, op2);
1260 }
1261
1262 static inline uint32_t efststgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1263 {
1264 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1265 return efscmpgt(env, op1, op2);
1266 }
1267
1268 static inline uint32_t efststeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1269 {
1270 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1271 return efscmpeq(env, op1, op2);
1272 }
1273
1274 #define HELPER_SINGLE_SPE_CMP(name) \
1275 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1276 { \
1277 return e##name(env, op1, op2); \
1278 }
1279 /* efststlt */
1280 HELPER_SINGLE_SPE_CMP(fststlt);
1281 /* efststgt */
1282 HELPER_SINGLE_SPE_CMP(fststgt);
1283 /* efststeq */
1284 HELPER_SINGLE_SPE_CMP(fststeq);
1285 /* efscmplt */
1286 HELPER_SINGLE_SPE_CMP(fscmplt);
1287 /* efscmpgt */
1288 HELPER_SINGLE_SPE_CMP(fscmpgt);
1289 /* efscmpeq */
1290 HELPER_SINGLE_SPE_CMP(fscmpeq);
1291
1292 static inline uint32_t evcmp_merge(int t0, int t1)
1293 {
1294 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1295 }
1296
1297 #define HELPER_VECTOR_SPE_CMP(name) \
1298 uint32_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1299 { \
1300 return evcmp_merge(e##name(env, op1 >> 32, op2 >> 32), \
1301 e##name(env, op1, op2)); \
1302 }
1303 /* evfststlt */
1304 HELPER_VECTOR_SPE_CMP(fststlt);
1305 /* evfststgt */
1306 HELPER_VECTOR_SPE_CMP(fststgt);
1307 /* evfststeq */
1308 HELPER_VECTOR_SPE_CMP(fststeq);
1309 /* evfscmplt */
1310 HELPER_VECTOR_SPE_CMP(fscmplt);
1311 /* evfscmpgt */
1312 HELPER_VECTOR_SPE_CMP(fscmpgt);
1313 /* evfscmpeq */
1314 HELPER_VECTOR_SPE_CMP(fscmpeq);
1315
1316 /* Double-precision floating-point conversion */
1317 uint64_t helper_efdcfsi(CPUPPCState *env, uint32_t val)
1318 {
1319 CPU_DoubleU u;
1320
1321 u.d = int32_to_float64(val, &env->vec_status);
1322
1323 return u.ll;
1324 }
1325
1326 uint64_t helper_efdcfsid(CPUPPCState *env, uint64_t val)
1327 {
1328 CPU_DoubleU u;
1329
1330 u.d = int64_to_float64(val, &env->vec_status);
1331
1332 return u.ll;
1333 }
1334
1335 uint64_t helper_efdcfui(CPUPPCState *env, uint32_t val)
1336 {
1337 CPU_DoubleU u;
1338
1339 u.d = uint32_to_float64(val, &env->vec_status);
1340
1341 return u.ll;
1342 }
1343
1344 uint64_t helper_efdcfuid(CPUPPCState *env, uint64_t val)
1345 {
1346 CPU_DoubleU u;
1347
1348 u.d = uint64_to_float64(val, &env->vec_status);
1349
1350 return u.ll;
1351 }
1352
1353 uint32_t helper_efdctsi(CPUPPCState *env, uint64_t val)
1354 {
1355 CPU_DoubleU u;
1356
1357 u.ll = val;
1358 /* NaN are not treated the same way IEEE 754 does */
1359 if (unlikely(float64_is_any_nan(u.d))) {
1360 return 0;
1361 }
1362
1363 return float64_to_int32(u.d, &env->vec_status);
1364 }
1365
1366 uint32_t helper_efdctui(CPUPPCState *env, uint64_t val)
1367 {
1368 CPU_DoubleU u;
1369
1370 u.ll = val;
1371 /* NaN are not treated the same way IEEE 754 does */
1372 if (unlikely(float64_is_any_nan(u.d))) {
1373 return 0;
1374 }
1375
1376 return float64_to_uint32(u.d, &env->vec_status);
1377 }
1378
1379 uint32_t helper_efdctsiz(CPUPPCState *env, uint64_t val)
1380 {
1381 CPU_DoubleU u;
1382
1383 u.ll = val;
1384 /* NaN are not treated the same way IEEE 754 does */
1385 if (unlikely(float64_is_any_nan(u.d))) {
1386 return 0;
1387 }
1388
1389 return float64_to_int32_round_to_zero(u.d, &env->vec_status);
1390 }
1391
1392 uint64_t helper_efdctsidz(CPUPPCState *env, uint64_t val)
1393 {
1394 CPU_DoubleU u;
1395
1396 u.ll = val;
1397 /* NaN are not treated the same way IEEE 754 does */
1398 if (unlikely(float64_is_any_nan(u.d))) {
1399 return 0;
1400 }
1401
1402 return float64_to_int64_round_to_zero(u.d, &env->vec_status);
1403 }
1404
1405 uint32_t helper_efdctuiz(CPUPPCState *env, uint64_t val)
1406 {
1407 CPU_DoubleU u;
1408
1409 u.ll = val;
1410 /* NaN are not treated the same way IEEE 754 does */
1411 if (unlikely(float64_is_any_nan(u.d))) {
1412 return 0;
1413 }
1414
1415 return float64_to_uint32_round_to_zero(u.d, &env->vec_status);
1416 }
1417
1418 uint64_t helper_efdctuidz(CPUPPCState *env, uint64_t val)
1419 {
1420 CPU_DoubleU u;
1421
1422 u.ll = val;
1423 /* NaN are not treated the same way IEEE 754 does */
1424 if (unlikely(float64_is_any_nan(u.d))) {
1425 return 0;
1426 }
1427
1428 return float64_to_uint64_round_to_zero(u.d, &env->vec_status);
1429 }
1430
1431 uint64_t helper_efdcfsf(CPUPPCState *env, uint32_t val)
1432 {
1433 CPU_DoubleU u;
1434 float64 tmp;
1435
1436 u.d = int32_to_float64(val, &env->vec_status);
1437 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1438 u.d = float64_div(u.d, tmp, &env->vec_status);
1439
1440 return u.ll;
1441 }
1442
1443 uint64_t helper_efdcfuf(CPUPPCState *env, uint32_t val)
1444 {
1445 CPU_DoubleU u;
1446 float64 tmp;
1447
1448 u.d = uint32_to_float64(val, &env->vec_status);
1449 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1450 u.d = float64_div(u.d, tmp, &env->vec_status);
1451
1452 return u.ll;
1453 }
1454
1455 uint32_t helper_efdctsf(CPUPPCState *env, uint64_t val)
1456 {
1457 CPU_DoubleU u;
1458 float64 tmp;
1459
1460 u.ll = val;
1461 /* NaN are not treated the same way IEEE 754 does */
1462 if (unlikely(float64_is_any_nan(u.d))) {
1463 return 0;
1464 }
1465 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1466 u.d = float64_mul(u.d, tmp, &env->vec_status);
1467
1468 return float64_to_int32(u.d, &env->vec_status);
1469 }
1470
1471 uint32_t helper_efdctuf(CPUPPCState *env, uint64_t val)
1472 {
1473 CPU_DoubleU u;
1474 float64 tmp;
1475
1476 u.ll = val;
1477 /* NaN are not treated the same way IEEE 754 does */
1478 if (unlikely(float64_is_any_nan(u.d))) {
1479 return 0;
1480 }
1481 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1482 u.d = float64_mul(u.d, tmp, &env->vec_status);
1483
1484 return float64_to_uint32(u.d, &env->vec_status);
1485 }
1486
1487 uint32_t helper_efscfd(CPUPPCState *env, uint64_t val)
1488 {
1489 CPU_DoubleU u1;
1490 CPU_FloatU u2;
1491
1492 u1.ll = val;
1493 u2.f = float64_to_float32(u1.d, &env->vec_status);
1494
1495 return u2.l;
1496 }
1497
1498 uint64_t helper_efdcfs(CPUPPCState *env, uint32_t val)
1499 {
1500 CPU_DoubleU u2;
1501 CPU_FloatU u1;
1502
1503 u1.l = val;
1504 u2.d = float32_to_float64(u1.f, &env->vec_status);
1505
1506 return u2.ll;
1507 }
1508
1509 /* Double precision fixed-point arithmetic */
1510 uint64_t helper_efdadd(CPUPPCState *env, uint64_t op1, uint64_t op2)
1511 {
1512 CPU_DoubleU u1, u2;
1513
1514 u1.ll = op1;
1515 u2.ll = op2;
1516 u1.d = float64_add(u1.d, u2.d, &env->vec_status);
1517 return u1.ll;
1518 }
1519
1520 uint64_t helper_efdsub(CPUPPCState *env, uint64_t op1, uint64_t op2)
1521 {
1522 CPU_DoubleU u1, u2;
1523
1524 u1.ll = op1;
1525 u2.ll = op2;
1526 u1.d = float64_sub(u1.d, u2.d, &env->vec_status);
1527 return u1.ll;
1528 }
1529
1530 uint64_t helper_efdmul(CPUPPCState *env, uint64_t op1, uint64_t op2)
1531 {
1532 CPU_DoubleU u1, u2;
1533
1534 u1.ll = op1;
1535 u2.ll = op2;
1536 u1.d = float64_mul(u1.d, u2.d, &env->vec_status);
1537 return u1.ll;
1538 }
1539
1540 uint64_t helper_efddiv(CPUPPCState *env, uint64_t op1, uint64_t op2)
1541 {
1542 CPU_DoubleU u1, u2;
1543
1544 u1.ll = op1;
1545 u2.ll = op2;
1546 u1.d = float64_div(u1.d, u2.d, &env->vec_status);
1547 return u1.ll;
1548 }
1549
1550 /* Double precision floating point helpers */
1551 uint32_t helper_efdtstlt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1552 {
1553 CPU_DoubleU u1, u2;
1554
1555 u1.ll = op1;
1556 u2.ll = op2;
1557 return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1558 }
1559
1560 uint32_t helper_efdtstgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1561 {
1562 CPU_DoubleU u1, u2;
1563
1564 u1.ll = op1;
1565 u2.ll = op2;
1566 return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4;
1567 }
1568
1569 uint32_t helper_efdtsteq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1570 {
1571 CPU_DoubleU u1, u2;
1572
1573 u1.ll = op1;
1574 u2.ll = op2;
1575 return float64_eq_quiet(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1576 }
1577
1578 uint32_t helper_efdcmplt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1579 {
1580 /* XXX: TODO: test special values (NaN, infinites, ...) */
1581 return helper_efdtstlt(env, op1, op2);
1582 }
1583
1584 uint32_t helper_efdcmpgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1585 {
1586 /* XXX: TODO: test special values (NaN, infinites, ...) */
1587 return helper_efdtstgt(env, op1, op2);
1588 }
1589
1590 uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1591 {
1592 /* XXX: TODO: test special values (NaN, infinites, ...) */
1593 return helper_efdtsteq(env, op1, op2);
1594 }
1595
1596 #define float64_to_float64(x, env) x
1597
1598
1599 /*
1600 * VSX_ADD_SUB - VSX floating point add/subtract
1601 * name - instruction mnemonic
1602 * op - operation (add or sub)
1603 * nels - number of elements (1, 2 or 4)
1604 * tp - type (float32 or float64)
1605 * fld - vsr_t field (VsrD(*) or VsrW(*))
1606 * sfprf - set FPRF
1607 */
1608 #define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp) \
1609 void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \
1610 ppc_vsr_t *xa, ppc_vsr_t *xb) \
1611 { \
1612 ppc_vsr_t t = *xt; \
1613 int i; \
1614 \
1615 helper_reset_fpstatus(env); \
1616 \
1617 for (i = 0; i < nels; i++) { \
1618 float_status tstat = env->fp_status; \
1619 set_float_exception_flags(0, &tstat); \
1620 t.fld = tp##_##op(xa->fld, xb->fld, &tstat); \
1621 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1622 \
1623 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1624 float_invalid_op_addsub(env, tstat.float_exception_flags, \
1625 sfprf, GETPC()); \
1626 } \
1627 \
1628 if (r2sp) { \
1629 t.fld = do_frsp(env, t.fld, GETPC()); \
1630 } \
1631 \
1632 if (sfprf) { \
1633 helper_compute_fprf_float64(env, t.fld); \
1634 } \
1635 } \
1636 *xt = t; \
1637 do_float_check_status(env, GETPC()); \
1638 }
1639
1640 VSX_ADD_SUB(xsadddp, add, 1, float64, VsrD(0), 1, 0)
1641 VSX_ADD_SUB(xsaddsp, add, 1, float64, VsrD(0), 1, 1)
1642 VSX_ADD_SUB(xvadddp, add, 2, float64, VsrD(i), 0, 0)
1643 VSX_ADD_SUB(xvaddsp, add, 4, float32, VsrW(i), 0, 0)
1644 VSX_ADD_SUB(xssubdp, sub, 1, float64, VsrD(0), 1, 0)
1645 VSX_ADD_SUB(xssubsp, sub, 1, float64, VsrD(0), 1, 1)
1646 VSX_ADD_SUB(xvsubdp, sub, 2, float64, VsrD(i), 0, 0)
1647 VSX_ADD_SUB(xvsubsp, sub, 4, float32, VsrW(i), 0, 0)
1648
1649 void helper_xsaddqp(CPUPPCState *env, uint32_t opcode,
1650 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
1651 {
1652 ppc_vsr_t t = *xt;
1653 float_status tstat;
1654
1655 helper_reset_fpstatus(env);
1656
1657 tstat = env->fp_status;
1658 if (unlikely(Rc(opcode) != 0)) {
1659 tstat.float_rounding_mode = float_round_to_odd;
1660 }
1661
1662 set_float_exception_flags(0, &tstat);
1663 t.f128 = float128_add(xa->f128, xb->f128, &tstat);
1664 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1665
1666 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
1667 float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC());
1668 }
1669
1670 helper_compute_fprf_float128(env, t.f128);
1671
1672 *xt = t;
1673 do_float_check_status(env, GETPC());
1674 }
1675
1676 /*
1677 * VSX_MUL - VSX floating point multiply
1678 * op - instruction mnemonic
1679 * nels - number of elements (1, 2 or 4)
1680 * tp - type (float32 or float64)
1681 * fld - vsr_t field (VsrD(*) or VsrW(*))
1682 * sfprf - set FPRF
1683 */
1684 #define VSX_MUL(op, nels, tp, fld, sfprf, r2sp) \
1685 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
1686 ppc_vsr_t *xa, ppc_vsr_t *xb) \
1687 { \
1688 ppc_vsr_t t = *xt; \
1689 int i; \
1690 \
1691 helper_reset_fpstatus(env); \
1692 \
1693 for (i = 0; i < nels; i++) { \
1694 float_status tstat = env->fp_status; \
1695 set_float_exception_flags(0, &tstat); \
1696 t.fld = tp##_mul(xa->fld, xb->fld, &tstat); \
1697 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1698 \
1699 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1700 float_invalid_op_mul(env, tstat.float_exception_flags, \
1701 sfprf, GETPC()); \
1702 } \
1703 \
1704 if (r2sp) { \
1705 t.fld = do_frsp(env, t.fld, GETPC()); \
1706 } \
1707 \
1708 if (sfprf) { \
1709 helper_compute_fprf_float64(env, t.fld); \
1710 } \
1711 } \
1712 \
1713 *xt = t; \
1714 do_float_check_status(env, GETPC()); \
1715 }
1716
1717 VSX_MUL(xsmuldp, 1, float64, VsrD(0), 1, 0)
1718 VSX_MUL(xsmulsp, 1, float64, VsrD(0), 1, 1)
1719 VSX_MUL(xvmuldp, 2, float64, VsrD(i), 0, 0)
1720 VSX_MUL(xvmulsp, 4, float32, VsrW(i), 0, 0)
1721
1722 void helper_xsmulqp(CPUPPCState *env, uint32_t opcode,
1723 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
1724 {
1725 ppc_vsr_t t = *xt;
1726 float_status tstat;
1727
1728 helper_reset_fpstatus(env);
1729 tstat = env->fp_status;
1730 if (unlikely(Rc(opcode) != 0)) {
1731 tstat.float_rounding_mode = float_round_to_odd;
1732 }
1733
1734 set_float_exception_flags(0, &tstat);
1735 t.f128 = float128_mul(xa->f128, xb->f128, &tstat);
1736 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1737
1738 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
1739 float_invalid_op_mul(env, tstat.float_exception_flags, 1, GETPC());
1740 }
1741 helper_compute_fprf_float128(env, t.f128);
1742
1743 *xt = t;
1744 do_float_check_status(env, GETPC());
1745 }
1746
1747 /*
1748 * VSX_DIV - VSX floating point divide
1749 * op - instruction mnemonic
1750 * nels - number of elements (1, 2 or 4)
1751 * tp - type (float32 or float64)
1752 * fld - vsr_t field (VsrD(*) or VsrW(*))
1753 * sfprf - set FPRF
1754 */
1755 #define VSX_DIV(op, nels, tp, fld, sfprf, r2sp) \
1756 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
1757 ppc_vsr_t *xa, ppc_vsr_t *xb) \
1758 { \
1759 ppc_vsr_t t = *xt; \
1760 int i; \
1761 \
1762 helper_reset_fpstatus(env); \
1763 \
1764 for (i = 0; i < nels; i++) { \
1765 float_status tstat = env->fp_status; \
1766 set_float_exception_flags(0, &tstat); \
1767 t.fld = tp##_div(xa->fld, xb->fld, &tstat); \
1768 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1769 \
1770 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1771 float_invalid_op_div(env, tstat.float_exception_flags, \
1772 sfprf, GETPC()); \
1773 } \
1774 if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { \
1775 float_zero_divide_excp(env, GETPC()); \
1776 } \
1777 \
1778 if (r2sp) { \
1779 t.fld = do_frsp(env, t.fld, GETPC()); \
1780 } \
1781 \
1782 if (sfprf) { \
1783 helper_compute_fprf_float64(env, t.fld); \
1784 } \
1785 } \
1786 \
1787 *xt = t; \
1788 do_float_check_status(env, GETPC()); \
1789 }
1790
1791 VSX_DIV(xsdivdp, 1, float64, VsrD(0), 1, 0)
1792 VSX_DIV(xsdivsp, 1, float64, VsrD(0), 1, 1)
1793 VSX_DIV(xvdivdp, 2, float64, VsrD(i), 0, 0)
1794 VSX_DIV(xvdivsp, 4, float32, VsrW(i), 0, 0)
1795
1796 void helper_xsdivqp(CPUPPCState *env, uint32_t opcode,
1797 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
1798 {
1799 ppc_vsr_t t = *xt;
1800 float_status tstat;
1801
1802 helper_reset_fpstatus(env);
1803 tstat = env->fp_status;
1804 if (unlikely(Rc(opcode) != 0)) {
1805 tstat.float_rounding_mode = float_round_to_odd;
1806 }
1807
1808 set_float_exception_flags(0, &tstat);
1809 t.f128 = float128_div(xa->f128, xb->f128, &tstat);
1810 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1811
1812 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
1813 float_invalid_op_div(env, tstat.float_exception_flags, 1, GETPC());
1814 }
1815 if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) {
1816 float_zero_divide_excp(env, GETPC());
1817 }
1818
1819 helper_compute_fprf_float128(env, t.f128);
1820 *xt = t;
1821 do_float_check_status(env, GETPC());
1822 }
1823
1824 /*
1825 * VSX_RE - VSX floating point reciprocal estimate
1826 * op - instruction mnemonic
1827 * nels - number of elements (1, 2 or 4)
1828 * tp - type (float32 or float64)
1829 * fld - vsr_t field (VsrD(*) or VsrW(*))
1830 * sfprf - set FPRF
1831 */
1832 #define VSX_RE(op, nels, tp, fld, sfprf, r2sp) \
1833 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
1834 { \
1835 ppc_vsr_t t = *xt; \
1836 int i; \
1837 \
1838 helper_reset_fpstatus(env); \
1839 \
1840 for (i = 0; i < nels; i++) { \
1841 if (unlikely(tp##_is_signaling_nan(xb->fld, &env->fp_status))) { \
1842 float_invalid_op_vxsnan(env, GETPC()); \
1843 } \
1844 t.fld = tp##_div(tp##_one, xb->fld, &env->fp_status); \
1845 \
1846 if (r2sp) { \
1847 t.fld = do_frsp(env, t.fld, GETPC()); \
1848 } \
1849 \
1850 if (sfprf) { \
1851 helper_compute_fprf_float64(env, t.fld); \
1852 } \
1853 } \
1854 \
1855 *xt = t; \
1856 do_float_check_status(env, GETPC()); \
1857 }
1858
1859 VSX_RE(xsredp, 1, float64, VsrD(0), 1, 0)
1860 VSX_RE(xsresp, 1, float64, VsrD(0), 1, 1)
1861 VSX_RE(xvredp, 2, float64, VsrD(i), 0, 0)
1862 VSX_RE(xvresp, 4, float32, VsrW(i), 0, 0)
1863
1864 /*
1865 * VSX_SQRT - VSX floating point square root
1866 * op - instruction mnemonic
1867 * nels - number of elements (1, 2 or 4)
1868 * tp - type (float32 or float64)
1869 * fld - vsr_t field (VsrD(*) or VsrW(*))
1870 * sfprf - set FPRF
1871 */
1872 #define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp) \
1873 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
1874 { \
1875 ppc_vsr_t t = *xt; \
1876 int i; \
1877 \
1878 helper_reset_fpstatus(env); \
1879 \
1880 for (i = 0; i < nels; i++) { \
1881 float_status tstat = env->fp_status; \
1882 set_float_exception_flags(0, &tstat); \
1883 t.fld = tp##_sqrt(xb->fld, &tstat); \
1884 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1885 \
1886 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1887 if (tp##_is_neg(xb->fld) && !tp##_is_zero(xb->fld)) { \
1888 float_invalid_op_vxsqrt(env, sfprf, GETPC()); \
1889 } else if (tp##_is_signaling_nan(xb->fld, &tstat)) { \
1890 float_invalid_op_vxsnan(env, GETPC()); \
1891 } \
1892 } \
1893 \
1894 if (r2sp) { \
1895 t.fld = do_frsp(env, t.fld, GETPC()); \
1896 } \
1897 \
1898 if (sfprf) { \
1899 helper_compute_fprf_float64(env, t.fld); \
1900 } \
1901 } \
1902 \
1903 *xt = t; \
1904 do_float_check_status(env, GETPC()); \
1905 }
1906
1907 VSX_SQRT(xssqrtdp, 1, float64, VsrD(0), 1, 0)
1908 VSX_SQRT(xssqrtsp, 1, float64, VsrD(0), 1, 1)
1909 VSX_SQRT(xvsqrtdp, 2, float64, VsrD(i), 0, 0)
1910 VSX_SQRT(xvsqrtsp, 4, float32, VsrW(i), 0, 0)
1911
1912 /*
1913 *VSX_RSQRTE - VSX floating point reciprocal square root estimate
1914 * op - instruction mnemonic
1915 * nels - number of elements (1, 2 or 4)
1916 * tp - type (float32 or float64)
1917 * fld - vsr_t field (VsrD(*) or VsrW(*))
1918 * sfprf - set FPRF
1919 */
1920 #define VSX_RSQRTE(op, nels, tp, fld, sfprf, r2sp) \
1921 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
1922 { \
1923 ppc_vsr_t t = *xt; \
1924 int i; \
1925 \
1926 helper_reset_fpstatus(env); \
1927 \
1928 for (i = 0; i < nels; i++) { \
1929 float_status tstat = env->fp_status; \
1930 set_float_exception_flags(0, &tstat); \
1931 t.fld = tp##_sqrt(xb->fld, &tstat); \
1932 t.fld = tp##_div(tp##_one, t.fld, &tstat); \
1933 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1934 \
1935 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1936 if (tp##_is_neg(xb->fld) && !tp##_is_zero(xb->fld)) { \
1937 float_invalid_op_vxsqrt(env, sfprf, GETPC()); \
1938 } else if (tp##_is_signaling_nan(xb->fld, &tstat)) { \
1939 float_invalid_op_vxsnan(env, GETPC()); \
1940 } \
1941 } \
1942 \
1943 if (r2sp) { \
1944 t.fld = do_frsp(env, t.fld, GETPC()); \
1945 } \
1946 \
1947 if (sfprf) { \
1948 helper_compute_fprf_float64(env, t.fld); \
1949 } \
1950 } \
1951 \
1952 *xt = t; \
1953 do_float_check_status(env, GETPC()); \
1954 }
1955
1956 VSX_RSQRTE(xsrsqrtedp, 1, float64, VsrD(0), 1, 0)
1957 VSX_RSQRTE(xsrsqrtesp, 1, float64, VsrD(0), 1, 1)
1958 VSX_RSQRTE(xvrsqrtedp, 2, float64, VsrD(i), 0, 0)
1959 VSX_RSQRTE(xvrsqrtesp, 4, float32, VsrW(i), 0, 0)
1960
1961 /*
1962 * VSX_TDIV - VSX floating point test for divide
1963 * op - instruction mnemonic
1964 * nels - number of elements (1, 2 or 4)
1965 * tp - type (float32 or float64)
1966 * fld - vsr_t field (VsrD(*) or VsrW(*))
1967 * emin - minimum unbiased exponent
1968 * emax - maximum unbiased exponent
1969 * nbits - number of fraction bits
1970 */
1971 #define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits) \
1972 void helper_##op(CPUPPCState *env, uint32_t opcode, \
1973 ppc_vsr_t *xa, ppc_vsr_t *xb) \
1974 { \
1975 int i; \
1976 int fe_flag = 0; \
1977 int fg_flag = 0; \
1978 \
1979 for (i = 0; i < nels; i++) { \
1980 if (unlikely(tp##_is_infinity(xa->fld) || \
1981 tp##_is_infinity(xb->fld) || \
1982 tp##_is_zero(xb->fld))) { \
1983 fe_flag = 1; \
1984 fg_flag = 1; \
1985 } else { \
1986 int e_a = ppc_##tp##_get_unbiased_exp(xa->fld); \
1987 int e_b = ppc_##tp##_get_unbiased_exp(xb->fld); \
1988 \
1989 if (unlikely(tp##_is_any_nan(xa->fld) || \
1990 tp##_is_any_nan(xb->fld))) { \
1991 fe_flag = 1; \
1992 } else if ((e_b <= emin) || (e_b >= (emax - 2))) { \
1993 fe_flag = 1; \
1994 } else if (!tp##_is_zero(xa->fld) && \
1995 (((e_a - e_b) >= emax) || \
1996 ((e_a - e_b) <= (emin + 1)) || \
1997 (e_a <= (emin + nbits)))) { \
1998 fe_flag = 1; \
1999 } \
2000 \
2001 if (unlikely(tp##_is_zero_or_denormal(xb->fld))) { \
2002 /* \
2003 * XB is not zero because of the above check and so \
2004 * must be denormalized. \
2005 */ \
2006 fg_flag = 1; \
2007 } \
2008 } \
2009 } \
2010 \
2011 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2012 }
2013
2014 VSX_TDIV(xstdivdp, 1, float64, VsrD(0), -1022, 1023, 52)
2015 VSX_TDIV(xvtdivdp, 2, float64, VsrD(i), -1022, 1023, 52)
2016 VSX_TDIV(xvtdivsp, 4, float32, VsrW(i), -126, 127, 23)
2017
2018 /*
2019 * VSX_TSQRT - VSX floating point test for square root
2020 * op - instruction mnemonic
2021 * nels - number of elements (1, 2 or 4)
2022 * tp - type (float32 or float64)
2023 * fld - vsr_t field (VsrD(*) or VsrW(*))
2024 * emin - minimum unbiased exponent
2025 * emax - maximum unbiased exponent
2026 * nbits - number of fraction bits
2027 */
2028 #define VSX_TSQRT(op, nels, tp, fld, emin, nbits) \
2029 void helper_##op(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb) \
2030 { \
2031 int i; \
2032 int fe_flag = 0; \
2033 int fg_flag = 0; \
2034 \
2035 for (i = 0; i < nels; i++) { \
2036 if (unlikely(tp##_is_infinity(xb->fld) || \
2037 tp##_is_zero(xb->fld))) { \
2038 fe_flag = 1; \
2039 fg_flag = 1; \
2040 } else { \
2041 int e_b = ppc_##tp##_get_unbiased_exp(xb->fld); \
2042 \
2043 if (unlikely(tp##_is_any_nan(xb->fld))) { \
2044 fe_flag = 1; \
2045 } else if (unlikely(tp##_is_zero(xb->fld))) { \
2046 fe_flag = 1; \
2047 } else if (unlikely(tp##_is_neg(xb->fld))) { \
2048 fe_flag = 1; \
2049 } else if (!tp##_is_zero(xb->fld) && \
2050 (e_b <= (emin + nbits))) { \
2051 fe_flag = 1; \
2052 } \
2053 \
2054 if (unlikely(tp##_is_zero_or_denormal(xb->fld))) { \
2055 /* \
2056 * XB is not zero because of the above check and \
2057 * therefore must be denormalized. \
2058 */ \
2059 fg_flag = 1; \
2060 } \
2061 } \
2062 } \
2063 \
2064 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2065 }
2066
2067 VSX_TSQRT(xstsqrtdp, 1, float64, VsrD(0), -1022, 52)
2068 VSX_TSQRT(xvtsqrtdp, 2, float64, VsrD(i), -1022, 52)
2069 VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23)
2070
2071 /*
2072 * VSX_MADD - VSX floating point muliply/add variations
2073 * op - instruction mnemonic
2074 * nels - number of elements (1, 2 or 4)
2075 * tp - type (float32 or float64)
2076 * fld - vsr_t field (VsrD(*) or VsrW(*))
2077 * maddflgs - flags for the float*muladd routine that control the
2078 * various forms (madd, msub, nmadd, nmsub)
2079 * sfprf - set FPRF
2080 */
2081 #define VSX_MADD(op, nels, tp, fld, maddflgs, sfprf, r2sp) \
2082 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2083 ppc_vsr_t *xa, ppc_vsr_t *b, ppc_vsr_t *c) \
2084 { \
2085 ppc_vsr_t t = *xt; \
2086 int i; \
2087 \
2088 helper_reset_fpstatus(env); \
2089 \
2090 for (i = 0; i < nels; i++) { \
2091 float_status tstat = env->fp_status; \
2092 set_float_exception_flags(0, &tstat); \
2093 if (r2sp && (tstat.float_rounding_mode == float_round_nearest_even)) {\
2094 /* \
2095 * Avoid double rounding errors by rounding the intermediate \
2096 * result to odd. \
2097 */ \
2098 set_float_rounding_mode(float_round_to_zero, &tstat); \
2099 t.fld = tp##_muladd(xa->fld, b->fld, c->fld, \
2100 maddflgs, &tstat); \
2101 t.fld |= (get_float_exception_flags(&tstat) & \
2102 float_flag_inexact) != 0; \
2103 } else { \
2104 t.fld = tp##_muladd(xa->fld, b->fld, c->fld, \
2105 maddflgs, &tstat); \
2106 } \
2107 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2108 \
2109 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2110 float_invalid_op_madd(env, tstat.float_exception_flags, \
2111 sfprf, GETPC()); \
2112 } \
2113 \
2114 if (r2sp) { \
2115 t.fld = do_frsp(env, t.fld, GETPC()); \
2116 } \
2117 \
2118 if (sfprf) { \
2119 helper_compute_fprf_float64(env, t.fld); \
2120 } \
2121 } \
2122 *xt = t; \
2123 do_float_check_status(env, GETPC()); \
2124 }
2125
2126 VSX_MADD(xsmadddp, 1, float64, VsrD(0), MADD_FLGS, 1, 0)
2127 VSX_MADD(xsmsubdp, 1, float64, VsrD(0), MSUB_FLGS, 1, 0)
2128 VSX_MADD(xsnmadddp, 1, float64, VsrD(0), NMADD_FLGS, 1, 0)
2129 VSX_MADD(xsnmsubdp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 0)
2130 VSX_MADD(xsmaddsp, 1, float64, VsrD(0), MADD_FLGS, 1, 1)
2131 VSX_MADD(xsmsubsp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1)
2132 VSX_MADD(xsnmaddsp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1)
2133 VSX_MADD(xsnmsubsp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1)
2134
2135 VSX_MADD(xvmadddp, 2, float64, VsrD(i), MADD_FLGS, 0, 0)
2136 VSX_MADD(xvmsubdp, 2, float64, VsrD(i), MSUB_FLGS, 0, 0)
2137 VSX_MADD(xvnmadddp, 2, float64, VsrD(i), NMADD_FLGS, 0, 0)
2138 VSX_MADD(xvnmsubdp, 2, float64, VsrD(i), NMSUB_FLGS, 0, 0)
2139
2140 VSX_MADD(xvmaddsp, 4, float32, VsrW(i), MADD_FLGS, 0, 0)
2141 VSX_MADD(xvmsubsp, 4, float32, VsrW(i), MSUB_FLGS, 0, 0)
2142 VSX_MADD(xvnmaddsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0)
2143 VSX_MADD(xvnmsubsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0)
2144
2145 /*
2146 * VSX_SCALAR_CMP_DP - VSX scalar floating point compare double precision
2147 * op - instruction mnemonic
2148 * cmp - comparison operation
2149 * exp - expected result of comparison
2150 * svxvc - set VXVC bit
2151 */
2152 #define VSX_SCALAR_CMP_DP(op, cmp, exp, svxvc) \
2153 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2154 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2155 { \
2156 ppc_vsr_t t = *xt; \
2157 bool vxsnan_flag = false, vxvc_flag = false, vex_flag = false; \
2158 \
2159 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \
2160 float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
2161 vxsnan_flag = true; \
2162 if (fpscr_ve == 0 && svxvc) { \
2163 vxvc_flag = true; \
2164 } \
2165 } else if (svxvc) { \
2166 vxvc_flag = float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) || \
2167 float64_is_quiet_nan(xb->VsrD(0), &env->fp_status); \
2168 } \
2169 if (vxsnan_flag) { \
2170 float_invalid_op_vxsnan(env, GETPC()); \
2171 } \
2172 if (vxvc_flag) { \
2173 float_invalid_op_vxvc(env, 0, GETPC()); \
2174 } \
2175 vex_flag = fpscr_ve && (vxvc_flag || vxsnan_flag); \
2176 \
2177 if (!vex_flag) { \
2178 if (float64_##cmp(xb->VsrD(0), xa->VsrD(0), \
2179 &env->fp_status) == exp) { \
2180 t.VsrD(0) = -1; \
2181 t.VsrD(1) = 0; \
2182 } else { \
2183 t.VsrD(0) = 0; \
2184 t.VsrD(1) = 0; \
2185 } \
2186 } \
2187 *xt = t; \
2188 do_float_check_status(env, GETPC()); \
2189 }
2190
2191 VSX_SCALAR_CMP_DP(xscmpeqdp, eq, 1, 0)
2192 VSX_SCALAR_CMP_DP(xscmpgedp, le, 1, 1)
2193 VSX_SCALAR_CMP_DP(xscmpgtdp, lt, 1, 1)
2194 VSX_SCALAR_CMP_DP(xscmpnedp, eq, 0, 0)
2195
2196 void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode,
2197 ppc_vsr_t *xa, ppc_vsr_t *xb)
2198 {
2199 int64_t exp_a, exp_b;
2200 uint32_t cc;
2201
2202 exp_a = extract64(xa->VsrD(0), 52, 11);
2203 exp_b = extract64(xb->VsrD(0), 52, 11);
2204
2205 if (unlikely(float64_is_any_nan(xa->VsrD(0)) ||
2206 float64_is_any_nan(xb->VsrD(0)))) {
2207 cc = CRF_SO;
2208 } else {
2209 if (exp_a < exp_b) {
2210 cc = CRF_LT;
2211 } else if (exp_a > exp_b) {
2212 cc = CRF_GT;
2213 } else {
2214 cc = CRF_EQ;
2215 }
2216 }
2217
2218 env->fpscr &= ~FP_FPCC;
2219 env->fpscr |= cc << FPSCR_FPCC;
2220 env->crf[BF(opcode)] = cc;
2221
2222 do_float_check_status(env, GETPC());
2223 }
2224
2225 void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode,
2226 ppc_vsr_t *xa, ppc_vsr_t *xb)
2227 {
2228 int64_t exp_a, exp_b;
2229 uint32_t cc;
2230
2231 exp_a = extract64(xa->VsrD(0), 48, 15);
2232 exp_b = extract64(xb->VsrD(0), 48, 15);
2233
2234 if (unlikely(float128_is_any_nan(xa->f128) ||
2235 float128_is_any_nan(xb->f128))) {
2236 cc = CRF_SO;
2237 } else {
2238 if (exp_a < exp_b) {
2239 cc = CRF_LT;
2240 } else if (exp_a > exp_b) {
2241 cc = CRF_GT;
2242 } else {
2243 cc = CRF_EQ;
2244 }
2245 }
2246
2247 env->fpscr &= ~FP_FPCC;
2248 env->fpscr |= cc << FPSCR_FPCC;
2249 env->crf[BF(opcode)] = cc;
2250
2251 do_float_check_status(env, GETPC());
2252 }
2253
2254 static inline void do_scalar_cmp(CPUPPCState *env, ppc_vsr_t *xa, ppc_vsr_t *xb,
2255 int crf_idx, bool ordered)
2256 {
2257 uint32_t cc;
2258 bool vxsnan_flag = false, vxvc_flag = false;
2259
2260 helper_reset_fpstatus(env);
2261
2262 switch (float64_compare(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) {
2263 case float_relation_less:
2264 cc = CRF_LT;
2265 break;
2266 case float_relation_equal:
2267 cc = CRF_EQ;
2268 break;
2269 case float_relation_greater:
2270 cc = CRF_GT;
2271 break;
2272 case float_relation_unordered:
2273 cc = CRF_SO;
2274
2275 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) ||
2276 float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) {
2277 vxsnan_flag = true;
2278 if (fpscr_ve == 0 && ordered) {
2279 vxvc_flag = true;
2280 }
2281 } else if (float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) ||
2282 float64_is_quiet_nan(xb->VsrD(0), &env->fp_status)) {
2283 if (ordered) {
2284 vxvc_flag = true;
2285 }
2286 }
2287
2288 break;
2289 default:
2290 g_assert_not_reached();
2291 }
2292
2293 env->fpscr &= ~FP_FPCC;
2294 env->fpscr |= cc << FPSCR_FPCC;
2295 env->crf[crf_idx] = cc;
2296
2297 if (vxsnan_flag) {
2298 float_invalid_op_vxsnan(env, GETPC());
2299 }
2300 if (vxvc_flag) {
2301 float_invalid_op_vxvc(env, 0, GETPC());
2302 }
2303
2304 do_float_check_status(env, GETPC());
2305 }
2306
2307 void helper_xscmpodp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2308 ppc_vsr_t *xb)
2309 {
2310 do_scalar_cmp(env, xa, xb, BF(opcode), true);
2311 }
2312
2313 void helper_xscmpudp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2314 ppc_vsr_t *xb)
2315 {
2316 do_scalar_cmp(env, xa, xb, BF(opcode), false);
2317 }
2318
2319 static inline void do_scalar_cmpq(CPUPPCState *env, ppc_vsr_t *xa,
2320 ppc_vsr_t *xb, int crf_idx, bool ordered)
2321 {
2322 uint32_t cc;
2323 bool vxsnan_flag = false, vxvc_flag = false;
2324
2325 helper_reset_fpstatus(env);
2326
2327 switch (float128_compare(xa->f128, xb->f128, &env->fp_status)) {
2328 case float_relation_less:
2329 cc = CRF_LT;
2330 break;
2331 case float_relation_equal:
2332 cc = CRF_EQ;
2333 break;
2334 case float_relation_greater:
2335 cc = CRF_GT;
2336 break;
2337 case float_relation_unordered:
2338 cc = CRF_SO;
2339
2340 if (float128_is_signaling_nan(xa->f128, &env->fp_status) ||
2341 float128_is_signaling_nan(xb->f128, &env->fp_status)) {
2342 vxsnan_flag = true;
2343 if (fpscr_ve == 0 && ordered) {
2344 vxvc_flag = true;
2345 }
2346 } else if (float128_is_quiet_nan(xa->f128, &env->fp_status) ||
2347 float128_is_quiet_nan(xb->f128, &env->fp_status)) {
2348 if (ordered) {
2349 vxvc_flag = true;
2350 }
2351 }
2352
2353 break;
2354 default:
2355 g_assert_not_reached();
2356 }
2357
2358 env->fpscr &= ~FP_FPCC;
2359 env->fpscr |= cc << FPSCR_FPCC;
2360 env->crf[crf_idx] = cc;
2361
2362 if (vxsnan_flag) {
2363 float_invalid_op_vxsnan(env, GETPC());
2364 }
2365 if (vxvc_flag) {
2366 float_invalid_op_vxvc(env, 0, GETPC());
2367 }
2368
2369 do_float_check_status(env, GETPC());
2370 }
2371
2372 void helper_xscmpoqp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2373 ppc_vsr_t *xb)
2374 {
2375 do_scalar_cmpq(env, xa, xb, BF(opcode), true);
2376 }
2377
2378 void helper_xscmpuqp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2379 ppc_vsr_t *xb)
2380 {
2381 do_scalar_cmpq(env, xa, xb, BF(opcode), false);
2382 }
2383
2384 /*
2385 * VSX_MAX_MIN - VSX floating point maximum/minimum
2386 * name - instruction mnemonic
2387 * op - operation (max or min)
2388 * nels - number of elements (1, 2 or 4)
2389 * tp - type (float32 or float64)
2390 * fld - vsr_t field (VsrD(*) or VsrW(*))
2391 */
2392 #define VSX_MAX_MIN(name, op, nels, tp, fld) \
2393 void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \
2394 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2395 { \
2396 ppc_vsr_t t = *xt; \
2397 int i; \
2398 \
2399 for (i = 0; i < nels; i++) { \
2400 t.fld = tp##_##op(xa->fld, xb->fld, &env->fp_status); \
2401 if (unlikely(tp##_is_signaling_nan(xa->fld, &env->fp_status) || \
2402 tp##_is_signaling_nan(xb->fld, &env->fp_status))) { \
2403 float_invalid_op_vxsnan(env, GETPC()); \
2404 } \
2405 } \
2406 \
2407 *xt = t; \
2408 do_float_check_status(env, GETPC()); \
2409 }
2410
2411 VSX_MAX_MIN(xsmaxdp, maxnum, 1, float64, VsrD(0))
2412 VSX_MAX_MIN(xvmaxdp, maxnum, 2, float64, VsrD(i))
2413 VSX_MAX_MIN(xvmaxsp, maxnum, 4, float32, VsrW(i))
2414 VSX_MAX_MIN(xsmindp, minnum, 1, float64, VsrD(0))
2415 VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
2416 VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
2417
2418 #define VSX_MAX_MINC(name, max) \
2419 void helper_##name(CPUPPCState *env, uint32_t opcode, \
2420 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
2421 { \
2422 ppc_vsr_t t = *xt; \
2423 bool vxsnan_flag = false, vex_flag = false; \
2424 \
2425 if (unlikely(float64_is_any_nan(xa->VsrD(0)) || \
2426 float64_is_any_nan(xb->VsrD(0)))) { \
2427 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \
2428 float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
2429 vxsnan_flag = true; \
2430 } \
2431 t.VsrD(0) = xb->VsrD(0); \
2432 } else if ((max && \
2433 !float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) || \
2434 (!max && \
2435 float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status))) { \
2436 t.VsrD(0) = xa->VsrD(0); \
2437 } else { \
2438 t.VsrD(0) = xb->VsrD(0); \
2439 } \
2440 \
2441 vex_flag = fpscr_ve & vxsnan_flag; \
2442 if (vxsnan_flag) { \
2443 float_invalid_op_vxsnan(env, GETPC()); \
2444 } \
2445 if (!vex_flag) { \
2446 *xt = t; \
2447 } \
2448 } \
2449
2450 VSX_MAX_MINC(xsmaxcdp, 1);
2451 VSX_MAX_MINC(xsmincdp, 0);
2452
2453 #define VSX_MAX_MINJ(name, max) \
2454 void helper_##name(CPUPPCState *env, uint32_t opcode, \
2455 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
2456 { \
2457 ppc_vsr_t t = *xt; \
2458 bool vxsnan_flag = false, vex_flag = false; \
2459 \
2460 if (unlikely(float64_is_any_nan(xa->VsrD(0)))) { \
2461 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status)) { \
2462 vxsnan_flag = true; \
2463 } \
2464 t.VsrD(0) = xa->VsrD(0); \
2465 } else if (unlikely(float64_is_any_nan(xb->VsrD(0)))) { \
2466 if (float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
2467 vxsnan_flag = true; \
2468 } \
2469 t.VsrD(0) = xb->VsrD(0); \
2470 } else if (float64_is_zero(xa->VsrD(0)) && \
2471 float64_is_zero(xb->VsrD(0))) { \
2472 if (max) { \
2473 if (!float64_is_neg(xa->VsrD(0)) || \
2474 !float64_is_neg(xb->VsrD(0))) { \
2475 t.VsrD(0) = 0ULL; \
2476 } else { \
2477 t.VsrD(0) = 0x8000000000000000ULL; \
2478 } \
2479 } else { \
2480 if (float64_is_neg(xa->VsrD(0)) || \
2481 float64_is_neg(xb->VsrD(0))) { \
2482 t.VsrD(0) = 0x8000000000000000ULL; \
2483 } else { \
2484 t.VsrD(0) = 0ULL; \
2485 } \
2486 } \
2487 } else if ((max && \
2488 !float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) || \
2489 (!max && \
2490 float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status))) { \
2491 t.VsrD(0) = xa->VsrD(0); \
2492 } else { \
2493 t.VsrD(0) = xb->VsrD(0); \
2494 } \
2495 \
2496 vex_flag = fpscr_ve & vxsnan_flag; \
2497 if (vxsnan_flag) { \
2498 float_invalid_op_vxsnan(env, GETPC()); \
2499 } \
2500 if (!vex_flag) { \
2501 *xt = t; \
2502 } \
2503 } \
2504
2505 VSX_MAX_MINJ(xsmaxjdp, 1);
2506 VSX_MAX_MINJ(xsminjdp, 0);
2507
2508 /*
2509 * VSX_CMP - VSX floating point compare
2510 * op - instruction mnemonic
2511 * nels - number of elements (1, 2 or 4)
2512 * tp - type (float32 or float64)
2513 * fld - vsr_t field (VsrD(*) or VsrW(*))
2514 * cmp - comparison operation
2515 * svxvc - set VXVC bit
2516 * exp - expected result of comparison
2517 */
2518 #define VSX_CMP(op, nels, tp, fld, cmp, svxvc, exp) \
2519 uint32_t helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2520 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2521 { \
2522 ppc_vsr_t t = *xt; \
2523 uint32_t crf6 = 0; \
2524 int i; \
2525 int all_true = 1; \
2526 int all_false = 1; \
2527 \
2528 for (i = 0; i < nels; i++) { \
2529 if (unlikely(tp##_is_any_nan(xa->fld) || \
2530 tp##_is_any_nan(xb->fld))) { \
2531 if (tp##_is_signaling_nan(xa->fld, &env->fp_status) || \
2532 tp##_is_signaling_nan(xb->fld, &env->fp_status)) { \
2533 float_invalid_op_vxsnan(env, GETPC()); \
2534 } \
2535 if (svxvc) { \
2536 float_invalid_op_vxvc(env, 0, GETPC()); \
2537 } \
2538 t.fld = 0; \
2539 all_true = 0; \
2540 } else { \
2541 if (tp##_##cmp(xb->fld, xa->fld, &env->fp_status) == exp) { \
2542 t.fld = -1; \
2543 all_false = 0; \
2544 } else { \
2545 t.fld = 0; \
2546 all_true = 0; \
2547 } \
2548 } \
2549 } \
2550 \
2551 *xt = t; \
2552 crf6 = (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); \
2553 return crf6; \
2554 }
2555
2556 VSX_CMP(xvcmpeqdp, 2, float64, VsrD(i), eq, 0, 1)
2557 VSX_CMP(xvcmpgedp, 2, float64, VsrD(i), le, 1, 1)
2558 VSX_CMP(xvcmpgtdp, 2, float64, VsrD(i), lt, 1, 1)
2559 VSX_CMP(xvcmpnedp, 2, float64, VsrD(i), eq, 0, 0)
2560 VSX_CMP(xvcmpeqsp, 4, float32, VsrW(i), eq, 0, 1)
2561 VSX_CMP(xvcmpgesp, 4, float32, VsrW(i), le, 1, 1)
2562 VSX_CMP(xvcmpgtsp, 4, float32, VsrW(i), lt, 1, 1)
2563 VSX_CMP(xvcmpnesp, 4, float32, VsrW(i), eq, 0, 0)
2564
2565 /*
2566 * VSX_CVT_FP_TO_FP - VSX floating point/floating point conversion
2567 * op - instruction mnemonic
2568 * nels - number of elements (1, 2 or 4)
2569 * stp - source type (float32 or float64)
2570 * ttp - target type (float32 or float64)
2571 * sfld - source vsr_t field
2572 * tfld - target vsr_t field (f32 or f64)
2573 * sfprf - set FPRF
2574 */
2575 #define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf) \
2576 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2577 { \
2578 ppc_vsr_t t = *xt; \
2579 int i; \
2580 \
2581 for (i = 0; i < nels; i++) { \
2582 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2583 if (unlikely(stp##_is_signaling_nan(xb->sfld, \
2584 &env->fp_status))) { \
2585 float_invalid_op_vxsnan(env, GETPC()); \
2586 t.tfld = ttp##_snan_to_qnan(t.tfld); \
2587 } \
2588 if (sfprf) { \
2589 helper_compute_fprf_##ttp(env, t.tfld); \
2590 } \
2591 } \
2592 \
2593 *xt = t; \
2594 do_float_check_status(env, GETPC()); \
2595 }
2596
2597 VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, VsrD(0), VsrW(0), 1)
2598 VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
2599 VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2 * i), 0)
2600 VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2 * i), VsrD(i), 0)
2601
2602 /*
2603 * VSX_CVT_FP_TO_FP_VECTOR - VSX floating point/floating point conversion
2604 * op - instruction mnemonic
2605 * nels - number of elements (1, 2 or 4)
2606 * stp - source type (float32 or float64)
2607 * ttp - target type (float32 or float64)
2608 * sfld - source vsr_t field
2609 * tfld - target vsr_t field (f32 or f64)
2610 * sfprf - set FPRF
2611 */
2612 #define VSX_CVT_FP_TO_FP_VECTOR(op, nels, stp, ttp, sfld, tfld, sfprf) \
2613 void helper_##op(CPUPPCState *env, uint32_t opcode, \
2614 ppc_vsr_t *xt, ppc_vsr_t *xb) \
2615 { \
2616 ppc_vsr_t t = *xt; \
2617 int i; \
2618 \
2619 for (i = 0; i < nels; i++) { \
2620 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2621 if (unlikely(stp##_is_signaling_nan(xb->sfld, \
2622 &env->fp_status))) { \
2623 float_invalid_op_vxsnan(env, GETPC()); \
2624 t.tfld = ttp##_snan_to_qnan(t.tfld); \
2625 } \
2626 if (sfprf) { \
2627 helper_compute_fprf_##ttp(env, t.tfld); \
2628 } \
2629 } \
2630 \
2631 *xt = t; \
2632 do_float_check_status(env, GETPC()); \
2633 }
2634
2635 VSX_CVT_FP_TO_FP_VECTOR(xscvdpqp, 1, float64, float128, VsrD(0), f128, 1)
2636
2637 /*
2638 * VSX_CVT_FP_TO_FP_HP - VSX floating point/floating point conversion
2639 * involving one half precision value
2640 * op - instruction mnemonic
2641 * nels - number of elements (1, 2 or 4)
2642 * stp - source type
2643 * ttp - target type
2644 * sfld - source vsr_t field
2645 * tfld - target vsr_t field
2646 * sfprf - set FPRF
2647 */
2648 #define VSX_CVT_FP_TO_FP_HP(op, nels, stp, ttp, sfld, tfld, sfprf) \
2649 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2650 { \
2651 ppc_vsr_t t = { }; \
2652 int i; \
2653 \
2654 for (i = 0; i < nels; i++) { \
2655 t.tfld = stp##_to_##ttp(xb->sfld, 1, &env->fp_status); \
2656 if (unlikely(stp##_is_signaling_nan(xb->sfld, \
2657 &env->fp_status))) { \
2658 float_invalid_op_vxsnan(env, GETPC()); \
2659 t.tfld = ttp##_snan_to_qnan(t.tfld); \
2660 } \
2661 if (sfprf) { \
2662 helper_compute_fprf_##ttp(env, t.tfld); \
2663 } \
2664 } \
2665 \
2666 *xt = t; \
2667 do_float_check_status(env, GETPC()); \
2668 }
2669
2670 VSX_CVT_FP_TO_FP_HP(xscvdphp, 1, float64, float16, VsrD(0), VsrH(3), 1)
2671 VSX_CVT_FP_TO_FP_HP(xscvhpdp, 1, float16, float64, VsrH(3), VsrD(0), 1)
2672 VSX_CVT_FP_TO_FP_HP(xvcvsphp, 4, float32, float16, VsrW(i), VsrH(2 * i + 1), 0)
2673 VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i), 0)
2674
2675 /*
2676 * xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be
2677 * added to this later.
2678 */
2679 void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode,
2680 ppc_vsr_t *xt, ppc_vsr_t *xb)
2681 {
2682 ppc_vsr_t t = { };
2683 float_status tstat;
2684
2685 tstat = env->fp_status;
2686 if (unlikely(Rc(opcode) != 0)) {
2687 tstat.float_rounding_mode = float_round_to_odd;
2688 }
2689
2690 t.VsrD(0) = float128_to_float64(xb->f128, &tstat);
2691 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
2692 if (unlikely(float128_is_signaling_nan(xb->f128, &tstat))) {
2693 float_invalid_op_vxsnan(env, GETPC());
2694 t.VsrD(0) = float64_snan_to_qnan(t.VsrD(0));
2695 }
2696 helper_compute_fprf_float64(env, t.VsrD(0));
2697
2698 *xt = t;
2699 do_float_check_status(env, GETPC());
2700 }
2701
2702 uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
2703 {
2704 uint64_t result, sign, exp, frac;
2705
2706 float_status tstat = env->fp_status;
2707 set_float_exception_flags(0, &tstat);
2708
2709 sign = extract64(xb, 63, 1);
2710 exp = extract64(xb, 52, 11);
2711 frac = extract64(xb, 0, 52) | 0x10000000000000ULL;
2712
2713 if (unlikely(exp == 0 && extract64(frac, 0, 52) != 0)) {
2714 /* DP denormal operand. */
2715 /* Exponent override to DP min exp. */
2716 exp = 1;
2717 /* Implicit bit override to 0. */
2718 frac = deposit64(frac, 53, 1, 0);
2719 }
2720
2721 if (unlikely(exp < 897 && frac != 0)) {
2722 /* SP tiny operand. */
2723 if (897 - exp > 63) {
2724 frac = 0;
2725 } else {
2726 /* Denormalize until exp = SP min exp. */
2727 frac >>= (897 - exp);
2728 }
2729 /* Exponent override to SP min exp - 1. */
2730 exp = 896;
2731 }
2732
2733 result = sign << 31;
2734 result |= extract64(exp, 10, 1) << 30;
2735 result |= extract64(exp, 0, 7) << 23;
2736 result |= extract64(frac, 29, 23);
2737
2738 /* hardware replicates result to both words of the doubleword result. */
2739 return (result << 32) | result;
2740 }
2741
2742 uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t xb)
2743 {
2744 float_status tstat = env->fp_status;
2745 set_float_exception_flags(0, &tstat);
2746
2747 return float32_to_float64(xb >> 32, &tstat);
2748 }
2749
2750 /*
2751 * VSX_CVT_FP_TO_INT - VSX floating point to integer conversion
2752 * op - instruction mnemonic
2753 * nels - number of elements (1, 2 or 4)
2754 * stp - source type (float32 or float64)
2755 * ttp - target type (int32, uint32, int64 or uint64)
2756 * sfld - source vsr_t field
2757 * tfld - target vsr_t field
2758 * rnan - resulting NaN
2759 */
2760 #define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, rnan) \
2761 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2762 { \
2763 int all_flags = env->fp_status.float_exception_flags, flags; \
2764 ppc_vsr_t t = *xt; \
2765 int i; \
2766 \
2767 for (i = 0; i < nels; i++) { \
2768 env->fp_status.float_exception_flags = 0; \
2769 t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
2770 flags = env->fp_status.float_exception_flags; \
2771 if (unlikely(flags & float_flag_invalid)) { \
2772 t.tfld = float_invalid_cvt(env, flags, t.tfld, rnan, 0, GETPC());\
2773 } \
2774 all_flags |= flags; \
2775 } \
2776 \
2777 *xt = t; \
2778 env->fp_status.float_exception_flags = all_flags; \
2779 do_float_check_status(env, GETPC()); \
2780 }
2781
2782 VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, VsrD(0), VsrD(0), \
2783 0x8000000000000000ULL)
2784 VSX_CVT_FP_TO_INT(xscvdpsxws, 1, float64, int32, VsrD(0), VsrW(1), \
2785 0x80000000U)
2786 VSX_CVT_FP_TO_INT(xscvdpuxds, 1, float64, uint64, VsrD(0), VsrD(0), 0ULL)
2787 VSX_CVT_FP_TO_INT(xscvdpuxws, 1, float64, uint32, VsrD(0), VsrW(1), 0U)
2788 VSX_CVT_FP_TO_INT(xvcvdpsxds, 2, float64, int64, VsrD(i), VsrD(i), \
2789 0x8000000000000000ULL)
2790 VSX_CVT_FP_TO_INT(xvcvdpsxws, 2, float64, int32, VsrD(i), VsrW(2 * i), \
2791 0x80000000U)
2792 VSX_CVT_FP_TO_INT(xvcvdpuxds, 2, float64, uint64, VsrD(i), VsrD(i), 0ULL)
2793 VSX_CVT_FP_TO_INT(xvcvdpuxws, 2, float64, uint32, VsrD(i), VsrW(2 * i), 0U)
2794 VSX_CVT_FP_TO_INT(xvcvspsxds, 2, float32, int64, VsrW(2 * i), VsrD(i), \
2795 0x8000000000000000ULL)
2796 VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, VsrW(i), VsrW(i), 0x80000000U)
2797 VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2 * i), VsrD(i), 0ULL)
2798 VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
2799
2800 /*
2801 * VSX_CVT_FP_TO_INT_VECTOR - VSX floating point to integer conversion
2802 * op - instruction mnemonic
2803 * stp - source type (float32 or float64)
2804 * ttp - target type (int32, uint32, int64 or uint64)
2805 * sfld - source vsr_t field
2806 * tfld - target vsr_t field
2807 * rnan - resulting NaN
2808 */
2809 #define VSX_CVT_FP_TO_INT_VECTOR(op, stp, ttp, sfld, tfld, rnan) \
2810 void helper_##op(CPUPPCState *env, uint32_t opcode, \
2811 ppc_vsr_t *xt, ppc_vsr_t *xb) \
2812 { \
2813 ppc_vsr_t t = { }; \
2814 int flags; \
2815 \
2816 t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
2817 flags = get_float_exception_flags(&env->fp_status); \
2818 if (flags & float_flag_invalid) { \
2819 t.tfld = float_invalid_cvt(env, flags, t.tfld, rnan, 0, GETPC()); \
2820 } \
2821 \
2822 *xt = t; \
2823 do_float_check_status(env, GETPC()); \
2824 }
2825
2826 VSX_CVT_FP_TO_INT_VECTOR(xscvqpsdz, float128, int64, f128, VsrD(0), \
2827 0x8000000000000000ULL)
2828
2829 VSX_CVT_FP_TO_INT_VECTOR(xscvqpswz, float128, int32, f128, VsrD(0), \
2830 0xffffffff80000000ULL)
2831 VSX_CVT_FP_TO_INT_VECTOR(xscvqpudz, float128, uint64, f128, VsrD(0), 0x0ULL)
2832 VSX_CVT_FP_TO_INT_VECTOR(xscvqpuwz, float128, uint32, f128, VsrD(0), 0x0ULL)
2833
2834 /*
2835 * VSX_CVT_INT_TO_FP - VSX integer to floating point conversion
2836 * op - instruction mnemonic
2837 * nels - number of elements (1, 2 or 4)
2838 * stp - source type (int32, uint32, int64 or uint64)
2839 * ttp - target type (float32 or float64)
2840 * sfld - source vsr_t field
2841 * tfld - target vsr_t field
2842 * jdef - definition of the j index (i or 2*i)
2843 * sfprf - set FPRF
2844 */
2845 #define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf, r2sp) \
2846 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2847 { \
2848 ppc_vsr_t t = *xt; \
2849 int i; \
2850 \
2851 for (i = 0; i < nels; i++) { \
2852 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2853 if (r2sp) { \
2854 t.tfld = do_frsp(env, t.tfld, GETPC()); \
2855 } \
2856 if (sfprf) { \
2857 helper_compute_fprf_float64(env, t.tfld); \
2858 } \
2859 } \
2860 \
2861 *xt = t; \
2862 do_float_check_status(env, GETPC()); \
2863 }
2864
2865 VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, VsrD(0), VsrD(0), 1, 0)
2866 VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 0)
2867 VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, VsrD(0), VsrD(0), 1, 1)
2868 VSX_CVT_INT_TO_FP(xscvuxdsp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 1)
2869 VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, VsrD(i), VsrD(i), 0, 0)
2870 VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, VsrD(i), VsrD(i), 0, 0)
2871 VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, VsrW(2 * i), VsrD(i), 0, 0)
2872 VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, VsrW(2 * i), VsrD(i), 0, 0)
2873 VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, VsrD(i), VsrW(2 * i), 0, 0)
2874 VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, VsrD(i), VsrW(2 * i), 0, 0)
2875 VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, 0)
2876 VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, 0)
2877
2878 /*
2879 * VSX_CVT_INT_TO_FP_VECTOR - VSX integer to floating point conversion
2880 * op - instruction mnemonic
2881 * stp - source type (int32, uint32, int64 or uint64)
2882 * ttp - target type (float32 or float64)
2883 * sfld - source vsr_t field
2884 * tfld - target vsr_t field
2885 */
2886 #define VSX_CVT_INT_TO_FP_VECTOR(op, stp, ttp, sfld, tfld) \
2887 void helper_##op(CPUPPCState *env, uint32_t opcode, \
2888 ppc_vsr_t *xt, ppc_vsr_t *xb) \
2889 { \
2890 ppc_vsr_t t = *xt; \
2891 \
2892 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2893 helper_compute_fprf_##ttp(env, t.tfld); \
2894 \
2895 *xt = t; \
2896 do_float_check_status(env, GETPC()); \
2897 }
2898
2899 VSX_CVT_INT_TO_FP_VECTOR(xscvsdqp, int64, float128, VsrD(0), f128)
2900 VSX_CVT_INT_TO_FP_VECTOR(xscvudqp, uint64, float128, VsrD(0), f128)
2901
2902 /*
2903 * For "use current rounding mode", define a value that will not be
2904 * one of the existing rounding model enums.
2905 */
2906 #define FLOAT_ROUND_CURRENT (float_round_nearest_even + float_round_down + \
2907 float_round_up + float_round_to_zero)
2908
2909 /*
2910 * VSX_ROUND - VSX floating point round
2911 * op - instruction mnemonic
2912 * nels - number of elements (1, 2 or 4)
2913 * tp - type (float32 or float64)
2914 * fld - vsr_t field (VsrD(*) or VsrW(*))
2915 * rmode - rounding mode
2916 * sfprf - set FPRF
2917 */
2918 #define VSX_ROUND(op, nels, tp, fld, rmode, sfprf) \
2919 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2920 { \
2921 ppc_vsr_t t = *xt; \
2922 int i; \
2923 FloatRoundMode curr_rounding_mode; \
2924 \
2925 if (rmode != FLOAT_ROUND_CURRENT) { \
2926 curr_rounding_mode = get_float_rounding_mode(&env->fp_status); \
2927 set_float_rounding_mode(rmode, &env->fp_status); \
2928 } \
2929 \
2930 for (i = 0; i < nels; i++) { \
2931 if (unlikely(tp##_is_signaling_nan(xb->fld, \
2932 &env->fp_status))) { \
2933 float_invalid_op_vxsnan(env, GETPC()); \
2934 t.fld = tp##_snan_to_qnan(xb->fld); \
2935 } else { \
2936 t.fld = tp##_round_to_int(xb->fld, &env->fp_status); \
2937 } \
2938 if (sfprf) { \
2939 helper_compute_fprf_float64(env, t.fld); \
2940 } \
2941 } \
2942 \
2943 /* \
2944 * If this is not a "use current rounding mode" instruction, \
2945 * then inhibit setting of the XX bit and restore rounding \
2946 * mode from FPSCR \
2947 */ \
2948 if (rmode != FLOAT_ROUND_CURRENT) { \
2949 set_float_rounding_mode(curr_rounding_mode, &env->fp_status); \
2950 env->fp_status.float_exception_flags &= ~float_flag_inexact; \
2951 } \
2952 \
2953 *xt = t; \
2954 do_float_check_status(env, GETPC()); \
2955 }
2956
2957 VSX_ROUND(xsrdpi, 1, float64, VsrD(0), float_round_ties_away, 1)
2958 VSX_ROUND(xsrdpic, 1, float64, VsrD(0), FLOAT_ROUND_CURRENT, 1)
2959 VSX_ROUND(xsrdpim, 1, float64, VsrD(0), float_round_down, 1)
2960 VSX_ROUND(xsrdpip, 1, float64, VsrD(0), float_round_up, 1)
2961 VSX_ROUND(xsrdpiz, 1, float64, VsrD(0), float_round_to_zero, 1)
2962
2963 VSX_ROUND(xvrdpi, 2, float64, VsrD(i), float_round_ties_away, 0)
2964 VSX_ROUND(xvrdpic, 2, float64, VsrD(i), FLOAT_ROUND_CURRENT, 0)
2965 VSX_ROUND(xvrdpim, 2, float64, VsrD(i), float_round_down, 0)
2966 VSX_ROUND(xvrdpip, 2, float64, VsrD(i), float_round_up, 0)
2967 VSX_ROUND(xvrdpiz, 2, float64, VsrD(i), float_round_to_zero, 0)
2968
2969 VSX_ROUND(xvrspi, 4, float32, VsrW(i), float_round_ties_away, 0)
2970 VSX_ROUND(xvrspic, 4, float32, VsrW(i), FLOAT_ROUND_CURRENT, 0)
2971 VSX_ROUND(xvrspim, 4, float32, VsrW(i), float_round_down, 0)
2972 VSX_ROUND(xvrspip, 4, float32, VsrW(i), float_round_up, 0)
2973 VSX_ROUND(xvrspiz, 4, float32, VsrW(i), float_round_to_zero, 0)
2974
2975 uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
2976 {
2977 helper_reset_fpstatus(env);
2978
2979 uint64_t xt = do_frsp(env, xb, GETPC());
2980
2981 helper_compute_fprf_float64(env, xt);
2982 do_float_check_status(env, GETPC());
2983 return xt;
2984 }
2985
2986 #define VSX_XXPERM(op, indexed) \
2987 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2988 ppc_vsr_t *xa, ppc_vsr_t *pcv) \
2989 { \
2990 ppc_vsr_t t = *xt; \
2991 int i, idx; \
2992 \
2993 for (i = 0; i < 16; i++) { \
2994 idx = pcv->VsrB(i) & 0x1F; \
2995 if (indexed) { \
2996 idx = 31 - idx; \
2997 } \
2998 t.VsrB(i) = (idx <= 15) ? xa->VsrB(idx) \
2999 : xt->VsrB(idx - 16); \
3000 } \
3001 *xt = t; \
3002 }
3003
3004 VSX_XXPERM(xxperm, 0)
3005 VSX_XXPERM(xxpermr, 1)
3006
3007 void helper_xvxsigsp(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb)
3008 {
3009 ppc_vsr_t t = { };
3010 uint32_t exp, i, fraction;
3011
3012 for (i = 0; i < 4; i++) {
3013 exp = (xb->VsrW(i) >> 23) & 0xFF;
3014 fraction = xb->VsrW(i) & 0x7FFFFF;
3015 if (exp != 0 && exp != 255) {
3016 t.VsrW(i) = fraction | 0x00800000;
3017 } else {
3018 t.VsrW(i) = fraction;
3019 }
3020 }
3021 *xt = t;
3022 }
3023
3024 /*
3025 * VSX_TEST_DC - VSX floating point test data class
3026 * op - instruction mnemonic
3027 * nels - number of elements (1, 2 or 4)
3028 * xbn - VSR register number
3029 * tp - type (float32 or float64)
3030 * fld - vsr_t field (VsrD(*) or VsrW(*))
3031 * tfld - target vsr_t field (VsrD(*) or VsrW(*))
3032 * fld_max - target field max
3033 * scrf - set result in CR and FPCC
3034 */
3035 #define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max, scrf) \
3036 void helper_##op(CPUPPCState *env, uint32_t opcode) \
3037 { \
3038 ppc_vsr_t *xt = &env->vsr[xT(opcode)]; \
3039 ppc_vsr_t *xb = &env->vsr[xbn]; \
3040 ppc_vsr_t t = { }; \
3041 uint32_t i, sign, dcmx; \
3042 uint32_t cc, match = 0; \
3043 \
3044 if (!scrf) { \
3045 dcmx = DCMX_XV(opcode); \
3046 } else { \
3047 t = *xt; \
3048 dcmx = DCMX(opcode); \
3049 } \
3050 \
3051 for (i = 0; i < nels; i++) { \
3052 sign = tp##_is_neg(xb->fld); \
3053 if (tp##_is_any_nan(xb->fld)) { \
3054 match = extract32(dcmx, 6, 1); \
3055 } else if (tp##_is_infinity(xb->fld)) { \
3056 match = extract32(dcmx, 4 + !sign, 1); \
3057 } else if (tp##_is_zero(xb->fld)) { \
3058 match = extract32(dcmx, 2 + !sign, 1); \
3059 } else if (tp##_is_zero_or_denormal(xb->fld)) { \
3060 match = extract32(dcmx, 0 + !sign, 1); \
3061 } \
3062 \
3063 if (scrf) { \
3064 cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT; \
3065 env->fpscr &= ~FP_FPCC; \
3066 env->fpscr |= cc << FPSCR_FPCC; \
3067 env->crf[BF(opcode)] = cc; \
3068 } else { \
3069 t.tfld = match ? fld_max : 0; \
3070 } \
3071 match = 0; \
3072 } \
3073 if (!scrf) { \
3074 *xt = t; \
3075 } \
3076 }
3077
3078 VSX_TEST_DC(xvtstdcdp, 2, xB(opcode), float64, VsrD(i), VsrD(i), UINT64_MAX, 0)
3079 VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MAX, 0)
3080 VSX_TEST_DC(xststdcdp, 1, xB(opcode), float64, VsrD(0), VsrD(0), 0, 1)
3081 VSX_TEST_DC(xststdcqp, 1, (rB(opcode) + 32), float128, f128, VsrD(0), 0, 1)
3082
3083 void helper_xststdcsp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb)
3084 {
3085 uint32_t dcmx, sign, exp;
3086 uint32_t cc, match = 0, not_sp = 0;
3087
3088 dcmx = DCMX(opcode);
3089 exp = (xb->VsrD(0) >> 52) & 0x7FF;
3090
3091 sign = float64_is_neg(xb->VsrD(0));
3092 if (float64_is_any_nan(xb->VsrD(0))) {
3093 match = extract32(dcmx, 6, 1);
3094 } else if (float64_is_infinity(xb->VsrD(0))) {
3095 match = extract32(dcmx, 4 + !sign, 1);
3096 } else if (float64_is_zero(xb->VsrD(0))) {
3097 match = extract32(dcmx, 2 + !sign, 1);
3098 } else if (float64_is_zero_or_denormal(xb->VsrD(0)) ||
3099 (exp > 0 && exp < 0x381)) {
3100 match = extract32(dcmx, 0 + !sign, 1);
3101 }
3102
3103 not_sp = !float64_eq(xb->VsrD(0),
3104 float32_to_float64(
3105 float64_to_float32(xb->VsrD(0), &env->fp_status),
3106 &env->fp_status), &env->fp_status);
3107
3108 cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT | not_sp << CRF_SO_BIT;
3109 env->fpscr &= ~FP_FPCC;
3110 env->fpscr |= cc << FPSCR_FPCC;
3111 env->crf[BF(opcode)] = cc;
3112 }
3113
3114 void helper_xsrqpi(CPUPPCState *env, uint32_t opcode,
3115 ppc_vsr_t *xt, ppc_vsr_t *xb)
3116 {
3117 ppc_vsr_t t = { };
3118 uint8_t r = Rrm(opcode);
3119 uint8_t ex = Rc(opcode);
3120 uint8_t rmc = RMC(opcode);
3121 uint8_t rmode = 0;
3122 float_status tstat;
3123
3124 helper_reset_fpstatus(env);
3125
3126 if (r == 0 && rmc == 0) {
3127 rmode = float_round_ties_away;
3128 } else if (r == 0 && rmc == 0x3) {
3129 rmode = fpscr_rn;
3130 } else if (r == 1) {
3131 switch (rmc) {
3132 case 0:
3133 rmode = float_round_nearest_even;
3134 break;
3135 case 1:
3136 rmode = float_round_to_zero;
3137 break;
3138 case 2:
3139 rmode = float_round_up;
3140 break;
3141 case 3:
3142 rmode = float_round_down;
3143 break;
3144 default:
3145 abort();
3146 }
3147 }
3148
3149 tstat = env->fp_status;
3150 set_float_exception_flags(0, &tstat);
3151 set_float_rounding_mode(rmode, &tstat);
3152 t.f128 = float128_round_to_int(xb->f128, &tstat);
3153 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3154
3155 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3156 if (float128_is_signaling_nan(xb->f128, &tstat)) {
3157 float_invalid_op_vxsnan(env, GETPC());
3158 t.f128 = float128_snan_to_qnan(t.f128);
3159 }
3160 }
3161
3162 if (ex == 0 && (tstat.float_exception_flags & float_flag_inexact)) {
3163 env->fp_status.float_exception_flags &= ~float_flag_inexact;
3164 }
3165
3166 helper_compute_fprf_float128(env, t.f128);
3167 do_float_check_status(env, GETPC());
3168 *xt = t;
3169 }
3170
3171 void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode,
3172 ppc_vsr_t *xt, ppc_vsr_t *xb)
3173 {
3174 ppc_vsr_t t = { };
3175 uint8_t r = Rrm(opcode);
3176 uint8_t rmc = RMC(opcode);
3177 uint8_t rmode = 0;
3178 floatx80 round_res;
3179 float_status tstat;
3180
3181 helper_reset_fpstatus(env);
3182
3183 if (r == 0 && rmc == 0) {
3184 rmode = float_round_ties_away;
3185 } else if (r == 0 && rmc == 0x3) {
3186 rmode = fpscr_rn;
3187 } else if (r == 1) {
3188 switch (rmc) {
3189 case 0:
3190 rmode = float_round_nearest_even;
3191 break;
3192 case 1:
3193 rmode = float_round_to_zero;
3194 break;
3195 case 2:
3196 rmode = float_round_up;
3197 break;
3198 case 3:
3199 rmode = float_round_down;
3200 break;
3201 default:
3202 abort();
3203 }
3204 }
3205
3206 tstat = env->fp_status;
3207 set_float_exception_flags(0, &tstat);
3208 set_float_rounding_mode(rmode, &tstat);
3209 round_res = float128_to_floatx80(xb->f128, &tstat);
3210 t.f128 = floatx80_to_float128(round_res, &tstat);
3211 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3212
3213 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3214 if (float128_is_signaling_nan(xb->f128, &tstat)) {
3215 float_invalid_op_vxsnan(env, GETPC());
3216 t.f128 = float128_snan_to_qnan(t.f128);
3217 }
3218 }
3219
3220 helper_compute_fprf_float128(env, t.f128);
3221 *xt = t;
3222 do_float_check_status(env, GETPC());
3223 }
3224
3225 void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode,
3226 ppc_vsr_t *xt, ppc_vsr_t *xb)
3227 {
3228 ppc_vsr_t t = { };
3229 float_status tstat;
3230
3231 helper_reset_fpstatus(env);
3232
3233 tstat = env->fp_status;
3234 if (unlikely(Rc(opcode) != 0)) {
3235 tstat.float_rounding_mode = float_round_to_odd;
3236 }
3237
3238 set_float_exception_flags(0, &tstat);
3239 t.f128 = float128_sqrt(xb->f128, &tstat);
3240 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3241
3242 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3243 if (float128_is_signaling_nan(xb->f128, &tstat)) {
3244 float_invalid_op_vxsnan(env, GETPC());
3245 t.f128 = float128_snan_to_qnan(xb->f128);
3246 } else if (float128_is_quiet_nan(xb->f128, &tstat)) {
3247 t.f128 = xb->f128;
3248 } else if (float128_is_neg(xb->f128) && !float128_is_zero(xb->f128)) {
3249 float_invalid_op_vxsqrt(env, 1, GETPC());
3250 t.f128 = float128_default_nan(&env->fp_status);
3251 }
3252 }
3253
3254 helper_compute_fprf_float128(env, t.f128);
3255 *xt = t;
3256 do_float_check_status(env, GETPC());
3257 }
3258
3259 void helper_xssubqp(CPUPPCState *env, uint32_t opcode,
3260 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
3261 {
3262 ppc_vsr_t t = *xt;
3263 float_status tstat;
3264
3265 helper_reset_fpstatus(env);
3266
3267 tstat = env->fp_status;
3268 if (unlikely(Rc(opcode) != 0)) {
3269 tstat.float_rounding_mode = float_round_to_odd;
3270 }
3271
3272 set_float_exception_flags(0, &tstat);
3273 t.f128 = float128_sub(xa->f128, xb->f128, &tstat);
3274 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3275
3276 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3277 float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC());
3278 }
3279
3280 helper_compute_fprf_float128(env, t.f128);
3281 *xt = t;
3282 do_float_check_status(env, GETPC());
3283 }
QEmu