2 * QEMU PowerPC 405 embedded processors emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
30 #include "hw/ppc/ppc.h"
31 #include "hw/i2c/ppc4xx_i2c.h"
33 #include "hw/qdev-properties.h"
35 #include "hw/char/serial.h"
36 #include "qemu/timer.h"
37 #include "sysemu/reset.h"
38 #include "sysemu/sysemu.h"
39 #include "exec/address-spaces.h"
40 #include "hw/intc/ppc-uic.h"
41 #include "hw/qdev-properties.h"
42 #include "qapi/error.h"
45 /*****************************************************************************/
46 /* Shared peripherals */
48 /*****************************************************************************/
49 /* PLB to OPB bridge */
56 static uint32_t dcr_read_pob(void *opaque
, int dcrn
)
58 Ppc405PobState
*pob
= opaque
;
72 /* Avoid gcc warning */
80 static void dcr_write_pob(void *opaque
, int dcrn
, uint32_t val
)
82 Ppc405PobState
*pob
= opaque
;
99 static void ppc405_pob_reset(DeviceState
*dev
)
101 Ppc405PobState
*pob
= PPC405_POB(dev
);
104 pob
->bear
= 0x00000000;
105 pob
->besr0
= 0x0000000;
106 pob
->besr1
= 0x0000000;
109 static void ppc405_pob_realize(DeviceState
*dev
, Error
**errp
)
111 Ppc405PobState
*pob
= PPC405_POB(dev
);
112 Ppc4xxDcrDeviceState
*dcr
= PPC4xx_DCR_DEVICE(dev
);
114 ppc4xx_dcr_register(dcr
, POB0_BEAR
, pob
, &dcr_read_pob
, &dcr_write_pob
);
115 ppc4xx_dcr_register(dcr
, POB0_BESR0
, pob
, &dcr_read_pob
, &dcr_write_pob
);
116 ppc4xx_dcr_register(dcr
, POB0_BESR1
, pob
, &dcr_read_pob
, &dcr_write_pob
);
119 static void ppc405_pob_class_init(ObjectClass
*oc
, void *data
)
121 DeviceClass
*dc
= DEVICE_CLASS(oc
);
123 dc
->realize
= ppc405_pob_realize
;
124 dc
->reset
= ppc405_pob_reset
;
125 /* Reason: only works as function of a ppc4xx SoC */
126 dc
->user_creatable
= false;
129 /*****************************************************************************/
131 static uint64_t opba_readb(void *opaque
, hwaddr addr
, unsigned size
)
133 Ppc405OpbaState
*opba
= opaque
;
148 trace_opba_readb(addr
, ret
);
152 static void opba_writeb(void *opaque
, hwaddr addr
, uint64_t value
,
155 Ppc405OpbaState
*opba
= opaque
;
157 trace_opba_writeb(addr
, value
);
161 opba
->cr
= value
& 0xF8;
164 opba
->pr
= value
& 0xFF;
170 static const MemoryRegionOps opba_ops
= {
172 .write
= opba_writeb
,
173 .impl
.min_access_size
= 1,
174 .impl
.max_access_size
= 1,
175 .valid
.min_access_size
= 1,
176 .valid
.max_access_size
= 4,
177 .endianness
= DEVICE_BIG_ENDIAN
,
180 static void ppc405_opba_reset(DeviceState
*dev
)
182 Ppc405OpbaState
*opba
= PPC405_OPBA(dev
);
184 opba
->cr
= 0x00; /* No dynamic priorities - park disabled */
188 static void ppc405_opba_realize(DeviceState
*dev
, Error
**errp
)
190 Ppc405OpbaState
*s
= PPC405_OPBA(dev
);
192 memory_region_init_io(&s
->io
, OBJECT(s
), &opba_ops
, s
, "opba", 2);
193 sysbus_init_mmio(SYS_BUS_DEVICE(s
), &s
->io
);
196 static void ppc405_opba_class_init(ObjectClass
*oc
, void *data
)
198 DeviceClass
*dc
= DEVICE_CLASS(oc
);
200 dc
->realize
= ppc405_opba_realize
;
201 dc
->reset
= ppc405_opba_reset
;
202 /* Reason: only works as function of a ppc4xx SoC */
203 dc
->user_creatable
= false;
206 /*****************************************************************************/
207 /* Code decompression controller */
210 /*****************************************************************************/
239 static uint32_t dcr_read_dma(void *opaque
, int dcrn
)
244 static void dcr_write_dma(void *opaque
, int dcrn
, uint32_t val
)
248 static void ppc405_dma_reset(DeviceState
*dev
)
250 Ppc405DmaState
*dma
= PPC405_DMA(dev
);
253 for (i
= 0; i
< 4; i
++) {
254 dma
->cr
[i
] = 0x00000000;
255 dma
->ct
[i
] = 0x00000000;
256 dma
->da
[i
] = 0x00000000;
257 dma
->sa
[i
] = 0x00000000;
258 dma
->sg
[i
] = 0x00000000;
260 dma
->sr
= 0x00000000;
261 dma
->sgc
= 0x00000000;
262 dma
->slp
= 0x7C000000;
263 dma
->pol
= 0x00000000;
266 static void ppc405_dma_realize(DeviceState
*dev
, Error
**errp
)
268 Ppc405DmaState
*dma
= PPC405_DMA(dev
);
269 Ppc4xxDcrDeviceState
*dcr
= PPC4xx_DCR_DEVICE(dev
);
272 for (i
= 0; i
< ARRAY_SIZE(dma
->irqs
); i
++) {
273 sysbus_init_irq(SYS_BUS_DEVICE(dma
), &dma
->irqs
[i
]);
276 ppc4xx_dcr_register(dcr
, DMA0_CR0
, dma
, &dcr_read_dma
, &dcr_write_dma
);
277 ppc4xx_dcr_register(dcr
, DMA0_CT0
, dma
, &dcr_read_dma
, &dcr_write_dma
);
278 ppc4xx_dcr_register(dcr
, DMA0_DA0
, dma
, &dcr_read_dma
, &dcr_write_dma
);
279 ppc4xx_dcr_register(dcr
, DMA0_SA0
, dma
, &dcr_read_dma
, &dcr_write_dma
);
280 ppc4xx_dcr_register(dcr
, DMA0_SG0
, dma
, &dcr_read_dma
, &dcr_write_dma
);
281 ppc4xx_dcr_register(dcr
, DMA0_CR1
, dma
, &dcr_read_dma
, &dcr_write_dma
);
282 ppc4xx_dcr_register(dcr
, DMA0_CT1
, dma
, &dcr_read_dma
, &dcr_write_dma
);
283 ppc4xx_dcr_register(dcr
, DMA0_DA1
, dma
, &dcr_read_dma
, &dcr_write_dma
);
284 ppc4xx_dcr_register(dcr
, DMA0_SA1
, dma
, &dcr_read_dma
, &dcr_write_dma
);
285 ppc4xx_dcr_register(dcr
, DMA0_SG1
, dma
, &dcr_read_dma
, &dcr_write_dma
);
286 ppc4xx_dcr_register(dcr
, DMA0_CR2
, dma
, &dcr_read_dma
, &dcr_write_dma
);
287 ppc4xx_dcr_register(dcr
, DMA0_CT2
, dma
, &dcr_read_dma
, &dcr_write_dma
);
288 ppc4xx_dcr_register(dcr
, DMA0_DA2
, dma
, &dcr_read_dma
, &dcr_write_dma
);
289 ppc4xx_dcr_register(dcr
, DMA0_SA2
, dma
, &dcr_read_dma
, &dcr_write_dma
);
290 ppc4xx_dcr_register(dcr
, DMA0_SG2
, dma
, &dcr_read_dma
, &dcr_write_dma
);
291 ppc4xx_dcr_register(dcr
, DMA0_CR3
, dma
, &dcr_read_dma
, &dcr_write_dma
);
292 ppc4xx_dcr_register(dcr
, DMA0_CT3
, dma
, &dcr_read_dma
, &dcr_write_dma
);
293 ppc4xx_dcr_register(dcr
, DMA0_DA3
, dma
, &dcr_read_dma
, &dcr_write_dma
);
294 ppc4xx_dcr_register(dcr
, DMA0_SA3
, dma
, &dcr_read_dma
, &dcr_write_dma
);
295 ppc4xx_dcr_register(dcr
, DMA0_SG3
, dma
, &dcr_read_dma
, &dcr_write_dma
);
296 ppc4xx_dcr_register(dcr
, DMA0_SR
, dma
, &dcr_read_dma
, &dcr_write_dma
);
297 ppc4xx_dcr_register(dcr
, DMA0_SGC
, dma
, &dcr_read_dma
, &dcr_write_dma
);
298 ppc4xx_dcr_register(dcr
, DMA0_SLP
, dma
, &dcr_read_dma
, &dcr_write_dma
);
299 ppc4xx_dcr_register(dcr
, DMA0_POL
, dma
, &dcr_read_dma
, &dcr_write_dma
);
302 static void ppc405_dma_class_init(ObjectClass
*oc
, void *data
)
304 DeviceClass
*dc
= DEVICE_CLASS(oc
);
306 dc
->realize
= ppc405_dma_realize
;
307 dc
->reset
= ppc405_dma_reset
;
308 /* Reason: only works as function of a ppc4xx SoC */
309 dc
->user_creatable
= false;
312 /*****************************************************************************/
314 static uint64_t ppc405_gpio_read(void *opaque
, hwaddr addr
, unsigned size
)
316 trace_ppc405_gpio_read(addr
, size
);
320 static void ppc405_gpio_write(void *opaque
, hwaddr addr
, uint64_t value
,
323 trace_ppc405_gpio_write(addr
, size
, value
);
326 static const MemoryRegionOps ppc405_gpio_ops
= {
327 .read
= ppc405_gpio_read
,
328 .write
= ppc405_gpio_write
,
329 .endianness
= DEVICE_NATIVE_ENDIAN
,
332 static void ppc405_gpio_realize(DeviceState
*dev
, Error
**errp
)
334 Ppc405GpioState
*s
= PPC405_GPIO(dev
);
336 memory_region_init_io(&s
->io
, OBJECT(s
), &ppc405_gpio_ops
, s
, "gpio",
338 sysbus_init_mmio(SYS_BUS_DEVICE(s
), &s
->io
);
341 static void ppc405_gpio_class_init(ObjectClass
*oc
, void *data
)
343 DeviceClass
*dc
= DEVICE_CLASS(oc
);
345 dc
->realize
= ppc405_gpio_realize
;
346 /* Reason: only works as function of a ppc4xx SoC */
347 dc
->user_creatable
= false;
350 /*****************************************************************************/
354 OCM0_ISACNTL
= 0x019,
356 OCM0_DSACNTL
= 0x01B,
359 static void ocm_update_mappings(Ppc405OcmState
*ocm
,
360 uint32_t isarc
, uint32_t isacntl
,
361 uint32_t dsarc
, uint32_t dsacntl
)
363 trace_ocm_update_mappings(isarc
, isacntl
, dsarc
, dsacntl
, ocm
->isarc
,
364 ocm
->isacntl
, ocm
->dsarc
, ocm
->dsacntl
);
366 if (ocm
->isarc
!= isarc
||
367 (ocm
->isacntl
& 0x80000000) != (isacntl
& 0x80000000)) {
368 if (ocm
->isacntl
& 0x80000000) {
369 /* Unmap previously assigned memory region */
370 trace_ocm_unmap("ISA", ocm
->isarc
);
371 memory_region_del_subregion(get_system_memory(), &ocm
->isarc_ram
);
373 if (isacntl
& 0x80000000) {
374 /* Map new instruction memory region */
375 trace_ocm_map("ISA", isarc
);
376 memory_region_add_subregion(get_system_memory(), isarc
,
380 if (ocm
->dsarc
!= dsarc
||
381 (ocm
->dsacntl
& 0x80000000) != (dsacntl
& 0x80000000)) {
382 if (ocm
->dsacntl
& 0x80000000) {
383 /* Beware not to unmap the region we just mapped */
384 if (!(isacntl
& 0x80000000) || ocm
->dsarc
!= isarc
) {
385 /* Unmap previously assigned memory region */
386 trace_ocm_unmap("DSA", ocm
->dsarc
);
387 memory_region_del_subregion(get_system_memory(),
391 if (dsacntl
& 0x80000000) {
392 /* Beware not to remap the region we just mapped */
393 if (!(isacntl
& 0x80000000) || dsarc
!= isarc
) {
394 /* Map new data memory region */
395 trace_ocm_map("DSA", dsarc
);
396 memory_region_add_subregion(get_system_memory(), dsarc
,
403 static uint32_t dcr_read_ocm(void *opaque
, int dcrn
)
405 Ppc405OcmState
*ocm
= opaque
;
429 static void dcr_write_ocm(void *opaque
, int dcrn
, uint32_t val
)
431 Ppc405OcmState
*ocm
= opaque
;
432 uint32_t isarc
, dsarc
, isacntl
, dsacntl
;
436 isacntl
= ocm
->isacntl
;
437 dsacntl
= ocm
->dsacntl
;
440 isarc
= val
& 0xFC000000;
443 isacntl
= val
& 0xC0000000;
446 isarc
= val
& 0xFC000000;
449 isacntl
= val
& 0xC0000000;
452 ocm_update_mappings(ocm
, isarc
, isacntl
, dsarc
, dsacntl
);
455 ocm
->isacntl
= isacntl
;
456 ocm
->dsacntl
= dsacntl
;
459 static void ppc405_ocm_reset(DeviceState
*dev
)
461 Ppc405OcmState
*ocm
= PPC405_OCM(dev
);
462 uint32_t isarc
, dsarc
, isacntl
, dsacntl
;
465 isacntl
= 0x00000000;
467 dsacntl
= 0x00000000;
468 ocm_update_mappings(ocm
, isarc
, isacntl
, dsarc
, dsacntl
);
471 ocm
->isacntl
= isacntl
;
472 ocm
->dsacntl
= dsacntl
;
475 static void ppc405_ocm_realize(DeviceState
*dev
, Error
**errp
)
477 Ppc405OcmState
*ocm
= PPC405_OCM(dev
);
478 Ppc4xxDcrDeviceState
*dcr
= PPC4xx_DCR_DEVICE(dev
);
480 /* XXX: Size is 4096 or 0x04000000 */
481 memory_region_init_ram(&ocm
->isarc_ram
, OBJECT(ocm
), "ppc405.ocm", 4 * KiB
,
483 memory_region_init_alias(&ocm
->dsarc_ram
, OBJECT(ocm
), "ppc405.dsarc",
484 &ocm
->isarc_ram
, 0, 4 * KiB
);
486 ppc4xx_dcr_register(dcr
, OCM0_ISARC
, ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
487 ppc4xx_dcr_register(dcr
, OCM0_ISACNTL
, ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
488 ppc4xx_dcr_register(dcr
, OCM0_DSARC
, ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
489 ppc4xx_dcr_register(dcr
, OCM0_DSACNTL
, ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
492 static void ppc405_ocm_class_init(ObjectClass
*oc
, void *data
)
494 DeviceClass
*dc
= DEVICE_CLASS(oc
);
496 dc
->realize
= ppc405_ocm_realize
;
497 dc
->reset
= ppc405_ocm_reset
;
498 /* Reason: only works as function of a ppc4xx SoC */
499 dc
->user_creatable
= false;
502 /*****************************************************************************/
503 /* General purpose timers */
504 static int ppc4xx_gpt_compare(Ppc405GptState
*gpt
, int n
)
510 static void ppc4xx_gpt_set_output(Ppc405GptState
*gpt
, int n
, int level
)
515 static void ppc4xx_gpt_set_outputs(Ppc405GptState
*gpt
)
521 for (i
= 0; i
< 5; i
++) {
522 if (gpt
->oe
& mask
) {
523 /* Output is enabled */
524 if (ppc4xx_gpt_compare(gpt
, i
)) {
525 /* Comparison is OK */
526 ppc4xx_gpt_set_output(gpt
, i
, gpt
->ol
& mask
);
528 /* Comparison is KO */
529 ppc4xx_gpt_set_output(gpt
, i
, gpt
->ol
& mask
? 0 : 1);
536 static void ppc4xx_gpt_set_irqs(Ppc405GptState
*gpt
)
542 for (i
= 0; i
< 5; i
++) {
543 if (gpt
->is
& gpt
->im
& mask
) {
544 qemu_irq_raise(gpt
->irqs
[i
]);
546 qemu_irq_lower(gpt
->irqs
[i
]);
552 static void ppc4xx_gpt_compute_timer(Ppc405GptState
*gpt
)
557 static uint64_t ppc4xx_gpt_read(void *opaque
, hwaddr addr
, unsigned size
)
559 Ppc405GptState
*gpt
= opaque
;
563 trace_ppc4xx_gpt_read(addr
, size
);
567 /* Time base counter */
568 ret
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + gpt
->tb_offset
,
569 gpt
->tb_freq
, NANOSECONDS_PER_SECOND
);
585 /* Interrupt status */
589 /* Interrupt enable */
594 idx
= (addr
- 0x80) >> 2;
595 ret
= gpt
->comp
[idx
];
599 idx
= (addr
- 0xC0) >> 2;
600 ret
= gpt
->mask
[idx
];
610 static void ppc4xx_gpt_write(void *opaque
, hwaddr addr
, uint64_t value
,
613 Ppc405GptState
*gpt
= opaque
;
616 trace_ppc4xx_gpt_write(addr
, size
, value
);
620 /* Time base counter */
621 gpt
->tb_offset
= muldiv64(value
, NANOSECONDS_PER_SECOND
, gpt
->tb_freq
)
622 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
623 ppc4xx_gpt_compute_timer(gpt
);
627 gpt
->oe
= value
& 0xF8000000;
628 ppc4xx_gpt_set_outputs(gpt
);
632 gpt
->ol
= value
& 0xF8000000;
633 ppc4xx_gpt_set_outputs(gpt
);
637 gpt
->im
= value
& 0x0000F800;
640 /* Interrupt status set */
641 gpt
->is
|= value
& 0x0000F800;
642 ppc4xx_gpt_set_irqs(gpt
);
645 /* Interrupt status clear */
646 gpt
->is
&= ~(value
& 0x0000F800);
647 ppc4xx_gpt_set_irqs(gpt
);
650 /* Interrupt enable */
651 gpt
->ie
= value
& 0x0000F800;
652 ppc4xx_gpt_set_irqs(gpt
);
656 idx
= (addr
- 0x80) >> 2;
657 gpt
->comp
[idx
] = value
& 0xF8000000;
658 ppc4xx_gpt_compute_timer(gpt
);
662 idx
= (addr
- 0xC0) >> 2;
663 gpt
->mask
[idx
] = value
& 0xF8000000;
664 ppc4xx_gpt_compute_timer(gpt
);
669 static const MemoryRegionOps gpt_ops
= {
670 .read
= ppc4xx_gpt_read
,
671 .write
= ppc4xx_gpt_write
,
672 .valid
.min_access_size
= 4,
673 .valid
.max_access_size
= 4,
674 .endianness
= DEVICE_NATIVE_ENDIAN
,
677 static void ppc4xx_gpt_cb(void *opaque
)
679 Ppc405GptState
*gpt
= opaque
;
681 ppc4xx_gpt_set_irqs(gpt
);
682 ppc4xx_gpt_set_outputs(gpt
);
683 ppc4xx_gpt_compute_timer(gpt
);
686 static void ppc405_gpt_reset(DeviceState
*dev
)
688 Ppc405GptState
*gpt
= PPC405_GPT(dev
);
691 timer_del(gpt
->timer
);
692 gpt
->oe
= 0x00000000;
693 gpt
->ol
= 0x00000000;
694 gpt
->im
= 0x00000000;
695 gpt
->is
= 0x00000000;
696 gpt
->ie
= 0x00000000;
697 for (i
= 0; i
< 5; i
++) {
698 gpt
->comp
[i
] = 0x00000000;
699 gpt
->mask
[i
] = 0x00000000;
703 static void ppc405_gpt_realize(DeviceState
*dev
, Error
**errp
)
705 Ppc405GptState
*s
= PPC405_GPT(dev
);
706 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
709 s
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, &ppc4xx_gpt_cb
, s
);
710 memory_region_init_io(&s
->iomem
, OBJECT(s
), &gpt_ops
, s
, "gpt", 0xd4);
711 sysbus_init_mmio(sbd
, &s
->iomem
);
713 for (i
= 0; i
< ARRAY_SIZE(s
->irqs
); i
++) {
714 sysbus_init_irq(sbd
, &s
->irqs
[i
]);
718 static void ppc405_gpt_finalize(Object
*obj
)
720 /* timer will be NULL if the GPT wasn't realized */
721 if (PPC405_GPT(obj
)->timer
) {
722 timer_del(PPC405_GPT(obj
)->timer
);
726 static void ppc405_gpt_class_init(ObjectClass
*oc
, void *data
)
728 DeviceClass
*dc
= DEVICE_CLASS(oc
);
730 dc
->realize
= ppc405_gpt_realize
;
731 dc
->reset
= ppc405_gpt_reset
;
732 /* Reason: only works as function of a ppc4xx SoC */
733 dc
->user_creatable
= false;
736 /*****************************************************************************/
740 PPC405EP_CPC0_PLLMR0
= 0x0F0,
741 PPC405EP_CPC0_BOOT
= 0x0F1,
742 PPC405EP_CPC0_EPCTL
= 0x0F3,
743 PPC405EP_CPC0_PLLMR1
= 0x0F4,
744 PPC405EP_CPC0_UCR
= 0x0F5,
745 PPC405EP_CPC0_SRR
= 0x0F6,
746 PPC405EP_CPC0_JTAGID
= 0x0F7,
747 PPC405EP_CPC0_PCI
= 0x0F9,
749 PPC405EP_CPC0_ER
= xxx
,
750 PPC405EP_CPC0_FR
= xxx
,
751 PPC405EP_CPC0_SR
= xxx
,
755 static void ppc405ep_compute_clocks(Ppc405CpcState
*cpc
)
757 uint32_t CPU_clk
, PLB_clk
, OPB_clk
, EBC_clk
, MAL_clk
, PCI_clk
;
758 uint32_t UART0_clk
, UART1_clk
;
759 uint64_t VCO_out
, PLL_out
;
763 if ((cpc
->pllmr
[1] & 0x80000000) && !(cpc
->pllmr
[1] & 0x40000000)) {
764 M
= (((cpc
->pllmr
[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
765 trace_ppc405ep_clocks_compute("FBMUL", (cpc
->pllmr
[1] >> 20) & 0xF, M
);
766 D
= 8 - ((cpc
->pllmr
[1] >> 16) & 0x7); /* FWDA */
767 trace_ppc405ep_clocks_compute("FWDA", (cpc
->pllmr
[1] >> 16) & 0x7, D
);
768 VCO_out
= (uint64_t)cpc
->sysclk
* M
* D
;
769 if (VCO_out
< 500000000UL || VCO_out
> 1000000000UL) {
770 /* Error - unlock the PLL */
771 qemu_log_mask(LOG_GUEST_ERROR
, "VCO out of range %" PRIu64
"\n",
774 cpc
->pllmr
[1] &= ~0x80000000;
778 PLL_out
= VCO_out
/ D
;
779 /* Pretend the PLL is locked */
780 cpc
->boot
|= 0x00000001;
785 PLL_out
= cpc
->sysclk
;
786 if (cpc
->pllmr
[1] & 0x40000000) {
787 /* Pretend the PLL is not locked */
788 cpc
->boot
&= ~0x00000001;
791 /* Now, compute all other clocks */
792 D
= ((cpc
->pllmr
[0] >> 20) & 0x3) + 1; /* CCDV */
793 trace_ppc405ep_clocks_compute("CCDV", (cpc
->pllmr
[0] >> 20) & 0x3, D
);
794 CPU_clk
= PLL_out
/ D
;
795 D
= ((cpc
->pllmr
[0] >> 16) & 0x3) + 1; /* CBDV */
796 trace_ppc405ep_clocks_compute("CBDV", (cpc
->pllmr
[0] >> 16) & 0x3, D
);
797 PLB_clk
= CPU_clk
/ D
;
798 D
= ((cpc
->pllmr
[0] >> 12) & 0x3) + 1; /* OPDV */
799 trace_ppc405ep_clocks_compute("OPDV", (cpc
->pllmr
[0] >> 12) & 0x3, D
);
800 OPB_clk
= PLB_clk
/ D
;
801 D
= ((cpc
->pllmr
[0] >> 8) & 0x3) + 2; /* EPDV */
802 trace_ppc405ep_clocks_compute("EPDV", (cpc
->pllmr
[0] >> 8) & 0x3, D
);
803 EBC_clk
= PLB_clk
/ D
;
804 D
= ((cpc
->pllmr
[0] >> 4) & 0x3) + 1; /* MPDV */
805 trace_ppc405ep_clocks_compute("MPDV", (cpc
->pllmr
[0] >> 4) & 0x3, D
);
806 MAL_clk
= PLB_clk
/ D
;
807 D
= (cpc
->pllmr
[0] & 0x3) + 1; /* PPDV */
808 trace_ppc405ep_clocks_compute("PPDV", cpc
->pllmr
[0] & 0x3, D
);
809 PCI_clk
= PLB_clk
/ D
;
810 D
= ((cpc
->ucr
- 1) & 0x7F) + 1; /* U0DIV */
811 trace_ppc405ep_clocks_compute("U0DIV", cpc
->ucr
& 0x7F, D
);
812 UART0_clk
= PLL_out
/ D
;
813 D
= (((cpc
->ucr
>> 8) - 1) & 0x7F) + 1; /* U1DIV */
814 trace_ppc405ep_clocks_compute("U1DIV", (cpc
->ucr
>> 8) & 0x7F, D
);
815 UART1_clk
= PLL_out
/ D
;
817 if (trace_event_get_state_backends(TRACE_PPC405EP_CLOCKS_SETUP
)) {
818 g_autofree
char *trace
= g_strdup_printf(
819 "Setup PPC405EP clocks - sysclk %" PRIu32
" VCO %" PRIu64
820 " PLL out %" PRIu64
" Hz\n"
821 "CPU %" PRIu32
" PLB %" PRIu32
" OPB %" PRIu32
" EBC %" PRIu32
822 " MAL %" PRIu32
" PCI %" PRIu32
" UART0 %" PRIu32
823 " UART1 %" PRIu32
"\n",
824 cpc
->sysclk
, VCO_out
, PLL_out
,
825 CPU_clk
, PLB_clk
, OPB_clk
, EBC_clk
, MAL_clk
, PCI_clk
,
826 UART0_clk
, UART1_clk
);
827 trace_ppc405ep_clocks_setup(trace
);
830 /* Setup CPU clocks */
831 clk_setup(&cpc
->clk_setup
[PPC405EP_CPU_CLK
], CPU_clk
);
832 /* Setup PLB clock */
833 clk_setup(&cpc
->clk_setup
[PPC405EP_PLB_CLK
], PLB_clk
);
834 /* Setup OPB clock */
835 clk_setup(&cpc
->clk_setup
[PPC405EP_OPB_CLK
], OPB_clk
);
836 /* Setup external clock */
837 clk_setup(&cpc
->clk_setup
[PPC405EP_EBC_CLK
], EBC_clk
);
838 /* Setup MAL clock */
839 clk_setup(&cpc
->clk_setup
[PPC405EP_MAL_CLK
], MAL_clk
);
840 /* Setup PCI clock */
841 clk_setup(&cpc
->clk_setup
[PPC405EP_PCI_CLK
], PCI_clk
);
842 /* Setup UART0 clock */
843 clk_setup(&cpc
->clk_setup
[PPC405EP_UART0_CLK
], UART0_clk
);
844 /* Setup UART1 clock */
845 clk_setup(&cpc
->clk_setup
[PPC405EP_UART1_CLK
], UART1_clk
);
848 static uint32_t dcr_read_epcpc(void *opaque
, int dcrn
)
850 Ppc405CpcState
*cpc
= opaque
;
854 case PPC405EP_CPC0_BOOT
:
857 case PPC405EP_CPC0_EPCTL
:
860 case PPC405EP_CPC0_PLLMR0
:
863 case PPC405EP_CPC0_PLLMR1
:
866 case PPC405EP_CPC0_UCR
:
869 case PPC405EP_CPC0_SRR
:
872 case PPC405EP_CPC0_JTAGID
:
875 case PPC405EP_CPC0_PCI
:
879 /* Avoid gcc warning */
887 static void dcr_write_epcpc(void *opaque
, int dcrn
, uint32_t val
)
889 Ppc405CpcState
*cpc
= opaque
;
892 case PPC405EP_CPC0_BOOT
:
893 /* Read-only register */
895 case PPC405EP_CPC0_EPCTL
:
896 /* Don't care for now */
897 cpc
->epctl
= val
& 0xC00000F3;
899 case PPC405EP_CPC0_PLLMR0
:
900 cpc
->pllmr
[0] = val
& 0x00633333;
901 ppc405ep_compute_clocks(cpc
);
903 case PPC405EP_CPC0_PLLMR1
:
904 cpc
->pllmr
[1] = val
& 0xC0F73FFF;
905 ppc405ep_compute_clocks(cpc
);
907 case PPC405EP_CPC0_UCR
:
908 /* UART control - don't care for now */
909 cpc
->ucr
= val
& 0x003F7F7F;
911 case PPC405EP_CPC0_SRR
:
914 case PPC405EP_CPC0_JTAGID
:
917 case PPC405EP_CPC0_PCI
:
923 static void ppc405_cpc_reset(DeviceState
*dev
)
925 Ppc405CpcState
*cpc
= PPC405_CPC(dev
);
927 cpc
->boot
= 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
928 cpc
->epctl
= 0x00000000;
929 cpc
->pllmr
[0] = 0x00021002;
930 cpc
->pllmr
[1] = 0x80a552be;
931 cpc
->ucr
= 0x00004646;
932 cpc
->srr
= 0x00040000;
933 cpc
->pci
= 0x00000000;
934 cpc
->er
= 0x00000000;
935 cpc
->fr
= 0x00000000;
936 cpc
->sr
= 0x00000000;
937 cpc
->jtagid
= 0x20267049;
938 ppc405ep_compute_clocks(cpc
);
941 /* XXX: sysclk should be between 25 and 100 MHz */
942 static void ppc405_cpc_realize(DeviceState
*dev
, Error
**errp
)
944 Ppc405CpcState
*cpc
= PPC405_CPC(dev
);
945 Ppc4xxDcrDeviceState
*dcr
= PPC4xx_DCR_DEVICE(dev
);
948 cpc
->clk_setup
[PPC405EP_CPU_CLK
].cb
=
949 ppc_40x_timers_init(&dcr
->cpu
->env
, cpc
->sysclk
, PPC_INTERRUPT_PIT
);
950 cpc
->clk_setup
[PPC405EP_CPU_CLK
].opaque
= &dcr
->cpu
->env
;
952 ppc4xx_dcr_register(dcr
, PPC405EP_CPC0_BOOT
, cpc
,
953 &dcr_read_epcpc
, &dcr_write_epcpc
);
954 ppc4xx_dcr_register(dcr
, PPC405EP_CPC0_EPCTL
, cpc
,
955 &dcr_read_epcpc
, &dcr_write_epcpc
);
956 ppc4xx_dcr_register(dcr
, PPC405EP_CPC0_PLLMR0
, cpc
,
957 &dcr_read_epcpc
, &dcr_write_epcpc
);
958 ppc4xx_dcr_register(dcr
, PPC405EP_CPC0_PLLMR1
, cpc
,
959 &dcr_read_epcpc
, &dcr_write_epcpc
);
960 ppc4xx_dcr_register(dcr
, PPC405EP_CPC0_UCR
, cpc
,
961 &dcr_read_epcpc
, &dcr_write_epcpc
);
962 ppc4xx_dcr_register(dcr
, PPC405EP_CPC0_SRR
, cpc
,
963 &dcr_read_epcpc
, &dcr_write_epcpc
);
964 ppc4xx_dcr_register(dcr
, PPC405EP_CPC0_JTAGID
, cpc
,
965 &dcr_read_epcpc
, &dcr_write_epcpc
);
966 ppc4xx_dcr_register(dcr
, PPC405EP_CPC0_PCI
, cpc
,
967 &dcr_read_epcpc
, &dcr_write_epcpc
);
970 static Property ppc405_cpc_properties
[] = {
971 DEFINE_PROP_UINT32("sys-clk", Ppc405CpcState
, sysclk
, 0),
972 DEFINE_PROP_END_OF_LIST(),
975 static void ppc405_cpc_class_init(ObjectClass
*oc
, void *data
)
977 DeviceClass
*dc
= DEVICE_CLASS(oc
);
979 dc
->realize
= ppc405_cpc_realize
;
980 dc
->reset
= ppc405_cpc_reset
;
981 /* Reason: only works as function of a ppc4xx SoC */
982 dc
->user_creatable
= false;
983 device_class_set_props(dc
, ppc405_cpc_properties
);
988 static void ppc405_soc_instance_init(Object
*obj
)
990 Ppc405SoCState
*s
= PPC405_SOC(obj
);
992 object_initialize_child(obj
, "cpu", &s
->cpu
,
993 POWERPC_CPU_TYPE_NAME("405ep"));
995 object_initialize_child(obj
, "uic", &s
->uic
, TYPE_PPC_UIC
);
997 object_initialize_child(obj
, "cpc", &s
->cpc
, TYPE_PPC405_CPC
);
998 object_property_add_alias(obj
, "sys-clk", OBJECT(&s
->cpc
), "sys-clk");
1000 object_initialize_child(obj
, "gpt", &s
->gpt
, TYPE_PPC405_GPT
);
1002 object_initialize_child(obj
, "ocm", &s
->ocm
, TYPE_PPC405_OCM
);
1004 object_initialize_child(obj
, "gpio", &s
->gpio
, TYPE_PPC405_GPIO
);
1006 object_initialize_child(obj
, "dma", &s
->dma
, TYPE_PPC405_DMA
);
1008 object_initialize_child(obj
, "i2c", &s
->i2c
, TYPE_PPC4xx_I2C
);
1010 object_initialize_child(obj
, "ebc", &s
->ebc
, TYPE_PPC4xx_EBC
);
1012 object_initialize_child(obj
, "opba", &s
->opba
, TYPE_PPC405_OPBA
);
1014 object_initialize_child(obj
, "pob", &s
->pob
, TYPE_PPC405_POB
);
1016 object_initialize_child(obj
, "plb", &s
->plb
, TYPE_PPC4xx_PLB
);
1018 object_initialize_child(obj
, "mal", &s
->mal
, TYPE_PPC4xx_MAL
);
1021 static void ppc405_reset(void *opaque
)
1023 cpu_reset(CPU(opaque
));
1026 static void ppc405_soc_realize(DeviceState
*dev
, Error
**errp
)
1028 Ppc405SoCState
*s
= PPC405_SOC(dev
);
1034 if (!qdev_realize(DEVICE(&s
->cpu
), NULL
, errp
)) {
1037 qemu_register_reset(ppc405_reset
, &s
->cpu
);
1041 ppc_dcr_init(env
, NULL
, NULL
);
1044 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s
->cpc
), &s
->cpu
, errp
)) {
1049 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s
->plb
), &s
->cpu
, errp
)) {
1053 /* PLB to OPB bridge */
1054 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s
->pob
), &s
->cpu
, errp
)) {
1059 sbd
= SYS_BUS_DEVICE(&s
->opba
);
1060 if (!sysbus_realize(sbd
, errp
)) {
1063 sysbus_mmio_map(sbd
, 0, 0xef600600);
1065 /* Universal interrupt controller */
1066 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s
->uic
), &s
->cpu
, errp
)) {
1069 sbd
= SYS_BUS_DEVICE(&s
->uic
);
1070 sysbus_connect_irq(sbd
, PPCUIC_OUTPUT_INT
,
1071 qdev_get_gpio_in(DEVICE(&s
->cpu
), PPC40x_INPUT_INT
));
1072 sysbus_connect_irq(sbd
, PPCUIC_OUTPUT_CINT
,
1073 qdev_get_gpio_in(DEVICE(&s
->cpu
), PPC40x_INPUT_CINT
));
1075 /* SDRAM controller */
1076 /* XXX 405EP has no ECC interrupt */
1077 s
->ram_banks
[0].base
= 0;
1078 s
->ram_banks
[0].size
= s
->ram_size
;
1079 memory_region_init_alias(&s
->ram_banks
[0].ram
, OBJECT(s
),
1080 "ppc405.sdram0", s
->dram_mr
,
1081 s
->ram_banks
[0].base
, s
->ram_banks
[0].size
);
1083 ppc4xx_sdram_init(env
, qdev_get_gpio_in(DEVICE(&s
->uic
), 17), 1,
1086 /* External bus controller */
1087 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s
->ebc
), &s
->cpu
, errp
)) {
1091 /* DMA controller */
1092 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s
->dma
), &s
->cpu
, errp
)) {
1095 sbd
= SYS_BUS_DEVICE(&s
->dma
);
1096 for (i
= 0; i
< ARRAY_SIZE(s
->dma
.irqs
); i
++) {
1097 sysbus_connect_irq(sbd
, i
, qdev_get_gpio_in(DEVICE(&s
->uic
), 5 + i
));
1100 /* I2C controller */
1101 sbd
= SYS_BUS_DEVICE(&s
->i2c
);
1102 if (!sysbus_realize(sbd
, errp
)) {
1105 sysbus_mmio_map(sbd
, 0, 0xef600500);
1106 sysbus_connect_irq(sbd
, 0, qdev_get_gpio_in(DEVICE(&s
->uic
), 2));
1109 sbd
= SYS_BUS_DEVICE(&s
->gpio
);
1110 if (!sysbus_realize(sbd
, errp
)) {
1113 sysbus_mmio_map(sbd
, 0, 0xef600700);
1116 if (serial_hd(0) != NULL
) {
1117 serial_mm_init(get_system_memory(), 0xef600300, 0,
1118 qdev_get_gpio_in(DEVICE(&s
->uic
), 0),
1119 PPC_SERIAL_MM_BAUDBASE
, serial_hd(0),
1122 if (serial_hd(1) != NULL
) {
1123 serial_mm_init(get_system_memory(), 0xef600400, 0,
1124 qdev_get_gpio_in(DEVICE(&s
->uic
), 1),
1125 PPC_SERIAL_MM_BAUDBASE
, serial_hd(1),
1130 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s
->ocm
), &s
->cpu
, errp
)) {
1135 sbd
= SYS_BUS_DEVICE(&s
->gpt
);
1136 if (!sysbus_realize(sbd
, errp
)) {
1139 sysbus_mmio_map(sbd
, 0, 0xef600000);
1140 for (i
= 0; i
< ARRAY_SIZE(s
->gpt
.irqs
); i
++) {
1141 sysbus_connect_irq(sbd
, i
, qdev_get_gpio_in(DEVICE(&s
->uic
), 19 + i
));
1145 object_property_set_int(OBJECT(&s
->mal
), "txc-num", 4, &error_abort
);
1146 object_property_set_int(OBJECT(&s
->mal
), "rxc-num", 2, &error_abort
);
1147 if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s
->mal
), &s
->cpu
, errp
)) {
1150 sbd
= SYS_BUS_DEVICE(&s
->mal
);
1151 for (i
= 0; i
< ARRAY_SIZE(s
->mal
.irqs
); i
++) {
1152 sysbus_connect_irq(sbd
, i
, qdev_get_gpio_in(DEVICE(&s
->uic
), 11 + i
));
1156 /* Uses UIC IRQs 9, 15, 17 */
1159 static Property ppc405_soc_properties
[] = {
1160 DEFINE_PROP_LINK("dram", Ppc405SoCState
, dram_mr
, TYPE_MEMORY_REGION
,
1162 DEFINE_PROP_UINT64("ram-size", Ppc405SoCState
, ram_size
, 0),
1163 DEFINE_PROP_END_OF_LIST(),
1166 static void ppc405_soc_class_init(ObjectClass
*oc
, void *data
)
1168 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1170 dc
->realize
= ppc405_soc_realize
;
1171 /* Reason: only works as part of a ppc405 board/machine */
1172 dc
->user_creatable
= false;
1173 device_class_set_props(dc
, ppc405_soc_properties
);
1176 static const TypeInfo ppc405_types
[] = {
1178 .name
= TYPE_PPC405_POB
,
1179 .parent
= TYPE_PPC4xx_DCR_DEVICE
,
1180 .instance_size
= sizeof(Ppc405PobState
),
1181 .class_init
= ppc405_pob_class_init
,
1183 .name
= TYPE_PPC405_OPBA
,
1184 .parent
= TYPE_SYS_BUS_DEVICE
,
1185 .instance_size
= sizeof(Ppc405OpbaState
),
1186 .class_init
= ppc405_opba_class_init
,
1188 .name
= TYPE_PPC405_DMA
,
1189 .parent
= TYPE_PPC4xx_DCR_DEVICE
,
1190 .instance_size
= sizeof(Ppc405DmaState
),
1191 .class_init
= ppc405_dma_class_init
,
1193 .name
= TYPE_PPC405_GPIO
,
1194 .parent
= TYPE_SYS_BUS_DEVICE
,
1195 .instance_size
= sizeof(Ppc405GpioState
),
1196 .class_init
= ppc405_gpio_class_init
,
1198 .name
= TYPE_PPC405_OCM
,
1199 .parent
= TYPE_PPC4xx_DCR_DEVICE
,
1200 .instance_size
= sizeof(Ppc405OcmState
),
1201 .class_init
= ppc405_ocm_class_init
,
1203 .name
= TYPE_PPC405_GPT
,
1204 .parent
= TYPE_SYS_BUS_DEVICE
,
1205 .instance_size
= sizeof(Ppc405GptState
),
1206 .instance_finalize
= ppc405_gpt_finalize
,
1207 .class_init
= ppc405_gpt_class_init
,
1209 .name
= TYPE_PPC405_CPC
,
1210 .parent
= TYPE_PPC4xx_DCR_DEVICE
,
1211 .instance_size
= sizeof(Ppc405CpcState
),
1212 .class_init
= ppc405_cpc_class_init
,
1214 .name
= TYPE_PPC405_SOC
,
1215 .parent
= TYPE_DEVICE
,
1216 .instance_size
= sizeof(Ppc405SoCState
),
1217 .instance_init
= ppc405_soc_instance_init
,
1218 .class_init
= ppc405_soc_class_init
,
1222 DEFINE_TYPES(ppc405_types
)