4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
22 #include "qemu-common.h"
23 #if !defined(CONFIG_USER_ONLY)
24 #include "hw/loader.h"
26 #include "sysemu/sysemu.h"
28 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
30 /* Reset a single ARMCPRegInfo register */
31 ARMCPRegInfo
*ri
= value
;
34 if (ri
->type
& ARM_CP_SPECIAL
) {
39 ri
->resetfn(&cpu
->env
, ri
);
43 /* A zero offset is never possible as it would be regs[0]
44 * so we use it to indicate that reset is being handled elsewhere.
45 * This is basically only used for fields in non-core coprocessors
46 * (like the pxa2xx ones).
48 if (!ri
->fieldoffset
) {
52 if (ri
->type
& ARM_CP_64BIT
) {
53 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
55 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
59 /* CPUClass::reset() */
60 static void arm_cpu_reset(CPUState
*s
)
62 ARMCPU
*cpu
= ARM_CPU(s
);
63 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
64 CPUARMState
*env
= &cpu
->env
;
68 memset(env
, 0, offsetof(CPUARMState
, breakpoints
));
69 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
70 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
71 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->mvfr0
;
72 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->mvfr1
;
74 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
75 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
78 #if defined(CONFIG_USER_ONLY)
79 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
80 /* For user mode we must enable access to coprocessors */
81 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
82 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
83 env
->cp15
.c15_cpar
= 3;
84 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
85 env
->cp15
.c15_cpar
= 1;
88 /* SVC mode with interrupts disabled. */
89 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
90 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
91 clear at reset. Initial SP and PC are loaded from ROM. */
95 env
->uncached_cpsr
&= ~CPSR_I
;
98 /* We should really use ldl_phys here, in case the guest
99 modified flash and reset itself. However images
100 loaded via -kernel have not been copied yet, so load the
101 values directly from there. */
102 env
->regs
[13] = ldl_p(rom
);
105 env
->regs
[15] = pc
& ~1;
108 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
110 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
111 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
112 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
113 set_float_detect_tininess(float_tininess_before_rounding
,
114 &env
->vfp
.fp_status
);
115 set_float_detect_tininess(float_tininess_before_rounding
,
116 &env
->vfp
.standard_fp_status
);
118 /* Reset is a state change for some CPUARMState fields which we
119 * bake assumptions about into translated code, so we need to
125 static inline void set_feature(CPUARMState
*env
, int feature
)
127 env
->features
|= 1ULL << feature
;
130 static void arm_cpu_initfn(Object
*obj
)
132 CPUState
*cs
= CPU(obj
);
133 ARMCPU
*cpu
= ARM_CPU(obj
);
136 cs
->env_ptr
= &cpu
->env
;
137 cpu_exec_init(&cpu
->env
);
138 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
141 if (tcg_enabled() && !inited
) {
143 arm_translate_init();
147 static void arm_cpu_finalizefn(Object
*obj
)
149 ARMCPU
*cpu
= ARM_CPU(obj
);
150 g_hash_table_destroy(cpu
->cp_regs
);
153 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
155 ARMCPU
*cpu
= ARM_CPU(dev
);
156 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
157 CPUARMState
*env
= &cpu
->env
;
159 /* Some features automatically imply others: */
160 if (arm_feature(env
, ARM_FEATURE_V8
)) {
161 set_feature(env
, ARM_FEATURE_V7
);
162 set_feature(env
, ARM_FEATURE_ARM_DIV
);
163 set_feature(env
, ARM_FEATURE_LPAE
);
165 if (arm_feature(env
, ARM_FEATURE_V7
)) {
166 set_feature(env
, ARM_FEATURE_VAPA
);
167 set_feature(env
, ARM_FEATURE_THUMB2
);
168 set_feature(env
, ARM_FEATURE_MPIDR
);
169 if (!arm_feature(env
, ARM_FEATURE_M
)) {
170 set_feature(env
, ARM_FEATURE_V6K
);
172 set_feature(env
, ARM_FEATURE_V6
);
175 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
176 set_feature(env
, ARM_FEATURE_V6
);
177 set_feature(env
, ARM_FEATURE_MVFR
);
179 if (arm_feature(env
, ARM_FEATURE_V6
)) {
180 set_feature(env
, ARM_FEATURE_V5
);
181 if (!arm_feature(env
, ARM_FEATURE_M
)) {
182 set_feature(env
, ARM_FEATURE_AUXCR
);
185 if (arm_feature(env
, ARM_FEATURE_V5
)) {
186 set_feature(env
, ARM_FEATURE_V4T
);
188 if (arm_feature(env
, ARM_FEATURE_M
)) {
189 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
191 if (arm_feature(env
, ARM_FEATURE_ARM_DIV
)) {
192 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
194 if (arm_feature(env
, ARM_FEATURE_VFP4
)) {
195 set_feature(env
, ARM_FEATURE_VFP3
);
197 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
198 set_feature(env
, ARM_FEATURE_VFP
);
200 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
201 set_feature(env
, ARM_FEATURE_V7MP
);
202 set_feature(env
, ARM_FEATURE_PXN
);
205 register_cp_regs_for_features(cpu
);
206 arm_cpu_register_gdb_regs_for_features(cpu
);
208 init_cpreg_list(cpu
);
212 acc
->parent_realize(dev
, errp
);
217 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
226 typename
= g_strdup_printf("%s-" TYPE_ARM_CPU
, cpu_model
);
227 oc
= object_class_by_name(typename
);
229 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
230 object_class_is_abstract(oc
)) {
236 static void arm926_initfn(Object
*obj
)
238 ARMCPU
*cpu
= ARM_CPU(obj
);
239 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
240 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
241 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
242 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
243 cpu
->midr
= 0x41069265;
244 cpu
->reset_fpsid
= 0x41011090;
245 cpu
->ctr
= 0x1dd20d2;
246 cpu
->reset_sctlr
= 0x00090078;
249 static void arm946_initfn(Object
*obj
)
251 ARMCPU
*cpu
= ARM_CPU(obj
);
252 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
253 set_feature(&cpu
->env
, ARM_FEATURE_MPU
);
254 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
255 cpu
->midr
= 0x41059461;
256 cpu
->ctr
= 0x0f004006;
257 cpu
->reset_sctlr
= 0x00000078;
260 static void arm1026_initfn(Object
*obj
)
262 ARMCPU
*cpu
= ARM_CPU(obj
);
263 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
264 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
265 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
266 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
267 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
268 cpu
->midr
= 0x4106a262;
269 cpu
->reset_fpsid
= 0x410110a0;
270 cpu
->ctr
= 0x1dd20d2;
271 cpu
->reset_sctlr
= 0x00090078;
272 cpu
->reset_auxcr
= 1;
274 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
275 ARMCPRegInfo ifar
= {
276 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
278 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_insn
),
281 define_one_arm_cp_reg(cpu
, &ifar
);
285 static void arm1136_r2_initfn(Object
*obj
)
287 ARMCPU
*cpu
= ARM_CPU(obj
);
288 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
289 * older core than plain "arm1136". In particular this does not
290 * have the v6K features.
291 * These ID register values are correct for 1136 but may be wrong
292 * for 1136_r2 (in particular r0p2 does not actually implement most
293 * of the ID registers).
295 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
296 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
297 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
298 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
299 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
300 cpu
->midr
= 0x4107b362;
301 cpu
->reset_fpsid
= 0x410120b4;
302 cpu
->mvfr0
= 0x11111111;
303 cpu
->mvfr1
= 0x00000000;
304 cpu
->ctr
= 0x1dd20d2;
305 cpu
->reset_sctlr
= 0x00050078;
306 cpu
->id_pfr0
= 0x111;
310 cpu
->id_mmfr0
= 0x01130003;
311 cpu
->id_mmfr1
= 0x10030302;
312 cpu
->id_mmfr2
= 0x01222110;
313 cpu
->id_isar0
= 0x00140011;
314 cpu
->id_isar1
= 0x12002111;
315 cpu
->id_isar2
= 0x11231111;
316 cpu
->id_isar3
= 0x01102131;
317 cpu
->id_isar4
= 0x141;
318 cpu
->reset_auxcr
= 7;
321 static void arm1136_initfn(Object
*obj
)
323 ARMCPU
*cpu
= ARM_CPU(obj
);
324 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
325 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
326 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
327 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
328 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
329 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
330 cpu
->midr
= 0x4117b363;
331 cpu
->reset_fpsid
= 0x410120b4;
332 cpu
->mvfr0
= 0x11111111;
333 cpu
->mvfr1
= 0x00000000;
334 cpu
->ctr
= 0x1dd20d2;
335 cpu
->reset_sctlr
= 0x00050078;
336 cpu
->id_pfr0
= 0x111;
340 cpu
->id_mmfr0
= 0x01130003;
341 cpu
->id_mmfr1
= 0x10030302;
342 cpu
->id_mmfr2
= 0x01222110;
343 cpu
->id_isar0
= 0x00140011;
344 cpu
->id_isar1
= 0x12002111;
345 cpu
->id_isar2
= 0x11231111;
346 cpu
->id_isar3
= 0x01102131;
347 cpu
->id_isar4
= 0x141;
348 cpu
->reset_auxcr
= 7;
351 static void arm1176_initfn(Object
*obj
)
353 ARMCPU
*cpu
= ARM_CPU(obj
);
354 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
355 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
356 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
357 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
358 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
359 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
360 cpu
->midr
= 0x410fb767;
361 cpu
->reset_fpsid
= 0x410120b5;
362 cpu
->mvfr0
= 0x11111111;
363 cpu
->mvfr1
= 0x00000000;
364 cpu
->ctr
= 0x1dd20d2;
365 cpu
->reset_sctlr
= 0x00050078;
366 cpu
->id_pfr0
= 0x111;
370 cpu
->id_mmfr0
= 0x01130003;
371 cpu
->id_mmfr1
= 0x10030302;
372 cpu
->id_mmfr2
= 0x01222100;
373 cpu
->id_isar0
= 0x0140011;
374 cpu
->id_isar1
= 0x12002111;
375 cpu
->id_isar2
= 0x11231121;
376 cpu
->id_isar3
= 0x01102131;
377 cpu
->id_isar4
= 0x01141;
378 cpu
->reset_auxcr
= 7;
381 static void arm11mpcore_initfn(Object
*obj
)
383 ARMCPU
*cpu
= ARM_CPU(obj
);
384 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
385 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
386 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
387 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
388 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
389 cpu
->midr
= 0x410fb022;
390 cpu
->reset_fpsid
= 0x410120b4;
391 cpu
->mvfr0
= 0x11111111;
392 cpu
->mvfr1
= 0x00000000;
393 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
394 cpu
->id_pfr0
= 0x111;
398 cpu
->id_mmfr0
= 0x01100103;
399 cpu
->id_mmfr1
= 0x10020302;
400 cpu
->id_mmfr2
= 0x01222000;
401 cpu
->id_isar0
= 0x00100011;
402 cpu
->id_isar1
= 0x12002111;
403 cpu
->id_isar2
= 0x11221011;
404 cpu
->id_isar3
= 0x01102131;
405 cpu
->id_isar4
= 0x141;
406 cpu
->reset_auxcr
= 1;
409 static void cortex_m3_initfn(Object
*obj
)
411 ARMCPU
*cpu
= ARM_CPU(obj
);
412 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
413 set_feature(&cpu
->env
, ARM_FEATURE_M
);
414 cpu
->midr
= 0x410fc231;
417 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
419 #ifndef CONFIG_USER_ONLY
420 CPUClass
*cc
= CPU_CLASS(oc
);
422 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
426 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
427 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
428 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
429 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
430 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
434 static void cortex_a8_initfn(Object
*obj
)
436 ARMCPU
*cpu
= ARM_CPU(obj
);
437 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
438 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
439 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
440 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
441 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
442 cpu
->midr
= 0x410fc080;
443 cpu
->reset_fpsid
= 0x410330c0;
444 cpu
->mvfr0
= 0x11110222;
445 cpu
->mvfr1
= 0x00011100;
446 cpu
->ctr
= 0x82048004;
447 cpu
->reset_sctlr
= 0x00c50078;
448 cpu
->id_pfr0
= 0x1031;
450 cpu
->id_dfr0
= 0x400;
452 cpu
->id_mmfr0
= 0x31100003;
453 cpu
->id_mmfr1
= 0x20000000;
454 cpu
->id_mmfr2
= 0x01202000;
455 cpu
->id_mmfr3
= 0x11;
456 cpu
->id_isar0
= 0x00101111;
457 cpu
->id_isar1
= 0x12112111;
458 cpu
->id_isar2
= 0x21232031;
459 cpu
->id_isar3
= 0x11112131;
460 cpu
->id_isar4
= 0x00111142;
461 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
462 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
463 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
464 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
465 cpu
->reset_auxcr
= 2;
466 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
469 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
470 /* power_control should be set to maximum latency. Again,
471 * default to 0 and set by private hook
473 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
474 .access
= PL1_RW
, .resetvalue
= 0,
475 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
476 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
477 .access
= PL1_RW
, .resetvalue
= 0,
478 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
479 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
480 .access
= PL1_RW
, .resetvalue
= 0,
481 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
482 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
483 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
484 /* TLB lockdown control */
485 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
486 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
487 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
488 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
489 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
490 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
491 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
492 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
493 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
494 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
498 static void cortex_a9_initfn(Object
*obj
)
500 ARMCPU
*cpu
= ARM_CPU(obj
);
501 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
502 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
503 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
504 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
505 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
506 /* Note that A9 supports the MP extensions even for
507 * A9UP and single-core A9MP (which are both different
508 * and valid configurations; we don't model A9UP).
510 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
511 cpu
->midr
= 0x410fc090;
512 cpu
->reset_fpsid
= 0x41033090;
513 cpu
->mvfr0
= 0x11110222;
514 cpu
->mvfr1
= 0x01111111;
515 cpu
->ctr
= 0x80038003;
516 cpu
->reset_sctlr
= 0x00c50078;
517 cpu
->id_pfr0
= 0x1031;
519 cpu
->id_dfr0
= 0x000;
521 cpu
->id_mmfr0
= 0x00100103;
522 cpu
->id_mmfr1
= 0x20000000;
523 cpu
->id_mmfr2
= 0x01230000;
524 cpu
->id_mmfr3
= 0x00002111;
525 cpu
->id_isar0
= 0x00101111;
526 cpu
->id_isar1
= 0x13112111;
527 cpu
->id_isar2
= 0x21232041;
528 cpu
->id_isar3
= 0x11112131;
529 cpu
->id_isar4
= 0x00111142;
530 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
531 cpu
->ccsidr
[0] = 0xe00fe015; /* 16k L1 dcache. */
532 cpu
->ccsidr
[1] = 0x200fe015; /* 16k L1 icache. */
534 ARMCPRegInfo cbar
= {
535 .name
= "CBAR", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4,
536 .opc2
= 0, .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
537 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_config_base_address
)
539 define_one_arm_cp_reg(cpu
, &cbar
);
540 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
544 #ifndef CONFIG_USER_ONLY
545 static int a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
548 /* Linux wants the number of processors from here.
549 * Might as well set the interrupt-controller bit too.
551 *value
= ((smp_cpus
- 1) << 24) | (1 << 23);
556 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
557 #ifndef CONFIG_USER_ONLY
558 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
559 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
560 .writefn
= arm_cp_write_ignore
, },
562 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
563 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
567 static void cortex_a15_initfn(Object
*obj
)
569 ARMCPU
*cpu
= ARM_CPU(obj
);
570 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
571 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
572 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
573 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
574 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
575 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
576 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
577 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
578 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
579 cpu
->midr
= 0x412fc0f1;
580 cpu
->reset_fpsid
= 0x410430f0;
581 cpu
->mvfr0
= 0x10110222;
582 cpu
->mvfr1
= 0x11111111;
583 cpu
->ctr
= 0x8444c004;
584 cpu
->reset_sctlr
= 0x00c50078;
585 cpu
->id_pfr0
= 0x00001131;
586 cpu
->id_pfr1
= 0x00011011;
587 cpu
->id_dfr0
= 0x02010555;
588 cpu
->id_afr0
= 0x00000000;
589 cpu
->id_mmfr0
= 0x10201105;
590 cpu
->id_mmfr1
= 0x20000000;
591 cpu
->id_mmfr2
= 0x01240000;
592 cpu
->id_mmfr3
= 0x02102211;
593 cpu
->id_isar0
= 0x02101110;
594 cpu
->id_isar1
= 0x13112111;
595 cpu
->id_isar2
= 0x21232041;
596 cpu
->id_isar3
= 0x11112131;
597 cpu
->id_isar4
= 0x10011142;
598 cpu
->clidr
= 0x0a200023;
599 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
600 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
601 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
602 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
605 static void ti925t_initfn(Object
*obj
)
607 ARMCPU
*cpu
= ARM_CPU(obj
);
608 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
609 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
610 cpu
->midr
= ARM_CPUID_TI925T
;
611 cpu
->ctr
= 0x5109149;
612 cpu
->reset_sctlr
= 0x00000070;
615 static void sa1100_initfn(Object
*obj
)
617 ARMCPU
*cpu
= ARM_CPU(obj
);
618 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
619 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
620 cpu
->midr
= 0x4401A11B;
621 cpu
->reset_sctlr
= 0x00000070;
624 static void sa1110_initfn(Object
*obj
)
626 ARMCPU
*cpu
= ARM_CPU(obj
);
627 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
628 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
629 cpu
->midr
= 0x6901B119;
630 cpu
->reset_sctlr
= 0x00000070;
633 static void pxa250_initfn(Object
*obj
)
635 ARMCPU
*cpu
= ARM_CPU(obj
);
636 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
637 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
638 cpu
->midr
= 0x69052100;
639 cpu
->ctr
= 0xd172172;
640 cpu
->reset_sctlr
= 0x00000078;
643 static void pxa255_initfn(Object
*obj
)
645 ARMCPU
*cpu
= ARM_CPU(obj
);
646 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
647 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
648 cpu
->midr
= 0x69052d00;
649 cpu
->ctr
= 0xd172172;
650 cpu
->reset_sctlr
= 0x00000078;
653 static void pxa260_initfn(Object
*obj
)
655 ARMCPU
*cpu
= ARM_CPU(obj
);
656 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
657 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
658 cpu
->midr
= 0x69052903;
659 cpu
->ctr
= 0xd172172;
660 cpu
->reset_sctlr
= 0x00000078;
663 static void pxa261_initfn(Object
*obj
)
665 ARMCPU
*cpu
= ARM_CPU(obj
);
666 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
667 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
668 cpu
->midr
= 0x69052d05;
669 cpu
->ctr
= 0xd172172;
670 cpu
->reset_sctlr
= 0x00000078;
673 static void pxa262_initfn(Object
*obj
)
675 ARMCPU
*cpu
= ARM_CPU(obj
);
676 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
677 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
678 cpu
->midr
= 0x69052d06;
679 cpu
->ctr
= 0xd172172;
680 cpu
->reset_sctlr
= 0x00000078;
683 static void pxa270a0_initfn(Object
*obj
)
685 ARMCPU
*cpu
= ARM_CPU(obj
);
686 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
687 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
688 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
689 cpu
->midr
= 0x69054110;
690 cpu
->ctr
= 0xd172172;
691 cpu
->reset_sctlr
= 0x00000078;
694 static void pxa270a1_initfn(Object
*obj
)
696 ARMCPU
*cpu
= ARM_CPU(obj
);
697 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
698 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
699 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
700 cpu
->midr
= 0x69054111;
701 cpu
->ctr
= 0xd172172;
702 cpu
->reset_sctlr
= 0x00000078;
705 static void pxa270b0_initfn(Object
*obj
)
707 ARMCPU
*cpu
= ARM_CPU(obj
);
708 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
709 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
710 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
711 cpu
->midr
= 0x69054112;
712 cpu
->ctr
= 0xd172172;
713 cpu
->reset_sctlr
= 0x00000078;
716 static void pxa270b1_initfn(Object
*obj
)
718 ARMCPU
*cpu
= ARM_CPU(obj
);
719 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
720 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
721 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
722 cpu
->midr
= 0x69054113;
723 cpu
->ctr
= 0xd172172;
724 cpu
->reset_sctlr
= 0x00000078;
727 static void pxa270c0_initfn(Object
*obj
)
729 ARMCPU
*cpu
= ARM_CPU(obj
);
730 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
731 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
732 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
733 cpu
->midr
= 0x69054114;
734 cpu
->ctr
= 0xd172172;
735 cpu
->reset_sctlr
= 0x00000078;
738 static void pxa270c5_initfn(Object
*obj
)
740 ARMCPU
*cpu
= ARM_CPU(obj
);
741 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
742 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
743 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
744 cpu
->midr
= 0x69054117;
745 cpu
->ctr
= 0xd172172;
746 cpu
->reset_sctlr
= 0x00000078;
749 static void arm_any_initfn(Object
*obj
)
751 ARMCPU
*cpu
= ARM_CPU(obj
);
752 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
753 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
754 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
755 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
756 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
757 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
758 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
759 cpu
->midr
= 0xffffffff;
762 typedef struct ARMCPUInfo
{
764 void (*initfn
)(Object
*obj
);
765 void (*class_init
)(ObjectClass
*oc
, void *data
);
768 static const ARMCPUInfo arm_cpus
[] = {
769 { .name
= "arm926", .initfn
= arm926_initfn
},
770 { .name
= "arm946", .initfn
= arm946_initfn
},
771 { .name
= "arm1026", .initfn
= arm1026_initfn
},
772 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
773 * older core than plain "arm1136". In particular this does not
774 * have the v6K features.
776 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
777 { .name
= "arm1136", .initfn
= arm1136_initfn
},
778 { .name
= "arm1176", .initfn
= arm1176_initfn
},
779 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
780 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
781 .class_init
= arm_v7m_class_init
},
782 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
783 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
784 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
785 { .name
= "ti925t", .initfn
= ti925t_initfn
},
786 { .name
= "sa1100", .initfn
= sa1100_initfn
},
787 { .name
= "sa1110", .initfn
= sa1110_initfn
},
788 { .name
= "pxa250", .initfn
= pxa250_initfn
},
789 { .name
= "pxa255", .initfn
= pxa255_initfn
},
790 { .name
= "pxa260", .initfn
= pxa260_initfn
},
791 { .name
= "pxa261", .initfn
= pxa261_initfn
},
792 { .name
= "pxa262", .initfn
= pxa262_initfn
},
793 /* "pxa270" is an alias for "pxa270-a0" */
794 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
795 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
796 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
797 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
798 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
799 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
800 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
801 { .name
= "any", .initfn
= arm_any_initfn
},
804 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
806 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
807 CPUClass
*cc
= CPU_CLASS(acc
);
808 DeviceClass
*dc
= DEVICE_CLASS(oc
);
810 acc
->parent_realize
= dc
->realize
;
811 dc
->realize
= arm_cpu_realizefn
;
813 acc
->parent_reset
= cc
->reset
;
814 cc
->reset
= arm_cpu_reset
;
816 cc
->class_by_name
= arm_cpu_class_by_name
;
817 cc
->do_interrupt
= arm_cpu_do_interrupt
;
818 cc
->dump_state
= arm_cpu_dump_state
;
819 cpu_class_set_vmsd(cc
, &vmstate_arm_cpu
);
822 static void cpu_register(const ARMCPUInfo
*info
)
824 TypeInfo type_info
= {
825 .parent
= TYPE_ARM_CPU
,
826 .instance_size
= sizeof(ARMCPU
),
827 .instance_init
= info
->initfn
,
828 .class_size
= sizeof(ARMCPUClass
),
829 .class_init
= info
->class_init
,
832 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
833 type_register(&type_info
);
834 g_free((void *)type_info
.name
);
837 static const TypeInfo arm_cpu_type_info
= {
838 .name
= TYPE_ARM_CPU
,
840 .instance_size
= sizeof(ARMCPU
),
841 .instance_init
= arm_cpu_initfn
,
842 .instance_finalize
= arm_cpu_finalizefn
,
844 .class_size
= sizeof(ARMCPUClass
),
845 .class_init
= arm_cpu_class_init
,
848 static void arm_cpu_register_types(void)
852 type_register_static(&arm_cpu_type_info
);
853 for (i
= 0; i
< ARRAY_SIZE(arm_cpus
); i
++) {
854 cpu_register(&arm_cpus
[i
]);
858 type_init(arm_cpu_register_types
)