target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/qmp/qerror.h"
  26 #if !defined(CONFIG_USER_ONLY)
  27 #include "hw/loader.h"
  28 #endif
  29 #include "hw/arm/arm.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/kvm.h"
  32 #include "kvm_arm.h"
  33
  34 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  35 {
  36     ARMCPU *cpu = ARM_CPU(cs);
  37
  38     cpu->env.regs[15] = value;
  39 }
  40
  41 static bool arm_cpu_has_work(CPUState *cs)
  42 {
  43     ARMCPU *cpu = ARM_CPU(cs);
  44
  45     return !cpu->powered_off
  46         && cs->interrupt_request &
  47         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  48          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  49          | CPU_INTERRUPT_EXITTB);
  50 }
  51
  52 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  53 {
  54     /* Reset a single ARMCPRegInfo register */
  55     ARMCPRegInfo *ri = value;
  56     ARMCPU *cpu = opaque;
  57
  58     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
  59         return;
  60     }
  61
  62     if (ri->resetfn) {
  63         ri->resetfn(&cpu->env, ri);
  64         return;
  65     }
  66
  67     /* A zero offset is never possible as it would be regs[0]
  68      * so we use it to indicate that reset is being handled elsewhere.
  69      * This is basically only used for fields in non-core coprocessors
  70      * (like the pxa2xx ones).
  71      */
  72     if (!ri->fieldoffset) {
  73         return;
  74     }
  75
  76     if (cpreg_field_is_64bit(ri)) {
  77         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  78     } else {
  79         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  80     }
  81 }
  82
  83 /* CPUClass::reset() */
  84 static void arm_cpu_reset(CPUState *s)
  85 {
  86     ARMCPU *cpu = ARM_CPU(s);
  87     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  88     CPUARMState *env = &cpu->env;
  89
  90     acc->parent_reset(s);
  91
  92     memset(env, 0, offsetof(CPUARMState, features));
  93     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  94     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  95     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  96     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  97     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
  98
  99     cpu->powered_off = cpu->start_powered_off;
 100     s->halted = cpu->start_powered_off;
 101
 102     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 103         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 104     }
 105
 106     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 107         /* 64 bit CPUs always start in 64 bit mode */
 108         env->aarch64 = 1;
 109 #if defined(CONFIG_USER_ONLY)
 110         env->pstate = PSTATE_MODE_EL0t;
 111         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 112         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 113         /* and to the FP/Neon instructions */
 114         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
 115 #else
 116         /* Reset into the highest available EL */
 117         if (arm_feature(env, ARM_FEATURE_EL3)) {
 118             env->pstate = PSTATE_MODE_EL3h;
 119         } else if (arm_feature(env, ARM_FEATURE_EL2)) {
 120             env->pstate = PSTATE_MODE_EL2h;
 121         } else {
 122             env->pstate = PSTATE_MODE_EL1h;
 123         }
 124         env->pc = cpu->rvbar;
 125 #endif
 126     } else {
 127 #if defined(CONFIG_USER_ONLY)
 128         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 129         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
 130 #endif
 131     }
 132
 133 #if defined(CONFIG_USER_ONLY)
 134     env->uncached_cpsr = ARM_CPU_MODE_USR;
 135     /* For user mode we must enable access to coprocessors */
 136     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 137     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 138         env->cp15.c15_cpar = 3;
 139     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 140         env->cp15.c15_cpar = 1;
 141     }
 142 #else
 143     /* SVC mode with interrupts disabled.  */
 144     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 145     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 146     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 147      * clear at reset. Initial SP and PC are loaded from ROM.
 148      */
 149     if (IS_M(env)) {
 150         uint32_t initial_msp; /* Loaded from 0x0 */
 151         uint32_t initial_pc; /* Loaded from 0x4 */
 152         uint8_t *rom;
 153
 154         env->daif &= ~PSTATE_I;
 155         rom = rom_ptr(0);
 156         if (rom) {
 157             /* Address zero is covered by ROM which hasn't yet been
 158              * copied into physical memory.
 159              */
 160             initial_msp = ldl_p(rom);
 161             initial_pc = ldl_p(rom + 4);
 162         } else {
 163             /* Address zero not covered by a ROM blob, or the ROM blob
 164              * is in non-modifiable memory and this is a second reset after
 165              * it got copied into memory. In the latter case, rom_ptr
 166              * will return a NULL pointer and we should use ldl_phys instead.
 167              */
 168             initial_msp = ldl_phys(s->as, 0);
 169             initial_pc = ldl_phys(s->as, 4);
 170         }
 171
 172         env->regs[13] = initial_msp & 0xFFFFFFFC;
 173         env->regs[15] = initial_pc & ~1;
 174         env->thumb = initial_pc & 1;
 175     }
 176
 177     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 178      * executing as AArch32 then check if highvecs are enabled and
 179      * adjust the PC accordingly.
 180      */
 181     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 182         env->regs[15] = 0xFFFF0000;
 183     }
 184
 185     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 186 #endif
 187     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 188     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 189     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 190     set_float_detect_tininess(float_tininess_before_rounding,
 191                               &env->vfp.fp_status);
 192     set_float_detect_tininess(float_tininess_before_rounding,
 193                               &env->vfp.standard_fp_status);
 194     tlb_flush(s, 1);
 195
 196 #ifndef CONFIG_USER_ONLY
 197     if (kvm_enabled()) {
 198         kvm_arm_reset_vcpu(cpu);
 199     }
 200 #endif
 201
 202     hw_breakpoint_update_all(cpu);
 203     hw_watchpoint_update_all(cpu);
 204 }
 205
 206 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 207 {
 208     CPUClass *cc = CPU_GET_CLASS(cs);
 209     CPUARMState *env = cs->env_ptr;
 210     uint32_t cur_el = arm_current_el(env);
 211     bool secure = arm_is_secure(env);
 212     uint32_t target_el;
 213     uint32_t excp_idx;
 214     bool ret = false;
 215
 216     if (interrupt_request & CPU_INTERRUPT_FIQ) {
 217         excp_idx = EXCP_FIQ;
 218         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 219         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 220             cs->exception_index = excp_idx;
 221             env->exception.target_el = target_el;
 222             cc->do_interrupt(cs);
 223             ret = true;
 224         }
 225     }
 226     if (interrupt_request & CPU_INTERRUPT_HARD) {
 227         excp_idx = EXCP_IRQ;
 228         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 229         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 230             cs->exception_index = excp_idx;
 231             env->exception.target_el = target_el;
 232             cc->do_interrupt(cs);
 233             ret = true;
 234         }
 235     }
 236     if (interrupt_request & CPU_INTERRUPT_VIRQ) {
 237         excp_idx = EXCP_VIRQ;
 238         target_el = 1;
 239         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 240             cs->exception_index = excp_idx;
 241             env->exception.target_el = target_el;
 242             cc->do_interrupt(cs);
 243             ret = true;
 244         }
 245     }
 246     if (interrupt_request & CPU_INTERRUPT_VFIQ) {
 247         excp_idx = EXCP_VFIQ;
 248         target_el = 1;
 249         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 250             cs->exception_index = excp_idx;
 251             env->exception.target_el = target_el;
 252             cc->do_interrupt(cs);
 253             ret = true;
 254         }
 255     }
 256
 257     return ret;
 258 }
 259
 260 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 261 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 262 {
 263     CPUClass *cc = CPU_GET_CLASS(cs);
 264     ARMCPU *cpu = ARM_CPU(cs);
 265     CPUARMState *env = &cpu->env;
 266     bool ret = false;
 267
 268
 269     if (interrupt_request & CPU_INTERRUPT_FIQ
 270         && !(env->daif & PSTATE_F)) {
 271         cs->exception_index = EXCP_FIQ;
 272         cc->do_interrupt(cs);
 273         ret = true;
 274     }
 275     /* ARMv7-M interrupt return works by loading a magic value
 276      * into the PC.  On real hardware the load causes the
 277      * return to occur.  The qemu implementation performs the
 278      * jump normally, then does the exception return when the
 279      * CPU tries to execute code at the magic address.
 280      * This will cause the magic PC value to be pushed to
 281      * the stack if an interrupt occurred at the wrong time.
 282      * We avoid this by disabling interrupts when
 283      * pc contains a magic address.
 284      */
 285     if (interrupt_request & CPU_INTERRUPT_HARD
 286         && !(env->daif & PSTATE_I)
 287         && (env->regs[15] < 0xfffffff0)) {
 288         cs->exception_index = EXCP_IRQ;
 289         cc->do_interrupt(cs);
 290         ret = true;
 291     }
 292     return ret;
 293 }
 294 #endif
 295
 296 #ifndef CONFIG_USER_ONLY
 297 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 298 {
 299     ARMCPU *cpu = opaque;
 300     CPUARMState *env = &cpu->env;
 301     CPUState *cs = CPU(cpu);
 302     static const int mask[] = {
 303         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 304         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 305         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 306         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 307     };
 308
 309     switch (irq) {
 310     case ARM_CPU_VIRQ:
 311     case ARM_CPU_VFIQ:
 312         if (!arm_feature(env, ARM_FEATURE_EL2)) {
 313             hw_error("%s: Virtual interrupt line %d with no EL2 support\n",
 314                      __func__, irq);
 315         }
 316         /* fall through */
 317     case ARM_CPU_IRQ:
 318     case ARM_CPU_FIQ:
 319         if (level) {
 320             cpu_interrupt(cs, mask[irq]);
 321         } else {
 322             cpu_reset_interrupt(cs, mask[irq]);
 323         }
 324         break;
 325     default:
 326         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 327     }
 328 }
 329
 330 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 331 {
 332 #ifdef CONFIG_KVM
 333     ARMCPU *cpu = opaque;
 334     CPUState *cs = CPU(cpu);
 335     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 336
 337     switch (irq) {
 338     case ARM_CPU_IRQ:
 339         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 340         break;
 341     case ARM_CPU_FIQ:
 342         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 343         break;
 344     default:
 345         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 346     }
 347     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 348     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 349 #endif
 350 }
 351
 352 static bool arm_cpu_is_big_endian(CPUState *cs)
 353 {
 354     ARMCPU *cpu = ARM_CPU(cs);
 355     CPUARMState *env = &cpu->env;
 356     int cur_el;
 357
 358     cpu_synchronize_state(cs);
 359
 360     /* In 32bit guest endianness is determined by looking at CPSR's E bit */
 361     if (!is_a64(env)) {
 362         return (env->uncached_cpsr & CPSR_E) ? 1 : 0;
 363     }
 364
 365     cur_el = arm_current_el(env);
 366
 367     if (cur_el == 0) {
 368         return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
 369     }
 370
 371     return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
 372 }
 373
 374 #endif
 375
 376 static inline void set_feature(CPUARMState *env, int feature)
 377 {
 378     env->features |= 1ULL << feature;
 379 }
 380
 381 static inline void unset_feature(CPUARMState *env, int feature)
 382 {
 383     env->features &= ~(1ULL << feature);
 384 }
 385
 386 #define ARM_CPUS_PER_CLUSTER 8
 387
 388 static void arm_cpu_initfn(Object *obj)
 389 {
 390     CPUState *cs = CPU(obj);
 391     ARMCPU *cpu = ARM_CPU(obj);
 392     static bool inited;
 393     uint32_t Aff1, Aff0;
 394
 395     cs->env_ptr = &cpu->env;
 396     cpu_exec_init(&cpu->env);
 397     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 398                                          g_free, g_free);
 399
 400     /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
 401      * We don't support setting cluster ID ([16..23]) (known as Aff2
 402      * in later ARM ARM versions), or any of the higher affinity level fields,
 403      * so these bits always RAZ.
 404      */
 405     Aff1 = cs->cpu_index / ARM_CPUS_PER_CLUSTER;
 406     Aff0 = cs->cpu_index % ARM_CPUS_PER_CLUSTER;
 407     cpu->mp_affinity = (Aff1 << 8) | Aff0;
 408
 409 #ifndef CONFIG_USER_ONLY
 410     /* Our inbound IRQ and FIQ lines */
 411     if (kvm_enabled()) {
 412         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 413          * the same interface as non-KVM CPUs.
 414          */
 415         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 416     } else {
 417         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 418     }
 419
 420     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 421                                                 arm_gt_ptimer_cb, cpu);
 422     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 423                                                 arm_gt_vtimer_cb, cpu);
 424     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 425                        ARRAY_SIZE(cpu->gt_timer_outputs));
 426 #endif
 427
 428     /* DTB consumers generally don't in fact care what the 'compatible'
 429      * string is, so always provide some string and trust that a hypothetical
 430      * picky DTB consumer will also provide a helpful error message.
 431      */
 432     cpu->dtb_compatible = "qemu,unknown";
 433     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 434     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 435
 436     if (tcg_enabled()) {
 437         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 438         if (!inited) {
 439             inited = true;
 440             arm_translate_init();
 441         }
 442     }
 443 }
 444
 445 static Property arm_cpu_reset_cbar_property =
 446             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 447
 448 static Property arm_cpu_reset_hivecs_property =
 449             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 450
 451 static Property arm_cpu_rvbar_property =
 452             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 453
 454 static Property arm_cpu_has_el3_property =
 455             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 456
 457 static Property arm_cpu_has_mpu_property =
 458             DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
 459
 460 static Property arm_cpu_pmsav7_dregion_property =
 461             DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16);
 462
 463 static void arm_cpu_post_init(Object *obj)
 464 {
 465     ARMCPU *cpu = ARM_CPU(obj);
 466
 467     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 468         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 469         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 470                                  &error_abort);
 471     }
 472
 473     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 474         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 475                                  &error_abort);
 476     }
 477
 478     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 479         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 480                                  &error_abort);
 481     }
 482
 483     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
 484         /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
 485          * prevent "has_el3" from existing on CPUs which cannot support EL3.
 486          */
 487         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
 488                                  &error_abort);
 489     }
 490
 491     if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
 492         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
 493                                  &error_abort);
 494         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
 495             qdev_property_add_static(DEVICE(obj),
 496                                      &arm_cpu_pmsav7_dregion_property,
 497                                      &error_abort);
 498         }
 499     }
 500
 501 }
 502
 503 static void arm_cpu_finalizefn(Object *obj)
 504 {
 505     ARMCPU *cpu = ARM_CPU(obj);
 506     g_hash_table_destroy(cpu->cp_regs);
 507 }
 508
 509 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 510 {
 511     CPUState *cs = CPU(dev);
 512     ARMCPU *cpu = ARM_CPU(dev);
 513     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 514     CPUARMState *env = &cpu->env;
 515
 516     /* Some features automatically imply others: */
 517     if (arm_feature(env, ARM_FEATURE_V8)) {
 518         set_feature(env, ARM_FEATURE_V7);
 519         set_feature(env, ARM_FEATURE_ARM_DIV);
 520         set_feature(env, ARM_FEATURE_LPAE);
 521     }
 522     if (arm_feature(env, ARM_FEATURE_V7)) {
 523         set_feature(env, ARM_FEATURE_VAPA);
 524         set_feature(env, ARM_FEATURE_THUMB2);
 525         set_feature(env, ARM_FEATURE_MPIDR);
 526         if (!arm_feature(env, ARM_FEATURE_M)) {
 527             set_feature(env, ARM_FEATURE_V6K);
 528         } else {
 529             set_feature(env, ARM_FEATURE_V6);
 530         }
 531     }
 532     if (arm_feature(env, ARM_FEATURE_V6K)) {
 533         set_feature(env, ARM_FEATURE_V6);
 534         set_feature(env, ARM_FEATURE_MVFR);
 535     }
 536     if (arm_feature(env, ARM_FEATURE_V6)) {
 537         set_feature(env, ARM_FEATURE_V5);
 538         if (!arm_feature(env, ARM_FEATURE_M)) {
 539             set_feature(env, ARM_FEATURE_AUXCR);
 540         }
 541     }
 542     if (arm_feature(env, ARM_FEATURE_V5)) {
 543         set_feature(env, ARM_FEATURE_V4T);
 544     }
 545     if (arm_feature(env, ARM_FEATURE_M)) {
 546         set_feature(env, ARM_FEATURE_THUMB_DIV);
 547     }
 548     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 549         set_feature(env, ARM_FEATURE_THUMB_DIV);
 550     }
 551     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 552         set_feature(env, ARM_FEATURE_VFP3);
 553         set_feature(env, ARM_FEATURE_VFP_FP16);
 554     }
 555     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 556         set_feature(env, ARM_FEATURE_VFP);
 557     }
 558     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 559         set_feature(env, ARM_FEATURE_V7MP);
 560         set_feature(env, ARM_FEATURE_PXN);
 561     }
 562     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 563         set_feature(env, ARM_FEATURE_CBAR);
 564     }
 565     if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 566         !arm_feature(env, ARM_FEATURE_M)) {
 567         set_feature(env, ARM_FEATURE_THUMB_DSP);
 568     }
 569
 570     if (cpu->reset_hivecs) {
 571             cpu->reset_sctlr |= (1 << 13);
 572     }
 573
 574     if (!cpu->has_el3) {
 575         /* If the has_el3 CPU property is disabled then we need to disable the
 576          * feature.
 577          */
 578         unset_feature(env, ARM_FEATURE_EL3);
 579
 580         /* Disable the security extension feature bits in the processor feature
 581          * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
 582          */
 583         cpu->id_pfr1 &= ~0xf0;
 584         cpu->id_aa64pfr0 &= ~0xf000;
 585     }
 586
 587     if (!cpu->has_mpu) {
 588         unset_feature(env, ARM_FEATURE_MPU);
 589     }
 590
 591     if (arm_feature(env, ARM_FEATURE_MPU) &&
 592         arm_feature(env, ARM_FEATURE_V7)) {
 593         uint32_t nr = cpu->pmsav7_dregion;
 594
 595         if (nr > 0xff) {
 596             error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32 "\n", nr);
 597             return;
 598         }
 599
 600         if (nr) {
 601             env->pmsav7.drbar = g_new0(uint32_t, nr);
 602             env->pmsav7.drsr = g_new0(uint32_t, nr);
 603             env->pmsav7.dracr = g_new0(uint32_t, nr);
 604         }
 605     }
 606
 607     register_cp_regs_for_features(cpu);
 608     arm_cpu_register_gdb_regs_for_features(cpu);
 609
 610     init_cpreg_list(cpu);
 611
 612     qemu_init_vcpu(cs);
 613     cpu_reset(cs);
 614
 615     acc->parent_realize(dev, errp);
 616 }
 617
 618 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 619 {
 620     ObjectClass *oc;
 621     char *typename;
 622     char **cpuname;
 623
 624     if (!cpu_model) {
 625         return NULL;
 626     }
 627
 628     cpuname = g_strsplit(cpu_model, ",", 1);
 629     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
 630     oc = object_class_by_name(typename);
 631     g_strfreev(cpuname);
 632     g_free(typename);
 633     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 634         object_class_is_abstract(oc)) {
 635         return NULL;
 636     }
 637     return oc;
 638 }
 639
 640 /* CPU models. These are not needed for the AArch64 linux-user build. */
 641 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 642
 643 static void arm926_initfn(Object *obj)
 644 {
 645     ARMCPU *cpu = ARM_CPU(obj);
 646
 647     cpu->dtb_compatible = "arm,arm926";
 648     set_feature(&cpu->env, ARM_FEATURE_V5);
 649     set_feature(&cpu->env, ARM_FEATURE_VFP);
 650     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 651     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 652     cpu->midr = 0x41069265;
 653     cpu->reset_fpsid = 0x41011090;
 654     cpu->ctr = 0x1dd20d2;
 655     cpu->reset_sctlr = 0x00090078;
 656 }
 657
 658 static void arm946_initfn(Object *obj)
 659 {
 660     ARMCPU *cpu = ARM_CPU(obj);
 661
 662     cpu->dtb_compatible = "arm,arm946";
 663     set_feature(&cpu->env, ARM_FEATURE_V5);
 664     set_feature(&cpu->env, ARM_FEATURE_MPU);
 665     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 666     cpu->midr = 0x41059461;
 667     cpu->ctr = 0x0f004006;
 668     cpu->reset_sctlr = 0x00000078;
 669 }
 670
 671 static void arm1026_initfn(Object *obj)
 672 {
 673     ARMCPU *cpu = ARM_CPU(obj);
 674
 675     cpu->dtb_compatible = "arm,arm1026";
 676     set_feature(&cpu->env, ARM_FEATURE_V5);
 677     set_feature(&cpu->env, ARM_FEATURE_VFP);
 678     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 679     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 680     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 681     cpu->midr = 0x4106a262;
 682     cpu->reset_fpsid = 0x410110a0;
 683     cpu->ctr = 0x1dd20d2;
 684     cpu->reset_sctlr = 0x00090078;
 685     cpu->reset_auxcr = 1;
 686     {
 687         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 688         ARMCPRegInfo ifar = {
 689             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 690             .access = PL1_RW,
 691             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 692             .resetvalue = 0
 693         };
 694         define_one_arm_cp_reg(cpu, &ifar);
 695     }
 696 }
 697
 698 static void arm1136_r2_initfn(Object *obj)
 699 {
 700     ARMCPU *cpu = ARM_CPU(obj);
 701     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 702      * older core than plain "arm1136". In particular this does not
 703      * have the v6K features.
 704      * These ID register values are correct for 1136 but may be wrong
 705      * for 1136_r2 (in particular r0p2 does not actually implement most
 706      * of the ID registers).
 707      */
 708
 709     cpu->dtb_compatible = "arm,arm1136";
 710     set_feature(&cpu->env, ARM_FEATURE_V6);
 711     set_feature(&cpu->env, ARM_FEATURE_VFP);
 712     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 713     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 714     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 715     cpu->midr = 0x4107b362;
 716     cpu->reset_fpsid = 0x410120b4;
 717     cpu->mvfr0 = 0x11111111;
 718     cpu->mvfr1 = 0x00000000;
 719     cpu->ctr = 0x1dd20d2;
 720     cpu->reset_sctlr = 0x00050078;
 721     cpu->id_pfr0 = 0x111;
 722     cpu->id_pfr1 = 0x1;
 723     cpu->id_dfr0 = 0x2;
 724     cpu->id_afr0 = 0x3;
 725     cpu->id_mmfr0 = 0x01130003;
 726     cpu->id_mmfr1 = 0x10030302;
 727     cpu->id_mmfr2 = 0x01222110;
 728     cpu->id_isar0 = 0x00140011;
 729     cpu->id_isar1 = 0x12002111;
 730     cpu->id_isar2 = 0x11231111;
 731     cpu->id_isar3 = 0x01102131;
 732     cpu->id_isar4 = 0x141;
 733     cpu->reset_auxcr = 7;
 734 }
 735
 736 static void arm1136_initfn(Object *obj)
 737 {
 738     ARMCPU *cpu = ARM_CPU(obj);
 739
 740     cpu->dtb_compatible = "arm,arm1136";
 741     set_feature(&cpu->env, ARM_FEATURE_V6K);
 742     set_feature(&cpu->env, ARM_FEATURE_V6);
 743     set_feature(&cpu->env, ARM_FEATURE_VFP);
 744     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 745     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 746     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 747     cpu->midr = 0x4117b363;
 748     cpu->reset_fpsid = 0x410120b4;
 749     cpu->mvfr0 = 0x11111111;
 750     cpu->mvfr1 = 0x00000000;
 751     cpu->ctr = 0x1dd20d2;
 752     cpu->reset_sctlr = 0x00050078;
 753     cpu->id_pfr0 = 0x111;
 754     cpu->id_pfr1 = 0x1;
 755     cpu->id_dfr0 = 0x2;
 756     cpu->id_afr0 = 0x3;
 757     cpu->id_mmfr0 = 0x01130003;
 758     cpu->id_mmfr1 = 0x10030302;
 759     cpu->id_mmfr2 = 0x01222110;
 760     cpu->id_isar0 = 0x00140011;
 761     cpu->id_isar1 = 0x12002111;
 762     cpu->id_isar2 = 0x11231111;
 763     cpu->id_isar3 = 0x01102131;
 764     cpu->id_isar4 = 0x141;
 765     cpu->reset_auxcr = 7;
 766 }
 767
 768 static void arm1176_initfn(Object *obj)
 769 {
 770     ARMCPU *cpu = ARM_CPU(obj);
 771
 772     cpu->dtb_compatible = "arm,arm1176";
 773     set_feature(&cpu->env, ARM_FEATURE_V6K);
 774     set_feature(&cpu->env, ARM_FEATURE_VFP);
 775     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 776     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 777     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 778     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 779     set_feature(&cpu->env, ARM_FEATURE_EL3);
 780     cpu->midr = 0x410fb767;
 781     cpu->reset_fpsid = 0x410120b5;
 782     cpu->mvfr0 = 0x11111111;
 783     cpu->mvfr1 = 0x00000000;
 784     cpu->ctr = 0x1dd20d2;
 785     cpu->reset_sctlr = 0x00050078;
 786     cpu->id_pfr0 = 0x111;
 787     cpu->id_pfr1 = 0x11;
 788     cpu->id_dfr0 = 0x33;
 789     cpu->id_afr0 = 0;
 790     cpu->id_mmfr0 = 0x01130003;
 791     cpu->id_mmfr1 = 0x10030302;
 792     cpu->id_mmfr2 = 0x01222100;
 793     cpu->id_isar0 = 0x0140011;
 794     cpu->id_isar1 = 0x12002111;
 795     cpu->id_isar2 = 0x11231121;
 796     cpu->id_isar3 = 0x01102131;
 797     cpu->id_isar4 = 0x01141;
 798     cpu->reset_auxcr = 7;
 799 }
 800
 801 static void arm11mpcore_initfn(Object *obj)
 802 {
 803     ARMCPU *cpu = ARM_CPU(obj);
 804
 805     cpu->dtb_compatible = "arm,arm11mpcore";
 806     set_feature(&cpu->env, ARM_FEATURE_V6K);
 807     set_feature(&cpu->env, ARM_FEATURE_VFP);
 808     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 809     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 810     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 811     cpu->midr = 0x410fb022;
 812     cpu->reset_fpsid = 0x410120b4;
 813     cpu->mvfr0 = 0x11111111;
 814     cpu->mvfr1 = 0x00000000;
 815     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 816     cpu->id_pfr0 = 0x111;
 817     cpu->id_pfr1 = 0x1;
 818     cpu->id_dfr0 = 0;
 819     cpu->id_afr0 = 0x2;
 820     cpu->id_mmfr0 = 0x01100103;
 821     cpu->id_mmfr1 = 0x10020302;
 822     cpu->id_mmfr2 = 0x01222000;
 823     cpu->id_isar0 = 0x00100011;
 824     cpu->id_isar1 = 0x12002111;
 825     cpu->id_isar2 = 0x11221011;
 826     cpu->id_isar3 = 0x01102131;
 827     cpu->id_isar4 = 0x141;
 828     cpu->reset_auxcr = 1;
 829 }
 830
 831 static void cortex_m3_initfn(Object *obj)
 832 {
 833     ARMCPU *cpu = ARM_CPU(obj);
 834     set_feature(&cpu->env, ARM_FEATURE_V7);
 835     set_feature(&cpu->env, ARM_FEATURE_M);
 836     cpu->midr = 0x410fc231;
 837 }
 838
 839 static void cortex_m4_initfn(Object *obj)
 840 {
 841     ARMCPU *cpu = ARM_CPU(obj);
 842
 843     set_feature(&cpu->env, ARM_FEATURE_V7);
 844     set_feature(&cpu->env, ARM_FEATURE_M);
 845     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 846     cpu->midr = 0x410fc240; /* r0p0 */
 847 }
 848 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 849 {
 850     CPUClass *cc = CPU_CLASS(oc);
 851
 852 #ifndef CONFIG_USER_ONLY
 853     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 854 #endif
 855
 856     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
 857 }
 858
 859 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
 860     /* Dummy the TCM region regs for the moment */
 861     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
 862       .access = PL1_RW, .type = ARM_CP_CONST },
 863     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
 864       .access = PL1_RW, .type = ARM_CP_CONST },
 865     REGINFO_SENTINEL
 866 };
 867
 868 static void cortex_r5_initfn(Object *obj)
 869 {
 870     ARMCPU *cpu = ARM_CPU(obj);
 871
 872     set_feature(&cpu->env, ARM_FEATURE_V7);
 873     set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
 874     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 875     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 876     set_feature(&cpu->env, ARM_FEATURE_MPU);
 877     cpu->midr = 0x411fc153; /* r1p3 */
 878     cpu->id_pfr0 = 0x0131;
 879     cpu->id_pfr1 = 0x001;
 880     cpu->id_dfr0 = 0x010400;
 881     cpu->id_afr0 = 0x0;
 882     cpu->id_mmfr0 = 0x0210030;
 883     cpu->id_mmfr1 = 0x00000000;
 884     cpu->id_mmfr2 = 0x01200000;
 885     cpu->id_mmfr3 = 0x0211;
 886     cpu->id_isar0 = 0x2101111;
 887     cpu->id_isar1 = 0x13112111;
 888     cpu->id_isar2 = 0x21232141;
 889     cpu->id_isar3 = 0x01112131;
 890     cpu->id_isar4 = 0x0010142;
 891     cpu->id_isar5 = 0x0;
 892     cpu->mp_is_up = true;
 893     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
 894 }
 895
 896 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 897     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 898       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 899     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 900       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 901     REGINFO_SENTINEL
 902 };
 903
 904 static void cortex_a8_initfn(Object *obj)
 905 {
 906     ARMCPU *cpu = ARM_CPU(obj);
 907
 908     cpu->dtb_compatible = "arm,cortex-a8";
 909     set_feature(&cpu->env, ARM_FEATURE_V7);
 910     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 911     set_feature(&cpu->env, ARM_FEATURE_NEON);
 912     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 913     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 914     set_feature(&cpu->env, ARM_FEATURE_EL3);
 915     cpu->midr = 0x410fc080;
 916     cpu->reset_fpsid = 0x410330c0;
 917     cpu->mvfr0 = 0x11110222;
 918     cpu->mvfr1 = 0x00011100;
 919     cpu->ctr = 0x82048004;
 920     cpu->reset_sctlr = 0x00c50078;
 921     cpu->id_pfr0 = 0x1031;
 922     cpu->id_pfr1 = 0x11;
 923     cpu->id_dfr0 = 0x400;
 924     cpu->id_afr0 = 0;
 925     cpu->id_mmfr0 = 0x31100003;
 926     cpu->id_mmfr1 = 0x20000000;
 927     cpu->id_mmfr2 = 0x01202000;
 928     cpu->id_mmfr3 = 0x11;
 929     cpu->id_isar0 = 0x00101111;
 930     cpu->id_isar1 = 0x12112111;
 931     cpu->id_isar2 = 0x21232031;
 932     cpu->id_isar3 = 0x11112131;
 933     cpu->id_isar4 = 0x00111142;
 934     cpu->dbgdidr = 0x15141000;
 935     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 936     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 937     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 938     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 939     cpu->reset_auxcr = 2;
 940     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 941 }
 942
 943 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 944     /* power_control should be set to maximum latency. Again,
 945      * default to 0 and set by private hook
 946      */
 947     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 948       .access = PL1_RW, .resetvalue = 0,
 949       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 950     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 951       .access = PL1_RW, .resetvalue = 0,
 952       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 953     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 954       .access = PL1_RW, .resetvalue = 0,
 955       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 956     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 957       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 958     /* TLB lockdown control */
 959     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 960       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 961     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 962       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 963     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 964       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 965     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 966       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 967     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 968       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 969     REGINFO_SENTINEL
 970 };
 971
 972 static void cortex_a9_initfn(Object *obj)
 973 {
 974     ARMCPU *cpu = ARM_CPU(obj);
 975
 976     cpu->dtb_compatible = "arm,cortex-a9";
 977     set_feature(&cpu->env, ARM_FEATURE_V7);
 978     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 979     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 980     set_feature(&cpu->env, ARM_FEATURE_NEON);
 981     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 982     set_feature(&cpu->env, ARM_FEATURE_EL3);
 983     /* Note that A9 supports the MP extensions even for
 984      * A9UP and single-core A9MP (which are both different
 985      * and valid configurations; we don't model A9UP).
 986      */
 987     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 988     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 989     cpu->midr = 0x410fc090;
 990     cpu->reset_fpsid = 0x41033090;
 991     cpu->mvfr0 = 0x11110222;
 992     cpu->mvfr1 = 0x01111111;
 993     cpu->ctr = 0x80038003;
 994     cpu->reset_sctlr = 0x00c50078;
 995     cpu->id_pfr0 = 0x1031;
 996     cpu->id_pfr1 = 0x11;
 997     cpu->id_dfr0 = 0x000;
 998     cpu->id_afr0 = 0;
 999     cpu->id_mmfr0 = 0x00100103;
1000     cpu->id_mmfr1 = 0x20000000;
1001     cpu->id_mmfr2 = 0x01230000;
1002     cpu->id_mmfr3 = 0x00002111;
1003     cpu->id_isar0 = 0x00101111;
1004     cpu->id_isar1 = 0x13112111;
1005     cpu->id_isar2 = 0x21232041;
1006     cpu->id_isar3 = 0x11112131;
1007     cpu->id_isar4 = 0x00111142;
1008     cpu->dbgdidr = 0x35141000;
1009     cpu->clidr = (1 << 27) | (1 << 24) | 3;
1010     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
1011     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
1012     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1013 }
1014
1015 #ifndef CONFIG_USER_ONLY
1016 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1017 {
1018     /* Linux wants the number of processors from here.
1019      * Might as well set the interrupt-controller bit too.
1020      */
1021     return ((smp_cpus - 1) << 24) | (1 << 23);
1022 }
1023 #endif
1024
1025 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1026 #ifndef CONFIG_USER_ONLY
1027     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1028       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1029       .writefn = arm_cp_write_ignore, },
1030 #endif
1031     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1032       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1033     REGINFO_SENTINEL
1034 };
1035
1036 static void cortex_a15_initfn(Object *obj)
1037 {
1038     ARMCPU *cpu = ARM_CPU(obj);
1039
1040     cpu->dtb_compatible = "arm,cortex-a15";
1041     set_feature(&cpu->env, ARM_FEATURE_V7);
1042     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1043     set_feature(&cpu->env, ARM_FEATURE_NEON);
1044     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1045     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1046     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1047     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1048     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1049     set_feature(&cpu->env, ARM_FEATURE_LPAE);
1050     set_feature(&cpu->env, ARM_FEATURE_EL3);
1051     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1052     cpu->midr = 0x412fc0f1;
1053     cpu->reset_fpsid = 0x410430f0;
1054     cpu->mvfr0 = 0x10110222;
1055     cpu->mvfr1 = 0x11111111;
1056     cpu->ctr = 0x8444c004;
1057     cpu->reset_sctlr = 0x00c50078;
1058     cpu->id_pfr0 = 0x00001131;
1059     cpu->id_pfr1 = 0x00011011;
1060     cpu->id_dfr0 = 0x02010555;
1061     cpu->id_afr0 = 0x00000000;
1062     cpu->id_mmfr0 = 0x10201105;
1063     cpu->id_mmfr1 = 0x20000000;
1064     cpu->id_mmfr2 = 0x01240000;
1065     cpu->id_mmfr3 = 0x02102211;
1066     cpu->id_isar0 = 0x02101110;
1067     cpu->id_isar1 = 0x13112111;
1068     cpu->id_isar2 = 0x21232041;
1069     cpu->id_isar3 = 0x11112131;
1070     cpu->id_isar4 = 0x10011142;
1071     cpu->dbgdidr = 0x3515f021;
1072     cpu->clidr = 0x0a200023;
1073     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1074     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1075     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1076     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1077 }
1078
1079 static void ti925t_initfn(Object *obj)
1080 {
1081     ARMCPU *cpu = ARM_CPU(obj);
1082     set_feature(&cpu->env, ARM_FEATURE_V4T);
1083     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1084     cpu->midr = ARM_CPUID_TI925T;
1085     cpu->ctr = 0x5109149;
1086     cpu->reset_sctlr = 0x00000070;
1087 }
1088
1089 static void sa1100_initfn(Object *obj)
1090 {
1091     ARMCPU *cpu = ARM_CPU(obj);
1092
1093     cpu->dtb_compatible = "intel,sa1100";
1094     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1095     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1096     cpu->midr = 0x4401A11B;
1097     cpu->reset_sctlr = 0x00000070;
1098 }
1099
1100 static void sa1110_initfn(Object *obj)
1101 {
1102     ARMCPU *cpu = ARM_CPU(obj);
1103     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1104     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1105     cpu->midr = 0x6901B119;
1106     cpu->reset_sctlr = 0x00000070;
1107 }
1108
1109 static void pxa250_initfn(Object *obj)
1110 {
1111     ARMCPU *cpu = ARM_CPU(obj);
1112
1113     cpu->dtb_compatible = "marvell,xscale";
1114     set_feature(&cpu->env, ARM_FEATURE_V5);
1115     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1116     cpu->midr = 0x69052100;
1117     cpu->ctr = 0xd172172;
1118     cpu->reset_sctlr = 0x00000078;
1119 }
1120
1121 static void pxa255_initfn(Object *obj)
1122 {
1123     ARMCPU *cpu = ARM_CPU(obj);
1124
1125     cpu->dtb_compatible = "marvell,xscale";
1126     set_feature(&cpu->env, ARM_FEATURE_V5);
1127     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1128     cpu->midr = 0x69052d00;
1129     cpu->ctr = 0xd172172;
1130     cpu->reset_sctlr = 0x00000078;
1131 }
1132
1133 static void pxa260_initfn(Object *obj)
1134 {
1135     ARMCPU *cpu = ARM_CPU(obj);
1136
1137     cpu->dtb_compatible = "marvell,xscale";
1138     set_feature(&cpu->env, ARM_FEATURE_V5);
1139     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1140     cpu->midr = 0x69052903;
1141     cpu->ctr = 0xd172172;
1142     cpu->reset_sctlr = 0x00000078;
1143 }
1144
1145 static void pxa261_initfn(Object *obj)
1146 {
1147     ARMCPU *cpu = ARM_CPU(obj);
1148
1149     cpu->dtb_compatible = "marvell,xscale";
1150     set_feature(&cpu->env, ARM_FEATURE_V5);
1151     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1152     cpu->midr = 0x69052d05;
1153     cpu->ctr = 0xd172172;
1154     cpu->reset_sctlr = 0x00000078;
1155 }
1156
1157 static void pxa262_initfn(Object *obj)
1158 {
1159     ARMCPU *cpu = ARM_CPU(obj);
1160
1161     cpu->dtb_compatible = "marvell,xscale";
1162     set_feature(&cpu->env, ARM_FEATURE_V5);
1163     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1164     cpu->midr = 0x69052d06;
1165     cpu->ctr = 0xd172172;
1166     cpu->reset_sctlr = 0x00000078;
1167 }
1168
1169 static void pxa270a0_initfn(Object *obj)
1170 {
1171     ARMCPU *cpu = ARM_CPU(obj);
1172
1173     cpu->dtb_compatible = "marvell,xscale";
1174     set_feature(&cpu->env, ARM_FEATURE_V5);
1175     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1176     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1177     cpu->midr = 0x69054110;
1178     cpu->ctr = 0xd172172;
1179     cpu->reset_sctlr = 0x00000078;
1180 }
1181
1182 static void pxa270a1_initfn(Object *obj)
1183 {
1184     ARMCPU *cpu = ARM_CPU(obj);
1185
1186     cpu->dtb_compatible = "marvell,xscale";
1187     set_feature(&cpu->env, ARM_FEATURE_V5);
1188     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1189     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1190     cpu->midr = 0x69054111;
1191     cpu->ctr = 0xd172172;
1192     cpu->reset_sctlr = 0x00000078;
1193 }
1194
1195 static void pxa270b0_initfn(Object *obj)
1196 {
1197     ARMCPU *cpu = ARM_CPU(obj);
1198
1199     cpu->dtb_compatible = "marvell,xscale";
1200     set_feature(&cpu->env, ARM_FEATURE_V5);
1201     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1202     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1203     cpu->midr = 0x69054112;
1204     cpu->ctr = 0xd172172;
1205     cpu->reset_sctlr = 0x00000078;
1206 }
1207
1208 static void pxa270b1_initfn(Object *obj)
1209 {
1210     ARMCPU *cpu = ARM_CPU(obj);
1211
1212     cpu->dtb_compatible = "marvell,xscale";
1213     set_feature(&cpu->env, ARM_FEATURE_V5);
1214     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1215     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1216     cpu->midr = 0x69054113;
1217     cpu->ctr = 0xd172172;
1218     cpu->reset_sctlr = 0x00000078;
1219 }
1220
1221 static void pxa270c0_initfn(Object *obj)
1222 {
1223     ARMCPU *cpu = ARM_CPU(obj);
1224
1225     cpu->dtb_compatible = "marvell,xscale";
1226     set_feature(&cpu->env, ARM_FEATURE_V5);
1227     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1228     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1229     cpu->midr = 0x69054114;
1230     cpu->ctr = 0xd172172;
1231     cpu->reset_sctlr = 0x00000078;
1232 }
1233
1234 static void pxa270c5_initfn(Object *obj)
1235 {
1236     ARMCPU *cpu = ARM_CPU(obj);
1237
1238     cpu->dtb_compatible = "marvell,xscale";
1239     set_feature(&cpu->env, ARM_FEATURE_V5);
1240     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1241     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1242     cpu->midr = 0x69054117;
1243     cpu->ctr = 0xd172172;
1244     cpu->reset_sctlr = 0x00000078;
1245 }
1246
1247 #ifdef CONFIG_USER_ONLY
1248 static void arm_any_initfn(Object *obj)
1249 {
1250     ARMCPU *cpu = ARM_CPU(obj);
1251     set_feature(&cpu->env, ARM_FEATURE_V8);
1252     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1253     set_feature(&cpu->env, ARM_FEATURE_NEON);
1254     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1255     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1256     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1257     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1258     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1259     set_feature(&cpu->env, ARM_FEATURE_CRC);
1260     cpu->midr = 0xffffffff;
1261 }
1262 #endif
1263
1264 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1265
1266 typedef struct ARMCPUInfo {
1267     const char *name;
1268     void (*initfn)(Object *obj);
1269     void (*class_init)(ObjectClass *oc, void *data);
1270 } ARMCPUInfo;
1271
1272 static const ARMCPUInfo arm_cpus[] = {
1273 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1274     { .name = "arm926",      .initfn = arm926_initfn },
1275     { .name = "arm946",      .initfn = arm946_initfn },
1276     { .name = "arm1026",     .initfn = arm1026_initfn },
1277     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1278      * older core than plain "arm1136". In particular this does not
1279      * have the v6K features.
1280      */
1281     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1282     { .name = "arm1136",     .initfn = arm1136_initfn },
1283     { .name = "arm1176",     .initfn = arm1176_initfn },
1284     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1285     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1286                              .class_init = arm_v7m_class_init },
1287     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
1288                              .class_init = arm_v7m_class_init },
1289     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
1290     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1291     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1292     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1293     { .name = "ti925t",      .initfn = ti925t_initfn },
1294     { .name = "sa1100",      .initfn = sa1100_initfn },
1295     { .name = "sa1110",      .initfn = sa1110_initfn },
1296     { .name = "pxa250",      .initfn = pxa250_initfn },
1297     { .name = "pxa255",      .initfn = pxa255_initfn },
1298     { .name = "pxa260",      .initfn = pxa260_initfn },
1299     { .name = "pxa261",      .initfn = pxa261_initfn },
1300     { .name = "pxa262",      .initfn = pxa262_initfn },
1301     /* "pxa270" is an alias for "pxa270-a0" */
1302     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1303     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1304     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1305     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1306     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1307     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1308     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1309 #ifdef CONFIG_USER_ONLY
1310     { .name = "any",         .initfn = arm_any_initfn },
1311 #endif
1312 #endif
1313     { .name = NULL }
1314 };
1315
1316 static Property arm_cpu_properties[] = {
1317     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1318     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1319     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1320     DEFINE_PROP_END_OF_LIST()
1321 };
1322
1323 #ifdef CONFIG_USER_ONLY
1324 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
1325                                     int mmu_idx)
1326 {
1327     ARMCPU *cpu = ARM_CPU(cs);
1328     CPUARMState *env = &cpu->env;
1329
1330     env->exception.vaddress = address;
1331     if (rw == 2) {
1332         cs->exception_index = EXCP_PREFETCH_ABORT;
1333     } else {
1334         cs->exception_index = EXCP_DATA_ABORT;
1335     }
1336     return 1;
1337 }
1338 #endif
1339
1340 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1341 {
1342     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1343     CPUClass *cc = CPU_CLASS(acc);
1344     DeviceClass *dc = DEVICE_CLASS(oc);
1345
1346     acc->parent_realize = dc->realize;
1347     dc->realize = arm_cpu_realizefn;
1348     dc->props = arm_cpu_properties;
1349
1350     acc->parent_reset = cc->reset;
1351     cc->reset = arm_cpu_reset;
1352
1353     cc->class_by_name = arm_cpu_class_by_name;
1354     cc->has_work = arm_cpu_has_work;
1355     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1356     cc->dump_state = arm_cpu_dump_state;
1357     cc->set_pc = arm_cpu_set_pc;
1358     cc->gdb_read_register = arm_cpu_gdb_read_register;
1359     cc->gdb_write_register = arm_cpu_gdb_write_register;
1360 #ifdef CONFIG_USER_ONLY
1361     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1362 #else
1363     cc->do_interrupt = arm_cpu_do_interrupt;
1364     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1365     cc->vmsd = &vmstate_arm_cpu;
1366     cc->virtio_is_big_endian = arm_cpu_is_big_endian;
1367 #endif
1368     cc->gdb_num_core_regs = 26;
1369     cc->gdb_core_xml_file = "arm-core.xml";
1370     cc->gdb_stop_before_watchpoint = true;
1371     cc->debug_excp_handler = arm_debug_excp_handler;
1372 }
1373
1374 static void cpu_register(const ARMCPUInfo *info)
1375 {
1376     TypeInfo type_info = {
1377         .parent = TYPE_ARM_CPU,
1378         .instance_size = sizeof(ARMCPU),
1379         .instance_init = info->initfn,
1380         .class_size = sizeof(ARMCPUClass),
1381         .class_init = info->class_init,
1382     };
1383
1384     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1385     type_register(&type_info);
1386     g_free((void *)type_info.name);
1387 }
1388
1389 static const TypeInfo arm_cpu_type_info = {
1390     .name = TYPE_ARM_CPU,
1391     .parent = TYPE_CPU,
1392     .instance_size = sizeof(ARMCPU),
1393     .instance_init = arm_cpu_initfn,
1394     .instance_post_init = arm_cpu_post_init,
1395     .instance_finalize = arm_cpu_finalizefn,
1396     .abstract = true,
1397     .class_size = sizeof(ARMCPUClass),
1398     .class_init = arm_cpu_class_init,
1399 };
1400
1401 static void arm_cpu_register_types(void)
1402 {
1403     const ARMCPUInfo *info = arm_cpus;
1404
1405     type_register_static(&arm_cpu_type_info);
1406
1407     while (info->name) {
1408         cpu_register(info);
1409         info++;
1410     }
1411 }
1412
1413 type_init(arm_cpu_register_types)