target/i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include "qemu/osdep.h"
  16 #include "qapi/error.h"
  17 #include <sys/ioctl.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include "standard-headers/asm-x86/kvm_para.h"
  22
  23 #include "qemu-common.h"
  24 #include "cpu.h"
  25 #include "sysemu/sysemu.h"
  26 #include "sysemu/hw_accel.h"
  27 #include "sysemu/kvm_int.h"
  28 #include "kvm_i386.h"
  29 #include "hyperv.h"
  30 #include "hyperv-proto.h"
  31
  32 #include "exec/gdbstub.h"
  33 #include "qemu/host-utils.h"
  34 #include "qemu/config-file.h"
  35 #include "qemu/error-report.h"
  36 #include "hw/i386/pc.h"
  37 #include "hw/i386/apic.h"
  38 #include "hw/i386/apic_internal.h"
  39 #include "hw/i386/apic-msidef.h"
  40 #include "hw/i386/intel_iommu.h"
  41 #include "hw/i386/x86-iommu.h"
  42
  43 #include "hw/pci/pci.h"
  44 #include "hw/pci/msi.h"
  45 #include "hw/pci/msix.h"
  46 #include "migration/blocker.h"
  47 #include "exec/memattrs.h"
  48 #include "trace.h"
  49
  50 //#define DEBUG_KVM
  51
  52 #ifdef DEBUG_KVM
  53 #define DPRINTF(fmt, ...) \
  54     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  55 #else
  56 #define DPRINTF(fmt, ...) \
  57     do { } while (0)
  58 #endif
  59
  60 #define MSR_KVM_WALL_CLOCK  0x11
  61 #define MSR_KVM_SYSTEM_TIME 0x12
  62
  63 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
  64  * 255 kvm_msr_entry structs */
  65 #define MSR_BUF_SIZE 4096
  66
  67 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  68     KVM_CAP_INFO(SET_TSS_ADDR),
  69     KVM_CAP_INFO(EXT_CPUID),
  70     KVM_CAP_INFO(MP_STATE),
  71     KVM_CAP_LAST_INFO
  72 };
  73
  74 static bool has_msr_star;
  75 static bool has_msr_hsave_pa;
  76 static bool has_msr_tsc_aux;
  77 static bool has_msr_tsc_adjust;
  78 static bool has_msr_tsc_deadline;
  79 static bool has_msr_feature_control;
  80 static bool has_msr_misc_enable;
  81 static bool has_msr_smbase;
  82 static bool has_msr_bndcfgs;
  83 static int lm_capable_kernel;
  84 static bool has_msr_hv_hypercall;
  85 static bool has_msr_hv_crash;
  86 static bool has_msr_hv_reset;
  87 static bool has_msr_hv_vpindex;
  88 static bool hv_vpindex_settable;
  89 static bool has_msr_hv_runtime;
  90 static bool has_msr_hv_synic;
  91 static bool has_msr_hv_stimer;
  92 static bool has_msr_hv_frequencies;
  93 static bool has_msr_hv_reenlightenment;
  94 static bool has_msr_xss;
  95 static bool has_msr_spec_ctrl;
  96 static bool has_msr_virt_ssbd;
  97 static bool has_msr_smi_count;
  98
  99 static uint32_t has_architectural_pmu_version;
 100 static uint32_t num_architectural_pmu_gp_counters;
 101 static uint32_t num_architectural_pmu_fixed_counters;
 102
 103 static int has_xsave;
 104 static int has_xcrs;
 105 static int has_pit_state2;
 106
 107 static bool has_msr_mcg_ext_ctl;
 108
 109 static struct kvm_cpuid2 *cpuid_cache;
 110
 111 int kvm_has_pit_state2(void)
 112 {
 113     return has_pit_state2;
 114 }
 115
 116 bool kvm_has_smm(void)
 117 {
 118     return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
 119 }
 120
 121 bool kvm_has_adjust_clock_stable(void)
 122 {
 123     int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
 124
 125     return (ret == KVM_CLOCK_TSC_STABLE);
 126 }
 127
 128 bool kvm_allows_irq0_override(void)
 129 {
 130     return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
 131 }
 132
 133 static bool kvm_x2apic_api_set_flags(uint64_t flags)
 134 {
 135     KVMState *s = KVM_STATE(current_machine->accelerator);
 136
 137     return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
 138 }
 139
 140 #define MEMORIZE(fn, _result) \
 141     ({ \
 142         static bool _memorized; \
 143         \
 144         if (_memorized) { \
 145             return _result; \
 146         } \
 147         _memorized = true; \
 148         _result = fn; \
 149     })
 150
 151 static bool has_x2apic_api;
 152
 153 bool kvm_has_x2apic_api(void)
 154 {
 155     return has_x2apic_api;
 156 }
 157
 158 bool kvm_enable_x2apic(void)
 159 {
 160     return MEMORIZE(
 161              kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
 162                                       KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
 163              has_x2apic_api);
 164 }
 165
 166 bool kvm_hv_vpindex_settable(void)
 167 {
 168     return hv_vpindex_settable;
 169 }
 170
 171 static int kvm_get_tsc(CPUState *cs)
 172 {
 173     X86CPU *cpu = X86_CPU(cs);
 174     CPUX86State *env = &cpu->env;
 175     struct {
 176         struct kvm_msrs info;
 177         struct kvm_msr_entry entries[1];
 178     } msr_data;
 179     int ret;
 180
 181     if (env->tsc_valid) {
 182         return 0;
 183     }
 184
 185     msr_data.info.nmsrs = 1;
 186     msr_data.entries[0].index = MSR_IA32_TSC;
 187     env->tsc_valid = !runstate_is_running();
 188
 189     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
 190     if (ret < 0) {
 191         return ret;
 192     }
 193
 194     assert(ret == 1);
 195     env->tsc = msr_data.entries[0].data;
 196     return 0;
 197 }
 198
 199 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
 200 {
 201     kvm_get_tsc(cpu);
 202 }
 203
 204 void kvm_synchronize_all_tsc(void)
 205 {
 206     CPUState *cpu;
 207
 208     if (kvm_enabled()) {
 209         CPU_FOREACH(cpu) {
 210             run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
 211         }
 212     }
 213 }
 214
 215 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
 216 {
 217     struct kvm_cpuid2 *cpuid;
 218     int r, size;
 219
 220     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
 221     cpuid = g_malloc0(size);
 222     cpuid->nent = max;
 223     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
 224     if (r == 0 && cpuid->nent >= max) {
 225         r = -E2BIG;
 226     }
 227     if (r < 0) {
 228         if (r == -E2BIG) {
 229             g_free(cpuid);
 230             return NULL;
 231         } else {
 232             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
 233                     strerror(-r));
 234             exit(1);
 235         }
 236     }
 237     return cpuid;
 238 }
 239
 240 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
 241  * for all entries.
 242  */
 243 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
 244 {
 245     struct kvm_cpuid2 *cpuid;
 246     int max = 1;
 247
 248     if (cpuid_cache != NULL) {
 249         return cpuid_cache;
 250     }
 251     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 252         max *= 2;
 253     }
 254     cpuid_cache = cpuid;
 255     return cpuid;
 256 }
 257
 258 static const struct kvm_para_features {
 259     int cap;
 260     int feature;
 261 } para_features[] = {
 262     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 263     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 264     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 265     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 266 };
 267
 268 static int get_para_features(KVMState *s)
 269 {
 270     int i, features = 0;
 271
 272     for (i = 0; i < ARRAY_SIZE(para_features); i++) {
 273         if (kvm_check_extension(s, para_features[i].cap)) {
 274             features |= (1 << para_features[i].feature);
 275         }
 276     }
 277
 278     return features;
 279 }
 280
 281 static bool host_tsx_blacklisted(void)
 282 {
 283     int family, model, stepping;\
 284     char vendor[CPUID_VENDOR_SZ + 1];
 285
 286     host_vendor_fms(vendor, &family, &model, &stepping);
 287
 288     /* Check if we are running on a Haswell host known to have broken TSX */
 289     return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
 290            (family == 6) &&
 291            ((model == 63 && stepping < 4) ||
 292             model == 60 || model == 69 || model == 70);
 293 }
 294
 295 /* Returns the value for a specific register on the cpuid entry
 296  */
 297 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
 298 {
 299     uint32_t ret = 0;
 300     switch (reg) {
 301     case R_EAX:
 302         ret = entry->eax;
 303         break;
 304     case R_EBX:
 305         ret = entry->ebx;
 306         break;
 307     case R_ECX:
 308         ret = entry->ecx;
 309         break;
 310     case R_EDX:
 311         ret = entry->edx;
 312         break;
 313     }
 314     return ret;
 315 }
 316
 317 /* Find matching entry for function/index on kvm_cpuid2 struct
 318  */
 319 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
 320                                                  uint32_t function,
 321                                                  uint32_t index)
 322 {
 323     int i;
 324     for (i = 0; i < cpuid->nent; ++i) {
 325         if (cpuid->entries[i].function == function &&
 326             cpuid->entries[i].index == index) {
 327             return &cpuid->entries[i];
 328         }
 329     }
 330     /* not found: */
 331     return NULL;
 332 }
 333
 334 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 335                                       uint32_t index, int reg)
 336 {
 337     struct kvm_cpuid2 *cpuid;
 338     uint32_t ret = 0;
 339     uint32_t cpuid_1_edx;
 340     bool found = false;
 341
 342     cpuid = get_supported_cpuid(s);
 343
 344     struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
 345     if (entry) {
 346         found = true;
 347         ret = cpuid_entry_get_reg(entry, reg);
 348     }
 349
 350     /* Fixups for the data returned by KVM, below */
 351
 352     if (function == 1 && reg == R_EDX) {
 353         /* KVM before 2.6.30 misreports the following features */
 354         ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 355     } else if (function == 1 && reg == R_ECX) {
 356         /* We can set the hypervisor flag, even if KVM does not return it on
 357          * GET_SUPPORTED_CPUID
 358          */
 359         ret |= CPUID_EXT_HYPERVISOR;
 360         /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
 361          * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
 362          * and the irqchip is in the kernel.
 363          */
 364         if (kvm_irqchip_in_kernel() &&
 365                 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
 366             ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
 367         }
 368
 369         /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
 370          * without the in-kernel irqchip
 371          */
 372         if (!kvm_irqchip_in_kernel()) {
 373             ret &= ~CPUID_EXT_X2APIC;
 374         }
 375
 376         if (enable_cpu_pm) {
 377             int disable_exits = kvm_check_extension(s,
 378                                                     KVM_CAP_X86_DISABLE_EXITS);
 379
 380             if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
 381                 ret |= CPUID_EXT_MONITOR;
 382             }
 383         }
 384     } else if (function == 6 && reg == R_EAX) {
 385         ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
 386     } else if (function == 7 && index == 0 && reg == R_EBX) {
 387         if (host_tsx_blacklisted()) {
 388             ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
 389         }
 390     } else if (function == 0x80000001 && reg == R_ECX) {
 391         /*
 392          * It's safe to enable TOPOEXT even if it's not returned by
 393          * GET_SUPPORTED_CPUID.  Unconditionally enabling TOPOEXT here allows
 394          * us to keep CPU models including TOPOEXT runnable on older kernels.
 395          */
 396         ret |= CPUID_EXT3_TOPOEXT;
 397     } else if (function == 0x80000001 && reg == R_EDX) {
 398         /* On Intel, kvm returns cpuid according to the Intel spec,
 399          * so add missing bits according to the AMD spec:
 400          */
 401         cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 402         ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
 403     } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
 404         /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
 405          * be enabled without the in-kernel irqchip
 406          */
 407         if (!kvm_irqchip_in_kernel()) {
 408             ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
 409         }
 410     } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
 411         ret |= 1U << KVM_HINTS_REALTIME;
 412         found = 1;
 413     }
 414
 415     /* fallback for older kernels */
 416     if ((function == KVM_CPUID_FEATURES) && !found) {
 417         ret = get_para_features(s);
 418     }
 419
 420     return ret;
 421 }
 422
 423 typedef struct HWPoisonPage {
 424     ram_addr_t ram_addr;
 425     QLIST_ENTRY(HWPoisonPage) list;
 426 } HWPoisonPage;
 427
 428 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 429     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 430
 431 static void kvm_unpoison_all(void *param)
 432 {
 433     HWPoisonPage *page, *next_page;
 434
 435     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 436         QLIST_REMOVE(page, list);
 437         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 438         g_free(page);
 439     }
 440 }
 441
 442 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 443 {
 444     HWPoisonPage *page;
 445
 446     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 447         if (page->ram_addr == ram_addr) {
 448             return;
 449         }
 450     }
 451     page = g_new(HWPoisonPage, 1);
 452     page->ram_addr = ram_addr;
 453     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 454 }
 455
 456 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 457                                      int *max_banks)
 458 {
 459     int r;
 460
 461     r = kvm_check_extension(s, KVM_CAP_MCE);
 462     if (r > 0) {
 463         *max_banks = r;
 464         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 465     }
 466     return -ENOSYS;
 467 }
 468
 469 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
 470 {
 471     CPUState *cs = CPU(cpu);
 472     CPUX86State *env = &cpu->env;
 473     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 474                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 475     uint64_t mcg_status = MCG_STATUS_MCIP;
 476     int flags = 0;
 477
 478     if (code == BUS_MCEERR_AR) {
 479         status |= MCI_STATUS_AR | 0x134;
 480         mcg_status |= MCG_STATUS_EIPV;
 481     } else {
 482         status |= 0xc0;
 483         mcg_status |= MCG_STATUS_RIPV;
 484     }
 485
 486     flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
 487     /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
 488      * guest kernel back into env->mcg_ext_ctl.
 489      */
 490     cpu_synchronize_state(cs);
 491     if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
 492         mcg_status |= MCG_STATUS_LMCE;
 493         flags = 0;
 494     }
 495
 496     cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
 497                        (MCM_ADDR_PHYS << 6) | 0xc, flags);
 498 }
 499
 500 static void hardware_memory_error(void)
 501 {
 502     fprintf(stderr, "Hardware memory error!\n");
 503     exit(1);
 504 }
 505
 506 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
 507 {
 508     X86CPU *cpu = X86_CPU(c);
 509     CPUX86State *env = &cpu->env;
 510     ram_addr_t ram_addr;
 511     hwaddr paddr;
 512
 513     /* If we get an action required MCE, it has been injected by KVM
 514      * while the VM was running.  An action optional MCE instead should
 515      * be coming from the main thread, which qemu_init_sigbus identifies
 516      * as the "early kill" thread.
 517      */
 518     assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
 519
 520     if ((env->mcg_cap & MCG_SER_P) && addr) {
 521         ram_addr = qemu_ram_addr_from_host(addr);
 522         if (ram_addr != RAM_ADDR_INVALID &&
 523             kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
 524             kvm_hwpoison_page_add(ram_addr);
 525             kvm_mce_inject(cpu, paddr, code);
 526             return;
 527         }
 528
 529         fprintf(stderr, "Hardware memory error for memory used by "
 530                 "QEMU itself instead of guest system!\n");
 531     }
 532
 533     if (code == BUS_MCEERR_AR) {
 534         hardware_memory_error();
 535     }
 536
 537     /* Hope we are lucky for AO MCE */
 538 }
 539
 540 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
 541 {
 542     CPUX86State *env = &cpu->env;
 543
 544     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 545         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 546         struct kvm_x86_mce mce;
 547
 548         env->exception_injected = -1;
 549
 550         /*
 551          * There must be at least one bank in use if an MCE is pending.
 552          * Find it and use its values for the event injection.
 553          */
 554         for (bank = 0; bank < bank_num; bank++) {
 555             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 556                 break;
 557             }
 558         }
 559         assert(bank < bank_num);
 560
 561         mce.bank = bank;
 562         mce.status = env->mce_banks[bank * 4 + 1];
 563         mce.mcg_status = env->mcg_status;
 564         mce.addr = env->mce_banks[bank * 4 + 2];
 565         mce.misc = env->mce_banks[bank * 4 + 3];
 566
 567         return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
 568     }
 569     return 0;
 570 }
 571
 572 static void cpu_update_state(void *opaque, int running, RunState state)
 573 {
 574     CPUX86State *env = opaque;
 575
 576     if (running) {
 577         env->tsc_valid = false;
 578     }
 579 }
 580
 581 unsigned long kvm_arch_vcpu_id(CPUState *cs)
 582 {
 583     X86CPU *cpu = X86_CPU(cs);
 584     return cpu->apic_id;
 585 }
 586
 587 #ifndef KVM_CPUID_SIGNATURE_NEXT
 588 #define KVM_CPUID_SIGNATURE_NEXT                0x40000100
 589 #endif
 590
 591 static bool hyperv_hypercall_available(X86CPU *cpu)
 592 {
 593     return cpu->hyperv_vapic ||
 594            (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
 595 }
 596
 597 static bool hyperv_enabled(X86CPU *cpu)
 598 {
 599     CPUState *cs = CPU(cpu);
 600     return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
 601            (hyperv_hypercall_available(cpu) ||
 602             cpu->hyperv_time  ||
 603             cpu->hyperv_relaxed_timing ||
 604             cpu->hyperv_crash ||
 605             cpu->hyperv_reset ||
 606             cpu->hyperv_vpindex ||
 607             cpu->hyperv_runtime ||
 608             cpu->hyperv_synic ||
 609             cpu->hyperv_stimer ||
 610             cpu->hyperv_reenlightenment ||
 611             cpu->hyperv_tlbflush ||
 612             cpu->hyperv_ipi);
 613 }
 614
 615 static int kvm_arch_set_tsc_khz(CPUState *cs)
 616 {
 617     X86CPU *cpu = X86_CPU(cs);
 618     CPUX86State *env = &cpu->env;
 619     int r;
 620
 621     if (!env->tsc_khz) {
 622         return 0;
 623     }
 624
 625     r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
 626         kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
 627         -ENOTSUP;
 628     if (r < 0) {
 629         /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
 630          * TSC frequency doesn't match the one we want.
 631          */
 632         int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
 633                        kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
 634                        -ENOTSUP;
 635         if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
 636             warn_report("TSC frequency mismatch between "
 637                         "VM (%" PRId64 " kHz) and host (%d kHz), "
 638                         "and TSC scaling unavailable",
 639                         env->tsc_khz, cur_freq);
 640             return r;
 641         }
 642     }
 643
 644     return 0;
 645 }
 646
 647 static bool tsc_is_stable_and_known(CPUX86State *env)
 648 {
 649     if (!env->tsc_khz) {
 650         return false;
 651     }
 652     return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
 653         || env->user_tsc_khz;
 654 }
 655
 656 static int hyperv_handle_properties(CPUState *cs)
 657 {
 658     X86CPU *cpu = X86_CPU(cs);
 659     CPUX86State *env = &cpu->env;
 660
 661     if (cpu->hyperv_relaxed_timing) {
 662         env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
 663     }
 664     if (cpu->hyperv_vapic) {
 665         env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
 666         env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
 667     }
 668     if (cpu->hyperv_time) {
 669         if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
 670             fprintf(stderr, "Hyper-V clocksources "
 671                     "(requested by 'hv-time' cpu flag) "
 672                     "are not supported by kernel\n");
 673             return -ENOSYS;
 674         }
 675         env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
 676         env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
 677         env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
 678     }
 679     if (cpu->hyperv_frequencies) {
 680         if (!has_msr_hv_frequencies) {
 681             fprintf(stderr, "Hyper-V frequency MSRs "
 682                     "(requested by 'hv-frequencies' cpu flag) "
 683                     "are not supported by kernel\n");
 684             return -ENOSYS;
 685         }
 686         env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
 687         env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
 688     }
 689     if (cpu->hyperv_crash) {
 690         if (!has_msr_hv_crash) {
 691             fprintf(stderr, "Hyper-V crash MSRs "
 692                     "(requested by 'hv-crash' cpu flag) "
 693                     "are not supported by kernel\n");
 694             return -ENOSYS;
 695         }
 696         env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
 697     }
 698     if (cpu->hyperv_reenlightenment) {
 699         if (!has_msr_hv_reenlightenment) {
 700             fprintf(stderr,
 701                     "Hyper-V Reenlightenment MSRs "
 702                     "(requested by 'hv-reenlightenment' cpu flag) "
 703                     "are not supported by kernel\n");
 704             return -ENOSYS;
 705         }
 706         env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
 707     }
 708     env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
 709     if (cpu->hyperv_reset) {
 710         if (!has_msr_hv_reset) {
 711             fprintf(stderr, "Hyper-V reset MSR "
 712                     "(requested by 'hv-reset' cpu flag) "
 713                     "is not supported by kernel\n");
 714             return -ENOSYS;
 715         }
 716         env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
 717     }
 718     if (cpu->hyperv_vpindex) {
 719         if (!has_msr_hv_vpindex) {
 720             fprintf(stderr, "Hyper-V VP_INDEX MSR "
 721                     "(requested by 'hv-vpindex' cpu flag) "
 722                     "is not supported by kernel\n");
 723             return -ENOSYS;
 724         }
 725         env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
 726     }
 727     if (cpu->hyperv_runtime) {
 728         if (!has_msr_hv_runtime) {
 729             fprintf(stderr, "Hyper-V VP_RUNTIME MSR "
 730                     "(requested by 'hv-runtime' cpu flag) "
 731                     "is not supported by kernel\n");
 732             return -ENOSYS;
 733         }
 734         env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
 735     }
 736     if (cpu->hyperv_synic) {
 737         if (!has_msr_hv_synic ||
 738             !kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_SYNIC)) {
 739             fprintf(stderr, "Hyper-V SynIC (requested by 'hv-synic' cpu flag) "
 740                     "is not supported by kernel\n");
 741             return -ENOSYS;
 742         }
 743
 744         env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
 745     }
 746     if (cpu->hyperv_stimer) {
 747         if (!has_msr_hv_stimer) {
 748             fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
 749             return -ENOSYS;
 750         }
 751         env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
 752     }
 753     return 0;
 754 }
 755
 756 static int hyperv_init_vcpu(X86CPU *cpu)
 757 {
 758     CPUState *cs = CPU(cpu);
 759     int ret;
 760
 761     if (cpu->hyperv_vpindex && !hv_vpindex_settable) {
 762         /*
 763          * the kernel doesn't support setting vp_index; assert that its value
 764          * is in sync
 765          */
 766         struct {
 767             struct kvm_msrs info;
 768             struct kvm_msr_entry entries[1];
 769         } msr_data = {
 770             .info.nmsrs = 1,
 771             .entries[0].index = HV_X64_MSR_VP_INDEX,
 772         };
 773
 774         ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
 775         if (ret < 0) {
 776             return ret;
 777         }
 778         assert(ret == 1);
 779
 780         if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
 781             error_report("kernel's vp_index != QEMU's vp_index");
 782             return -ENXIO;
 783         }
 784     }
 785
 786     if (cpu->hyperv_synic) {
 787         ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0);
 788         if (ret < 0) {
 789             error_report("failed to turn on HyperV SynIC in KVM: %s",
 790                          strerror(-ret));
 791             return ret;
 792         }
 793     }
 794
 795     return 0;
 796 }
 797
 798 static Error *invtsc_mig_blocker;
 799
 800 #define KVM_MAX_CPUID_ENTRIES  100
 801
 802 int kvm_arch_init_vcpu(CPUState *cs)
 803 {
 804     struct {
 805         struct kvm_cpuid2 cpuid;
 806         struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
 807     } QEMU_PACKED cpuid_data;
 808     X86CPU *cpu = X86_CPU(cs);
 809     CPUX86State *env = &cpu->env;
 810     uint32_t limit, i, j, cpuid_i;
 811     uint32_t unused;
 812     struct kvm_cpuid_entry2 *c;
 813     uint32_t signature[3];
 814     int kvm_base = KVM_CPUID_SIGNATURE;
 815     int r;
 816     Error *local_err = NULL;
 817
 818     memset(&cpuid_data, 0, sizeof(cpuid_data));
 819
 820     cpuid_i = 0;
 821
 822     r = kvm_arch_set_tsc_khz(cs);
 823     if (r < 0) {
 824         goto fail;
 825     }
 826
 827     /* vcpu's TSC frequency is either specified by user, or following
 828      * the value used by KVM if the former is not present. In the
 829      * latter case, we query it from KVM and record in env->tsc_khz,
 830      * so that vcpu's TSC frequency can be migrated later via this field.
 831      */
 832     if (!env->tsc_khz) {
 833         r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
 834             kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
 835             -ENOTSUP;
 836         if (r > 0) {
 837             env->tsc_khz = r;
 838         }
 839     }
 840
 841     /* Paravirtualization CPUIDs */
 842     if (hyperv_enabled(cpu)) {
 843         c = &cpuid_data.entries[cpuid_i++];
 844         c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
 845         if (!cpu->hyperv_vendor_id) {
 846             memcpy(signature, "Microsoft Hv", 12);
 847         } else {
 848             size_t len = strlen(cpu->hyperv_vendor_id);
 849
 850             if (len > 12) {
 851                 error_report("hv-vendor-id truncated to 12 characters");
 852                 len = 12;
 853             }
 854             memset(signature, 0, 12);
 855             memcpy(signature, cpu->hyperv_vendor_id, len);
 856         }
 857         c->eax = HV_CPUID_MIN;
 858         c->ebx = signature[0];
 859         c->ecx = signature[1];
 860         c->edx = signature[2];
 861
 862         c = &cpuid_data.entries[cpuid_i++];
 863         c->function = HV_CPUID_INTERFACE;
 864         memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
 865         c->eax = signature[0];
 866         c->ebx = 0;
 867         c->ecx = 0;
 868         c->edx = 0;
 869
 870         c = &cpuid_data.entries[cpuid_i++];
 871         c->function = HV_CPUID_VERSION;
 872         c->eax = 0x00001bbc;
 873         c->ebx = 0x00060001;
 874
 875         c = &cpuid_data.entries[cpuid_i++];
 876         c->function = HV_CPUID_FEATURES;
 877         r = hyperv_handle_properties(cs);
 878         if (r) {
 879             return r;
 880         }
 881         c->eax = env->features[FEAT_HYPERV_EAX];
 882         c->ebx = env->features[FEAT_HYPERV_EBX];
 883         c->edx = env->features[FEAT_HYPERV_EDX];
 884
 885         c = &cpuid_data.entries[cpuid_i++];
 886         c->function = HV_CPUID_ENLIGHTMENT_INFO;
 887         if (cpu->hyperv_relaxed_timing) {
 888             c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
 889         }
 890         if (cpu->hyperv_vapic) {
 891             c->eax |= HV_APIC_ACCESS_RECOMMENDED;
 892         }
 893         if (cpu->hyperv_tlbflush) {
 894             if (kvm_check_extension(cs->kvm_state,
 895                                     KVM_CAP_HYPERV_TLBFLUSH) <= 0) {
 896                 fprintf(stderr, "Hyper-V TLB flush support "
 897                         "(requested by 'hv-tlbflush' cpu flag) "
 898                         " is not supported by kernel\n");
 899                 return -ENOSYS;
 900             }
 901             c->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
 902             c->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
 903         }
 904         if (cpu->hyperv_ipi) {
 905             if (kvm_check_extension(cs->kvm_state,
 906                                     KVM_CAP_HYPERV_SEND_IPI) <= 0) {
 907                 fprintf(stderr, "Hyper-V IPI send support "
 908                         "(requested by 'hv-ipi' cpu flag) "
 909                         " is not supported by kernel\n");
 910                 return -ENOSYS;
 911             }
 912             c->eax |= HV_CLUSTER_IPI_RECOMMENDED;
 913             c->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
 914         }
 915
 916         c->ebx = cpu->hyperv_spinlock_attempts;
 917
 918         c = &cpuid_data.entries[cpuid_i++];
 919         c->function = HV_CPUID_IMPLEMENT_LIMITS;
 920
 921         c->eax = cpu->hv_max_vps;
 922         c->ebx = 0x40;
 923
 924         kvm_base = KVM_CPUID_SIGNATURE_NEXT;
 925         has_msr_hv_hypercall = true;
 926     }
 927
 928     if (cpu->expose_kvm) {
 929         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 930         c = &cpuid_data.entries[cpuid_i++];
 931         c->function = KVM_CPUID_SIGNATURE | kvm_base;
 932         c->eax = KVM_CPUID_FEATURES | kvm_base;
 933         c->ebx = signature[0];
 934         c->ecx = signature[1];
 935         c->edx = signature[2];
 936
 937         c = &cpuid_data.entries[cpuid_i++];
 938         c->function = KVM_CPUID_FEATURES | kvm_base;
 939         c->eax = env->features[FEAT_KVM];
 940         c->edx = env->features[FEAT_KVM_HINTS];
 941     }
 942
 943     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 944
 945     for (i = 0; i <= limit; i++) {
 946         if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 947             fprintf(stderr, "unsupported level value: 0x%x\n", limit);
 948             abort();
 949         }
 950         c = &cpuid_data.entries[cpuid_i++];
 951
 952         switch (i) {
 953         case 2: {
 954             /* Keep reading function 2 till all the input is received */
 955             int times;
 956
 957             c->function = i;
 958             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 959                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 960             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 961             times = c->eax & 0xff;
 962
 963             for (j = 1; j < times; ++j) {
 964                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 965                     fprintf(stderr, "cpuid_data is full, no space for "
 966                             "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
 967                     abort();
 968                 }
 969                 c = &cpuid_data.entries[cpuid_i++];
 970                 c->function = i;
 971                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 972                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 973             }
 974             break;
 975         }
 976         case 4:
 977         case 0xb:
 978         case 0xd:
 979             for (j = 0; ; j++) {
 980                 if (i == 0xd && j == 64) {
 981                     break;
 982                 }
 983                 c->function = i;
 984                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 985                 c->index = j;
 986                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 987
 988                 if (i == 4 && c->eax == 0) {
 989                     break;
 990                 }
 991                 if (i == 0xb && !(c->ecx & 0xff00)) {
 992                     break;
 993                 }
 994                 if (i == 0xd && c->eax == 0) {
 995                     continue;
 996                 }
 997                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 998                     fprintf(stderr, "cpuid_data is full, no space for "
 999                             "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1000                     abort();
1001                 }
1002                 c = &cpuid_data.entries[cpuid_i++];
1003             }
1004             break;
1005         case 0x14: {
1006             uint32_t times;
1007
1008             c->function = i;
1009             c->index = 0;
1010             c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1011             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1012             times = c->eax;
1013
1014             for (j = 1; j <= times; ++j) {
1015                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1016                     fprintf(stderr, "cpuid_data is full, no space for "
1017                                 "cpuid(eax:0x14,ecx:0x%x)\n", j);
1018                     abort();
1019                 }
1020                 c = &cpuid_data.entries[cpuid_i++];
1021                 c->function = i;
1022                 c->index = j;
1023                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1024                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1025             }
1026             break;
1027         }
1028         default:
1029             c->function = i;
1030             c->flags = 0;
1031             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1032             break;
1033         }
1034     }
1035
1036     if (limit >= 0x0a) {
1037         uint32_t eax, edx;
1038
1039         cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1040
1041         has_architectural_pmu_version = eax & 0xff;
1042         if (has_architectural_pmu_version > 0) {
1043             num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1044
1045             /* Shouldn't be more than 32, since that's the number of bits
1046              * available in EBX to tell us _which_ counters are available.
1047              * Play it safe.
1048              */
1049             if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1050                 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1051             }
1052
1053             if (has_architectural_pmu_version > 1) {
1054                 num_architectural_pmu_fixed_counters = edx & 0x1f;
1055
1056                 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1057                     num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1058                 }
1059             }
1060         }
1061     }
1062
1063     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
1064
1065     for (i = 0x80000000; i <= limit; i++) {
1066         if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1067             fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1068             abort();
1069         }
1070         c = &cpuid_data.entries[cpuid_i++];
1071
1072         switch (i) {
1073         case 0x8000001d:
1074             /* Query for all AMD cache information leaves */
1075             for (j = 0; ; j++) {
1076                 c->function = i;
1077                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1078                 c->index = j;
1079                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1080
1081                 if (c->eax == 0) {
1082                     break;
1083                 }
1084                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1085                     fprintf(stderr, "cpuid_data is full, no space for "
1086                             "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1087                     abort();
1088                 }
1089                 c = &cpuid_data.entries[cpuid_i++];
1090             }
1091             break;
1092         default:
1093             c->function = i;
1094             c->flags = 0;
1095             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1096             break;
1097         }
1098     }
1099
1100     /* Call Centaur's CPUID instructions they are supported. */
1101     if (env->cpuid_xlevel2 > 0) {
1102         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1103
1104         for (i = 0xC0000000; i <= limit; i++) {
1105             if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1106                 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1107                 abort();
1108             }
1109             c = &cpuid_data.entries[cpuid_i++];
1110
1111             c->function = i;
1112             c->flags = 0;
1113             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1114         }
1115     }
1116
1117     cpuid_data.cpuid.nent = cpuid_i;
1118
1119     if (((env->cpuid_version >> 8)&0xF) >= 6
1120         && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
1121            (CPUID_MCE | CPUID_MCA)
1122         && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
1123         uint64_t mcg_cap, unsupported_caps;
1124         int banks;
1125         int ret;
1126
1127         ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
1128         if (ret < 0) {
1129             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1130             return ret;
1131         }
1132
1133         if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
1134             error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1135                          (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
1136             return -ENOTSUP;
1137         }
1138
1139         unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1140         if (unsupported_caps) {
1141             if (unsupported_caps & MCG_LMCE_P) {
1142                 error_report("kvm: LMCE not supported");
1143                 return -ENOTSUP;
1144             }
1145             warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1146                         unsupported_caps);
1147         }
1148
1149         env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1150         ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
1151         if (ret < 0) {
1152             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1153             return ret;
1154         }
1155     }
1156
1157     qemu_add_vm_change_state_handler(cpu_update_state, env);
1158
1159     c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1160     if (c) {
1161         has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1162                                   !!(c->ecx & CPUID_EXT_SMX);
1163     }
1164
1165     if (env->mcg_cap & MCG_LMCE_P) {
1166         has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1167     }
1168
1169     if (!env->user_tsc_khz) {
1170         if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1171             invtsc_mig_blocker == NULL) {
1172             /* for migration */
1173             error_setg(&invtsc_mig_blocker,
1174                        "State blocked by non-migratable CPU device"
1175                        " (invtsc flag)");
1176             r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1177             if (local_err) {
1178                 error_report_err(local_err);
1179                 error_free(invtsc_mig_blocker);
1180                 goto fail;
1181             }
1182             /* for savevm */
1183             vmstate_x86_cpu.unmigratable = 1;
1184         }
1185     }
1186
1187     if (cpu->vmware_cpuid_freq
1188         /* Guests depend on 0x40000000 to detect this feature, so only expose
1189          * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1190         && cpu->expose_kvm
1191         && kvm_base == KVM_CPUID_SIGNATURE
1192         /* TSC clock must be stable and known for this feature. */
1193         && tsc_is_stable_and_known(env)) {
1194
1195         c = &cpuid_data.entries[cpuid_i++];
1196         c->function = KVM_CPUID_SIGNATURE | 0x10;
1197         c->eax = env->tsc_khz;
1198         /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1199          * APIC_BUS_CYCLE_NS */
1200         c->ebx = 1000000;
1201         c->ecx = c->edx = 0;
1202
1203         c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1204         c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1205     }
1206
1207     cpuid_data.cpuid.nent = cpuid_i;
1208
1209     cpuid_data.cpuid.padding = 0;
1210     r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1211     if (r) {
1212         goto fail;
1213     }
1214
1215     if (has_xsave) {
1216         env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1217     }
1218     cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1219
1220     if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1221         has_msr_tsc_aux = false;
1222     }
1223
1224     r = hyperv_init_vcpu(cpu);
1225     if (r) {
1226         goto fail;
1227     }
1228
1229     return 0;
1230
1231  fail:
1232     migrate_del_blocker(invtsc_mig_blocker);
1233     return r;
1234 }
1235
1236 void kvm_arch_reset_vcpu(X86CPU *cpu)
1237 {
1238     CPUX86State *env = &cpu->env;
1239
1240     env->xcr0 = 1;
1241     if (kvm_irqchip_in_kernel()) {
1242         env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1243                                           KVM_MP_STATE_UNINITIALIZED;
1244     } else {
1245         env->mp_state = KVM_MP_STATE_RUNNABLE;
1246     }
1247
1248     if (cpu->hyperv_synic) {
1249         int i;
1250         for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1251             env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1252         }
1253     }
1254 }
1255
1256 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1257 {
1258     CPUX86State *env = &cpu->env;
1259
1260     /* APs get directly into wait-for-SIPI state.  */
1261     if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1262         env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1263     }
1264 }
1265
1266 static int kvm_get_supported_msrs(KVMState *s)
1267 {
1268     static int kvm_supported_msrs;
1269     int ret = 0;
1270
1271     /* first time */
1272     if (kvm_supported_msrs == 0) {
1273         struct kvm_msr_list msr_list, *kvm_msr_list;
1274
1275         kvm_supported_msrs = -1;
1276
1277         /* Obtain MSR list from KVM.  These are the MSRs that we must
1278          * save/restore */
1279         msr_list.nmsrs = 0;
1280         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1281         if (ret < 0 && ret != -E2BIG) {
1282             return ret;
1283         }
1284         /* Old kernel modules had a bug and could write beyond the provided
1285            memory. Allocate at least a safe amount of 1K. */
1286         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1287                                               msr_list.nmsrs *
1288                                               sizeof(msr_list.indices[0])));
1289
1290         kvm_msr_list->nmsrs = msr_list.nmsrs;
1291         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1292         if (ret >= 0) {
1293             int i;
1294
1295             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1296                 switch (kvm_msr_list->indices[i]) {
1297                 case MSR_STAR:
1298                     has_msr_star = true;
1299                     break;
1300                 case MSR_VM_HSAVE_PA:
1301                     has_msr_hsave_pa = true;
1302                     break;
1303                 case MSR_TSC_AUX:
1304                     has_msr_tsc_aux = true;
1305                     break;
1306                 case MSR_TSC_ADJUST:
1307                     has_msr_tsc_adjust = true;
1308                     break;
1309                 case MSR_IA32_TSCDEADLINE:
1310                     has_msr_tsc_deadline = true;
1311                     break;
1312                 case MSR_IA32_SMBASE:
1313                     has_msr_smbase = true;
1314                     break;
1315                 case MSR_SMI_COUNT:
1316                     has_msr_smi_count = true;
1317                     break;
1318                 case MSR_IA32_MISC_ENABLE:
1319                     has_msr_misc_enable = true;
1320                     break;
1321                 case MSR_IA32_BNDCFGS:
1322                     has_msr_bndcfgs = true;
1323                     break;
1324                 case MSR_IA32_XSS:
1325                     has_msr_xss = true;
1326                     break;
1327                 case HV_X64_MSR_CRASH_CTL:
1328                     has_msr_hv_crash = true;
1329                     break;
1330                 case HV_X64_MSR_RESET:
1331                     has_msr_hv_reset = true;
1332                     break;
1333                 case HV_X64_MSR_VP_INDEX:
1334                     has_msr_hv_vpindex = true;
1335                     break;
1336                 case HV_X64_MSR_VP_RUNTIME:
1337                     has_msr_hv_runtime = true;
1338                     break;
1339                 case HV_X64_MSR_SCONTROL:
1340                     has_msr_hv_synic = true;
1341                     break;
1342                 case HV_X64_MSR_STIMER0_CONFIG:
1343                     has_msr_hv_stimer = true;
1344                     break;
1345                 case HV_X64_MSR_TSC_FREQUENCY:
1346                     has_msr_hv_frequencies = true;
1347                     break;
1348                 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1349                     has_msr_hv_reenlightenment = true;
1350                     break;
1351                 case MSR_IA32_SPEC_CTRL:
1352                     has_msr_spec_ctrl = true;
1353                     break;
1354                 case MSR_VIRT_SSBD:
1355                     has_msr_virt_ssbd = true;
1356                     break;
1357                 }
1358             }
1359         }
1360
1361         g_free(kvm_msr_list);
1362     }
1363
1364     return ret;
1365 }
1366
1367 static Notifier smram_machine_done;
1368 static KVMMemoryListener smram_listener;
1369 static AddressSpace smram_address_space;
1370 static MemoryRegion smram_as_root;
1371 static MemoryRegion smram_as_mem;
1372
1373 static void register_smram_listener(Notifier *n, void *unused)
1374 {
1375     MemoryRegion *smram =
1376         (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1377
1378     /* Outer container... */
1379     memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1380     memory_region_set_enabled(&smram_as_root, true);
1381
1382     /* ... with two regions inside: normal system memory with low
1383      * priority, and...
1384      */
1385     memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1386                              get_system_memory(), 0, ~0ull);
1387     memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1388     memory_region_set_enabled(&smram_as_mem, true);
1389
1390     if (smram) {
1391         /* ... SMRAM with higher priority */
1392         memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1393         memory_region_set_enabled(smram, true);
1394     }
1395
1396     address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1397     kvm_memory_listener_register(kvm_state, &smram_listener,
1398                                  &smram_address_space, 1);
1399 }
1400
1401 int kvm_arch_init(MachineState *ms, KVMState *s)
1402 {
1403     uint64_t identity_base = 0xfffbc000;
1404     uint64_t shadow_mem;
1405     int ret;
1406     struct utsname utsname;
1407
1408     has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1409     has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1410     has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1411
1412     hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1413
1414     ret = kvm_get_supported_msrs(s);
1415     if (ret < 0) {
1416         return ret;
1417     }
1418
1419     uname(&utsname);
1420     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1421
1422     /*
1423      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1424      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
1425      * Since these must be part of guest physical memory, we need to allocate
1426      * them, both by setting their start addresses in the kernel and by
1427      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1428      *
1429      * Older KVM versions may not support setting the identity map base. In
1430      * that case we need to stick with the default, i.e. a 256K maximum BIOS
1431      * size.
1432      */
1433     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1434         /* Allows up to 16M BIOSes. */
1435         identity_base = 0xfeffc000;
1436
1437         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1438         if (ret < 0) {
1439             return ret;
1440         }
1441     }
1442
1443     /* Set TSS base one page after EPT identity map. */
1444     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1445     if (ret < 0) {
1446         return ret;
1447     }
1448
1449     /* Tell fw_cfg to notify the BIOS to reserve the range. */
1450     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1451     if (ret < 0) {
1452         fprintf(stderr, "e820_add_entry() table is full\n");
1453         return ret;
1454     }
1455     qemu_register_reset(kvm_unpoison_all, NULL);
1456
1457     shadow_mem = machine_kvm_shadow_mem(ms);
1458     if (shadow_mem != -1) {
1459         shadow_mem /= 4096;
1460         ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1461         if (ret < 0) {
1462             return ret;
1463         }
1464     }
1465
1466     if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1467         object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1468         pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
1469         smram_machine_done.notify = register_smram_listener;
1470         qemu_add_machine_init_done_notifier(&smram_machine_done);
1471     }
1472
1473     if (enable_cpu_pm) {
1474         int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
1475         int ret;
1476
1477 /* Work around for kernel header with a typo. TODO: fix header and drop. */
1478 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
1479 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
1480 #endif
1481         if (disable_exits) {
1482             disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
1483                               KVM_X86_DISABLE_EXITS_HLT |
1484                               KVM_X86_DISABLE_EXITS_PAUSE);
1485         }
1486
1487         ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
1488                                 disable_exits);
1489         if (ret < 0) {
1490             error_report("kvm: guest stopping CPU not supported: %s",
1491                          strerror(-ret));
1492         }
1493     }
1494
1495     return 0;
1496 }
1497
1498 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1499 {
1500     lhs->selector = rhs->selector;
1501     lhs->base = rhs->base;
1502     lhs->limit = rhs->limit;
1503     lhs->type = 3;
1504     lhs->present = 1;
1505     lhs->dpl = 3;
1506     lhs->db = 0;
1507     lhs->s = 1;
1508     lhs->l = 0;
1509     lhs->g = 0;
1510     lhs->avl = 0;
1511     lhs->unusable = 0;
1512 }
1513
1514 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1515 {
1516     unsigned flags = rhs->flags;
1517     lhs->selector = rhs->selector;
1518     lhs->base = rhs->base;
1519     lhs->limit = rhs->limit;
1520     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1521     lhs->present = (flags & DESC_P_MASK) != 0;
1522     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1523     lhs->db = (flags >> DESC_B_SHIFT) & 1;
1524     lhs->s = (flags & DESC_S_MASK) != 0;
1525     lhs->l = (flags >> DESC_L_SHIFT) & 1;
1526     lhs->g = (flags & DESC_G_MASK) != 0;
1527     lhs->avl = (flags & DESC_AVL_MASK) != 0;
1528     lhs->unusable = !lhs->present;
1529     lhs->padding = 0;
1530 }
1531
1532 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1533 {
1534     lhs->selector = rhs->selector;
1535     lhs->base = rhs->base;
1536     lhs->limit = rhs->limit;
1537     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1538                  ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1539                  (rhs->dpl << DESC_DPL_SHIFT) |
1540                  (rhs->db << DESC_B_SHIFT) |
1541                  (rhs->s * DESC_S_MASK) |
1542                  (rhs->l << DESC_L_SHIFT) |
1543                  (rhs->g * DESC_G_MASK) |
1544                  (rhs->avl * DESC_AVL_MASK);
1545 }
1546
1547 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1548 {
1549     if (set) {
1550         *kvm_reg = *qemu_reg;
1551     } else {
1552         *qemu_reg = *kvm_reg;
1553     }
1554 }
1555
1556 static int kvm_getput_regs(X86CPU *cpu, int set)
1557 {
1558     CPUX86State *env = &cpu->env;
1559     struct kvm_regs regs;
1560     int ret = 0;
1561
1562     if (!set) {
1563         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1564         if (ret < 0) {
1565             return ret;
1566         }
1567     }
1568
1569     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1570     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1571     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1572     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1573     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1574     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1575     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1576     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1577 #ifdef TARGET_X86_64
1578     kvm_getput_reg(&regs.r8, &env->regs[8], set);
1579     kvm_getput_reg(&regs.r9, &env->regs[9], set);
1580     kvm_getput_reg(&regs.r10, &env->regs[10], set);
1581     kvm_getput_reg(&regs.r11, &env->regs[11], set);
1582     kvm_getput_reg(&regs.r12, &env->regs[12], set);
1583     kvm_getput_reg(&regs.r13, &env->regs[13], set);
1584     kvm_getput_reg(&regs.r14, &env->regs[14], set);
1585     kvm_getput_reg(&regs.r15, &env->regs[15], set);
1586 #endif
1587
1588     kvm_getput_reg(&regs.rflags, &env->eflags, set);
1589     kvm_getput_reg(&regs.rip, &env->eip, set);
1590
1591     if (set) {
1592         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1593     }
1594
1595     return ret;
1596 }
1597
1598 static int kvm_put_fpu(X86CPU *cpu)
1599 {
1600     CPUX86State *env = &cpu->env;
1601     struct kvm_fpu fpu;
1602     int i;
1603
1604     memset(&fpu, 0, sizeof fpu);
1605     fpu.fsw = env->fpus & ~(7 << 11);
1606     fpu.fsw |= (env->fpstt & 7) << 11;
1607     fpu.fcw = env->fpuc;
1608     fpu.last_opcode = env->fpop;
1609     fpu.last_ip = env->fpip;
1610     fpu.last_dp = env->fpdp;
1611     for (i = 0; i < 8; ++i) {
1612         fpu.ftwx |= (!env->fptags[i]) << i;
1613     }
1614     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1615     for (i = 0; i < CPU_NB_REGS; i++) {
1616         stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1617         stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1618     }
1619     fpu.mxcsr = env->mxcsr;
1620
1621     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1622 }
1623
1624 #define XSAVE_FCW_FSW     0
1625 #define XSAVE_FTW_FOP     1
1626 #define XSAVE_CWD_RIP     2
1627 #define XSAVE_CWD_RDP     4
1628 #define XSAVE_MXCSR       6
1629 #define XSAVE_ST_SPACE    8
1630 #define XSAVE_XMM_SPACE   40
1631 #define XSAVE_XSTATE_BV   128
1632 #define XSAVE_YMMH_SPACE  144
1633 #define XSAVE_BNDREGS     240
1634 #define XSAVE_BNDCSR      256
1635 #define XSAVE_OPMASK      272
1636 #define XSAVE_ZMM_Hi256   288
1637 #define XSAVE_Hi16_ZMM    416
1638 #define XSAVE_PKRU        672
1639
1640 #define XSAVE_BYTE_OFFSET(word_offset) \
1641     ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
1642
1643 #define ASSERT_OFFSET(word_offset, field) \
1644     QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1645                       offsetof(X86XSaveArea, field))
1646
1647 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1648 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1649 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1650 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1651 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1652 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1653 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1654 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1655 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1656 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1657 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1658 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1659 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1660 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1661 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1662
1663 static int kvm_put_xsave(X86CPU *cpu)
1664 {
1665     CPUX86State *env = &cpu->env;
1666     X86XSaveArea *xsave = env->xsave_buf;
1667
1668     if (!has_xsave) {
1669         return kvm_put_fpu(cpu);
1670     }
1671     x86_cpu_xsave_all_areas(cpu, xsave);
1672
1673     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1674 }
1675
1676 static int kvm_put_xcrs(X86CPU *cpu)
1677 {
1678     CPUX86State *env = &cpu->env;
1679     struct kvm_xcrs xcrs = {};
1680
1681     if (!has_xcrs) {
1682         return 0;
1683     }
1684
1685     xcrs.nr_xcrs = 1;
1686     xcrs.flags = 0;
1687     xcrs.xcrs[0].xcr = 0;
1688     xcrs.xcrs[0].value = env->xcr0;
1689     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1690 }
1691
1692 static int kvm_put_sregs(X86CPU *cpu)
1693 {
1694     CPUX86State *env = &cpu->env;
1695     struct kvm_sregs sregs;
1696
1697     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1698     if (env->interrupt_injected >= 0) {
1699         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1700                 (uint64_t)1 << (env->interrupt_injected % 64);
1701     }
1702
1703     if ((env->eflags & VM_MASK)) {
1704         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1705         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1706         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1707         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1708         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1709         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1710     } else {
1711         set_seg(&sregs.cs, &env->segs[R_CS]);
1712         set_seg(&sregs.ds, &env->segs[R_DS]);
1713         set_seg(&sregs.es, &env->segs[R_ES]);
1714         set_seg(&sregs.fs, &env->segs[R_FS]);
1715         set_seg(&sregs.gs, &env->segs[R_GS]);
1716         set_seg(&sregs.ss, &env->segs[R_SS]);
1717     }
1718
1719     set_seg(&sregs.tr, &env->tr);
1720     set_seg(&sregs.ldt, &env->ldt);
1721
1722     sregs.idt.limit = env->idt.limit;
1723     sregs.idt.base = env->idt.base;
1724     memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1725     sregs.gdt.limit = env->gdt.limit;
1726     sregs.gdt.base = env->gdt.base;
1727     memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1728
1729     sregs.cr0 = env->cr[0];
1730     sregs.cr2 = env->cr[2];
1731     sregs.cr3 = env->cr[3];
1732     sregs.cr4 = env->cr[4];
1733
1734     sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1735     sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1736
1737     sregs.efer = env->efer;
1738
1739     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1740 }
1741
1742 static void kvm_msr_buf_reset(X86CPU *cpu)
1743 {
1744     memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1745 }
1746
1747 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1748 {
1749     struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1750     void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1751     struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1752
1753     assert((void *)(entry + 1) <= limit);
1754
1755     entry->index = index;
1756     entry->reserved = 0;
1757     entry->data = value;
1758     msrs->nmsrs++;
1759 }
1760
1761 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1762 {
1763     kvm_msr_buf_reset(cpu);
1764     kvm_msr_entry_add(cpu, index, value);
1765
1766     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1767 }
1768
1769 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1770 {
1771     int ret;
1772
1773     ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1774     assert(ret == 1);
1775 }
1776
1777 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1778 {
1779     CPUX86State *env = &cpu->env;
1780     int ret;
1781
1782     if (!has_msr_tsc_deadline) {
1783         return 0;
1784     }
1785
1786     ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1787     if (ret < 0) {
1788         return ret;
1789     }
1790
1791     assert(ret == 1);
1792     return 0;
1793 }
1794
1795 /*
1796  * Provide a separate write service for the feature control MSR in order to
1797  * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1798  * before writing any other state because forcibly leaving nested mode
1799  * invalidates the VCPU state.
1800  */
1801 static int kvm_put_msr_feature_control(X86CPU *cpu)
1802 {
1803     int ret;
1804
1805     if (!has_msr_feature_control) {
1806         return 0;
1807     }
1808
1809     ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1810                           cpu->env.msr_ia32_feature_control);
1811     if (ret < 0) {
1812         return ret;
1813     }
1814
1815     assert(ret == 1);
1816     return 0;
1817 }
1818
1819 static int kvm_put_msrs(X86CPU *cpu, int level)
1820 {
1821     CPUX86State *env = &cpu->env;
1822     int i;
1823     int ret;
1824
1825     kvm_msr_buf_reset(cpu);
1826
1827     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1828     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1829     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1830     kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1831     if (has_msr_star) {
1832         kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1833     }
1834     if (has_msr_hsave_pa) {
1835         kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1836     }
1837     if (has_msr_tsc_aux) {
1838         kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1839     }
1840     if (has_msr_tsc_adjust) {
1841         kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1842     }
1843     if (has_msr_misc_enable) {
1844         kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1845                           env->msr_ia32_misc_enable);
1846     }
1847     if (has_msr_smbase) {
1848         kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1849     }
1850     if (has_msr_smi_count) {
1851         kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
1852     }
1853     if (has_msr_bndcfgs) {
1854         kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1855     }
1856     if (has_msr_xss) {
1857         kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1858     }
1859     if (has_msr_spec_ctrl) {
1860         kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
1861     }
1862     if (has_msr_virt_ssbd) {
1863         kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
1864     }
1865
1866 #ifdef TARGET_X86_64
1867     if (lm_capable_kernel) {
1868         kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1869         kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1870         kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1871         kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1872     }
1873 #endif
1874
1875     /*
1876      * The following MSRs have side effects on the guest or are too heavy
1877      * for normal writeback. Limit them to reset or full state updates.
1878      */
1879     if (level >= KVM_PUT_RESET_STATE) {
1880         kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1881         kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1882         kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1883         if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
1884             kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1885         }
1886         if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
1887             kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1888         }
1889         if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
1890             kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1891         }
1892         if (has_architectural_pmu_version > 0) {
1893             if (has_architectural_pmu_version > 1) {
1894                 /* Stop the counter.  */
1895                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1896                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1897             }
1898
1899             /* Set the counter values.  */
1900             for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
1901                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1902                                   env->msr_fixed_counters[i]);
1903             }
1904             for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
1905                 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1906                                   env->msr_gp_counters[i]);
1907                 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1908                                   env->msr_gp_evtsel[i]);
1909             }
1910             if (has_architectural_pmu_version > 1) {
1911                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1912                                   env->msr_global_status);
1913                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1914                                   env->msr_global_ovf_ctrl);
1915
1916                 /* Now start the PMU.  */
1917                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1918                                   env->msr_fixed_ctr_ctrl);
1919                 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1920                                   env->msr_global_ctrl);
1921             }
1922         }
1923         /*
1924          * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
1925          * only sync them to KVM on the first cpu
1926          */
1927         if (current_cpu == first_cpu) {
1928             if (has_msr_hv_hypercall) {
1929                 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1930                                   env->msr_hv_guest_os_id);
1931                 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1932                                   env->msr_hv_hypercall);
1933             }
1934             if (cpu->hyperv_time) {
1935                 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
1936                                   env->msr_hv_tsc);
1937             }
1938             if (cpu->hyperv_reenlightenment) {
1939                 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
1940                                   env->msr_hv_reenlightenment_control);
1941                 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
1942                                   env->msr_hv_tsc_emulation_control);
1943                 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
1944                                   env->msr_hv_tsc_emulation_status);
1945             }
1946         }
1947         if (cpu->hyperv_vapic) {
1948             kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1949                               env->msr_hv_vapic);
1950         }
1951         if (has_msr_hv_crash) {
1952             int j;
1953
1954             for (j = 0; j < HV_CRASH_PARAMS; j++)
1955                 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1956                                   env->msr_hv_crash_params[j]);
1957
1958             kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
1959         }
1960         if (has_msr_hv_runtime) {
1961             kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1962         }
1963         if (cpu->hyperv_vpindex && hv_vpindex_settable) {
1964             kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
1965                               hyperv_vp_index(CPU(cpu)));
1966         }
1967         if (cpu->hyperv_synic) {
1968             int j;
1969
1970             kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
1971
1972             kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1973                               env->msr_hv_synic_control);
1974             kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1975                               env->msr_hv_synic_evt_page);
1976             kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1977                               env->msr_hv_synic_msg_page);
1978
1979             for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1980                 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1981                                   env->msr_hv_synic_sint[j]);
1982             }
1983         }
1984         if (has_msr_hv_stimer) {
1985             int j;
1986
1987             for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1988                 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1989                                 env->msr_hv_stimer_config[j]);
1990             }
1991
1992             for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1993                 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1994                                 env->msr_hv_stimer_count[j]);
1995             }
1996         }
1997         if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
1998             uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1999
2000             kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2001             kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2002             kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2003             kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2004             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2005             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2006             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2007             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2008             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2009             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2010             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2011             kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
2012             for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2013                 /* The CPU GPs if we write to a bit above the physical limit of
2014                  * the host CPU (and KVM emulates that)
2015                  */
2016                 uint64_t mask = env->mtrr_var[i].mask;
2017                 mask &= phys_mask;
2018
2019                 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2020                                   env->mtrr_var[i].base);
2021                 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
2022             }
2023         }
2024         if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2025             int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2026                                                     0x14, 1, R_EAX) & 0x7;
2027
2028             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2029                             env->msr_rtit_ctrl);
2030             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2031                             env->msr_rtit_status);
2032             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2033                             env->msr_rtit_output_base);
2034             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2035                             env->msr_rtit_output_mask);
2036             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2037                             env->msr_rtit_cr3_match);
2038             for (i = 0; i < addr_num; i++) {
2039                 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2040                             env->msr_rtit_addrs[i]);
2041             }
2042         }
2043
2044         /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2045          *       kvm_put_msr_feature_control. */
2046     }
2047     if (env->mcg_cap) {
2048         int i;
2049
2050         kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2051         kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
2052         if (has_msr_mcg_ext_ctl) {
2053             kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2054         }
2055         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2056             kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
2057         }
2058     }
2059
2060     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2061     if (ret < 0) {
2062         return ret;
2063     }
2064
2065     if (ret < cpu->kvm_msr_buf->nmsrs) {
2066         struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2067         error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2068                      (uint32_t)e->index, (uint64_t)e->data);
2069     }
2070
2071     assert(ret == cpu->kvm_msr_buf->nmsrs);
2072     return 0;
2073 }
2074
2075
2076 static int kvm_get_fpu(X86CPU *cpu)
2077 {
2078     CPUX86State *env = &cpu->env;
2079     struct kvm_fpu fpu;
2080     int i, ret;
2081
2082     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
2083     if (ret < 0) {
2084         return ret;
2085     }
2086
2087     env->fpstt = (fpu.fsw >> 11) & 7;
2088     env->fpus = fpu.fsw;
2089     env->fpuc = fpu.fcw;
2090     env->fpop = fpu.last_opcode;
2091     env->fpip = fpu.last_ip;
2092     env->fpdp = fpu.last_dp;
2093     for (i = 0; i < 8; ++i) {
2094         env->fptags[i] = !((fpu.ftwx >> i) & 1);
2095     }
2096     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
2097     for (i = 0; i < CPU_NB_REGS; i++) {
2098         env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2099         env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
2100     }
2101     env->mxcsr = fpu.mxcsr;
2102
2103     return 0;
2104 }
2105
2106 static int kvm_get_xsave(X86CPU *cpu)
2107 {
2108     CPUX86State *env = &cpu->env;
2109     X86XSaveArea *xsave = env->xsave_buf;
2110     int ret;
2111
2112     if (!has_xsave) {
2113         return kvm_get_fpu(cpu);
2114     }
2115
2116     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
2117     if (ret < 0) {
2118         return ret;
2119     }
2120     x86_cpu_xrstor_all_areas(cpu, xsave);
2121
2122     return 0;
2123 }
2124
2125 static int kvm_get_xcrs(X86CPU *cpu)
2126 {
2127     CPUX86State *env = &cpu->env;
2128     int i, ret;
2129     struct kvm_xcrs xcrs;
2130
2131     if (!has_xcrs) {
2132         return 0;
2133     }
2134
2135     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
2136     if (ret < 0) {
2137         return ret;
2138     }
2139
2140     for (i = 0; i < xcrs.nr_xcrs; i++) {
2141         /* Only support xcr0 now */
2142         if (xcrs.xcrs[i].xcr == 0) {
2143             env->xcr0 = xcrs.xcrs[i].value;
2144             break;
2145         }
2146     }
2147     return 0;
2148 }
2149
2150 static int kvm_get_sregs(X86CPU *cpu)
2151 {
2152     CPUX86State *env = &cpu->env;
2153     struct kvm_sregs sregs;
2154     int bit, i, ret;
2155
2156     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
2157     if (ret < 0) {
2158         return ret;
2159     }
2160
2161     /* There can only be one pending IRQ set in the bitmap at a time, so try
2162        to find it and save its number instead (-1 for none). */
2163     env->interrupt_injected = -1;
2164     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2165         if (sregs.interrupt_bitmap[i]) {
2166             bit = ctz64(sregs.interrupt_bitmap[i]);
2167             env->interrupt_injected = i * 64 + bit;
2168             break;
2169         }
2170     }
2171
2172     get_seg(&env->segs[R_CS], &sregs.cs);
2173     get_seg(&env->segs[R_DS], &sregs.ds);
2174     get_seg(&env->segs[R_ES], &sregs.es);
2175     get_seg(&env->segs[R_FS], &sregs.fs);
2176     get_seg(&env->segs[R_GS], &sregs.gs);
2177     get_seg(&env->segs[R_SS], &sregs.ss);
2178
2179     get_seg(&env->tr, &sregs.tr);
2180     get_seg(&env->ldt, &sregs.ldt);
2181
2182     env->idt.limit = sregs.idt.limit;
2183     env->idt.base = sregs.idt.base;
2184     env->gdt.limit = sregs.gdt.limit;
2185     env->gdt.base = sregs.gdt.base;
2186
2187     env->cr[0] = sregs.cr0;
2188     env->cr[2] = sregs.cr2;
2189     env->cr[3] = sregs.cr3;
2190     env->cr[4] = sregs.cr4;
2191
2192     env->efer = sregs.efer;
2193
2194     /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
2195     x86_update_hflags(env);
2196
2197     return 0;
2198 }
2199
2200 static int kvm_get_msrs(X86CPU *cpu)
2201 {
2202     CPUX86State *env = &cpu->env;
2203     struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
2204     int ret, i;
2205     uint64_t mtrr_top_bits;
2206
2207     kvm_msr_buf_reset(cpu);
2208
2209     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2210     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2211     kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2212     kvm_msr_entry_add(cpu, MSR_PAT, 0);
2213     if (has_msr_star) {
2214         kvm_msr_entry_add(cpu, MSR_STAR, 0);
2215     }
2216     if (has_msr_hsave_pa) {
2217         kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
2218     }
2219     if (has_msr_tsc_aux) {
2220         kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2221     }
2222     if (has_msr_tsc_adjust) {
2223         kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2224     }
2225     if (has_msr_tsc_deadline) {
2226         kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2227     }
2228     if (has_msr_misc_enable) {
2229         kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2230     }
2231     if (has_msr_smbase) {
2232         kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2233     }
2234     if (has_msr_smi_count) {
2235         kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2236     }
2237     if (has_msr_feature_control) {
2238         kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2239     }
2240     if (has_msr_bndcfgs) {
2241         kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2242     }
2243     if (has_msr_xss) {
2244         kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2245     }
2246     if (has_msr_spec_ctrl) {
2247         kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2248     }
2249     if (has_msr_virt_ssbd) {
2250         kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2251     }
2252     if (!env->tsc_valid) {
2253         kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2254         env->tsc_valid = !runstate_is_running();
2255     }
2256
2257 #ifdef TARGET_X86_64
2258     if (lm_capable_kernel) {
2259         kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2260         kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2261         kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2262         kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2263     }
2264 #endif
2265     kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2266     kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2267     if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2268         kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2269     }
2270     if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2271         kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2272     }
2273     if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2274         kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2275     }
2276     if (has_architectural_pmu_version > 0) {
2277         if (has_architectural_pmu_version > 1) {
2278             kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2279             kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2280             kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2281             kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2282         }
2283         for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2284             kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2285         }
2286         for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2287             kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2288             kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2289         }
2290     }
2291
2292     if (env->mcg_cap) {
2293         kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2294         kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2295         if (has_msr_mcg_ext_ctl) {
2296             kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2297         }
2298         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2299             kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2300         }
2301     }
2302
2303     if (has_msr_hv_hypercall) {
2304         kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2305         kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2306     }
2307     if (cpu->hyperv_vapic) {
2308         kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2309     }
2310     if (cpu->hyperv_time) {
2311         kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2312     }
2313     if (cpu->hyperv_reenlightenment) {
2314         kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2315         kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2316         kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2317     }
2318     if (has_msr_hv_crash) {
2319         int j;
2320
2321         for (j = 0; j < HV_CRASH_PARAMS; j++) {
2322             kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2323         }
2324     }
2325     if (has_msr_hv_runtime) {
2326         kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2327     }
2328     if (cpu->hyperv_synic) {
2329         uint32_t msr;
2330
2331         kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2332         kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2333         kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2334         for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2335             kvm_msr_entry_add(cpu, msr, 0);
2336         }
2337     }
2338     if (has_msr_hv_stimer) {
2339         uint32_t msr;
2340
2341         for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2342              msr++) {
2343             kvm_msr_entry_add(cpu, msr, 0);
2344         }
2345     }
2346     if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2347         kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2348         kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2349         kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2350         kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2351         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2352         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2353         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2354         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2355         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2356         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2357         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2358         kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2359         for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2360             kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2361             kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2362         }
2363     }
2364
2365     if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2366         int addr_num =
2367             kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2368
2369         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2370         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2371         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2372         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2373         kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2374         for (i = 0; i < addr_num; i++) {
2375             kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2376         }
2377     }
2378
2379     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2380     if (ret < 0) {
2381         return ret;
2382     }
2383
2384     if (ret < cpu->kvm_msr_buf->nmsrs) {
2385         struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2386         error_report("error: failed to get MSR 0x%" PRIx32,
2387                      (uint32_t)e->index);
2388     }
2389
2390     assert(ret == cpu->kvm_msr_buf->nmsrs);
2391     /*
2392      * MTRR masks: Each mask consists of 5 parts
2393      * a  10..0: must be zero
2394      * b  11   : valid bit
2395      * c n-1.12: actual mask bits
2396      * d  51..n: reserved must be zero
2397      * e  63.52: reserved must be zero
2398      *
2399      * 'n' is the number of physical bits supported by the CPU and is
2400      * apparently always <= 52.   We know our 'n' but don't know what
2401      * the destinations 'n' is; it might be smaller, in which case
2402      * it masks (c) on loading. It might be larger, in which case
2403      * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2404      * we're migrating to.
2405      */
2406
2407     if (cpu->fill_mtrr_mask) {
2408         QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2409         assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2410         mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2411     } else {
2412         mtrr_top_bits = 0;
2413     }
2414
2415     for (i = 0; i < ret; i++) {
2416         uint32_t index = msrs[i].index;
2417         switch (index) {
2418         case MSR_IA32_SYSENTER_CS:
2419             env->sysenter_cs = msrs[i].data;
2420             break;
2421         case MSR_IA32_SYSENTER_ESP:
2422             env->sysenter_esp = msrs[i].data;
2423             break;
2424         case MSR_IA32_SYSENTER_EIP:
2425             env->sysenter_eip = msrs[i].data;
2426             break;
2427         case MSR_PAT:
2428             env->pat = msrs[i].data;
2429             break;
2430         case MSR_STAR:
2431             env->star = msrs[i].data;
2432             break;
2433 #ifdef TARGET_X86_64
2434         case MSR_CSTAR:
2435             env->cstar = msrs[i].data;
2436             break;
2437         case MSR_KERNELGSBASE:
2438             env->kernelgsbase = msrs[i].data;
2439             break;
2440         case MSR_FMASK:
2441             env->fmask = msrs[i].data;
2442             break;
2443         case MSR_LSTAR:
2444             env->lstar = msrs[i].data;
2445             break;
2446 #endif
2447         case MSR_IA32_TSC:
2448             env->tsc = msrs[i].data;
2449             break;
2450         case MSR_TSC_AUX:
2451             env->tsc_aux = msrs[i].data;
2452             break;
2453         case MSR_TSC_ADJUST:
2454             env->tsc_adjust = msrs[i].data;
2455             break;
2456         case MSR_IA32_TSCDEADLINE:
2457             env->tsc_deadline = msrs[i].data;
2458             break;
2459         case MSR_VM_HSAVE_PA:
2460             env->vm_hsave = msrs[i].data;
2461             break;
2462         case MSR_KVM_SYSTEM_TIME:
2463             env->system_time_msr = msrs[i].data;
2464             break;
2465         case MSR_KVM_WALL_CLOCK:
2466             env->wall_clock_msr = msrs[i].data;
2467             break;
2468         case MSR_MCG_STATUS:
2469             env->mcg_status = msrs[i].data;
2470             break;
2471         case MSR_MCG_CTL:
2472             env->mcg_ctl = msrs[i].data;
2473             break;
2474         case MSR_MCG_EXT_CTL:
2475             env->mcg_ext_ctl = msrs[i].data;
2476             break;
2477         case MSR_IA32_MISC_ENABLE:
2478             env->msr_ia32_misc_enable = msrs[i].data;
2479             break;
2480         case MSR_IA32_SMBASE:
2481             env->smbase = msrs[i].data;
2482             break;
2483         case MSR_SMI_COUNT:
2484             env->msr_smi_count = msrs[i].data;
2485             break;
2486         case MSR_IA32_FEATURE_CONTROL:
2487             env->msr_ia32_feature_control = msrs[i].data;
2488             break;
2489         case MSR_IA32_BNDCFGS:
2490             env->msr_bndcfgs = msrs[i].data;
2491             break;
2492         case MSR_IA32_XSS:
2493             env->xss = msrs[i].data;
2494             break;
2495         default:
2496             if (msrs[i].index >= MSR_MC0_CTL &&
2497                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2498                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2499             }
2500             break;
2501         case MSR_KVM_ASYNC_PF_EN:
2502             env->async_pf_en_msr = msrs[i].data;
2503             break;
2504         case MSR_KVM_PV_EOI_EN:
2505             env->pv_eoi_en_msr = msrs[i].data;
2506             break;
2507         case MSR_KVM_STEAL_TIME:
2508             env->steal_time_msr = msrs[i].data;
2509             break;
2510         case MSR_CORE_PERF_FIXED_CTR_CTRL:
2511             env->msr_fixed_ctr_ctrl = msrs[i].data;
2512             break;
2513         case MSR_CORE_PERF_GLOBAL_CTRL:
2514             env->msr_global_ctrl = msrs[i].data;
2515             break;
2516         case MSR_CORE_PERF_GLOBAL_STATUS:
2517             env->msr_global_status = msrs[i].data;
2518             break;
2519         case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2520             env->msr_global_ovf_ctrl = msrs[i].data;
2521             break;
2522         case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2523             env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2524             break;
2525         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2526             env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2527             break;
2528         case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2529             env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2530             break;
2531         case HV_X64_MSR_HYPERCALL:
2532             env->msr_hv_hypercall = msrs[i].data;
2533             break;
2534         case HV_X64_MSR_GUEST_OS_ID:
2535             env->msr_hv_guest_os_id = msrs[i].data;
2536             break;
2537         case HV_X64_MSR_APIC_ASSIST_PAGE:
2538             env->msr_hv_vapic = msrs[i].data;
2539             break;
2540         case HV_X64_MSR_REFERENCE_TSC:
2541             env->msr_hv_tsc = msrs[i].data;
2542             break;
2543         case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2544             env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2545             break;
2546         case HV_X64_MSR_VP_RUNTIME:
2547             env->msr_hv_runtime = msrs[i].data;
2548             break;
2549         case HV_X64_MSR_SCONTROL:
2550             env->msr_hv_synic_control = msrs[i].data;
2551             break;
2552         case HV_X64_MSR_SIEFP:
2553             env->msr_hv_synic_evt_page = msrs[i].data;
2554             break;
2555         case HV_X64_MSR_SIMP:
2556             env->msr_hv_synic_msg_page = msrs[i].data;
2557             break;
2558         case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2559             env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2560             break;
2561         case HV_X64_MSR_STIMER0_CONFIG:
2562         case HV_X64_MSR_STIMER1_CONFIG:
2563         case HV_X64_MSR_STIMER2_CONFIG:
2564         case HV_X64_MSR_STIMER3_CONFIG:
2565             env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2566                                 msrs[i].data;
2567             break;
2568         case HV_X64_MSR_STIMER0_COUNT:
2569         case HV_X64_MSR_STIMER1_COUNT:
2570         case HV_X64_MSR_STIMER2_COUNT:
2571         case HV_X64_MSR_STIMER3_COUNT:
2572             env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2573                                 msrs[i].data;
2574             break;
2575         case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2576             env->msr_hv_reenlightenment_control = msrs[i].data;
2577             break;
2578         case HV_X64_MSR_TSC_EMULATION_CONTROL:
2579             env->msr_hv_tsc_emulation_control = msrs[i].data;
2580             break;
2581         case HV_X64_MSR_TSC_EMULATION_STATUS:
2582             env->msr_hv_tsc_emulation_status = msrs[i].data;
2583             break;
2584         case MSR_MTRRdefType:
2585             env->mtrr_deftype = msrs[i].data;
2586             break;
2587         case MSR_MTRRfix64K_00000:
2588             env->mtrr_fixed[0] = msrs[i].data;
2589             break;
2590         case MSR_MTRRfix16K_80000:
2591             env->mtrr_fixed[1] = msrs[i].data;
2592             break;
2593         case MSR_MTRRfix16K_A0000:
2594             env->mtrr_fixed[2] = msrs[i].data;
2595             break;
2596         case MSR_MTRRfix4K_C0000:
2597             env->mtrr_fixed[3] = msrs[i].data;
2598             break;
2599         case MSR_MTRRfix4K_C8000:
2600             env->mtrr_fixed[4] = msrs[i].data;
2601             break;
2602         case MSR_MTRRfix4K_D0000:
2603             env->mtrr_fixed[5] = msrs[i].data;
2604             break;
2605         case MSR_MTRRfix4K_D8000:
2606             env->mtrr_fixed[6] = msrs[i].data;
2607             break;
2608         case MSR_MTRRfix4K_E0000:
2609             env->mtrr_fixed[7] = msrs[i].data;
2610             break;
2611         case MSR_MTRRfix4K_E8000:
2612             env->mtrr_fixed[8] = msrs[i].data;
2613             break;
2614         case MSR_MTRRfix4K_F0000:
2615             env->mtrr_fixed[9] = msrs[i].data;
2616             break;
2617         case MSR_MTRRfix4K_F8000:
2618             env->mtrr_fixed[10] = msrs[i].data;
2619             break;
2620         case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2621             if (index & 1) {
2622                 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2623                                                                mtrr_top_bits;
2624             } else {
2625                 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2626             }
2627             break;
2628         case MSR_IA32_SPEC_CTRL:
2629             env->spec_ctrl = msrs[i].data;
2630             break;
2631         case MSR_VIRT_SSBD:
2632             env->virt_ssbd = msrs[i].data;
2633             break;
2634         case MSR_IA32_RTIT_CTL:
2635             env->msr_rtit_ctrl = msrs[i].data;
2636             break;
2637         case MSR_IA32_RTIT_STATUS:
2638             env->msr_rtit_status = msrs[i].data;
2639             break;
2640         case MSR_IA32_RTIT_OUTPUT_BASE:
2641             env->msr_rtit_output_base = msrs[i].data;
2642             break;
2643         case MSR_IA32_RTIT_OUTPUT_MASK:
2644             env->msr_rtit_output_mask = msrs[i].data;
2645             break;
2646         case MSR_IA32_RTIT_CR3_MATCH:
2647             env->msr_rtit_cr3_match = msrs[i].data;
2648             break;
2649         case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2650             env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
2651             break;
2652         }
2653     }
2654
2655     return 0;
2656 }
2657
2658 static int kvm_put_mp_state(X86CPU *cpu)
2659 {
2660     struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2661
2662     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2663 }
2664
2665 static int kvm_get_mp_state(X86CPU *cpu)
2666 {
2667     CPUState *cs = CPU(cpu);
2668     CPUX86State *env = &cpu->env;
2669     struct kvm_mp_state mp_state;
2670     int ret;
2671
2672     ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2673     if (ret < 0) {
2674         return ret;
2675     }
2676     env->mp_state = mp_state.mp_state;
2677     if (kvm_irqchip_in_kernel()) {
2678         cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2679     }
2680     return 0;
2681 }
2682
2683 static int kvm_get_apic(X86CPU *cpu)
2684 {
2685     DeviceState *apic = cpu->apic_state;
2686     struct kvm_lapic_state kapic;
2687     int ret;
2688
2689     if (apic && kvm_irqchip_in_kernel()) {
2690         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2691         if (ret < 0) {
2692             return ret;
2693         }
2694
2695         kvm_get_apic_state(apic, &kapic);
2696     }
2697     return 0;
2698 }
2699
2700 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2701 {
2702     CPUState *cs = CPU(cpu);
2703     CPUX86State *env = &cpu->env;
2704     struct kvm_vcpu_events events = {};
2705
2706     if (!kvm_has_vcpu_events()) {
2707         return 0;
2708     }
2709
2710     events.exception.injected = (env->exception_injected >= 0);
2711     events.exception.nr = env->exception_injected;
2712     events.exception.has_error_code = env->has_error_code;
2713     events.exception.error_code = env->error_code;
2714
2715     events.interrupt.injected = (env->interrupt_injected >= 0);
2716     events.interrupt.nr = env->interrupt_injected;
2717     events.interrupt.soft = env->soft_interrupt;
2718
2719     events.nmi.injected = env->nmi_injected;
2720     events.nmi.pending = env->nmi_pending;
2721     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2722
2723     events.sipi_vector = env->sipi_vector;
2724     events.flags = 0;
2725
2726     if (has_msr_smbase) {
2727         events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2728         events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2729         if (kvm_irqchip_in_kernel()) {
2730             /* As soon as these are moved to the kernel, remove them
2731              * from cs->interrupt_request.
2732              */
2733             events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2734             events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2735             cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2736         } else {
2737             /* Keep these in cs->interrupt_request.  */
2738             events.smi.pending = 0;
2739             events.smi.latched_init = 0;
2740         }
2741         /* Stop SMI delivery on old machine types to avoid a reboot
2742          * on an inward migration of an old VM.
2743          */
2744         if (!cpu->kvm_no_smi_migration) {
2745             events.flags |= KVM_VCPUEVENT_VALID_SMM;
2746         }
2747     }
2748
2749     if (level >= KVM_PUT_RESET_STATE) {
2750         events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2751         if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2752             events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2753         }
2754     }
2755
2756     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2757 }
2758
2759 static int kvm_get_vcpu_events(X86CPU *cpu)
2760 {
2761     CPUX86State *env = &cpu->env;
2762     struct kvm_vcpu_events events;
2763     int ret;
2764
2765     if (!kvm_has_vcpu_events()) {
2766         return 0;
2767     }
2768
2769     memset(&events, 0, sizeof(events));
2770     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2771     if (ret < 0) {
2772        return ret;
2773     }
2774     env->exception_injected =
2775        events.exception.injected ? events.exception.nr : -1;
2776     env->has_error_code = events.exception.has_error_code;
2777     env->error_code = events.exception.error_code;
2778
2779     env->interrupt_injected =
2780         events.interrupt.injected ? events.interrupt.nr : -1;
2781     env->soft_interrupt = events.interrupt.soft;
2782
2783     env->nmi_injected = events.nmi.injected;
2784     env->nmi_pending = events.nmi.pending;
2785     if (events.nmi.masked) {
2786         env->hflags2 |= HF2_NMI_MASK;
2787     } else {
2788         env->hflags2 &= ~HF2_NMI_MASK;
2789     }
2790
2791     if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2792         if (events.smi.smm) {
2793             env->hflags |= HF_SMM_MASK;
2794         } else {
2795             env->hflags &= ~HF_SMM_MASK;
2796         }
2797         if (events.smi.pending) {
2798             cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2799         } else {
2800             cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2801         }
2802         if (events.smi.smm_inside_nmi) {
2803             env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2804         } else {
2805             env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2806         }
2807         if (events.smi.latched_init) {
2808             cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2809         } else {
2810             cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2811         }
2812     }
2813
2814     env->sipi_vector = events.sipi_vector;
2815
2816     return 0;
2817 }
2818
2819 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2820 {
2821     CPUState *cs = CPU(cpu);
2822     CPUX86State *env = &cpu->env;
2823     int ret = 0;
2824     unsigned long reinject_trap = 0;
2825
2826     if (!kvm_has_vcpu_events()) {
2827         if (env->exception_injected == 1) {
2828             reinject_trap = KVM_GUESTDBG_INJECT_DB;
2829         } else if (env->exception_injected == 3) {
2830             reinject_trap = KVM_GUESTDBG_INJECT_BP;
2831         }
2832         env->exception_injected = -1;
2833     }
2834
2835     /*
2836      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2837      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2838      * by updating the debug state once again if single-stepping is on.
2839      * Another reason to call kvm_update_guest_debug here is a pending debug
2840      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2841      * reinject them via SET_GUEST_DEBUG.
2842      */
2843     if (reinject_trap ||
2844         (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2845         ret = kvm_update_guest_debug(cs, reinject_trap);
2846     }
2847     return ret;
2848 }
2849
2850 static int kvm_put_debugregs(X86CPU *cpu)
2851 {
2852     CPUX86State *env = &cpu->env;
2853     struct kvm_debugregs dbgregs;
2854     int i;
2855
2856     if (!kvm_has_debugregs()) {
2857         return 0;
2858     }
2859
2860     for (i = 0; i < 4; i++) {
2861         dbgregs.db[i] = env->dr[i];
2862     }
2863     dbgregs.dr6 = env->dr[6];
2864     dbgregs.dr7 = env->dr[7];
2865     dbgregs.flags = 0;
2866
2867     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2868 }
2869
2870 static int kvm_get_debugregs(X86CPU *cpu)
2871 {
2872     CPUX86State *env = &cpu->env;
2873     struct kvm_debugregs dbgregs;
2874     int i, ret;
2875
2876     if (!kvm_has_debugregs()) {
2877         return 0;
2878     }
2879
2880     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2881     if (ret < 0) {
2882         return ret;
2883     }
2884     for (i = 0; i < 4; i++) {
2885         env->dr[i] = dbgregs.db[i];
2886     }
2887     env->dr[4] = env->dr[6] = dbgregs.dr6;
2888     env->dr[5] = env->dr[7] = dbgregs.dr7;
2889
2890     return 0;
2891 }
2892
2893 int kvm_arch_put_registers(CPUState *cpu, int level)
2894 {
2895     X86CPU *x86_cpu = X86_CPU(cpu);
2896     int ret;
2897
2898     assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2899
2900     if (level >= KVM_PUT_RESET_STATE) {
2901         ret = kvm_put_msr_feature_control(x86_cpu);
2902         if (ret < 0) {
2903             return ret;
2904         }
2905     }
2906
2907     if (level == KVM_PUT_FULL_STATE) {
2908         /* We don't check for kvm_arch_set_tsc_khz() errors here,
2909          * because TSC frequency mismatch shouldn't abort migration,
2910          * unless the user explicitly asked for a more strict TSC
2911          * setting (e.g. using an explicit "tsc-freq" option).
2912          */
2913         kvm_arch_set_tsc_khz(cpu);
2914     }
2915
2916     ret = kvm_getput_regs(x86_cpu, 1);
2917     if (ret < 0) {
2918         return ret;
2919     }
2920     ret = kvm_put_xsave(x86_cpu);
2921     if (ret < 0) {
2922         return ret;
2923     }
2924     ret = kvm_put_xcrs(x86_cpu);
2925     if (ret < 0) {
2926         return ret;
2927     }
2928     ret = kvm_put_sregs(x86_cpu);
2929     if (ret < 0) {
2930         return ret;
2931     }
2932     /* must be before kvm_put_msrs */
2933     ret = kvm_inject_mce_oldstyle(x86_cpu);
2934     if (ret < 0) {
2935         return ret;
2936     }
2937     ret = kvm_put_msrs(x86_cpu, level);
2938     if (ret < 0) {
2939         return ret;
2940     }
2941     ret = kvm_put_vcpu_events(x86_cpu, level);
2942     if (ret < 0) {
2943         return ret;
2944     }
2945     if (level >= KVM_PUT_RESET_STATE) {
2946         ret = kvm_put_mp_state(x86_cpu);
2947         if (ret < 0) {
2948             return ret;
2949         }
2950     }
2951
2952     ret = kvm_put_tscdeadline_msr(x86_cpu);
2953     if (ret < 0) {
2954         return ret;
2955     }
2956     ret = kvm_put_debugregs(x86_cpu);
2957     if (ret < 0) {
2958         return ret;
2959     }
2960     /* must be last */
2961     ret = kvm_guest_debug_workarounds(x86_cpu);
2962     if (ret < 0) {
2963         return ret;
2964     }
2965     return 0;
2966 }
2967
2968 int kvm_arch_get_registers(CPUState *cs)
2969 {
2970     X86CPU *cpu = X86_CPU(cs);
2971     int ret;
2972
2973     assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2974
2975     ret = kvm_get_vcpu_events(cpu);
2976     if (ret < 0) {
2977         goto out;
2978     }
2979     /*
2980      * KVM_GET_MPSTATE can modify CS and RIP, call it before
2981      * KVM_GET_REGS and KVM_GET_SREGS.
2982      */
2983     ret = kvm_get_mp_state(cpu);
2984     if (ret < 0) {
2985         goto out;
2986     }
2987     ret = kvm_getput_regs(cpu, 0);
2988     if (ret < 0) {
2989         goto out;
2990     }
2991     ret = kvm_get_xsave(cpu);
2992     if (ret < 0) {
2993         goto out;
2994     }
2995     ret = kvm_get_xcrs(cpu);
2996     if (ret < 0) {
2997         goto out;
2998     }
2999     ret = kvm_get_sregs(cpu);
3000     if (ret < 0) {
3001         goto out;
3002     }
3003     ret = kvm_get_msrs(cpu);
3004     if (ret < 0) {
3005         goto out;
3006     }
3007     ret = kvm_get_apic(cpu);
3008     if (ret < 0) {
3009         goto out;
3010     }
3011     ret = kvm_get_debugregs(cpu);
3012     if (ret < 0) {
3013         goto out;
3014     }
3015     ret = 0;
3016  out:
3017     cpu_sync_bndcs_hflags(&cpu->env);
3018     return ret;
3019 }
3020
3021 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
3022 {
3023     X86CPU *x86_cpu = X86_CPU(cpu);
3024     CPUX86State *env = &x86_cpu->env;
3025     int ret;
3026
3027     /* Inject NMI */
3028     if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3029         if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3030             qemu_mutex_lock_iothread();
3031             cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3032             qemu_mutex_unlock_iothread();
3033             DPRINTF("injected NMI\n");
3034             ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3035             if (ret < 0) {
3036                 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3037                         strerror(-ret));
3038             }
3039         }
3040         if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3041             qemu_mutex_lock_iothread();
3042             cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3043             qemu_mutex_unlock_iothread();
3044             DPRINTF("injected SMI\n");
3045             ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3046             if (ret < 0) {
3047                 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3048                         strerror(-ret));
3049             }
3050         }
3051     }
3052
3053     if (!kvm_pic_in_kernel()) {
3054         qemu_mutex_lock_iothread();
3055     }
3056
3057     /* Force the VCPU out of its inner loop to process any INIT requests
3058      * or (for userspace APIC, but it is cheap to combine the checks here)
3059      * pending TPR access reports.
3060      */
3061     if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
3062         if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3063             !(env->hflags & HF_SMM_MASK)) {
3064             cpu->exit_request = 1;
3065         }
3066         if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3067             cpu->exit_request = 1;
3068         }
3069     }
3070
3071     if (!kvm_pic_in_kernel()) {
3072         /* Try to inject an interrupt if the guest can accept it */
3073         if (run->ready_for_interrupt_injection &&
3074             (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
3075             (env->eflags & IF_MASK)) {
3076             int irq;
3077
3078             cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
3079             irq = cpu_get_pic_interrupt(env);
3080             if (irq >= 0) {
3081                 struct kvm_interrupt intr;
3082
3083                 intr.irq = irq;
3084                 DPRINTF("injected interrupt %d\n", irq);
3085                 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
3086                 if (ret < 0) {
3087                     fprintf(stderr,
3088                             "KVM: injection failed, interrupt lost (%s)\n",
3089                             strerror(-ret));
3090                 }
3091             }
3092         }
3093
3094         /* If we have an interrupt but the guest is not ready to receive an
3095          * interrupt, request an interrupt window exit.  This will
3096          * cause a return to userspace as soon as the guest is ready to
3097          * receive interrupts. */
3098         if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
3099             run->request_interrupt_window = 1;
3100         } else {
3101             run->request_interrupt_window = 0;
3102         }
3103
3104         DPRINTF("setting tpr\n");
3105         run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
3106
3107         qemu_mutex_unlock_iothread();
3108     }
3109 }
3110
3111 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
3112 {
3113     X86CPU *x86_cpu = X86_CPU(cpu);
3114     CPUX86State *env = &x86_cpu->env;
3115
3116     if (run->flags & KVM_RUN_X86_SMM) {
3117         env->hflags |= HF_SMM_MASK;
3118     } else {
3119         env->hflags &= ~HF_SMM_MASK;
3120     }
3121     if (run->if_flag) {
3122         env->eflags |= IF_MASK;
3123     } else {
3124         env->eflags &= ~IF_MASK;
3125     }
3126
3127     /* We need to protect the apic state against concurrent accesses from
3128      * different threads in case the userspace irqchip is used. */
3129     if (!kvm_irqchip_in_kernel()) {
3130         qemu_mutex_lock_iothread();
3131     }
3132     cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3133     cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
3134     if (!kvm_irqchip_in_kernel()) {
3135         qemu_mutex_unlock_iothread();
3136     }
3137     return cpu_get_mem_attrs(env);
3138 }
3139
3140 int kvm_arch_process_async_events(CPUState *cs)
3141 {
3142     X86CPU *cpu = X86_CPU(cs);
3143     CPUX86State *env = &cpu->env;
3144
3145     if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
3146         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3147         assert(env->mcg_cap);
3148
3149         cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
3150
3151         kvm_cpu_synchronize_state(cs);
3152
3153         if (env->exception_injected == EXCP08_DBLE) {
3154             /* this means triple fault */
3155             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
3156             cs->exit_request = 1;
3157             return 0;
3158         }
3159         env->exception_injected = EXCP12_MCHK;
3160         env->has_error_code = 0;
3161
3162         cs->halted = 0;
3163         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3164             env->mp_state = KVM_MP_STATE_RUNNABLE;
3165         }
3166     }
3167
3168     if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3169         !(env->hflags & HF_SMM_MASK)) {
3170         kvm_cpu_synchronize_state(cs);
3171         do_cpu_init(cpu);
3172     }
3173
3174     if (kvm_irqchip_in_kernel()) {
3175         return 0;
3176     }
3177
3178     if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3179         cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
3180         apic_poll_irq(cpu->apic_state);
3181     }
3182     if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3183          (env->eflags & IF_MASK)) ||
3184         (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3185         cs->halted = 0;
3186     }
3187     if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
3188         kvm_cpu_synchronize_state(cs);
3189         do_cpu_sipi(cpu);
3190     }
3191     if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3192         cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
3193         kvm_cpu_synchronize_state(cs);
3194         apic_handle_tpr_access_report(cpu->apic_state, env->eip,
3195                                       env->tpr_access_type);
3196     }
3197
3198     return cs->halted;
3199 }
3200
3201 static int kvm_handle_halt(X86CPU *cpu)
3202 {
3203     CPUState *cs = CPU(cpu);
3204     CPUX86State *env = &cpu->env;
3205
3206     if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3207           (env->eflags & IF_MASK)) &&
3208         !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3209         cs->halted = 1;
3210         return EXCP_HLT;
3211     }
3212
3213     return 0;
3214 }
3215
3216 static int kvm_handle_tpr_access(X86CPU *cpu)
3217 {
3218     CPUState *cs = CPU(cpu);
3219     struct kvm_run *run = cs->kvm_run;
3220
3221     apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
3222                                   run->tpr_access.is_write ? TPR_ACCESS_WRITE
3223                                                            : TPR_ACCESS_READ);
3224     return 1;
3225 }
3226
3227 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3228 {
3229     static const uint8_t int3 = 0xcc;
3230
3231     if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3232         cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
3233         return -EINVAL;
3234     }
3235     return 0;
3236 }
3237
3238 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3239 {
3240     uint8_t int3;
3241
3242     if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3243         cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
3244         return -EINVAL;
3245     }
3246     return 0;
3247 }
3248
3249 static struct {
3250     target_ulong addr;
3251     int len;
3252     int type;
3253 } hw_breakpoint[4];
3254
3255 static int nb_hw_breakpoint;
3256
3257 static int find_hw_breakpoint(target_ulong addr, int len, int type)
3258 {
3259     int n;
3260
3261     for (n = 0; n < nb_hw_breakpoint; n++) {
3262         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
3263             (hw_breakpoint[n].len == len || len == -1)) {
3264             return n;
3265         }
3266     }
3267     return -1;
3268 }
3269
3270 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3271                                   target_ulong len, int type)
3272 {
3273     switch (type) {
3274     case GDB_BREAKPOINT_HW:
3275         len = 1;
3276         break;
3277     case GDB_WATCHPOINT_WRITE:
3278     case GDB_WATCHPOINT_ACCESS:
3279         switch (len) {
3280         case 1:
3281             break;
3282         case 2:
3283         case 4:
3284         case 8:
3285             if (addr & (len - 1)) {
3286                 return -EINVAL;
3287             }
3288             break;
3289         default:
3290             return -EINVAL;
3291         }
3292         break;
3293     default:
3294         return -ENOSYS;
3295     }
3296
3297     if (nb_hw_breakpoint == 4) {
3298         return -ENOBUFS;
3299     }
3300     if (find_hw_breakpoint(addr, len, type) >= 0) {
3301         return -EEXIST;
3302     }
3303     hw_breakpoint[nb_hw_breakpoint].addr = addr;
3304     hw_breakpoint[nb_hw_breakpoint].len = len;
3305     hw_breakpoint[nb_hw_breakpoint].type = type;
3306     nb_hw_breakpoint++;
3307
3308     return 0;
3309 }
3310
3311 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3312                                   target_ulong len, int type)
3313 {
3314     int n;
3315
3316     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3317     if (n < 0) {
3318         return -ENOENT;
3319     }
3320     nb_hw_breakpoint--;
3321     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3322
3323     return 0;
3324 }
3325
3326 void kvm_arch_remove_all_hw_breakpoints(void)
3327 {
3328     nb_hw_breakpoint = 0;
3329 }
3330
3331 static CPUWatchpoint hw_watchpoint;
3332
3333 static int kvm_handle_debug(X86CPU *cpu,
3334                             struct kvm_debug_exit_arch *arch_info)
3335 {
3336     CPUState *cs = CPU(cpu);
3337     CPUX86State *env = &cpu->env;
3338     int ret = 0;
3339     int n;
3340
3341     if (arch_info->exception == 1) {
3342         if (arch_info->dr6 & (1 << 14)) {
3343             if (cs->singlestep_enabled) {
3344                 ret = EXCP_DEBUG;
3345             }
3346         } else {
3347             for (n = 0; n < 4; n++) {
3348                 if (arch_info->dr6 & (1 << n)) {
3349                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3350                     case 0x0:
3351                         ret = EXCP_DEBUG;
3352                         break;
3353                     case 0x1:
3354                         ret = EXCP_DEBUG;
3355                         cs->watchpoint_hit = &hw_watchpoint;
3356                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3357                         hw_watchpoint.flags = BP_MEM_WRITE;
3358                         break;
3359                     case 0x3:
3360                         ret = EXCP_DEBUG;
3361                         cs->watchpoint_hit = &hw_watchpoint;
3362                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3363                         hw_watchpoint.flags = BP_MEM_ACCESS;
3364                         break;
3365                     }
3366                 }
3367             }
3368         }
3369     } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3370         ret = EXCP_DEBUG;
3371     }
3372     if (ret == 0) {
3373         cpu_synchronize_state(cs);
3374         assert(env->exception_injected == -1);
3375
3376         /* pass to guest */
3377         env->exception_injected = arch_info->exception;
3378         env->has_error_code = 0;
3379     }
3380
3381     return ret;
3382 }
3383
3384 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3385 {
3386     const uint8_t type_code[] = {
3387         [GDB_BREAKPOINT_HW] = 0x0,
3388         [GDB_WATCHPOINT_WRITE] = 0x1,
3389         [GDB_WATCHPOINT_ACCESS] = 0x3
3390     };
3391     const uint8_t len_code[] = {
3392         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3393     };
3394     int n;
3395
3396     if (kvm_sw_breakpoints_active(cpu)) {
3397         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3398     }
3399     if (nb_hw_breakpoint > 0) {
3400         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3401         dbg->arch.debugreg[7] = 0x0600;
3402         for (n = 0; n < nb_hw_breakpoint; n++) {
3403             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3404             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3405                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3406                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3407         }
3408     }
3409 }
3410
3411 static bool host_supports_vmx(void)
3412 {
3413     uint32_t ecx, unused;
3414
3415     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3416     return ecx & CPUID_EXT_VMX;
3417 }
3418
3419 #define VMX_INVALID_GUEST_STATE 0x80000021
3420
3421 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3422 {
3423     X86CPU *cpu = X86_CPU(cs);
3424     uint64_t code;
3425     int ret;
3426
3427     switch (run->exit_reason) {
3428     case KVM_EXIT_HLT:
3429         DPRINTF("handle_hlt\n");
3430         qemu_mutex_lock_iothread();
3431         ret = kvm_handle_halt(cpu);
3432         qemu_mutex_unlock_iothread();
3433         break;
3434     case KVM_EXIT_SET_TPR:
3435         ret = 0;
3436         break;
3437     case KVM_EXIT_TPR_ACCESS:
3438         qemu_mutex_lock_iothread();
3439         ret = kvm_handle_tpr_access(cpu);
3440         qemu_mutex_unlock_iothread();
3441         break;
3442     case KVM_EXIT_FAIL_ENTRY:
3443         code = run->fail_entry.hardware_entry_failure_reason;
3444         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3445                 code);
3446         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3447             fprintf(stderr,
3448                     "\nIf you're running a guest on an Intel machine without "
3449                         "unrestricted mode\n"
3450                     "support, the failure can be most likely due to the guest "
3451                         "entering an invalid\n"
3452                     "state for Intel VT. For example, the guest maybe running "
3453                         "in big real mode\n"
3454                     "which is not supported on less recent Intel processors."
3455                         "\n\n");
3456         }
3457         ret = -1;
3458         break;
3459     case KVM_EXIT_EXCEPTION:
3460         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3461                 run->ex.exception, run->ex.error_code);
3462         ret = -1;
3463         break;
3464     case KVM_EXIT_DEBUG:
3465         DPRINTF("kvm_exit_debug\n");
3466         qemu_mutex_lock_iothread();
3467         ret = kvm_handle_debug(cpu, &run->debug.arch);
3468         qemu_mutex_unlock_iothread();
3469         break;
3470     case KVM_EXIT_HYPERV:
3471         ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3472         break;
3473     case KVM_EXIT_IOAPIC_EOI:
3474         ioapic_eoi_broadcast(run->eoi.vector);
3475         ret = 0;
3476         break;
3477     default:
3478         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3479         ret = -1;
3480         break;
3481     }
3482
3483     return ret;
3484 }
3485
3486 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3487 {
3488     X86CPU *cpu = X86_CPU(cs);
3489     CPUX86State *env = &cpu->env;
3490
3491     kvm_cpu_synchronize_state(cs);
3492     return !(env->cr[0] & CR0_PE_MASK) ||
3493            ((env->segs[R_CS].selector  & 3) != 3);
3494 }
3495
3496 void kvm_arch_init_irq_routing(KVMState *s)
3497 {
3498     if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3499         /* If kernel can't do irq routing, interrupt source
3500          * override 0->2 cannot be set up as required by HPET.
3501          * So we have to disable it.
3502          */
3503         no_hpet = 1;
3504     }
3505     /* We know at this point that we're using the in-kernel
3506      * irqchip, so we can use irqfds, and on x86 we know
3507      * we can use msi via irqfd and GSI routing.
3508      */
3509     kvm_msi_via_irqfd_allowed = true;
3510     kvm_gsi_routing_allowed = true;
3511
3512     if (kvm_irqchip_is_split()) {
3513         int i;
3514
3515         /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3516            MSI routes for signaling interrupts to the local apics. */
3517         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3518             if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3519                 error_report("Could not enable split IRQ mode.");
3520                 exit(1);
3521             }
3522         }
3523     }
3524 }
3525
3526 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3527 {
3528     int ret;
3529     if (machine_kernel_irqchip_split(ms)) {
3530         ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3531         if (ret) {
3532             error_report("Could not enable split irqchip mode: %s",
3533                          strerror(-ret));
3534             exit(1);
3535         } else {
3536             DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3537             kvm_split_irqchip = true;
3538             return 1;
3539         }
3540     } else {
3541         return 0;
3542     }
3543 }
3544
3545 /* Classic KVM device assignment interface. Will remain x86 only. */
3546 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3547                           uint32_t flags, uint32_t *dev_id)
3548 {
3549     struct kvm_assigned_pci_dev dev_data = {
3550         .segnr = dev_addr->domain,
3551         .busnr = dev_addr->bus,
3552         .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3553         .flags = flags,
3554     };
3555     int ret;
3556
3557     dev_data.assigned_dev_id =
3558         (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3559
3560     ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3561     if (ret < 0) {
3562         return ret;
3563     }
3564
3565     *dev_id = dev_data.assigned_dev_id;
3566
3567     return 0;
3568 }
3569
3570 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3571 {
3572     struct kvm_assigned_pci_dev dev_data = {
3573         .assigned_dev_id = dev_id,
3574     };
3575
3576     return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3577 }
3578
3579 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3580                                    uint32_t irq_type, uint32_t guest_irq)
3581 {
3582     struct kvm_assigned_irq assigned_irq = {
3583         .assigned_dev_id = dev_id,
3584         .guest_irq = guest_irq,
3585         .flags = irq_type,
3586     };
3587
3588     if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3589         return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3590     } else {
3591         return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3592     }
3593 }
3594
3595 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3596                            uint32_t guest_irq)
3597 {
3598     uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3599         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3600
3601     return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3602 }
3603
3604 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3605 {
3606     struct kvm_assigned_pci_dev dev_data = {
3607         .assigned_dev_id = dev_id,
3608         .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3609     };
3610
3611     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3612 }
3613
3614 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3615                                      uint32_t type)
3616 {
3617     struct kvm_assigned_irq assigned_irq = {
3618         .assigned_dev_id = dev_id,
3619         .flags = type,
3620     };
3621
3622     return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3623 }
3624
3625 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3626 {
3627     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3628         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3629 }
3630
3631 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3632 {
3633     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3634                                               KVM_DEV_IRQ_GUEST_MSI, virq);
3635 }
3636
3637 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3638 {
3639     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3640                                                 KVM_DEV_IRQ_HOST_MSI);
3641 }
3642
3643 bool kvm_device_msix_supported(KVMState *s)
3644 {
3645     /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3646      * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3647     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3648 }
3649
3650 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3651                                  uint32_t nr_vectors)
3652 {
3653     struct kvm_assigned_msix_nr msix_nr = {
3654         .assigned_dev_id = dev_id,
3655         .entry_nr = nr_vectors,
3656     };
3657
3658     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3659 }
3660
3661 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3662                                int virq)
3663 {
3664     struct kvm_assigned_msix_entry msix_entry = {
3665         .assigned_dev_id = dev_id,
3666         .gsi = virq,
3667         .entry = vector,
3668     };
3669
3670     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3671 }
3672
3673 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3674 {
3675     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3676                                               KVM_DEV_IRQ_GUEST_MSIX, 0);
3677 }
3678
3679 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3680 {
3681     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3682                                                 KVM_DEV_IRQ_HOST_MSIX);
3683 }
3684
3685 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3686                              uint64_t address, uint32_t data, PCIDevice *dev)
3687 {
3688     X86IOMMUState *iommu = x86_iommu_get_default();
3689
3690     if (iommu) {
3691         int ret;
3692         MSIMessage src, dst;
3693         X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3694
3695         if (!class->int_remap) {
3696             return 0;
3697         }
3698
3699         src.address = route->u.msi.address_hi;
3700         src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3701         src.address |= route->u.msi.address_lo;
3702         src.data = route->u.msi.data;
3703
3704         ret = class->int_remap(iommu, &src, &dst, dev ? \
3705                                pci_requester_id(dev) : \
3706                                X86_IOMMU_SID_INVALID);
3707         if (ret) {
3708             trace_kvm_x86_fixup_msi_error(route->gsi);
3709             return 1;
3710         }
3711
3712         route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3713         route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3714         route->u.msi.data = dst.data;
3715     }
3716
3717     return 0;
3718 }
3719
3720 typedef struct MSIRouteEntry MSIRouteEntry;
3721
3722 struct MSIRouteEntry {
3723     PCIDevice *dev;             /* Device pointer */
3724     int vector;                 /* MSI/MSIX vector index */
3725     int virq;                   /* Virtual IRQ index */
3726     QLIST_ENTRY(MSIRouteEntry) list;
3727 };
3728
3729 /* List of used GSI routes */
3730 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3731     QLIST_HEAD_INITIALIZER(msi_route_list);
3732
3733 static void kvm_update_msi_routes_all(void *private, bool global,
3734                                       uint32_t index, uint32_t mask)
3735 {
3736     int cnt = 0;
3737     MSIRouteEntry *entry;
3738     MSIMessage msg;
3739     PCIDevice *dev;
3740
3741     /* TODO: explicit route update */
3742     QLIST_FOREACH(entry, &msi_route_list, list) {
3743         cnt++;
3744         dev = entry->dev;
3745         if (!msix_enabled(dev) && !msi_enabled(dev)) {
3746             continue;
3747         }
3748         msg = pci_get_msi_message(dev, entry->vector);
3749         kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
3750     }
3751     kvm_irqchip_commit_routes(kvm_state);
3752     trace_kvm_x86_update_msi_routes(cnt);
3753 }
3754
3755 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3756                                 int vector, PCIDevice *dev)
3757 {
3758     static bool notify_list_inited = false;
3759     MSIRouteEntry *entry;
3760
3761     if (!dev) {
3762         /* These are (possibly) IOAPIC routes only used for split
3763          * kernel irqchip mode, while what we are housekeeping are
3764          * PCI devices only. */
3765         return 0;
3766     }
3767
3768     entry = g_new0(MSIRouteEntry, 1);
3769     entry->dev = dev;
3770     entry->vector = vector;
3771     entry->virq = route->gsi;
3772     QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3773
3774     trace_kvm_x86_add_msi_route(route->gsi);
3775
3776     if (!notify_list_inited) {
3777         /* For the first time we do add route, add ourselves into
3778          * IOMMU's IEC notify list if needed. */
3779         X86IOMMUState *iommu = x86_iommu_get_default();
3780         if (iommu) {
3781             x86_iommu_iec_register_notifier(iommu,
3782                                             kvm_update_msi_routes_all,
3783                                             NULL);
3784         }
3785         notify_list_inited = true;
3786     }
3787     return 0;
3788 }
3789
3790 int kvm_arch_release_virq_post(int virq)
3791 {
3792     MSIRouteEntry *entry, *next;
3793     QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3794         if (entry->virq == virq) {
3795             trace_kvm_x86_remove_msi_route(virq);
3796             QLIST_REMOVE(entry, list);
3797             g_free(entry);
3798             break;
3799         }
3800     }
3801     return 0;
3802 }
3803
3804 int kvm_arch_msi_data_to_gsi(uint32_t data)
3805 {
3806     abort();
3807 }