4 typedef struct QEMU_PACKED NvmeBar
{
18 uint8_t padding
[3520]; /* not used by QEMU */
25 uint8_t reserved
[484];
36 CAP_MPSMIN_SHIFT
= 48,
37 CAP_MPSMAX_SHIFT
= 52,
42 CAP_MQES_MASK
= 0xffff,
49 CAP_MPSMIN_MASK
= 0xf,
50 CAP_MPSMAX_MASK
= 0xf,
54 #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK)
55 #define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK)
56 #define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK)
57 #define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK)
58 #define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK)
59 #define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK)
60 #define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK)
61 #define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK)
62 #define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK)
64 #define NVME_CAP_SET_MQES(cap, val) (cap |= (uint64_t)(val & CAP_MQES_MASK) \
66 #define NVME_CAP_SET_CQR(cap, val) (cap |= (uint64_t)(val & CAP_CQR_MASK) \
68 #define NVME_CAP_SET_AMS(cap, val) (cap |= (uint64_t)(val & CAP_AMS_MASK) \
70 #define NVME_CAP_SET_TO(cap, val) (cap |= (uint64_t)(val & CAP_TO_MASK) \
72 #define NVME_CAP_SET_DSTRD(cap, val) (cap |= (uint64_t)(val & CAP_DSTRD_MASK) \
74 #define NVME_CAP_SET_NSSRS(cap, val) (cap |= (uint64_t)(val & CAP_NSSRS_MASK) \
76 #define NVME_CAP_SET_CSS(cap, val) (cap |= (uint64_t)(val & CAP_CSS_MASK) \
78 #define NVME_CAP_SET_MPSMIN(cap, val) (cap |= (uint64_t)(val & CAP_MPSMIN_MASK)\
80 #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\
82 #define NVME_CAP_SET_PMRS(cap, val) (cap |= (uint64_t)(val & CAP_PMR_MASK)\
86 NVME_CAP_CSS_NVM
= 1 << 0,
87 NVME_CAP_CSS_ADMIN_ONLY
= 1 << 7,
106 CC_IOSQES_MASK
= 0xf,
107 CC_IOCQES_MASK
= 0xf,
110 #define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK)
111 #define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK)
112 #define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK)
113 #define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK)
114 #define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK)
115 #define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK)
116 #define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK)
119 NVME_CC_CSS_NVM
= 0x0,
120 NVME_CC_CSS_ADMIN_ONLY
= 0x7,
127 CSTS_NSSRO_SHIFT
= 4,
133 CSTS_SHST_MASK
= 0x3,
134 CSTS_NSSRO_MASK
= 0x1,
138 NVME_CSTS_READY
= 1 << CSTS_RDY_SHIFT
,
139 NVME_CSTS_FAILED
= 1 << CSTS_CFS_SHIFT
,
140 NVME_CSTS_SHST_NORMAL
= 0 << CSTS_SHST_SHIFT
,
141 NVME_CSTS_SHST_PROGRESS
= 1 << CSTS_SHST_SHIFT
,
142 NVME_CSTS_SHST_COMPLETE
= 2 << CSTS_SHST_SHIFT
,
143 NVME_CSTS_NSSRO
= 1 << CSTS_NSSRO_SHIFT
,
146 #define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK)
147 #define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK)
148 #define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK)
149 #define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK)
157 AQA_ASQS_MASK
= 0xfff,
158 AQA_ACQS_MASK
= 0xfff,
161 #define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK)
162 #define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK)
164 enum NvmeCmblocShift
{
165 CMBLOC_BIR_SHIFT
= 0,
166 CMBLOC_OFST_SHIFT
= 12,
169 enum NvmeCmblocMask
{
170 CMBLOC_BIR_MASK
= 0x7,
171 CMBLOC_OFST_MASK
= 0xfffff,
174 #define NVME_CMBLOC_BIR(cmbloc) ((cmbloc >> CMBLOC_BIR_SHIFT) & \
176 #define NVME_CMBLOC_OFST(cmbloc)((cmbloc >> CMBLOC_OFST_SHIFT) & \
179 #define NVME_CMBLOC_SET_BIR(cmbloc, val) \
180 (cmbloc |= (uint64_t)(val & CMBLOC_BIR_MASK) << CMBLOC_BIR_SHIFT)
181 #define NVME_CMBLOC_SET_OFST(cmbloc, val) \
182 (cmbloc |= (uint64_t)(val & CMBLOC_OFST_MASK) << CMBLOC_OFST_SHIFT)
184 enum NvmeCmbszShift
{
187 CMBSZ_LISTS_SHIFT
= 2,
195 CMBSZ_SQS_MASK
= 0x1,
196 CMBSZ_CQS_MASK
= 0x1,
197 CMBSZ_LISTS_MASK
= 0x1,
198 CMBSZ_RDS_MASK
= 0x1,
199 CMBSZ_WDS_MASK
= 0x1,
200 CMBSZ_SZU_MASK
= 0xf,
201 CMBSZ_SZ_MASK
= 0xfffff,
204 #define NVME_CMBSZ_SQS(cmbsz) ((cmbsz >> CMBSZ_SQS_SHIFT) & CMBSZ_SQS_MASK)
205 #define NVME_CMBSZ_CQS(cmbsz) ((cmbsz >> CMBSZ_CQS_SHIFT) & CMBSZ_CQS_MASK)
206 #define NVME_CMBSZ_LISTS(cmbsz)((cmbsz >> CMBSZ_LISTS_SHIFT) & CMBSZ_LISTS_MASK)
207 #define NVME_CMBSZ_RDS(cmbsz) ((cmbsz >> CMBSZ_RDS_SHIFT) & CMBSZ_RDS_MASK)
208 #define NVME_CMBSZ_WDS(cmbsz) ((cmbsz >> CMBSZ_WDS_SHIFT) & CMBSZ_WDS_MASK)
209 #define NVME_CMBSZ_SZU(cmbsz) ((cmbsz >> CMBSZ_SZU_SHIFT) & CMBSZ_SZU_MASK)
210 #define NVME_CMBSZ_SZ(cmbsz) ((cmbsz >> CMBSZ_SZ_SHIFT) & CMBSZ_SZ_MASK)
212 #define NVME_CMBSZ_SET_SQS(cmbsz, val) \
213 (cmbsz |= (uint64_t)(val & CMBSZ_SQS_MASK) << CMBSZ_SQS_SHIFT)
214 #define NVME_CMBSZ_SET_CQS(cmbsz, val) \
215 (cmbsz |= (uint64_t)(val & CMBSZ_CQS_MASK) << CMBSZ_CQS_SHIFT)
216 #define NVME_CMBSZ_SET_LISTS(cmbsz, val) \
217 (cmbsz |= (uint64_t)(val & CMBSZ_LISTS_MASK) << CMBSZ_LISTS_SHIFT)
218 #define NVME_CMBSZ_SET_RDS(cmbsz, val) \
219 (cmbsz |= (uint64_t)(val & CMBSZ_RDS_MASK) << CMBSZ_RDS_SHIFT)
220 #define NVME_CMBSZ_SET_WDS(cmbsz, val) \
221 (cmbsz |= (uint64_t)(val & CMBSZ_WDS_MASK) << CMBSZ_WDS_SHIFT)
222 #define NVME_CMBSZ_SET_SZU(cmbsz, val) \
223 (cmbsz |= (uint64_t)(val & CMBSZ_SZU_MASK) << CMBSZ_SZU_SHIFT)
224 #define NVME_CMBSZ_SET_SZ(cmbsz, val) \
225 (cmbsz |= (uint64_t)(val & CMBSZ_SZ_MASK) << CMBSZ_SZ_SHIFT)
227 #define NVME_CMBSZ_GETSIZE(cmbsz) \
228 (NVME_CMBSZ_SZ(cmbsz) * (1 << (12 + 4 * NVME_CMBSZ_SZU(cmbsz))))
230 enum NvmePmrcapShift
{
231 PMRCAP_RDS_SHIFT
= 3,
232 PMRCAP_WDS_SHIFT
= 4,
233 PMRCAP_BIR_SHIFT
= 5,
234 PMRCAP_PMRTU_SHIFT
= 8,
235 PMRCAP_PMRWBM_SHIFT
= 10,
236 PMRCAP_PMRTO_SHIFT
= 16,
237 PMRCAP_CMSS_SHIFT
= 24,
240 enum NvmePmrcapMask
{
241 PMRCAP_RDS_MASK
= 0x1,
242 PMRCAP_WDS_MASK
= 0x1,
243 PMRCAP_BIR_MASK
= 0x7,
244 PMRCAP_PMRTU_MASK
= 0x3,
245 PMRCAP_PMRWBM_MASK
= 0xf,
246 PMRCAP_PMRTO_MASK
= 0xff,
247 PMRCAP_CMSS_MASK
= 0x1,
250 #define NVME_PMRCAP_RDS(pmrcap) \
251 ((pmrcap >> PMRCAP_RDS_SHIFT) & PMRCAP_RDS_MASK)
252 #define NVME_PMRCAP_WDS(pmrcap) \
253 ((pmrcap >> PMRCAP_WDS_SHIFT) & PMRCAP_WDS_MASK)
254 #define NVME_PMRCAP_BIR(pmrcap) \
255 ((pmrcap >> PMRCAP_BIR_SHIFT) & PMRCAP_BIR_MASK)
256 #define NVME_PMRCAP_PMRTU(pmrcap) \
257 ((pmrcap >> PMRCAP_PMRTU_SHIFT) & PMRCAP_PMRTU_MASK)
258 #define NVME_PMRCAP_PMRWBM(pmrcap) \
259 ((pmrcap >> PMRCAP_PMRWBM_SHIFT) & PMRCAP_PMRWBM_MASK)
260 #define NVME_PMRCAP_PMRTO(pmrcap) \
261 ((pmrcap >> PMRCAP_PMRTO_SHIFT) & PMRCAP_PMRTO_MASK)
262 #define NVME_PMRCAP_CMSS(pmrcap) \
263 ((pmrcap >> PMRCAP_CMSS_SHIFT) & PMRCAP_CMSS_MASK)
265 #define NVME_PMRCAP_SET_RDS(pmrcap, val) \
266 (pmrcap |= (uint64_t)(val & PMRCAP_RDS_MASK) << PMRCAP_RDS_SHIFT)
267 #define NVME_PMRCAP_SET_WDS(pmrcap, val) \
268 (pmrcap |= (uint64_t)(val & PMRCAP_WDS_MASK) << PMRCAP_WDS_SHIFT)
269 #define NVME_PMRCAP_SET_BIR(pmrcap, val) \
270 (pmrcap |= (uint64_t)(val & PMRCAP_BIR_MASK) << PMRCAP_BIR_SHIFT)
271 #define NVME_PMRCAP_SET_PMRTU(pmrcap, val) \
272 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTU_MASK) << PMRCAP_PMRTU_SHIFT)
273 #define NVME_PMRCAP_SET_PMRWBM(pmrcap, val) \
274 (pmrcap |= (uint64_t)(val & PMRCAP_PMRWBM_MASK) << PMRCAP_PMRWBM_SHIFT)
275 #define NVME_PMRCAP_SET_PMRTO(pmrcap, val) \
276 (pmrcap |= (uint64_t)(val & PMRCAP_PMRTO_MASK) << PMRCAP_PMRTO_SHIFT)
277 #define NVME_PMRCAP_SET_CMSS(pmrcap, val) \
278 (pmrcap |= (uint64_t)(val & PMRCAP_CMSS_MASK) << PMRCAP_CMSS_SHIFT)
280 enum NvmePmrctlShift
{
284 enum NvmePmrctlMask
{
285 PMRCTL_EN_MASK
= 0x1,
288 #define NVME_PMRCTL_EN(pmrctl) ((pmrctl >> PMRCTL_EN_SHIFT) & PMRCTL_EN_MASK)
290 #define NVME_PMRCTL_SET_EN(pmrctl, val) \
291 (pmrctl |= (uint64_t)(val & PMRCTL_EN_MASK) << PMRCTL_EN_SHIFT)
293 enum NvmePmrstsShift
{
294 PMRSTS_ERR_SHIFT
= 0,
295 PMRSTS_NRDY_SHIFT
= 8,
296 PMRSTS_HSTS_SHIFT
= 9,
297 PMRSTS_CBAI_SHIFT
= 12,
300 enum NvmePmrstsMask
{
301 PMRSTS_ERR_MASK
= 0xff,
302 PMRSTS_NRDY_MASK
= 0x1,
303 PMRSTS_HSTS_MASK
= 0x7,
304 PMRSTS_CBAI_MASK
= 0x1,
307 #define NVME_PMRSTS_ERR(pmrsts) \
308 ((pmrsts >> PMRSTS_ERR_SHIFT) & PMRSTS_ERR_MASK)
309 #define NVME_PMRSTS_NRDY(pmrsts) \
310 ((pmrsts >> PMRSTS_NRDY_SHIFT) & PMRSTS_NRDY_MASK)
311 #define NVME_PMRSTS_HSTS(pmrsts) \
312 ((pmrsts >> PMRSTS_HSTS_SHIFT) & PMRSTS_HSTS_MASK)
313 #define NVME_PMRSTS_CBAI(pmrsts) \
314 ((pmrsts >> PMRSTS_CBAI_SHIFT) & PMRSTS_CBAI_MASK)
316 #define NVME_PMRSTS_SET_ERR(pmrsts, val) \
317 (pmrsts |= (uint64_t)(val & PMRSTS_ERR_MASK) << PMRSTS_ERR_SHIFT)
318 #define NVME_PMRSTS_SET_NRDY(pmrsts, val) \
319 (pmrsts |= (uint64_t)(val & PMRSTS_NRDY_MASK) << PMRSTS_NRDY_SHIFT)
320 #define NVME_PMRSTS_SET_HSTS(pmrsts, val) \
321 (pmrsts |= (uint64_t)(val & PMRSTS_HSTS_MASK) << PMRSTS_HSTS_SHIFT)
322 #define NVME_PMRSTS_SET_CBAI(pmrsts, val) \
323 (pmrsts |= (uint64_t)(val & PMRSTS_CBAI_MASK) << PMRSTS_CBAI_SHIFT)
325 enum NvmePmrebsShift
{
326 PMREBS_PMRSZU_SHIFT
= 0,
327 PMREBS_RBB_SHIFT
= 4,
328 PMREBS_PMRWBZ_SHIFT
= 8,
331 enum NvmePmrebsMask
{
332 PMREBS_PMRSZU_MASK
= 0xf,
333 PMREBS_RBB_MASK
= 0x1,
334 PMREBS_PMRWBZ_MASK
= 0xffffff,
337 #define NVME_PMREBS_PMRSZU(pmrebs) \
338 ((pmrebs >> PMREBS_PMRSZU_SHIFT) & PMREBS_PMRSZU_MASK)
339 #define NVME_PMREBS_RBB(pmrebs) \
340 ((pmrebs >> PMREBS_RBB_SHIFT) & PMREBS_RBB_MASK)
341 #define NVME_PMREBS_PMRWBZ(pmrebs) \
342 ((pmrebs >> PMREBS_PMRWBZ_SHIFT) & PMREBS_PMRWBZ_MASK)
344 #define NVME_PMREBS_SET_PMRSZU(pmrebs, val) \
345 (pmrebs |= (uint64_t)(val & PMREBS_PMRSZU_MASK) << PMREBS_PMRSZU_SHIFT)
346 #define NVME_PMREBS_SET_RBB(pmrebs, val) \
347 (pmrebs |= (uint64_t)(val & PMREBS_RBB_MASK) << PMREBS_RBB_SHIFT)
348 #define NVME_PMREBS_SET_PMRWBZ(pmrebs, val) \
349 (pmrebs |= (uint64_t)(val & PMREBS_PMRWBZ_MASK) << PMREBS_PMRWBZ_SHIFT)
351 enum NvmePmrswtpShift
{
352 PMRSWTP_PMRSWTU_SHIFT
= 0,
353 PMRSWTP_PMRSWTV_SHIFT
= 8,
356 enum NvmePmrswtpMask
{
357 PMRSWTP_PMRSWTU_MASK
= 0xf,
358 PMRSWTP_PMRSWTV_MASK
= 0xffffff,
361 #define NVME_PMRSWTP_PMRSWTU(pmrswtp) \
362 ((pmrswtp >> PMRSWTP_PMRSWTU_SHIFT) & PMRSWTP_PMRSWTU_MASK)
363 #define NVME_PMRSWTP_PMRSWTV(pmrswtp) \
364 ((pmrswtp >> PMRSWTP_PMRSWTV_SHIFT) & PMRSWTP_PMRSWTV_MASK)
366 #define NVME_PMRSWTP_SET_PMRSWTU(pmrswtp, val) \
367 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTU_MASK) << PMRSWTP_PMRSWTU_SHIFT)
368 #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \
369 (pmrswtp |= (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWTV_SHIFT)
371 enum NvmePmrmscShift
{
372 PMRMSC_CMSE_SHIFT
= 1,
373 PMRMSC_CBA_SHIFT
= 12,
376 enum NvmePmrmscMask
{
377 PMRMSC_CMSE_MASK
= 0x1,
378 PMRMSC_CBA_MASK
= 0xfffffffffffff,
381 #define NVME_PMRMSC_CMSE(pmrmsc) \
382 ((pmrmsc >> PMRMSC_CMSE_SHIFT) & PMRMSC_CMSE_MASK)
383 #define NVME_PMRMSC_CBA(pmrmsc) \
384 ((pmrmsc >> PMRMSC_CBA_SHIFT) & PMRMSC_CBA_MASK)
386 #define NVME_PMRMSC_SET_CMSE(pmrmsc, val) \
387 (pmrmsc |= (uint64_t)(val & PMRMSC_CMSE_MASK) << PMRMSC_CMSE_SHIFT)
388 #define NVME_PMRMSC_SET_CBA(pmrmsc, val) \
389 (pmrmsc |= (uint64_t)(val & PMRMSC_CBA_MASK) << PMRMSC_CBA_SHIFT)
391 enum NvmeSglDescriptorType
{
392 NVME_SGL_DESCR_TYPE_DATA_BLOCK
= 0x0,
393 NVME_SGL_DESCR_TYPE_BIT_BUCKET
= 0x1,
394 NVME_SGL_DESCR_TYPE_SEGMENT
= 0x2,
395 NVME_SGL_DESCR_TYPE_LAST_SEGMENT
= 0x3,
396 NVME_SGL_DESCR_TYPE_KEYED_DATA_BLOCK
= 0x4,
398 NVME_SGL_DESCR_TYPE_VENDOR_SPECIFIC
= 0xf,
401 enum NvmeSglDescriptorSubtype
{
402 NVME_SGL_DESCR_SUBTYPE_ADDRESS
= 0x0,
405 typedef struct QEMU_PACKED NvmeSglDescriptor
{
412 #define NVME_SGL_TYPE(type) ((type >> 4) & 0xf)
413 #define NVME_SGL_SUBTYPE(type) (type & 0xf)
415 typedef union NvmeCmdDptr
{
421 NvmeSglDescriptor sgl
;
426 NVME_PSDT_SGL_MPTR_CONTIGUOUS
= 0x1,
427 NVME_PSDT_SGL_MPTR_SGL
= 0x2,
430 typedef struct QEMU_PACKED NvmeCmd
{
446 #define NVME_CMD_FLAGS_FUSE(flags) (flags & 0x3)
447 #define NVME_CMD_FLAGS_PSDT(flags) ((flags >> 6) & 0x3)
449 enum NvmeAdminCommands
{
450 NVME_ADM_CMD_DELETE_SQ
= 0x00,
451 NVME_ADM_CMD_CREATE_SQ
= 0x01,
452 NVME_ADM_CMD_GET_LOG_PAGE
= 0x02,
453 NVME_ADM_CMD_DELETE_CQ
= 0x04,
454 NVME_ADM_CMD_CREATE_CQ
= 0x05,
455 NVME_ADM_CMD_IDENTIFY
= 0x06,
456 NVME_ADM_CMD_ABORT
= 0x08,
457 NVME_ADM_CMD_SET_FEATURES
= 0x09,
458 NVME_ADM_CMD_GET_FEATURES
= 0x0a,
459 NVME_ADM_CMD_ASYNC_EV_REQ
= 0x0c,
460 NVME_ADM_CMD_ACTIVATE_FW
= 0x10,
461 NVME_ADM_CMD_DOWNLOAD_FW
= 0x11,
462 NVME_ADM_CMD_FORMAT_NVM
= 0x80,
463 NVME_ADM_CMD_SECURITY_SEND
= 0x81,
464 NVME_ADM_CMD_SECURITY_RECV
= 0x82,
467 enum NvmeIoCommands
{
468 NVME_CMD_FLUSH
= 0x00,
469 NVME_CMD_WRITE
= 0x01,
470 NVME_CMD_READ
= 0x02,
471 NVME_CMD_WRITE_UNCOR
= 0x04,
472 NVME_CMD_COMPARE
= 0x05,
473 NVME_CMD_WRITE_ZEROES
= 0x08,
477 typedef struct QEMU_PACKED NvmeDeleteQ
{
487 typedef struct QEMU_PACKED NvmeCreateCq
{
501 #define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1)
502 #define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1)
504 typedef struct QEMU_PACKED NvmeCreateSq
{
518 #define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1)
519 #define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3)
521 enum NvmeQueueFlags
{
523 NVME_Q_PRIO_URGENT
= 0,
524 NVME_Q_PRIO_HIGH
= 1,
525 NVME_Q_PRIO_NORMAL
= 2,
529 typedef struct QEMU_PACKED NvmeIdentify
{
541 typedef struct QEMU_PACKED NvmeRwCmd
{
559 NVME_RW_LR
= 1 << 15,
560 NVME_RW_FUA
= 1 << 14,
561 NVME_RW_DSM_FREQ_UNSPEC
= 0,
562 NVME_RW_DSM_FREQ_TYPICAL
= 1,
563 NVME_RW_DSM_FREQ_RARE
= 2,
564 NVME_RW_DSM_FREQ_READS
= 3,
565 NVME_RW_DSM_FREQ_WRITES
= 4,
566 NVME_RW_DSM_FREQ_RW
= 5,
567 NVME_RW_DSM_FREQ_ONCE
= 6,
568 NVME_RW_DSM_FREQ_PREFETCH
= 7,
569 NVME_RW_DSM_FREQ_TEMP
= 8,
570 NVME_RW_DSM_LATENCY_NONE
= 0 << 4,
571 NVME_RW_DSM_LATENCY_IDLE
= 1 << 4,
572 NVME_RW_DSM_LATENCY_NORM
= 2 << 4,
573 NVME_RW_DSM_LATENCY_LOW
= 3 << 4,
574 NVME_RW_DSM_SEQ_REQ
= 1 << 6,
575 NVME_RW_DSM_COMPRESSED
= 1 << 7,
576 NVME_RW_PRINFO_PRACT
= 1 << 13,
577 NVME_RW_PRINFO_PRCHK_GUARD
= 1 << 12,
578 NVME_RW_PRINFO_PRCHK_APP
= 1 << 11,
579 NVME_RW_PRINFO_PRCHK_REF
= 1 << 10,
582 typedef struct QEMU_PACKED NvmeDsmCmd
{
595 NVME_DSMGMT_IDR
= 1 << 0,
596 NVME_DSMGMT_IDW
= 1 << 1,
597 NVME_DSMGMT_AD
= 1 << 2,
600 typedef struct QEMU_PACKED NvmeDsmRange
{
606 enum NvmeAsyncEventRequest
{
607 NVME_AER_TYPE_ERROR
= 0,
608 NVME_AER_TYPE_SMART
= 1,
609 NVME_AER_TYPE_IO_SPECIFIC
= 6,
610 NVME_AER_TYPE_VENDOR_SPECIFIC
= 7,
611 NVME_AER_INFO_ERR_INVALID_DB_REGISTER
= 0,
612 NVME_AER_INFO_ERR_INVALID_DB_VALUE
= 1,
613 NVME_AER_INFO_ERR_DIAG_FAIL
= 2,
614 NVME_AER_INFO_ERR_PERS_INTERNAL_ERR
= 3,
615 NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR
= 4,
616 NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR
= 5,
617 NVME_AER_INFO_SMART_RELIABILITY
= 0,
618 NVME_AER_INFO_SMART_TEMP_THRESH
= 1,
619 NVME_AER_INFO_SMART_SPARE_THRESH
= 2,
622 typedef struct QEMU_PACKED NvmeAerResult
{
629 typedef struct QEMU_PACKED NvmeCqe
{
638 enum NvmeStatusCodes
{
639 NVME_SUCCESS
= 0x0000,
640 NVME_INVALID_OPCODE
= 0x0001,
641 NVME_INVALID_FIELD
= 0x0002,
642 NVME_CID_CONFLICT
= 0x0003,
643 NVME_DATA_TRAS_ERROR
= 0x0004,
644 NVME_POWER_LOSS_ABORT
= 0x0005,
645 NVME_INTERNAL_DEV_ERROR
= 0x0006,
646 NVME_CMD_ABORT_REQ
= 0x0007,
647 NVME_CMD_ABORT_SQ_DEL
= 0x0008,
648 NVME_CMD_ABORT_FAILED_FUSE
= 0x0009,
649 NVME_CMD_ABORT_MISSING_FUSE
= 0x000a,
650 NVME_INVALID_NSID
= 0x000b,
651 NVME_CMD_SEQ_ERROR
= 0x000c,
652 NVME_INVALID_SGL_SEG_DESCR
= 0x000d,
653 NVME_INVALID_NUM_SGL_DESCRS
= 0x000e,
654 NVME_DATA_SGL_LEN_INVALID
= 0x000f,
655 NVME_MD_SGL_LEN_INVALID
= 0x0010,
656 NVME_SGL_DESCR_TYPE_INVALID
= 0x0011,
657 NVME_INVALID_USE_OF_CMB
= 0x0012,
658 NVME_INVALID_PRP_OFFSET
= 0x0013,
659 NVME_LBA_RANGE
= 0x0080,
660 NVME_CAP_EXCEEDED
= 0x0081,
661 NVME_NS_NOT_READY
= 0x0082,
662 NVME_NS_RESV_CONFLICT
= 0x0083,
663 NVME_INVALID_CQID
= 0x0100,
664 NVME_INVALID_QID
= 0x0101,
665 NVME_MAX_QSIZE_EXCEEDED
= 0x0102,
666 NVME_ACL_EXCEEDED
= 0x0103,
667 NVME_RESERVED
= 0x0104,
668 NVME_AER_LIMIT_EXCEEDED
= 0x0105,
669 NVME_INVALID_FW_SLOT
= 0x0106,
670 NVME_INVALID_FW_IMAGE
= 0x0107,
671 NVME_INVALID_IRQ_VECTOR
= 0x0108,
672 NVME_INVALID_LOG_ID
= 0x0109,
673 NVME_INVALID_FORMAT
= 0x010a,
674 NVME_FW_REQ_RESET
= 0x010b,
675 NVME_INVALID_QUEUE_DEL
= 0x010c,
676 NVME_FID_NOT_SAVEABLE
= 0x010d,
677 NVME_FEAT_NOT_CHANGEABLE
= 0x010e,
678 NVME_FEAT_NOT_NS_SPEC
= 0x010f,
679 NVME_FW_REQ_SUSYSTEM_RESET
= 0x0110,
680 NVME_CONFLICTING_ATTRS
= 0x0180,
681 NVME_INVALID_PROT_INFO
= 0x0181,
682 NVME_WRITE_TO_RO
= 0x0182,
683 NVME_WRITE_FAULT
= 0x0280,
684 NVME_UNRECOVERED_READ
= 0x0281,
685 NVME_E2E_GUARD_ERROR
= 0x0282,
686 NVME_E2E_APP_ERROR
= 0x0283,
687 NVME_E2E_REF_ERROR
= 0x0284,
688 NVME_CMP_FAILURE
= 0x0285,
689 NVME_ACCESS_DENIED
= 0x0286,
692 NVME_NO_COMPLETE
= 0xffff,
695 typedef struct QEMU_PACKED NvmeFwSlotInfoLog
{
697 uint8_t reserved1
[7];
705 uint8_t reserved2
[448];
708 typedef struct QEMU_PACKED NvmeErrorLog
{
709 uint64_t error_count
;
712 uint16_t status_field
;
713 uint16_t param_error_location
;
720 typedef struct QEMU_PACKED NvmeSmartLog
{
721 uint8_t critical_warning
;
722 uint16_t temperature
;
723 uint8_t available_spare
;
724 uint8_t available_spare_threshold
;
725 uint8_t percentage_used
;
726 uint8_t reserved1
[26];
727 uint64_t data_units_read
[2];
728 uint64_t data_units_written
[2];
729 uint64_t host_read_commands
[2];
730 uint64_t host_write_commands
[2];
731 uint64_t controller_busy_time
[2];
732 uint64_t power_cycles
[2];
733 uint64_t power_on_hours
[2];
734 uint64_t unsafe_shutdowns
[2];
735 uint64_t media_errors
[2];
736 uint64_t number_of_error_log_entries
[2];
737 uint8_t reserved2
[320];
741 NVME_SMART_SPARE
= 1 << 0,
742 NVME_SMART_TEMPERATURE
= 1 << 1,
743 NVME_SMART_RELIABILITY
= 1 << 2,
744 NVME_SMART_MEDIA_READ_ONLY
= 1 << 3,
745 NVME_SMART_FAILED_VOLATILE_MEDIA
= 1 << 4,
748 enum NvmeLogIdentifier
{
749 NVME_LOG_ERROR_INFO
= 0x01,
750 NVME_LOG_SMART_INFO
= 0x02,
751 NVME_LOG_FW_SLOT_INFO
= 0x03,
754 typedef struct QEMU_PACKED NvmePSD
{
766 #define NVME_IDENTIFY_DATA_SIZE 4096
769 NVME_ID_CNS_NS
= 0x0,
770 NVME_ID_CNS_CTRL
= 0x1,
771 NVME_ID_CNS_NS_ACTIVE_LIST
= 0x2,
772 NVME_ID_CNS_NS_DESCR_LIST
= 0x3,
775 typedef struct QEMU_PACKED NvmeIdCtrl
{
793 uint8_t rsvd128
[128];
819 uint8_t rsvd332
[180];
835 uint8_t rsvd540
[228];
837 uint8_t rsvd1024
[1024];
842 enum NvmeIdCtrlOacs
{
843 NVME_OACS_SECURITY
= 1 << 0,
844 NVME_OACS_FORMAT
= 1 << 1,
845 NVME_OACS_FW
= 1 << 2,
848 enum NvmeIdCtrlOncs
{
849 NVME_ONCS_COMPARE
= 1 << 0,
850 NVME_ONCS_WRITE_UNCORR
= 1 << 1,
851 NVME_ONCS_DSM
= 1 << 2,
852 NVME_ONCS_WRITE_ZEROES
= 1 << 3,
853 NVME_ONCS_FEATURES
= 1 << 4,
854 NVME_ONCS_RESRVATIONS
= 1 << 5,
855 NVME_ONCS_TIMESTAMP
= 1 << 6,
858 enum NvmeIdCtrlFrmw
{
859 NVME_FRMW_SLOT1_RO
= 1 << 0,
863 NVME_LPA_NS_SMART
= 1 << 0,
864 NVME_LPA_EXTENDED
= 1 << 2,
867 #define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf)
868 #define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf)
869 #define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf)
870 #define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf)
872 #define NVME_CTRL_SGLS_SUPPORT_MASK (0x3 << 0)
873 #define NVME_CTRL_SGLS_SUPPORT_NO_ALIGN (0x1 << 0)
874 #define NVME_CTRL_SGLS_SUPPORT_DWORD_ALIGN (0x1 << 1)
875 #define NVME_CTRL_SGLS_KEYED (0x1 << 2)
876 #define NVME_CTRL_SGLS_BITBUCKET (0x1 << 16)
877 #define NVME_CTRL_SGLS_MPTR_CONTIGUOUS (0x1 << 17)
878 #define NVME_CTRL_SGLS_EXCESS_LENGTH (0x1 << 18)
879 #define NVME_CTRL_SGLS_MPTR_SGL (0x1 << 19)
880 #define NVME_CTRL_SGLS_ADDR_OFFSET (0x1 << 20)
882 #define NVME_ARB_AB(arb) (arb & 0x7)
883 #define NVME_ARB_AB_NOLIMIT 0x7
884 #define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff)
885 #define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff)
886 #define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff)
888 #define NVME_INTC_THR(intc) (intc & 0xff)
889 #define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff)
891 #define NVME_INTVC_NOCOALESCING (0x1 << 16)
893 #define NVME_TEMP_THSEL(temp) ((temp >> 20) & 0x3)
894 #define NVME_TEMP_THSEL_OVER 0x0
895 #define NVME_TEMP_THSEL_UNDER 0x1
897 #define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf)
898 #define NVME_TEMP_TMPSEL_COMPOSITE 0x0
900 #define NVME_TEMP_TMPTH(temp) (temp & 0xffff)
902 #define NVME_AEC_SMART(aec) (aec & 0xff)
903 #define NVME_AEC_NS_ATTR(aec) ((aec >> 8) & 0x1)
904 #define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1)
906 enum NvmeFeatureIds
{
907 NVME_ARBITRATION
= 0x1,
908 NVME_POWER_MANAGEMENT
= 0x2,
909 NVME_LBA_RANGE_TYPE
= 0x3,
910 NVME_TEMPERATURE_THRESHOLD
= 0x4,
911 NVME_ERROR_RECOVERY
= 0x5,
912 NVME_VOLATILE_WRITE_CACHE
= 0x6,
913 NVME_NUMBER_OF_QUEUES
= 0x7,
914 NVME_INTERRUPT_COALESCING
= 0x8,
915 NVME_INTERRUPT_VECTOR_CONF
= 0x9,
916 NVME_WRITE_ATOMICITY
= 0xa,
917 NVME_ASYNCHRONOUS_EVENT_CONF
= 0xb,
918 NVME_TIMESTAMP
= 0xe,
919 NVME_SOFTWARE_PROGRESS_MARKER
= 0x80,
920 NVME_FID_MAX
= 0x100,
923 typedef enum NvmeFeatureCap
{
924 NVME_FEAT_CAP_SAVE
= 1 << 0,
925 NVME_FEAT_CAP_NS
= 1 << 1,
926 NVME_FEAT_CAP_CHANGE
= 1 << 2,
929 typedef enum NvmeGetFeatureSelect
{
930 NVME_GETFEAT_SELECT_CURRENT
= 0x0,
931 NVME_GETFEAT_SELECT_DEFAULT
= 0x1,
932 NVME_GETFEAT_SELECT_SAVED
= 0x2,
933 NVME_GETFEAT_SELECT_CAP
= 0x3,
934 } NvmeGetFeatureSelect
;
936 #define NVME_GETSETFEAT_FID_MASK 0xff
937 #define NVME_GETSETFEAT_FID(dw10) (dw10 & NVME_GETSETFEAT_FID_MASK)
939 #define NVME_GETFEAT_SELECT_SHIFT 8
940 #define NVME_GETFEAT_SELECT_MASK 0x7
941 #define NVME_GETFEAT_SELECT(dw10) \
942 ((dw10 >> NVME_GETFEAT_SELECT_SHIFT) & NVME_GETFEAT_SELECT_MASK)
944 #define NVME_SETFEAT_SAVE_SHIFT 31
945 #define NVME_SETFEAT_SAVE_MASK 0x1
946 #define NVME_SETFEAT_SAVE(dw10) \
947 ((dw10 >> NVME_SETFEAT_SAVE_SHIFT) & NVME_SETFEAT_SAVE_MASK)
949 typedef struct QEMU_PACKED NvmeRangeType
{
959 typedef struct QEMU_PACKED NvmeLBAF
{
965 #define NVME_NSID_BROADCAST 0xffffffff
967 typedef struct QEMU_PACKED NvmeIdNs
{
993 uint8_t rsvd192
[192];
997 typedef struct QEMU_PACKED NvmeIdNsDescr
{
1004 NVME_NIDT_EUI64_LEN
= 8,
1005 NVME_NIDT_NGUID_LEN
= 16,
1006 NVME_NIDT_UUID_LEN
= 16,
1009 enum NvmeNsIdentifierType
{
1010 NVME_NIDT_EUI64
= 0x1,
1011 NVME_NIDT_NGUID
= 0x2,
1012 NVME_NIDT_UUID
= 0x3,
1015 /*Deallocate Logical Block Features*/
1016 #define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10)
1017 #define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08)
1019 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR(dlfeat) ((dlfeat) & 0x7)
1020 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_UNDEFINED 0
1021 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ZEROES 1
1022 #define NVME_ID_NS_DLFEAT_READ_BEHAVIOR_ONES 2
1025 #define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1))
1026 #define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1)
1027 #define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf))
1028 #define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1)
1029 #define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1))
1030 #define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1)
1031 #define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1)
1032 #define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1)
1033 #define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1)
1034 #define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1))
1035 #define NVME_ID_NS_DPC_TYPE_MASK 0x7
1042 DPS_TYPE_MASK
= 0x7,
1043 DPS_FIRST_EIGHT
= 8,
1046 static inline void _nvme_check_size(void)
1048 QEMU_BUILD_BUG_ON(sizeof(NvmeBar
) != 4096);
1049 QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult
) != 4);
1050 QEMU_BUILD_BUG_ON(sizeof(NvmeCqe
) != 16);
1051 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange
) != 16);
1052 QEMU_BUILD_BUG_ON(sizeof(NvmeCmd
) != 64);
1053 QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ
) != 64);
1054 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq
) != 64);
1055 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq
) != 64);
1056 QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify
) != 64);
1057 QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd
) != 64);
1058 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd
) != 64);
1059 QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType
) != 64);
1060 QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog
) != 64);
1061 QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog
) != 512);
1062 QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog
) != 512);
1063 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl
) != 4096);
1064 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs
) != 4096);
1065 QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor
) != 16);
1066 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr
) != 4);