2 * ARM Generic/Distributed Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 /* This file contains implementation code for the RealView EB interrupt
11 * controller, MPCore distributed interrupt controller and ARMv7-M
12 * Nested Vectored Interrupt Controller.
13 * It is compiled in two ways:
14 * (1) as a standalone file to produce a sysbus device which is a GIC
15 * that can be used on the realview board and as one of the builtin
16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
17 * (2) by being directly #included into armv7m_nvic.c to produce the
21 #include "qemu/osdep.h"
22 #include "hw/sysbus.h"
23 #include "gic_internal.h"
24 #include "qapi/error.h"
28 #include "sysemu/kvm.h"
30 /* #define DEBUG_GIC */
33 #define DEBUG_GIC_GATE 1
35 #define DEBUG_GIC_GATE 0
38 #define DPRINTF(fmt, ...) do { \
39 if (DEBUG_GIC_GATE) { \
40 fprintf(stderr, "%s: " fmt, __func__, ## __VA_ARGS__); \
44 static const uint8_t gic_id_11mpcore
[] = {
45 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
48 static const uint8_t gic_id_gicv1
[] = {
49 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
52 static const uint8_t gic_id_gicv2
[] = {
53 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
56 static inline int gic_get_current_cpu(GICState
*s
)
59 return current_cpu
->cpu_index
;
64 static inline int gic_get_current_vcpu(GICState
*s
)
66 return gic_get_current_cpu(s
) + GIC_NCPU
;
69 /* Return true if this GIC config has interrupt groups, which is
70 * true if we're a GICv2, or a GICv1 with the security extensions.
72 static inline bool gic_has_groups(GICState
*s
)
74 return s
->revision
== 2 || s
->security_extn
;
77 static inline bool gic_cpu_ns_access(GICState
*s
, int cpu
, MemTxAttrs attrs
)
79 return !gic_is_vcpu(cpu
) && s
->security_extn
&& !attrs
.secure
;
82 static inline void gic_get_best_irq(GICState
*s
, int cpu
,
83 int *best_irq
, int *best_prio
, int *group
)
91 for (irq
= 0; irq
< s
->num_irq
; irq
++) {
92 if (GIC_DIST_TEST_ENABLED(irq
, cm
) && gic_test_pending(s
, irq
, cm
) &&
93 (!GIC_DIST_TEST_ACTIVE(irq
, cm
)) &&
94 (irq
< GIC_INTERNAL
|| GIC_DIST_TARGET(irq
) & cm
)) {
95 if (GIC_DIST_GET_PRIORITY(irq
, cpu
) < *best_prio
) {
96 *best_prio
= GIC_DIST_GET_PRIORITY(irq
, cpu
);
102 if (*best_irq
< 1023) {
103 *group
= GIC_DIST_TEST_GROUP(*best_irq
, cm
);
107 static inline void gic_get_best_virq(GICState
*s
, int cpu
,
108 int *best_irq
, int *best_prio
, int *group
)
115 for (lr_idx
= 0; lr_idx
< s
->num_lrs
; lr_idx
++) {
116 uint32_t lr_entry
= s
->h_lr
[lr_idx
][cpu
];
117 int state
= GICH_LR_STATE(lr_entry
);
119 if (state
== GICH_LR_STATE_PENDING
) {
120 int prio
= GICH_LR_PRIORITY(lr_entry
);
122 if (prio
< *best_prio
) {
124 *best_irq
= GICH_LR_VIRT_ID(lr_entry
);
125 *group
= GICH_LR_GROUP(lr_entry
);
131 /* Return true if IRQ signaling is enabled for the given cpu and at least one
132 * of the given groups:
133 * - in the non-virt case, the distributor must be enabled for one of the
135 * - in the virt case, the virtual interface must be enabled.
136 * - in all cases, the (v)CPU interface must be enabled for one of the given
139 static inline bool gic_irq_signaling_enabled(GICState
*s
, int cpu
, bool virt
,
142 if (!virt
&& !(s
->ctlr
& group_mask
)) {
146 if (virt
&& !(s
->h_hcr
[cpu
] & R_GICH_HCR_EN_MASK
)) {
150 if (!(s
->cpu_ctlr
[cpu
] & group_mask
)) {
157 /* TODO: Many places that call this routine could be optimized. */
158 /* Update interrupt status after enabled or pending bits have been changed. */
159 static inline void gic_update_internal(GICState
*s
, bool virt
)
163 int irq_level
, fiq_level
;
166 qemu_irq
*irq_lines
= virt
? s
->parent_virq
: s
->parent_irq
;
167 qemu_irq
*fiq_lines
= virt
? s
->parent_vfiq
: s
->parent_fiq
;
169 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
170 cpu_iface
= virt
? (cpu
+ GIC_NCPU
) : cpu
;
172 s
->current_pending
[cpu_iface
] = 1023;
173 if (!gic_irq_signaling_enabled(s
, cpu
, virt
,
174 GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
)) {
175 qemu_irq_lower(irq_lines
[cpu
]);
176 qemu_irq_lower(fiq_lines
[cpu
]);
181 gic_get_best_virq(s
, cpu
, &best_irq
, &best_prio
, &group
);
183 gic_get_best_irq(s
, cpu
, &best_irq
, &best_prio
, &group
);
186 if (best_irq
!= 1023) {
187 trace_gic_update_bestirq(virt
? "vcpu" : "cpu", cpu
,
189 s
->priority_mask
[cpu_iface
],
190 s
->running_priority
[cpu_iface
]);
193 irq_level
= fiq_level
= 0;
195 if (best_prio
< s
->priority_mask
[cpu_iface
]) {
196 s
->current_pending
[cpu_iface
] = best_irq
;
197 if (best_prio
< s
->running_priority
[cpu_iface
]) {
198 if (gic_irq_signaling_enabled(s
, cpu
, virt
, 1 << group
)) {
200 s
->cpu_ctlr
[cpu_iface
] & GICC_CTLR_FIQ_EN
) {
201 DPRINTF("Raised pending FIQ %d (cpu %d)\n",
202 best_irq
, cpu_iface
);
204 trace_gic_update_set_irq(cpu
, virt
? "vfiq" : "fiq",
207 DPRINTF("Raised pending IRQ %d (cpu %d)\n",
208 best_irq
, cpu_iface
);
210 trace_gic_update_set_irq(cpu
, virt
? "virq" : "irq",
217 qemu_set_irq(irq_lines
[cpu
], irq_level
);
218 qemu_set_irq(fiq_lines
[cpu
], fiq_level
);
222 static void gic_update(GICState
*s
)
224 gic_update_internal(s
, false);
227 /* Return true if this LR is empty, i.e. the corresponding bit
230 static inline bool gic_lr_entry_is_free(uint32_t entry
)
232 return (GICH_LR_STATE(entry
) == GICH_LR_STATE_INVALID
)
233 && (GICH_LR_HW(entry
) || !GICH_LR_EOI(entry
));
236 /* Return true if this LR should trigger an EOI maintenance interrupt, i.e. the
237 * corrsponding bit in EISR is set.
239 static inline bool gic_lr_entry_is_eoi(uint32_t entry
)
241 return (GICH_LR_STATE(entry
) == GICH_LR_STATE_INVALID
)
242 && !GICH_LR_HW(entry
) && GICH_LR_EOI(entry
);
245 static inline void gic_extract_lr_info(GICState
*s
, int cpu
,
246 int *num_eoi
, int *num_valid
, int *num_pending
)
254 for (lr_idx
= 0; lr_idx
< s
->num_lrs
; lr_idx
++) {
255 uint32_t *entry
= &s
->h_lr
[lr_idx
][cpu
];
257 if (gic_lr_entry_is_eoi(*entry
)) {
261 if (GICH_LR_STATE(*entry
) != GICH_LR_STATE_INVALID
) {
265 if (GICH_LR_STATE(*entry
) == GICH_LR_STATE_PENDING
) {
271 static void gic_compute_misr(GICState
*s
, int cpu
)
274 int vcpu
= cpu
+ GIC_NCPU
;
276 int num_eoi
, num_valid
, num_pending
;
278 gic_extract_lr_info(s
, cpu
, &num_eoi
, &num_valid
, &num_pending
);
282 value
|= R_GICH_MISR_EOI_MASK
;
285 /* U: true if only 0 or 1 LR entry is valid */
286 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_UIE_MASK
) && (num_valid
< 2)) {
287 value
|= R_GICH_MISR_U_MASK
;
290 /* LRENP: EOICount is not 0 */
291 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_LRENPIE_MASK
) &&
292 ((s
->h_hcr
[cpu
] & R_GICH_HCR_EOICount_MASK
) != 0)) {
293 value
|= R_GICH_MISR_LRENP_MASK
;
296 /* NP: no pending interrupts */
297 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_NPIE_MASK
) && (num_pending
== 0)) {
298 value
|= R_GICH_MISR_NP_MASK
;
301 /* VGrp0E: group0 virq signaling enabled */
302 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_VGRP0EIE_MASK
) &&
303 (s
->cpu_ctlr
[vcpu
] & GICC_CTLR_EN_GRP0
)) {
304 value
|= R_GICH_MISR_VGrp0E_MASK
;
307 /* VGrp0D: group0 virq signaling disabled */
308 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_VGRP0DIE_MASK
) &&
309 !(s
->cpu_ctlr
[vcpu
] & GICC_CTLR_EN_GRP0
)) {
310 value
|= R_GICH_MISR_VGrp0D_MASK
;
313 /* VGrp1E: group1 virq signaling enabled */
314 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_VGRP1EIE_MASK
) &&
315 (s
->cpu_ctlr
[vcpu
] & GICC_CTLR_EN_GRP1
)) {
316 value
|= R_GICH_MISR_VGrp1E_MASK
;
319 /* VGrp1D: group1 virq signaling disabled */
320 if ((s
->h_hcr
[cpu
] & R_GICH_HCR_VGRP1DIE_MASK
) &&
321 !(s
->cpu_ctlr
[vcpu
] & GICC_CTLR_EN_GRP1
)) {
322 value
|= R_GICH_MISR_VGrp1D_MASK
;
325 s
->h_misr
[cpu
] = value
;
328 static void gic_update_maintenance(GICState
*s
)
333 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
334 gic_compute_misr(s
, cpu
);
335 maint_level
= (s
->h_hcr
[cpu
] & R_GICH_HCR_EN_MASK
) && s
->h_misr
[cpu
];
337 trace_gic_update_maintenance_irq(cpu
, maint_level
);
338 qemu_set_irq(s
->maintenance_irq
[cpu
], maint_level
);
342 static void gic_update_virt(GICState
*s
)
344 gic_update_internal(s
, true);
345 gic_update_maintenance(s
);
348 static void gic_set_irq_11mpcore(GICState
*s
, int irq
, int level
,
352 GIC_DIST_SET_LEVEL(irq
, cm
);
353 if (GIC_DIST_TEST_EDGE_TRIGGER(irq
) || GIC_DIST_TEST_ENABLED(irq
, cm
)) {
354 DPRINTF("Set %d pending mask %x\n", irq
, target
);
355 GIC_DIST_SET_PENDING(irq
, target
);
358 GIC_DIST_CLEAR_LEVEL(irq
, cm
);
362 static void gic_set_irq_generic(GICState
*s
, int irq
, int level
,
366 GIC_DIST_SET_LEVEL(irq
, cm
);
367 DPRINTF("Set %d pending mask %x\n", irq
, target
);
368 if (GIC_DIST_TEST_EDGE_TRIGGER(irq
)) {
369 GIC_DIST_SET_PENDING(irq
, target
);
372 GIC_DIST_CLEAR_LEVEL(irq
, cm
);
376 /* Process a change in an external IRQ input. */
377 static void gic_set_irq(void *opaque
, int irq
, int level
)
379 /* Meaning of the 'irq' parameter:
380 * [0..N-1] : external interrupts
381 * [N..N+31] : PPI (internal) interrupts for CPU 0
382 * [N+32..N+63] : PPI (internal interrupts for CPU 1
385 GICState
*s
= (GICState
*)opaque
;
387 if (irq
< (s
->num_irq
- GIC_INTERNAL
)) {
388 /* The first external input line is internal interrupt 32. */
391 target
= GIC_DIST_TARGET(irq
);
394 irq
-= (s
->num_irq
- GIC_INTERNAL
);
395 cpu
= irq
/ GIC_INTERNAL
;
401 assert(irq
>= GIC_NR_SGIS
);
403 if (level
== GIC_DIST_TEST_LEVEL(irq
, cm
)) {
407 if (s
->revision
== REV_11MPCORE
) {
408 gic_set_irq_11mpcore(s
, irq
, level
, cm
, target
);
410 gic_set_irq_generic(s
, irq
, level
, cm
, target
);
412 trace_gic_set_irq(irq
, level
, cm
, target
);
417 static uint16_t gic_get_current_pending_irq(GICState
*s
, int cpu
,
420 uint16_t pending_irq
= s
->current_pending
[cpu
];
422 if (pending_irq
< GIC_MAXIRQ
&& gic_has_groups(s
)) {
423 int group
= gic_test_group(s
, pending_irq
, cpu
);
425 /* On a GIC without the security extensions, reading this register
426 * behaves in the same way as a secure access to a GIC with them.
428 bool secure
= !gic_cpu_ns_access(s
, cpu
, attrs
);
430 if (group
== 0 && !secure
) {
431 /* Group0 interrupts hidden from Non-secure access */
434 if (group
== 1 && secure
&& !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_ACK_CTL
)) {
435 /* Group1 interrupts only seen by Secure access if
444 static int gic_get_group_priority(GICState
*s
, int cpu
, int irq
)
446 /* Return the group priority of the specified interrupt
447 * (which is the top bits of its priority, with the number
448 * of bits masked determined by the applicable binary point register).
453 if (gic_has_groups(s
) &&
454 !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) &&
455 gic_test_group(s
, irq
, cpu
)) {
456 bpr
= s
->abpr
[cpu
] - 1;
462 /* a BPR of 0 means the group priority bits are [7:1];
463 * a BPR of 1 means they are [7:2], and so on down to
464 * a BPR of 7 meaning no group priority bits at all.
466 mask
= ~0U << ((bpr
& 7) + 1);
468 return gic_get_priority(s
, irq
, cpu
) & mask
;
471 static void gic_activate_irq(GICState
*s
, int cpu
, int irq
)
473 /* Set the appropriate Active Priority Register bit for this IRQ,
474 * and update the running priority.
476 int prio
= gic_get_group_priority(s
, cpu
, irq
);
477 int min_bpr
= gic_is_vcpu(cpu
) ? GIC_VIRT_MIN_BPR
: GIC_MIN_BPR
;
478 int preemption_level
= prio
>> (min_bpr
+ 1);
479 int regno
= preemption_level
/ 32;
480 int bitno
= preemption_level
% 32;
481 uint32_t *papr
= NULL
;
483 if (gic_is_vcpu(cpu
)) {
485 papr
= &s
->h_apr
[gic_get_vcpu_real_id(cpu
)];
486 } else if (gic_has_groups(s
) && gic_test_group(s
, irq
, cpu
)) {
487 papr
= &s
->nsapr
[regno
][cpu
];
489 papr
= &s
->apr
[regno
][cpu
];
492 *papr
|= (1 << bitno
);
494 s
->running_priority
[cpu
] = prio
;
495 gic_set_active(s
, irq
, cpu
);
498 static int gic_get_prio_from_apr_bits(GICState
*s
, int cpu
)
500 /* Recalculate the current running priority for this CPU based
501 * on the set bits in the Active Priority Registers.
505 if (gic_is_vcpu(cpu
)) {
506 uint32_t apr
= s
->h_apr
[gic_get_vcpu_real_id(cpu
)];
508 return ctz32(apr
) << (GIC_VIRT_MIN_BPR
+ 1);
514 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
515 uint32_t apr
= s
->apr
[i
][cpu
] | s
->nsapr
[i
][cpu
];
519 return (i
* 32 + ctz32(apr
)) << (GIC_MIN_BPR
+ 1);
524 static void gic_drop_prio(GICState
*s
, int cpu
, int group
)
526 /* Drop the priority of the currently active interrupt in the
529 * Note that we can guarantee (because of the requirement to nest
530 * GICC_IAR reads [which activate an interrupt and raise priority]
531 * with GICC_EOIR writes [which drop the priority for the interrupt])
532 * that the interrupt we're being called for is the highest priority
533 * active interrupt, meaning that it has the lowest set bit in the
536 * If the guest does not honour the ordering constraints then the
537 * behaviour of the GIC is UNPREDICTABLE, which for us means that
538 * the values of the APR registers might become incorrect and the
539 * running priority will be wrong, so interrupts that should preempt
540 * might not do so, and interrupts that should not preempt might do so.
542 if (gic_is_vcpu(cpu
)) {
543 int rcpu
= gic_get_vcpu_real_id(cpu
);
545 if (s
->h_apr
[rcpu
]) {
546 /* Clear lowest set bit */
547 s
->h_apr
[rcpu
] &= s
->h_apr
[rcpu
] - 1;
552 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
553 uint32_t *papr
= group
? &s
->nsapr
[i
][cpu
] : &s
->apr
[i
][cpu
];
557 /* Clear lowest set bit */
563 s
->running_priority
[cpu
] = gic_get_prio_from_apr_bits(s
, cpu
);
566 static inline uint32_t gic_clear_pending_sgi(GICState
*s
, int irq
, int cpu
)
571 if (!gic_is_vcpu(cpu
)) {
572 /* Lookup the source CPU for the SGI and clear this in the
573 * sgi_pending map. Return the src and clear the overall pending
574 * state on this CPU if the SGI is not pending from any CPUs.
576 assert(s
->sgi_pending
[irq
][cpu
] != 0);
577 src
= ctz32(s
->sgi_pending
[irq
][cpu
]);
578 s
->sgi_pending
[irq
][cpu
] &= ~(1 << src
);
579 if (s
->sgi_pending
[irq
][cpu
] == 0) {
580 gic_clear_pending(s
, irq
, cpu
);
582 ret
= irq
| ((src
& 0x7) << 10);
584 uint32_t *lr_entry
= gic_get_lr_entry(s
, irq
, cpu
);
585 src
= GICH_LR_CPUID(*lr_entry
);
587 gic_clear_pending(s
, irq
, cpu
);
588 ret
= irq
| (src
<< 10);
594 uint32_t gic_acknowledge_irq(GICState
*s
, int cpu
, MemTxAttrs attrs
)
598 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately
599 * for the case where this GIC supports grouping and the pending interrupt
600 * is in the wrong group.
602 irq
= gic_get_current_pending_irq(s
, cpu
, attrs
);
603 trace_gic_acknowledge_irq(gic_is_vcpu(cpu
) ? "vcpu" : "cpu",
604 gic_get_vcpu_real_id(cpu
), irq
);
606 if (irq
>= GIC_MAXIRQ
) {
607 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq
);
611 if (gic_get_priority(s
, irq
, cpu
) >= s
->running_priority
[cpu
]) {
612 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq
);
616 gic_activate_irq(s
, cpu
, irq
);
618 if (s
->revision
== REV_11MPCORE
) {
619 /* Clear pending flags for both level and edge triggered interrupts.
620 * Level triggered IRQs will be reasserted once they become inactive.
622 gic_clear_pending(s
, irq
, cpu
);
625 if (irq
< GIC_NR_SGIS
) {
626 ret
= gic_clear_pending_sgi(s
, irq
, cpu
);
628 gic_clear_pending(s
, irq
, cpu
);
633 if (gic_is_vcpu(cpu
)) {
638 DPRINTF("ACK %d\n", irq
);
642 void gic_dist_set_priority(GICState
*s
, int cpu
, int irq
, uint8_t val
,
645 if (s
->security_extn
&& !attrs
.secure
) {
646 if (!GIC_DIST_TEST_GROUP(irq
, (1 << cpu
))) {
647 return; /* Ignore Non-secure access of Group0 IRQ */
649 val
= 0x80 | (val
>> 1); /* Non-secure view */
652 if (irq
< GIC_INTERNAL
) {
653 s
->priority1
[irq
][cpu
] = val
;
655 s
->priority2
[(irq
) - GIC_INTERNAL
] = val
;
659 static uint32_t gic_dist_get_priority(GICState
*s
, int cpu
, int irq
,
662 uint32_t prio
= GIC_DIST_GET_PRIORITY(irq
, cpu
);
664 if (s
->security_extn
&& !attrs
.secure
) {
665 if (!GIC_DIST_TEST_GROUP(irq
, (1 << cpu
))) {
666 return 0; /* Non-secure access cannot read priority of Group0 IRQ */
668 prio
= (prio
<< 1) & 0xff; /* Non-secure view */
673 static void gic_set_priority_mask(GICState
*s
, int cpu
, uint8_t pmask
,
676 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
677 if (s
->priority_mask
[cpu
] & 0x80) {
678 /* Priority Mask in upper half */
679 pmask
= 0x80 | (pmask
>> 1);
681 /* Non-secure write ignored if priority mask is in lower half */
685 s
->priority_mask
[cpu
] = pmask
;
688 static uint32_t gic_get_priority_mask(GICState
*s
, int cpu
, MemTxAttrs attrs
)
690 uint32_t pmask
= s
->priority_mask
[cpu
];
692 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
694 /* Priority Mask in upper half, return Non-secure view */
695 pmask
= (pmask
<< 1) & 0xff;
697 /* Priority Mask in lower half, RAZ */
704 static uint32_t gic_get_cpu_control(GICState
*s
, int cpu
, MemTxAttrs attrs
)
706 uint32_t ret
= s
->cpu_ctlr
[cpu
];
708 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
709 /* Construct the NS banked view of GICC_CTLR from the correct
710 * bits of the S banked view. We don't need to move the bypass
711 * control bits because we don't implement that (IMPDEF) part
712 * of the GIC architecture.
714 ret
= (ret
& (GICC_CTLR_EN_GRP1
| GICC_CTLR_EOIMODE_NS
)) >> 1;
719 static void gic_set_cpu_control(GICState
*s
, int cpu
, uint32_t value
,
724 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
725 /* The NS view can only write certain bits in the register;
726 * the rest are unchanged
728 mask
= GICC_CTLR_EN_GRP1
;
729 if (s
->revision
== 2) {
730 mask
|= GICC_CTLR_EOIMODE_NS
;
732 s
->cpu_ctlr
[cpu
] &= ~mask
;
733 s
->cpu_ctlr
[cpu
] |= (value
<< 1) & mask
;
735 if (s
->revision
== 2) {
736 mask
= s
->security_extn
? GICC_CTLR_V2_S_MASK
: GICC_CTLR_V2_MASK
;
738 mask
= s
->security_extn
? GICC_CTLR_V1_S_MASK
: GICC_CTLR_V1_MASK
;
740 s
->cpu_ctlr
[cpu
] = value
& mask
;
742 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, "
743 "Group1 Interrupts %sabled\n", cpu
,
744 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP0
) ? "En" : "Dis",
745 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP1
) ? "En" : "Dis");
748 static uint8_t gic_get_running_priority(GICState
*s
, int cpu
, MemTxAttrs attrs
)
750 if ((s
->revision
!= REV_11MPCORE
) && (s
->running_priority
[cpu
] > 0xff)) {
755 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
756 if (s
->running_priority
[cpu
] & 0x80) {
757 /* Running priority in upper half of range: return the Non-secure
758 * view of the priority.
760 return s
->running_priority
[cpu
] << 1;
762 /* Running priority in lower half of range: RAZ */
766 return s
->running_priority
[cpu
];
770 /* Return true if we should split priority drop and interrupt deactivation,
771 * ie whether the relevant EOIMode bit is set.
773 static bool gic_eoi_split(GICState
*s
, int cpu
, MemTxAttrs attrs
)
775 if (s
->revision
!= 2) {
776 /* Before GICv2 prio-drop and deactivate are not separable */
779 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
780 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE_NS
;
782 return s
->cpu_ctlr
[cpu
] & GICC_CTLR_EOIMODE
;
785 static void gic_deactivate_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
789 if (irq
>= GIC_MAXIRQ
|| (!gic_is_vcpu(cpu
) && irq
>= s
->num_irq
)) {
791 * This handles two cases:
792 * 1. If software writes the ID of a spurious interrupt [ie 1023]
793 * to the GICC_DIR, the GIC ignores that write.
794 * 2. If software writes the number of a non-existent interrupt
795 * this must be a subcase of "value written is not an active interrupt"
796 * and so this is UNPREDICTABLE. We choose to ignore it. For vCPUs,
797 * all IRQs potentially exist, so this limit does not apply.
802 if (!gic_eoi_split(s
, cpu
, attrs
)) {
803 /* This is UNPREDICTABLE; we choose to ignore it */
804 qemu_log_mask(LOG_GUEST_ERROR
,
805 "gic_deactivate_irq: GICC_DIR write when EOIMode clear");
809 if (gic_is_vcpu(cpu
) && !gic_virq_is_valid(s
, irq
, cpu
)) {
810 /* This vIRQ does not have an LR entry which is either active or
811 * pending and active. Increment EOICount and ignore the write.
813 int rcpu
= gic_get_vcpu_real_id(cpu
);
814 s
->h_hcr
[rcpu
] += 1 << R_GICH_HCR_EOICount_SHIFT
;
816 /* Update the virtual interface in case a maintenance interrupt should
823 group
= gic_has_groups(s
) && gic_test_group(s
, irq
, cpu
);
825 if (gic_cpu_ns_access(s
, cpu
, attrs
) && !group
) {
826 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq
);
830 gic_clear_active(s
, irq
, cpu
);
833 static void gic_complete_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
838 DPRINTF("EOI %d\n", irq
);
839 if (gic_is_vcpu(cpu
)) {
840 /* The call to gic_prio_drop() will clear a bit in GICH_APR iff the
841 * running prio is < 0x100.
843 bool prio_drop
= s
->running_priority
[cpu
] < 0x100;
845 if (irq
>= GIC_MAXIRQ
) {
846 /* Ignore spurious interrupt */
850 gic_drop_prio(s
, cpu
, 0);
852 if (!gic_eoi_split(s
, cpu
, attrs
)) {
853 bool valid
= gic_virq_is_valid(s
, irq
, cpu
);
854 if (prio_drop
&& !valid
) {
855 /* We are in a situation where:
856 * - V_CTRL.EOIMode is false (no EOI split),
857 * - The call to gic_drop_prio() cleared a bit in GICH_APR,
858 * - This vIRQ does not have an LR entry which is either
859 * active or pending and active.
860 * In that case, we must increment EOICount.
862 int rcpu
= gic_get_vcpu_real_id(cpu
);
863 s
->h_hcr
[rcpu
] += 1 << R_GICH_HCR_EOICount_SHIFT
;
865 gic_clear_active(s
, irq
, cpu
);
873 if (irq
>= s
->num_irq
) {
874 /* This handles two cases:
875 * 1. If software writes the ID of a spurious interrupt [ie 1023]
876 * to the GICC_EOIR, the GIC ignores that write.
877 * 2. If software writes the number of a non-existent interrupt
878 * this must be a subcase of "value written does not match the last
879 * valid interrupt value read from the Interrupt Acknowledge
880 * register" and so this is UNPREDICTABLE. We choose to ignore it.
884 if (s
->running_priority
[cpu
] == 0x100) {
885 return; /* No active IRQ. */
888 if (s
->revision
== REV_11MPCORE
) {
889 /* Mark level triggered interrupts as pending if they are still
891 if (!GIC_DIST_TEST_EDGE_TRIGGER(irq
) && GIC_DIST_TEST_ENABLED(irq
, cm
)
892 && GIC_DIST_TEST_LEVEL(irq
, cm
)
893 && (GIC_DIST_TARGET(irq
) & cm
) != 0) {
894 DPRINTF("Set %d pending mask %x\n", irq
, cm
);
895 GIC_DIST_SET_PENDING(irq
, cm
);
899 group
= gic_has_groups(s
) && gic_test_group(s
, irq
, cpu
);
901 if (gic_cpu_ns_access(s
, cpu
, attrs
) && !group
) {
902 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq
);
906 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1
907 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1,
908 * i.e. go ahead and complete the irq anyway.
911 gic_drop_prio(s
, cpu
, group
);
913 /* In GICv2 the guest can choose to split priority-drop and deactivate */
914 if (!gic_eoi_split(s
, cpu
, attrs
)) {
915 gic_clear_active(s
, irq
, cpu
);
920 static uint32_t gic_dist_readb(void *opaque
, hwaddr offset
, MemTxAttrs attrs
)
922 GICState
*s
= (GICState
*)opaque
;
930 cpu
= gic_get_current_cpu(s
);
932 if (offset
< 0x100) {
933 if (offset
== 0) { /* GICD_CTLR */
934 if (s
->security_extn
&& !attrs
.secure
) {
935 /* The NS bank of this register is just an alias of the
936 * EnableGrp1 bit in the S bank version.
938 return extract32(s
->ctlr
, 1, 1);
944 /* Interrupt Controller Type Register */
945 return ((s
->num_irq
/ 32) - 1)
946 | ((s
->num_cpu
- 1) << 5)
947 | (s
->security_extn
<< 10);
950 if (offset
>= 0x80) {
951 /* Interrupt Group Registers: these RAZ/WI if this is an NS
952 * access to a GIC with the security extensions, or if the GIC
953 * doesn't have groups at all.
956 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
957 /* Every byte offset holds 8 group status bits */
958 irq
= (offset
- 0x080) * 8 + GIC_BASE_IRQ
;
959 if (irq
>= s
->num_irq
) {
962 for (i
= 0; i
< 8; i
++) {
963 if (GIC_DIST_TEST_GROUP(irq
+ i
, cm
)) {
971 } else if (offset
< 0x200) {
972 /* Interrupt Set/Clear Enable. */
974 irq
= (offset
- 0x100) * 8;
976 irq
= (offset
- 0x180) * 8;
978 if (irq
>= s
->num_irq
)
981 for (i
= 0; i
< 8; i
++) {
982 if (s
->security_extn
&& !attrs
.secure
&&
983 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
984 continue; /* Ignore Non-secure access of Group0 IRQ */
987 if (GIC_DIST_TEST_ENABLED(irq
+ i
, cm
)) {
991 } else if (offset
< 0x300) {
992 /* Interrupt Set/Clear Pending. */
994 irq
= (offset
- 0x200) * 8;
996 irq
= (offset
- 0x280) * 8;
998 if (irq
>= s
->num_irq
)
1001 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
1002 for (i
= 0; i
< 8; i
++) {
1003 if (s
->security_extn
&& !attrs
.secure
&&
1004 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1005 continue; /* Ignore Non-secure access of Group0 IRQ */
1008 if (gic_test_pending(s
, irq
+ i
, mask
)) {
1012 } else if (offset
< 0x400) {
1013 /* Interrupt Set/Clear Active. */
1014 if (offset
< 0x380) {
1015 irq
= (offset
- 0x300) * 8;
1016 } else if (s
->revision
== 2) {
1017 irq
= (offset
- 0x380) * 8;
1022 irq
+= GIC_BASE_IRQ
;
1023 if (irq
>= s
->num_irq
)
1026 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
1027 for (i
= 0; i
< 8; i
++) {
1028 if (s
->security_extn
&& !attrs
.secure
&&
1029 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1030 continue; /* Ignore Non-secure access of Group0 IRQ */
1033 if (GIC_DIST_TEST_ACTIVE(irq
+ i
, mask
)) {
1037 } else if (offset
< 0x800) {
1038 /* Interrupt Priority. */
1039 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
1040 if (irq
>= s
->num_irq
)
1042 res
= gic_dist_get_priority(s
, cpu
, irq
, attrs
);
1043 } else if (offset
< 0xc00) {
1044 /* Interrupt CPU Target. */
1045 if (s
->num_cpu
== 1 && s
->revision
!= REV_11MPCORE
) {
1046 /* For uniprocessor GICs these RAZ/WI */
1049 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
1050 if (irq
>= s
->num_irq
) {
1053 if (irq
< 29 && s
->revision
== REV_11MPCORE
) {
1055 } else if (irq
< GIC_INTERNAL
) {
1058 res
= GIC_DIST_TARGET(irq
);
1061 } else if (offset
< 0xf00) {
1062 /* Interrupt Configuration. */
1063 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
1064 if (irq
>= s
->num_irq
)
1067 for (i
= 0; i
< 4; i
++) {
1068 if (s
->security_extn
&& !attrs
.secure
&&
1069 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1070 continue; /* Ignore Non-secure access of Group0 IRQ */
1073 if (GIC_DIST_TEST_MODEL(irq
+ i
)) {
1074 res
|= (1 << (i
* 2));
1076 if (GIC_DIST_TEST_EDGE_TRIGGER(irq
+ i
)) {
1077 res
|= (2 << (i
* 2));
1080 } else if (offset
< 0xf10) {
1082 } else if (offset
< 0xf30) {
1083 if (s
->revision
== REV_11MPCORE
) {
1087 if (offset
< 0xf20) {
1088 /* GICD_CPENDSGIRn */
1089 irq
= (offset
- 0xf10);
1091 irq
= (offset
- 0xf20);
1092 /* GICD_SPENDSGIRn */
1095 if (s
->security_extn
&& !attrs
.secure
&&
1096 !GIC_DIST_TEST_GROUP(irq
, 1 << cpu
)) {
1097 res
= 0; /* Ignore Non-secure access of Group0 IRQ */
1099 res
= s
->sgi_pending
[irq
][cpu
];
1101 } else if (offset
< 0xfd0) {
1103 } else if (offset
< 0x1000) {
1107 switch (s
->revision
) {
1109 res
= gic_id_11mpcore
[(offset
- 0xfd0) >> 2];
1112 res
= gic_id_gicv1
[(offset
- 0xfd0) >> 2];
1115 res
= gic_id_gicv2
[(offset
- 0xfd0) >> 2];
1122 g_assert_not_reached();
1126 qemu_log_mask(LOG_GUEST_ERROR
,
1127 "gic_dist_readb: Bad offset %x\n", (int)offset
);
1131 static MemTxResult
gic_dist_read(void *opaque
, hwaddr offset
, uint64_t *data
,
1132 unsigned size
, MemTxAttrs attrs
)
1136 *data
= gic_dist_readb(opaque
, offset
, attrs
);
1139 *data
= gic_dist_readb(opaque
, offset
, attrs
);
1140 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
1143 *data
= gic_dist_readb(opaque
, offset
, attrs
);
1144 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
1145 *data
|= gic_dist_readb(opaque
, offset
+ 2, attrs
) << 16;
1146 *data
|= gic_dist_readb(opaque
, offset
+ 3, attrs
) << 24;
1152 trace_gic_dist_read(offset
, size
, *data
);
1156 static void gic_dist_writeb(void *opaque
, hwaddr offset
,
1157 uint32_t value
, MemTxAttrs attrs
)
1159 GICState
*s
= (GICState
*)opaque
;
1164 cpu
= gic_get_current_cpu(s
);
1165 if (offset
< 0x100) {
1167 if (s
->security_extn
&& !attrs
.secure
) {
1168 /* NS version is just an alias of the S version's bit 1 */
1169 s
->ctlr
= deposit32(s
->ctlr
, 1, 1, value
);
1170 } else if (gic_has_groups(s
)) {
1171 s
->ctlr
= value
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
);
1173 s
->ctlr
= value
& GICD_CTLR_EN_GRP0
;
1175 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n",
1176 s
->ctlr
& GICD_CTLR_EN_GRP0
? "En" : "Dis",
1177 s
->ctlr
& GICD_CTLR_EN_GRP1
? "En" : "Dis");
1178 } else if (offset
< 4) {
1180 } else if (offset
>= 0x80) {
1181 /* Interrupt Group Registers: RAZ/WI for NS access to secure
1182 * GIC, or for GICs without groups.
1184 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
1185 /* Every byte offset holds 8 group status bits */
1186 irq
= (offset
- 0x80) * 8 + GIC_BASE_IRQ
;
1187 if (irq
>= s
->num_irq
) {
1190 for (i
= 0; i
< 8; i
++) {
1191 /* Group bits are banked for private interrupts */
1192 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
1193 if (value
& (1 << i
)) {
1194 /* Group1 (Non-secure) */
1195 GIC_DIST_SET_GROUP(irq
+ i
, cm
);
1197 /* Group0 (Secure) */
1198 GIC_DIST_CLEAR_GROUP(irq
+ i
, cm
);
1205 } else if (offset
< 0x180) {
1206 /* Interrupt Set Enable. */
1207 irq
= (offset
- 0x100) * 8 + GIC_BASE_IRQ
;
1208 if (irq
>= s
->num_irq
)
1210 if (irq
< GIC_NR_SGIS
) {
1214 for (i
= 0; i
< 8; i
++) {
1215 if (value
& (1 << i
)) {
1217 (irq
< GIC_INTERNAL
) ? (1 << cpu
)
1218 : GIC_DIST_TARGET(irq
+ i
);
1219 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
1221 if (s
->security_extn
&& !attrs
.secure
&&
1222 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1223 continue; /* Ignore Non-secure access of Group0 IRQ */
1226 if (!GIC_DIST_TEST_ENABLED(irq
+ i
, cm
)) {
1227 DPRINTF("Enabled IRQ %d\n", irq
+ i
);
1228 trace_gic_enable_irq(irq
+ i
);
1230 GIC_DIST_SET_ENABLED(irq
+ i
, cm
);
1231 /* If a raised level triggered IRQ enabled then mark
1233 if (GIC_DIST_TEST_LEVEL(irq
+ i
, mask
)
1234 && !GIC_DIST_TEST_EDGE_TRIGGER(irq
+ i
)) {
1235 DPRINTF("Set %d pending mask %x\n", irq
+ i
, mask
);
1236 GIC_DIST_SET_PENDING(irq
+ i
, mask
);
1240 } else if (offset
< 0x200) {
1241 /* Interrupt Clear Enable. */
1242 irq
= (offset
- 0x180) * 8 + GIC_BASE_IRQ
;
1243 if (irq
>= s
->num_irq
)
1245 if (irq
< GIC_NR_SGIS
) {
1249 for (i
= 0; i
< 8; i
++) {
1250 if (value
& (1 << i
)) {
1251 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
1253 if (s
->security_extn
&& !attrs
.secure
&&
1254 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1255 continue; /* Ignore Non-secure access of Group0 IRQ */
1258 if (GIC_DIST_TEST_ENABLED(irq
+ i
, cm
)) {
1259 DPRINTF("Disabled IRQ %d\n", irq
+ i
);
1260 trace_gic_disable_irq(irq
+ i
);
1262 GIC_DIST_CLEAR_ENABLED(irq
+ i
, cm
);
1265 } else if (offset
< 0x280) {
1266 /* Interrupt Set Pending. */
1267 irq
= (offset
- 0x200) * 8 + GIC_BASE_IRQ
;
1268 if (irq
>= s
->num_irq
)
1270 if (irq
< GIC_NR_SGIS
) {
1274 for (i
= 0; i
< 8; i
++) {
1275 if (value
& (1 << i
)) {
1276 if (s
->security_extn
&& !attrs
.secure
&&
1277 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1278 continue; /* Ignore Non-secure access of Group0 IRQ */
1281 GIC_DIST_SET_PENDING(irq
+ i
, GIC_DIST_TARGET(irq
+ i
));
1284 } else if (offset
< 0x300) {
1285 /* Interrupt Clear Pending. */
1286 irq
= (offset
- 0x280) * 8 + GIC_BASE_IRQ
;
1287 if (irq
>= s
->num_irq
)
1289 if (irq
< GIC_NR_SGIS
) {
1293 for (i
= 0; i
< 8; i
++) {
1294 if (s
->security_extn
&& !attrs
.secure
&&
1295 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1296 continue; /* Ignore Non-secure access of Group0 IRQ */
1299 /* ??? This currently clears the pending bit for all CPUs, even
1300 for per-CPU interrupts. It's unclear whether this is the
1302 if (value
& (1 << i
)) {
1303 GIC_DIST_CLEAR_PENDING(irq
+ i
, ALL_CPU_MASK
);
1306 } else if (offset
< 0x380) {
1307 /* Interrupt Set Active. */
1308 if (s
->revision
!= 2) {
1312 irq
= (offset
- 0x300) * 8 + GIC_BASE_IRQ
;
1313 if (irq
>= s
->num_irq
) {
1317 /* This register is banked per-cpu for PPIs */
1318 int cm
= irq
< GIC_INTERNAL
? (1 << cpu
) : ALL_CPU_MASK
;
1320 for (i
= 0; i
< 8; i
++) {
1321 if (s
->security_extn
&& !attrs
.secure
&&
1322 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1323 continue; /* Ignore Non-secure access of Group0 IRQ */
1326 if (value
& (1 << i
)) {
1327 GIC_DIST_SET_ACTIVE(irq
+ i
, cm
);
1330 } else if (offset
< 0x400) {
1331 /* Interrupt Clear Active. */
1332 if (s
->revision
!= 2) {
1336 irq
= (offset
- 0x380) * 8 + GIC_BASE_IRQ
;
1337 if (irq
>= s
->num_irq
) {
1341 /* This register is banked per-cpu for PPIs */
1342 int cm
= irq
< GIC_INTERNAL
? (1 << cpu
) : ALL_CPU_MASK
;
1344 for (i
= 0; i
< 8; i
++) {
1345 if (s
->security_extn
&& !attrs
.secure
&&
1346 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1347 continue; /* Ignore Non-secure access of Group0 IRQ */
1350 if (value
& (1 << i
)) {
1351 GIC_DIST_CLEAR_ACTIVE(irq
+ i
, cm
);
1354 } else if (offset
< 0x800) {
1355 /* Interrupt Priority. */
1356 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
1357 if (irq
>= s
->num_irq
)
1359 gic_dist_set_priority(s
, cpu
, irq
, value
, attrs
);
1360 } else if (offset
< 0xc00) {
1361 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
1362 * annoying exception of the 11MPCore's GIC.
1364 if (s
->num_cpu
!= 1 || s
->revision
== REV_11MPCORE
) {
1365 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
1366 if (irq
>= s
->num_irq
) {
1369 if (irq
< 29 && s
->revision
== REV_11MPCORE
) {
1371 } else if (irq
< GIC_INTERNAL
) {
1372 value
= ALL_CPU_MASK
;
1374 s
->irq_target
[irq
] = value
& ALL_CPU_MASK
;
1376 } else if (offset
< 0xf00) {
1377 /* Interrupt Configuration. */
1378 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
1379 if (irq
>= s
->num_irq
)
1381 if (irq
< GIC_NR_SGIS
)
1383 for (i
= 0; i
< 4; i
++) {
1384 if (s
->security_extn
&& !attrs
.secure
&&
1385 !GIC_DIST_TEST_GROUP(irq
+ i
, 1 << cpu
)) {
1386 continue; /* Ignore Non-secure access of Group0 IRQ */
1389 if (s
->revision
== REV_11MPCORE
) {
1390 if (value
& (1 << (i
* 2))) {
1391 GIC_DIST_SET_MODEL(irq
+ i
);
1393 GIC_DIST_CLEAR_MODEL(irq
+ i
);
1396 if (value
& (2 << (i
* 2))) {
1397 GIC_DIST_SET_EDGE_TRIGGER(irq
+ i
);
1399 GIC_DIST_CLEAR_EDGE_TRIGGER(irq
+ i
);
1402 } else if (offset
< 0xf10) {
1403 /* 0xf00 is only handled for 32-bit writes. */
1405 } else if (offset
< 0xf20) {
1406 /* GICD_CPENDSGIRn */
1407 if (s
->revision
== REV_11MPCORE
) {
1410 irq
= (offset
- 0xf10);
1412 if (!s
->security_extn
|| attrs
.secure
||
1413 GIC_DIST_TEST_GROUP(irq
, 1 << cpu
)) {
1414 s
->sgi_pending
[irq
][cpu
] &= ~value
;
1415 if (s
->sgi_pending
[irq
][cpu
] == 0) {
1416 GIC_DIST_CLEAR_PENDING(irq
, 1 << cpu
);
1419 } else if (offset
< 0xf30) {
1420 /* GICD_SPENDSGIRn */
1421 if (s
->revision
== REV_11MPCORE
) {
1424 irq
= (offset
- 0xf20);
1426 if (!s
->security_extn
|| attrs
.secure
||
1427 GIC_DIST_TEST_GROUP(irq
, 1 << cpu
)) {
1428 GIC_DIST_SET_PENDING(irq
, 1 << cpu
);
1429 s
->sgi_pending
[irq
][cpu
] |= value
;
1437 qemu_log_mask(LOG_GUEST_ERROR
,
1438 "gic_dist_writeb: Bad offset %x\n", (int)offset
);
1441 static void gic_dist_writew(void *opaque
, hwaddr offset
,
1442 uint32_t value
, MemTxAttrs attrs
)
1444 gic_dist_writeb(opaque
, offset
, value
& 0xff, attrs
);
1445 gic_dist_writeb(opaque
, offset
+ 1, value
>> 8, attrs
);
1448 static void gic_dist_writel(void *opaque
, hwaddr offset
,
1449 uint32_t value
, MemTxAttrs attrs
)
1451 GICState
*s
= (GICState
*)opaque
;
1452 if (offset
== 0xf00) {
1458 cpu
= gic_get_current_cpu(s
);
1459 irq
= value
& 0x3ff;
1460 switch ((value
>> 24) & 3) {
1462 mask
= (value
>> 16) & ALL_CPU_MASK
;
1465 mask
= ALL_CPU_MASK
^ (1 << cpu
);
1471 DPRINTF("Bad Soft Int target filter\n");
1472 mask
= ALL_CPU_MASK
;
1475 GIC_DIST_SET_PENDING(irq
, mask
);
1476 target_cpu
= ctz32(mask
);
1477 while (target_cpu
< GIC_NCPU
) {
1478 s
->sgi_pending
[irq
][target_cpu
] |= (1 << cpu
);
1479 mask
&= ~(1 << target_cpu
);
1480 target_cpu
= ctz32(mask
);
1485 gic_dist_writew(opaque
, offset
, value
& 0xffff, attrs
);
1486 gic_dist_writew(opaque
, offset
+ 2, value
>> 16, attrs
);
1489 static MemTxResult
gic_dist_write(void *opaque
, hwaddr offset
, uint64_t data
,
1490 unsigned size
, MemTxAttrs attrs
)
1492 trace_gic_dist_write(offset
, size
, data
);
1496 gic_dist_writeb(opaque
, offset
, data
, attrs
);
1499 gic_dist_writew(opaque
, offset
, data
, attrs
);
1502 gic_dist_writel(opaque
, offset
, data
, attrs
);
1509 static inline uint32_t gic_apr_ns_view(GICState
*s
, int cpu
, int regno
)
1511 /* Return the Nonsecure view of GICC_APR<regno>. This is the
1512 * second half of GICC_NSAPR.
1514 switch (GIC_MIN_BPR
) {
1517 return s
->nsapr
[regno
+ 2][cpu
];
1522 return s
->nsapr
[regno
+ 1][cpu
];
1527 return extract32(s
->nsapr
[0][cpu
], 16, 16);
1532 return extract32(s
->nsapr
[0][cpu
], 8, 8);
1536 g_assert_not_reached();
1541 static inline void gic_apr_write_ns_view(GICState
*s
, int cpu
, int regno
,
1544 /* Write the Nonsecure view of GICC_APR<regno>. */
1545 switch (GIC_MIN_BPR
) {
1548 s
->nsapr
[regno
+ 2][cpu
] = value
;
1553 s
->nsapr
[regno
+ 1][cpu
] = value
;
1558 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 16, 16, value
);
1563 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 8, 8, value
);
1567 g_assert_not_reached();
1571 static MemTxResult
gic_cpu_read(GICState
*s
, int cpu
, int offset
,
1572 uint64_t *data
, MemTxAttrs attrs
)
1575 case 0x00: /* Control */
1576 *data
= gic_get_cpu_control(s
, cpu
, attrs
);
1578 case 0x04: /* Priority mask */
1579 *data
= gic_get_priority_mask(s
, cpu
, attrs
);
1581 case 0x08: /* Binary Point */
1582 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1583 if (s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) {
1584 /* NS view of BPR when CBPR is 1 */
1585 *data
= MIN(s
->bpr
[cpu
] + 1, 7);
1587 /* BPR is banked. Non-secure copy stored in ABPR. */
1588 *data
= s
->abpr
[cpu
];
1591 *data
= s
->bpr
[cpu
];
1594 case 0x0c: /* Acknowledge */
1595 *data
= gic_acknowledge_irq(s
, cpu
, attrs
);
1597 case 0x14: /* Running Priority */
1598 *data
= gic_get_running_priority(s
, cpu
, attrs
);
1600 case 0x18: /* Highest Pending Interrupt */
1601 *data
= gic_get_current_pending_irq(s
, cpu
, attrs
);
1603 case 0x1c: /* Aliased Binary Point */
1604 /* GIC v2, no security: ABPR
1605 * GIC v1, no security: not implemented (RAZ/WI)
1606 * With security extensions, secure access: ABPR (alias of NS BPR)
1607 * With security extensions, nonsecure access: RAZ/WI
1609 if (!gic_has_groups(s
) || (gic_cpu_ns_access(s
, cpu
, attrs
))) {
1612 *data
= s
->abpr
[cpu
];
1615 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1617 int regno
= (offset
- 0xd0) / 4;
1618 int nr_aprs
= gic_is_vcpu(cpu
) ? GIC_VIRT_NR_APRS
: GIC_NR_APRS
;
1620 if (regno
>= nr_aprs
|| s
->revision
!= 2) {
1622 } else if (gic_is_vcpu(cpu
)) {
1623 *data
= s
->h_apr
[gic_get_vcpu_real_id(cpu
)];
1624 } else if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1625 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1626 *data
= gic_apr_ns_view(s
, regno
, cpu
);
1628 *data
= s
->apr
[regno
][cpu
];
1632 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1634 int regno
= (offset
- 0xe0) / 4;
1636 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2 || !gic_has_groups(s
) ||
1637 gic_cpu_ns_access(s
, cpu
, attrs
) || gic_is_vcpu(cpu
)) {
1640 *data
= s
->nsapr
[regno
][cpu
];
1645 qemu_log_mask(LOG_GUEST_ERROR
,
1646 "gic_cpu_read: Bad offset %x\n", (int)offset
);
1651 trace_gic_cpu_read(gic_is_vcpu(cpu
) ? "vcpu" : "cpu",
1652 gic_get_vcpu_real_id(cpu
), offset
, *data
);
1656 static MemTxResult
gic_cpu_write(GICState
*s
, int cpu
, int offset
,
1657 uint32_t value
, MemTxAttrs attrs
)
1659 trace_gic_cpu_write(gic_is_vcpu(cpu
) ? "vcpu" : "cpu",
1660 gic_get_vcpu_real_id(cpu
), offset
, value
);
1663 case 0x00: /* Control */
1664 gic_set_cpu_control(s
, cpu
, value
, attrs
);
1666 case 0x04: /* Priority mask */
1667 gic_set_priority_mask(s
, cpu
, value
, attrs
);
1669 case 0x08: /* Binary Point */
1670 if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1671 if (s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) {
1672 /* WI when CBPR is 1 */
1675 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1678 int min_bpr
= gic_is_vcpu(cpu
) ? GIC_VIRT_MIN_BPR
: GIC_MIN_BPR
;
1679 s
->bpr
[cpu
] = MAX(value
& 0x7, min_bpr
);
1682 case 0x10: /* End Of Interrupt */
1683 gic_complete_irq(s
, cpu
, value
& 0x3ff, attrs
);
1685 case 0x1c: /* Aliased Binary Point */
1686 if (!gic_has_groups(s
) || (gic_cpu_ns_access(s
, cpu
, attrs
))) {
1687 /* unimplemented, or NS access: RAZ/WI */
1690 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1693 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1695 int regno
= (offset
- 0xd0) / 4;
1696 int nr_aprs
= gic_is_vcpu(cpu
) ? GIC_VIRT_NR_APRS
: GIC_NR_APRS
;
1698 if (regno
>= nr_aprs
|| s
->revision
!= 2) {
1701 if (gic_is_vcpu(cpu
)) {
1702 s
->h_apr
[gic_get_vcpu_real_id(cpu
)] = value
;
1703 } else if (gic_cpu_ns_access(s
, cpu
, attrs
)) {
1704 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1705 gic_apr_write_ns_view(s
, regno
, cpu
, value
);
1707 s
->apr
[regno
][cpu
] = value
;
1711 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1713 int regno
= (offset
- 0xe0) / 4;
1715 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1718 if (gic_is_vcpu(cpu
)) {
1721 if (!gic_has_groups(s
) || (gic_cpu_ns_access(s
, cpu
, attrs
))) {
1724 s
->nsapr
[regno
][cpu
] = value
;
1729 gic_deactivate_irq(s
, cpu
, value
& 0x3ff, attrs
);
1732 qemu_log_mask(LOG_GUEST_ERROR
,
1733 "gic_cpu_write: Bad offset %x\n", (int)offset
);
1737 if (gic_is_vcpu(cpu
)) {
1746 /* Wrappers to read/write the GIC CPU interface for the current CPU */
1747 static MemTxResult
gic_thiscpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1748 unsigned size
, MemTxAttrs attrs
)
1750 GICState
*s
= (GICState
*)opaque
;
1751 return gic_cpu_read(s
, gic_get_current_cpu(s
), addr
, data
, attrs
);
1754 static MemTxResult
gic_thiscpu_write(void *opaque
, hwaddr addr
,
1755 uint64_t value
, unsigned size
,
1758 GICState
*s
= (GICState
*)opaque
;
1759 return gic_cpu_write(s
, gic_get_current_cpu(s
), addr
, value
, attrs
);
1762 /* Wrappers to read/write the GIC CPU interface for a specific CPU.
1763 * These just decode the opaque pointer into GICState* + cpu id.
1765 static MemTxResult
gic_do_cpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1766 unsigned size
, MemTxAttrs attrs
)
1768 GICState
**backref
= (GICState
**)opaque
;
1769 GICState
*s
= *backref
;
1770 int id
= (backref
- s
->backref
);
1771 return gic_cpu_read(s
, id
, addr
, data
, attrs
);
1774 static MemTxResult
gic_do_cpu_write(void *opaque
, hwaddr addr
,
1775 uint64_t value
, unsigned size
,
1778 GICState
**backref
= (GICState
**)opaque
;
1779 GICState
*s
= *backref
;
1780 int id
= (backref
- s
->backref
);
1781 return gic_cpu_write(s
, id
, addr
, value
, attrs
);
1784 static MemTxResult
gic_thisvcpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1785 unsigned size
, MemTxAttrs attrs
)
1787 GICState
*s
= (GICState
*)opaque
;
1789 return gic_cpu_read(s
, gic_get_current_vcpu(s
), addr
, data
, attrs
);
1792 static MemTxResult
gic_thisvcpu_write(void *opaque
, hwaddr addr
,
1793 uint64_t value
, unsigned size
,
1796 GICState
*s
= (GICState
*)opaque
;
1798 return gic_cpu_write(s
, gic_get_current_vcpu(s
), addr
, value
, attrs
);
1801 static uint32_t gic_compute_eisr(GICState
*s
, int cpu
, int lr_start
)
1806 for (lr_idx
= lr_start
; lr_idx
< s
->num_lrs
; lr_idx
++) {
1807 uint32_t *entry
= &s
->h_lr
[lr_idx
][cpu
];
1808 ret
= deposit32(ret
, lr_idx
- lr_start
, 1,
1809 gic_lr_entry_is_eoi(*entry
));
1815 static uint32_t gic_compute_elrsr(GICState
*s
, int cpu
, int lr_start
)
1820 for (lr_idx
= lr_start
; lr_idx
< s
->num_lrs
; lr_idx
++) {
1821 uint32_t *entry
= &s
->h_lr
[lr_idx
][cpu
];
1822 ret
= deposit32(ret
, lr_idx
- lr_start
, 1,
1823 gic_lr_entry_is_free(*entry
));
1829 static void gic_vmcr_write(GICState
*s
, uint32_t value
, MemTxAttrs attrs
)
1831 int vcpu
= gic_get_current_vcpu(s
);
1837 ctlr
= FIELD_EX32(value
, GICH_VMCR
, VMCCtlr
);
1838 abpr
= FIELD_EX32(value
, GICH_VMCR
, VMABP
);
1839 bpr
= FIELD_EX32(value
, GICH_VMCR
, VMBP
);
1840 prio_mask
= FIELD_EX32(value
, GICH_VMCR
, VMPriMask
) << 3;
1842 gic_set_cpu_control(s
, vcpu
, ctlr
, attrs
);
1843 s
->abpr
[vcpu
] = MAX(abpr
, GIC_VIRT_MIN_ABPR
);
1844 s
->bpr
[vcpu
] = MAX(bpr
, GIC_VIRT_MIN_BPR
);
1845 gic_set_priority_mask(s
, vcpu
, prio_mask
, attrs
);
1848 static MemTxResult
gic_hyp_read(void *opaque
, int cpu
, hwaddr addr
,
1849 uint64_t *data
, MemTxAttrs attrs
)
1851 GICState
*s
= ARM_GIC(opaque
);
1852 int vcpu
= cpu
+ GIC_NCPU
;
1855 case A_GICH_HCR
: /* Hypervisor Control */
1856 *data
= s
->h_hcr
[cpu
];
1859 case A_GICH_VTR
: /* VGIC Type */
1860 *data
= FIELD_DP32(0, GICH_VTR
, ListRegs
, s
->num_lrs
- 1);
1861 *data
= FIELD_DP32(*data
, GICH_VTR
, PREbits
,
1862 GIC_VIRT_MAX_GROUP_PRIO_BITS
- 1);
1863 *data
= FIELD_DP32(*data
, GICH_VTR
, PRIbits
,
1864 (7 - GIC_VIRT_MIN_BPR
) - 1);
1867 case A_GICH_VMCR
: /* Virtual Machine Control */
1868 *data
= FIELD_DP32(0, GICH_VMCR
, VMCCtlr
,
1869 extract32(s
->cpu_ctlr
[vcpu
], 0, 10));
1870 *data
= FIELD_DP32(*data
, GICH_VMCR
, VMABP
, s
->abpr
[vcpu
]);
1871 *data
= FIELD_DP32(*data
, GICH_VMCR
, VMBP
, s
->bpr
[vcpu
]);
1872 *data
= FIELD_DP32(*data
, GICH_VMCR
, VMPriMask
,
1873 extract32(s
->priority_mask
[vcpu
], 3, 5));
1876 case A_GICH_MISR
: /* Maintenance Interrupt Status */
1877 *data
= s
->h_misr
[cpu
];
1880 case A_GICH_EISR0
: /* End of Interrupt Status 0 and 1 */
1882 *data
= gic_compute_eisr(s
, cpu
, (addr
- A_GICH_EISR0
) * 8);
1885 case A_GICH_ELRSR0
: /* Empty List Status 0 and 1 */
1887 *data
= gic_compute_elrsr(s
, cpu
, (addr
- A_GICH_ELRSR0
) * 8);
1890 case A_GICH_APR
: /* Active Priorities */
1891 *data
= s
->h_apr
[cpu
];
1894 case A_GICH_LR0
... A_GICH_LR63
: /* List Registers */
1896 int lr_idx
= (addr
- A_GICH_LR0
) / 4;
1898 if (lr_idx
> s
->num_lrs
) {
1901 *data
= s
->h_lr
[lr_idx
][cpu
];
1907 qemu_log_mask(LOG_GUEST_ERROR
,
1908 "gic_hyp_read: Bad offset %" HWADDR_PRIx
"\n", addr
);
1912 trace_gic_hyp_read(addr
, *data
);
1916 static MemTxResult
gic_hyp_write(void *opaque
, int cpu
, hwaddr addr
,
1917 uint64_t value
, MemTxAttrs attrs
)
1919 GICState
*s
= ARM_GIC(opaque
);
1920 int vcpu
= cpu
+ GIC_NCPU
;
1922 trace_gic_hyp_write(addr
, value
);
1925 case A_GICH_HCR
: /* Hypervisor Control */
1926 s
->h_hcr
[cpu
] = value
& GICH_HCR_MASK
;
1929 case A_GICH_VMCR
: /* Virtual Machine Control */
1930 gic_vmcr_write(s
, value
, attrs
);
1933 case A_GICH_APR
: /* Active Priorities */
1934 s
->h_apr
[cpu
] = value
;
1935 s
->running_priority
[vcpu
] = gic_get_prio_from_apr_bits(s
, vcpu
);
1938 case A_GICH_LR0
... A_GICH_LR63
: /* List Registers */
1940 int lr_idx
= (addr
- A_GICH_LR0
) / 4;
1942 if (lr_idx
> s
->num_lrs
) {
1946 s
->h_lr
[lr_idx
][cpu
] = value
& GICH_LR_MASK
;
1947 trace_gic_lr_entry(cpu
, lr_idx
, s
->h_lr
[lr_idx
][cpu
]);
1952 qemu_log_mask(LOG_GUEST_ERROR
,
1953 "gic_hyp_write: Bad offset %" HWADDR_PRIx
"\n", addr
);
1961 static MemTxResult
gic_thiscpu_hyp_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1962 unsigned size
, MemTxAttrs attrs
)
1964 GICState
*s
= (GICState
*)opaque
;
1966 return gic_hyp_read(s
, gic_get_current_cpu(s
), addr
, data
, attrs
);
1969 static MemTxResult
gic_thiscpu_hyp_write(void *opaque
, hwaddr addr
,
1970 uint64_t value
, unsigned size
,
1973 GICState
*s
= (GICState
*)opaque
;
1975 return gic_hyp_write(s
, gic_get_current_cpu(s
), addr
, value
, attrs
);
1978 static MemTxResult
gic_do_hyp_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1979 unsigned size
, MemTxAttrs attrs
)
1981 GICState
**backref
= (GICState
**)opaque
;
1982 GICState
*s
= *backref
;
1983 int id
= (backref
- s
->backref
);
1985 return gic_hyp_read(s
, id
, addr
, data
, attrs
);
1988 static MemTxResult
gic_do_hyp_write(void *opaque
, hwaddr addr
,
1989 uint64_t value
, unsigned size
,
1992 GICState
**backref
= (GICState
**)opaque
;
1993 GICState
*s
= *backref
;
1994 int id
= (backref
- s
->backref
);
1996 return gic_hyp_write(s
, id
+ GIC_NCPU
, addr
, value
, attrs
);
2000 static const MemoryRegionOps gic_ops
[2] = {
2002 .read_with_attrs
= gic_dist_read
,
2003 .write_with_attrs
= gic_dist_write
,
2004 .endianness
= DEVICE_NATIVE_ENDIAN
,
2007 .read_with_attrs
= gic_thiscpu_read
,
2008 .write_with_attrs
= gic_thiscpu_write
,
2009 .endianness
= DEVICE_NATIVE_ENDIAN
,
2013 static const MemoryRegionOps gic_cpu_ops
= {
2014 .read_with_attrs
= gic_do_cpu_read
,
2015 .write_with_attrs
= gic_do_cpu_write
,
2016 .endianness
= DEVICE_NATIVE_ENDIAN
,
2019 static const MemoryRegionOps gic_virt_ops
[2] = {
2021 .read_with_attrs
= gic_thiscpu_hyp_read
,
2022 .write_with_attrs
= gic_thiscpu_hyp_write
,
2023 .endianness
= DEVICE_NATIVE_ENDIAN
,
2026 .read_with_attrs
= gic_thisvcpu_read
,
2027 .write_with_attrs
= gic_thisvcpu_write
,
2028 .endianness
= DEVICE_NATIVE_ENDIAN
,
2032 static const MemoryRegionOps gic_viface_ops
= {
2033 .read_with_attrs
= gic_do_hyp_read
,
2034 .write_with_attrs
= gic_do_hyp_write
,
2035 .endianness
= DEVICE_NATIVE_ENDIAN
,
2038 static void arm_gic_realize(DeviceState
*dev
, Error
**errp
)
2040 /* Device instance realize function for the GIC sysbus device */
2042 GICState
*s
= ARM_GIC(dev
);
2043 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
2044 ARMGICClass
*agc
= ARM_GIC_GET_CLASS(s
);
2045 Error
*local_err
= NULL
;
2047 agc
->parent_realize(dev
, &local_err
);
2049 error_propagate(errp
, local_err
);
2053 if (kvm_enabled() && !kvm_arm_supports_user_irq()) {
2054 error_setg(errp
, "KVM with user space irqchip only works when the "
2055 "host kernel supports KVM_CAP_ARM_USER_IRQ");
2059 /* This creates distributor, main CPU interface (s->cpuiomem[0]) and if
2060 * enabled, virtualization extensions related interfaces (main virtual
2061 * interface (s->vifaceiomem[0]) and virtual CPU interface).
2063 gic_init_irqs_and_mmio(s
, gic_set_irq
, gic_ops
, gic_virt_ops
);
2065 /* Extra core-specific regions for the CPU interfaces. This is
2066 * necessary for "franken-GIC" implementations, for example on
2068 * NB that the memory region size of 0x100 applies for the 11MPCore
2069 * and also cores following the GIC v1 spec (ie A9).
2070 * GIC v2 defines a larger memory region (0x1000) so this will need
2071 * to be extended when we implement A15.
2073 for (i
= 0; i
< s
->num_cpu
; i
++) {
2075 memory_region_init_io(&s
->cpuiomem
[i
+1], OBJECT(s
), &gic_cpu_ops
,
2076 &s
->backref
[i
], "gic_cpu", 0x100);
2077 sysbus_init_mmio(sbd
, &s
->cpuiomem
[i
+1]);
2080 /* Extra core-specific regions for virtual interfaces. This is required by
2081 * the GICv2 specification.
2084 for (i
= 0; i
< s
->num_cpu
; i
++) {
2085 memory_region_init_io(&s
->vifaceiomem
[i
+ 1], OBJECT(s
),
2086 &gic_viface_ops
, &s
->backref
[i
],
2087 "gic_viface", 0x200);
2088 sysbus_init_mmio(sbd
, &s
->vifaceiomem
[i
+ 1]);
2094 static void arm_gic_class_init(ObjectClass
*klass
, void *data
)
2096 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2097 ARMGICClass
*agc
= ARM_GIC_CLASS(klass
);
2099 device_class_set_parent_realize(dc
, arm_gic_realize
, &agc
->parent_realize
);
2102 static const TypeInfo arm_gic_info
= {
2103 .name
= TYPE_ARM_GIC
,
2104 .parent
= TYPE_ARM_GIC_COMMON
,
2105 .instance_size
= sizeof(GICState
),
2106 .class_init
= arm_gic_class_init
,
2107 .class_size
= sizeof(ARMGICClass
),
2110 static void arm_gic_register_types(void)
2112 type_register_static(&arm_gic_info
);
2115 type_init(arm_gic_register_types
)