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ppc: Don't update NIP on conditional trap instructions
[qemu.git] / target-ppc / translate.c
blob93cd98c6add158a65eb69def23bc6c273c7a3c36
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91 tcg_ctx.tcg_env = cpu_env;
92
93 p = cpu_reg_names;
94 cpu_reg_names_size = sizeof(cpu_reg_names);
95
96 for (i = 0; i < 8; i++) {
97 snprintf(p, cpu_reg_names_size, "crf%d", i);
98 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
99 offsetof(CPUPPCState, crf[i]), p);
100 p += 5;
101 cpu_reg_names_size -= 5;
102 }
103
104 for (i = 0; i < 32; i++) {
105 snprintf(p, cpu_reg_names_size, "r%d", i);
106 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gpr[i]), p);
108 p += (i < 10) ? 3 : 4;
109 cpu_reg_names_size -= (i < 10) ? 3 : 4;
110 snprintf(p, cpu_reg_names_size, "r%dH", i);
111 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
112 offsetof(CPUPPCState, gprh[i]), p);
113 p += (i < 10) ? 4 : 5;
114 cpu_reg_names_size -= (i < 10) ? 4 : 5;
115
116 snprintf(p, cpu_reg_names_size, "fp%d", i);
117 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
118 offsetof(CPUPPCState, fpr[i]), p);
119 p += (i < 10) ? 4 : 5;
120 cpu_reg_names_size -= (i < 10) ? 4 : 5;
121
122 snprintf(p, cpu_reg_names_size, "avr%dH", i);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
125 offsetof(CPUPPCState, avr[i].u64[0]), p);
126 #else
127 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
128 offsetof(CPUPPCState, avr[i].u64[1]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 cpu_reg_names_size -= (i < 10) ? 6 : 7;
132
133 snprintf(p, cpu_reg_names_size, "avr%dL", i);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
136 offsetof(CPUPPCState, avr[i].u64[1]), p);
137 #else
138 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
139 offsetof(CPUPPCState, avr[i].u64[0]), p);
140 #endif
141 p += (i < 10) ? 6 : 7;
142 cpu_reg_names_size -= (i < 10) ? 6 : 7;
143 snprintf(p, cpu_reg_names_size, "vsr%d", i);
144 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
145 offsetof(CPUPPCState, vsr[i]), p);
146 p += (i < 10) ? 5 : 6;
147 cpu_reg_names_size -= (i < 10) ? 5 : 6;
148 }
149
150 cpu_nip = tcg_global_mem_new(cpu_env,
151 offsetof(CPUPPCState, nip), "nip");
152
153 cpu_msr = tcg_global_mem_new(cpu_env,
154 offsetof(CPUPPCState, msr), "msr");
155
156 cpu_ctr = tcg_global_mem_new(cpu_env,
157 offsetof(CPUPPCState, ctr), "ctr");
158
159 cpu_lr = tcg_global_mem_new(cpu_env,
160 offsetof(CPUPPCState, lr), "lr");
161
162 #if defined(TARGET_PPC64)
163 cpu_cfar = tcg_global_mem_new(cpu_env,
164 offsetof(CPUPPCState, cfar), "cfar");
165 #endif
166
167 cpu_xer = tcg_global_mem_new(cpu_env,
168 offsetof(CPUPPCState, xer), "xer");
169 cpu_so = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, so), "SO");
171 cpu_ov = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, ov), "OV");
173 cpu_ca = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ca), "CA");
175
176 cpu_reserve = tcg_global_mem_new(cpu_env,
177 offsetof(CPUPPCState, reserve_addr),
178 "reserve_addr");
179
180 cpu_fpscr = tcg_global_mem_new(cpu_env,
181 offsetof(CPUPPCState, fpscr), "fpscr");
182
183 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
184 offsetof(CPUPPCState, access_type), "access_type");
185
186 done_init = 1;
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 struct TranslationBlock *tb;
192 target_ulong nip;
193 uint32_t opcode;
194 uint32_t exception;
195 /* Routine used to access memory */
196 bool pr, hv, dr, le_mode;
197 bool lazy_tlb_flush;
198 int mem_idx;
199 int access_type;
200 /* Translation flags */
201 TCGMemOp default_tcg_memop_mask;
202 #if defined(TARGET_PPC64)
203 bool sf_mode;
204 bool has_cfar;
205 #endif
206 bool fpu_enabled;
207 bool altivec_enabled;
208 bool vsx_enabled;
209 bool spe_enabled;
210 bool tm_enabled;
211 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
212 int singlestep_enabled;
213 uint64_t insns_flags;
214 uint64_t insns_flags2;
215 };
216
217 /* Return true iff byteswap is needed in a scalar memop */
218 static inline bool need_byteswap(const DisasContext *ctx)
219 {
220 #if defined(TARGET_WORDS_BIGENDIAN)
221 return ctx->le_mode;
222 #else
223 return !ctx->le_mode;
224 #endif
225 }
226
227 /* True when active word size < size of target_long. */
228 #ifdef TARGET_PPC64
229 # define NARROW_MODE(C) (!(C)->sf_mode)
230 #else
231 # define NARROW_MODE(C) 0
232 #endif
233
234 struct opc_handler_t {
235 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
236 uint32_t inval1;
237 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
238 uint32_t inval2;
239 /* instruction type */
240 uint64_t type;
241 /* extended instruction type */
242 uint64_t type2;
243 /* handler */
244 void (*handler)(DisasContext *ctx);
245 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
246 const char *oname;
247 #endif
248 #if defined(DO_PPC_STATISTICS)
249 uint64_t count;
250 #endif
251 };
252
253 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
254 {
255 if (ctx->access_type != access_type) {
256 tcg_gen_movi_i32(cpu_access_type, access_type);
257 ctx->access_type = access_type;
258 }
259 }
260
261 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
262 {
263 if (NARROW_MODE(ctx)) {
264 nip = (uint32_t)nip;
265 }
266 tcg_gen_movi_tl(cpu_nip, nip);
267 }
268
269 static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
270 {
271 TCGv_i32 t0, t1;
272
273 /* These are all synchronous exceptions, we set the PC back to
274 * the faulting instruction
275 */
276 if (ctx->exception == POWERPC_EXCP_NONE) {
277 gen_update_nip(ctx, ctx->nip - 4);
278 }
279 t0 = tcg_const_i32(excp);
280 t1 = tcg_const_i32(error);
281 gen_helper_raise_exception_err(cpu_env, t0, t1);
282 tcg_temp_free_i32(t0);
283 tcg_temp_free_i32(t1);
284 ctx->exception = (excp);
285 }
286
287 static void gen_exception(DisasContext *ctx, uint32_t excp)
288 {
289 TCGv_i32 t0;
290
291 /* These are all synchronous exceptions, we set the PC back to
292 * the faulting instruction
293 */
294 if (ctx->exception == POWERPC_EXCP_NONE) {
295 gen_update_nip(ctx, ctx->nip - 4);
296 }
297 t0 = tcg_const_i32(excp);
298 gen_helper_raise_exception(cpu_env, t0);
299 tcg_temp_free_i32(t0);
300 ctx->exception = (excp);
301 }
302
303 static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
304 target_ulong nip)
305 {
306 TCGv_i32 t0;
307
308 gen_update_nip(ctx, nip);
309 t0 = tcg_const_i32(excp);
310 gen_helper_raise_exception(cpu_env, t0);
311 tcg_temp_free_i32(t0);
312 ctx->exception = (excp);
313 }
314
315 static void gen_debug_exception(DisasContext *ctx)
316 {
317 TCGv_i32 t0;
318
319 /* These are all synchronous exceptions, we set the PC back to
320 * the faulting instruction
321 */
322 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
323 (ctx->exception != POWERPC_EXCP_SYNC)) {
324 gen_update_nip(ctx, ctx->nip - 4);
325 }
326 t0 = tcg_const_i32(EXCP_DEBUG);
327 gen_helper_raise_exception(cpu_env, t0);
328 tcg_temp_free_i32(t0);
329 }
330
331 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
332 {
333 /* Will be converted to program check if needed */
334 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error);
335 }
336
337 static inline void gen_priv_exception(DisasContext *ctx, uint32_t error)
338 {
339 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error);
340 }
341
342 static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error)
343 {
344 /* Will be converted to program check if needed */
345 gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error);
346 }
347
348 /* Stop translation */
349 static inline void gen_stop_exception(DisasContext *ctx)
350 {
351 gen_update_nip(ctx, ctx->nip);
352 ctx->exception = POWERPC_EXCP_STOP;
353 }
354
355 #ifndef CONFIG_USER_ONLY
356 /* No need to update nip here, as execution flow will change */
357 static inline void gen_sync_exception(DisasContext *ctx)
358 {
359 ctx->exception = POWERPC_EXCP_SYNC;
360 }
361 #endif
362
363 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
364 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
365
366 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
367 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
368
369 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
370 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
371
372 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
373 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
374
375 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
376 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
377
378 typedef struct opcode_t {
379 unsigned char opc1, opc2, opc3, opc4;
380 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
381 unsigned char pad[4];
382 #endif
383 opc_handler_t handler;
384 const char *oname;
385 } opcode_t;
386
387 /* Helpers for priv. check */
388 #define GEN_PRIV \
389 do { \
390 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
391 } while (0)
392
393 #if defined(CONFIG_USER_ONLY)
394 #define CHK_HV GEN_PRIV
395 #define CHK_SV GEN_PRIV
396 #define CHK_HVRM GEN_PRIV
397 #else
398 #define CHK_HV \
399 do { \
400 if (unlikely(ctx->pr || !ctx->hv)) { \
401 GEN_PRIV; \
402 } \
403 } while (0)
404 #define CHK_SV \
405 do { \
406 if (unlikely(ctx->pr)) { \
407 GEN_PRIV; \
408 } \
409 } while (0)
410 #define CHK_HVRM \
411 do { \
412 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
413 GEN_PRIV; \
414 } \
415 } while (0)
416 #endif
417
418 #define CHK_NONE
419
420
421 /*****************************************************************************/
422 /*** Instruction decoding ***/
423 #define EXTRACT_HELPER(name, shift, nb) \
424 static inline uint32_t name(uint32_t opcode) \
425 { \
426 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
427 }
428
429 #define EXTRACT_SHELPER(name, shift, nb) \
430 static inline int32_t name(uint32_t opcode) \
431 { \
432 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
433 }
434
435 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
436 static inline uint32_t name(uint32_t opcode) \
437 { \
438 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
439 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
440 }
441
442 #define EXTRACT_HELPER_DXFORM(name, \
443 d0_bits, shift_op_d0, shift_d0, \
444 d1_bits, shift_op_d1, shift_d1, \
445 d2_bits, shift_op_d2, shift_d2) \
446 static inline int16_t name(uint32_t opcode) \
447 { \
448 return \
449 (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
450 (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
451 (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \
452 }
453
454
455 /* Opcode part 1 */
456 EXTRACT_HELPER(opc1, 26, 6);
457 /* Opcode part 2 */
458 EXTRACT_HELPER(opc2, 1, 5);
459 /* Opcode part 3 */
460 EXTRACT_HELPER(opc3, 6, 5);
461 /* Opcode part 4 */
462 EXTRACT_HELPER(opc4, 16, 5);
463 /* Update Cr0 flags */
464 EXTRACT_HELPER(Rc, 0, 1);
465 /* Update Cr6 flags (Altivec) */
466 EXTRACT_HELPER(Rc21, 10, 1);
467 /* Destination */
468 EXTRACT_HELPER(rD, 21, 5);
469 /* Source */
470 EXTRACT_HELPER(rS, 21, 5);
471 /* First operand */
472 EXTRACT_HELPER(rA, 16, 5);
473 /* Second operand */
474 EXTRACT_HELPER(rB, 11, 5);
475 /* Third operand */
476 EXTRACT_HELPER(rC, 6, 5);
477 /*** Get CRn ***/
478 EXTRACT_HELPER(crfD, 23, 3);
479 EXTRACT_HELPER(crfS, 18, 3);
480 EXTRACT_HELPER(crbD, 21, 5);
481 EXTRACT_HELPER(crbA, 16, 5);
482 EXTRACT_HELPER(crbB, 11, 5);
483 /* SPR / TBL */
484 EXTRACT_HELPER(_SPR, 11, 10);
485 static inline uint32_t SPR(uint32_t opcode)
486 {
487 uint32_t sprn = _SPR(opcode);
488
489 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
490 }
491 /*** Get constants ***/
492 /* 16 bits signed immediate value */
493 EXTRACT_SHELPER(SIMM, 0, 16);
494 /* 16 bits unsigned immediate value */
495 EXTRACT_HELPER(UIMM, 0, 16);
496 /* 5 bits signed immediate value */
497 EXTRACT_HELPER(SIMM5, 16, 5);
498 /* 5 bits signed immediate value */
499 EXTRACT_HELPER(UIMM5, 16, 5);
500 /* Bit count */
501 EXTRACT_HELPER(NB, 11, 5);
502 /* Shift count */
503 EXTRACT_HELPER(SH, 11, 5);
504 /* Vector shift count */
505 EXTRACT_HELPER(VSH, 6, 4);
506 /* Mask start */
507 EXTRACT_HELPER(MB, 6, 5);
508 /* Mask end */
509 EXTRACT_HELPER(ME, 1, 5);
510 /* Trap operand */
511 EXTRACT_HELPER(TO, 21, 5);
512
513 EXTRACT_HELPER(CRM, 12, 8);
514
515 #ifndef CONFIG_USER_ONLY
516 EXTRACT_HELPER(SR, 16, 4);
517 #endif
518
519 /* mtfsf/mtfsfi */
520 EXTRACT_HELPER(FPBF, 23, 3);
521 EXTRACT_HELPER(FPIMM, 12, 4);
522 EXTRACT_HELPER(FPL, 25, 1);
523 EXTRACT_HELPER(FPFLM, 17, 8);
524 EXTRACT_HELPER(FPW, 16, 1);
525
526 /* addpcis */
527 EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
528
529 /*** Jump target decoding ***/
530 /* Immediate address */
531 static inline target_ulong LI(uint32_t opcode)
532 {
533 return (opcode >> 0) & 0x03FFFFFC;
534 }
535
536 static inline uint32_t BD(uint32_t opcode)
537 {
538 return (opcode >> 0) & 0xFFFC;
539 }
540
541 EXTRACT_HELPER(BO, 21, 5);
542 EXTRACT_HELPER(BI, 16, 5);
543 /* Absolute/relative address */
544 EXTRACT_HELPER(AA, 1, 1);
545 /* Link */
546 EXTRACT_HELPER(LK, 0, 1);
547
548 /* DFP Z22-form */
549 EXTRACT_HELPER(DCM, 10, 6)
550
551 /* DFP Z23-form */
552 EXTRACT_HELPER(RMC, 9, 2)
553
554 /* Create a mask between <start> and <end> bits */
555 static inline target_ulong MASK(uint32_t start, uint32_t end)
556 {
557 target_ulong ret;
558
559 #if defined(TARGET_PPC64)
560 if (likely(start == 0)) {
561 ret = UINT64_MAX << (63 - end);
562 } else if (likely(end == 63)) {
563 ret = UINT64_MAX >> start;
564 }
565 #else
566 if (likely(start == 0)) {
567 ret = UINT32_MAX << (31 - end);
568 } else if (likely(end == 31)) {
569 ret = UINT32_MAX >> start;
570 }
571 #endif
572 else {
573 ret = (((target_ulong)(-1ULL)) >> (start)) ^
574 (((target_ulong)(-1ULL) >> (end)) >> 1);
575 if (unlikely(start > end))
576 return ~ret;
577 }
578
579 return ret;
580 }
581
582 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
583 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
584 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
585 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
586 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
587 EXTRACT_HELPER(DM, 8, 2);
588 EXTRACT_HELPER(UIM, 16, 2);
589 EXTRACT_HELPER(SHW, 8, 2);
590 EXTRACT_HELPER(SP, 19, 2);
591 /*****************************************************************************/
592 /* PowerPC instructions table */
593
594 #if defined(DO_PPC_STATISTICS)
595 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
596 { \
597 .opc1 = op1, \
598 .opc2 = op2, \
599 .opc3 = op3, \
600 .opc4 = 0xff, \
601 .handler = { \
602 .inval1 = invl, \
603 .type = _typ, \
604 .type2 = _typ2, \
605 .handler = &gen_##name, \
606 .oname = stringify(name), \
607 }, \
608 .oname = stringify(name), \
609 }
610 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
611 { \
612 .opc1 = op1, \
613 .opc2 = op2, \
614 .opc3 = op3, \
615 .opc4 = 0xff, \
616 .handler = { \
617 .inval1 = invl1, \
618 .inval2 = invl2, \
619 .type = _typ, \
620 .type2 = _typ2, \
621 .handler = &gen_##name, \
622 .oname = stringify(name), \
623 }, \
624 .oname = stringify(name), \
625 }
626 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
627 { \
628 .opc1 = op1, \
629 .opc2 = op2, \
630 .opc3 = op3, \
631 .opc4 = 0xff, \
632 .handler = { \
633 .inval1 = invl, \
634 .type = _typ, \
635 .type2 = _typ2, \
636 .handler = &gen_##name, \
637 .oname = onam, \
638 }, \
639 .oname = onam, \
640 }
641 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
642 { \
643 .opc1 = op1, \
644 .opc2 = op2, \
645 .opc3 = op3, \
646 .opc4 = op4, \
647 .handler = { \
648 .inval1 = invl, \
649 .type = _typ, \
650 .type2 = _typ2, \
651 .handler = &gen_##name, \
652 .oname = stringify(name), \
653 }, \
654 .oname = stringify(name), \
655 }
656 #else
657 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
658 { \
659 .opc1 = op1, \
660 .opc2 = op2, \
661 .opc3 = op3, \
662 .opc4 = 0xff, \
663 .handler = { \
664 .inval1 = invl, \
665 .type = _typ, \
666 .type2 = _typ2, \
667 .handler = &gen_##name, \
668 }, \
669 .oname = stringify(name), \
670 }
671 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
672 { \
673 .opc1 = op1, \
674 .opc2 = op2, \
675 .opc3 = op3, \
676 .opc4 = 0xff, \
677 .handler = { \
678 .inval1 = invl1, \
679 .inval2 = invl2, \
680 .type = _typ, \
681 .type2 = _typ2, \
682 .handler = &gen_##name, \
683 }, \
684 .oname = stringify(name), \
685 }
686 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
687 { \
688 .opc1 = op1, \
689 .opc2 = op2, \
690 .opc3 = op3, \
691 .opc4 = 0xff, \
692 .handler = { \
693 .inval1 = invl, \
694 .type = _typ, \
695 .type2 = _typ2, \
696 .handler = &gen_##name, \
697 }, \
698 .oname = onam, \
699 }
700 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
701 { \
702 .opc1 = op1, \
703 .opc2 = op2, \
704 .opc3 = op3, \
705 .opc4 = op4, \
706 .handler = { \
707 .inval1 = invl, \
708 .type = _typ, \
709 .type2 = _typ2, \
710 .handler = &gen_##name, \
711 }, \
712 .oname = stringify(name), \
713 }
714 #endif
715
716 /* SPR load/store helpers */
717 static inline void gen_load_spr(TCGv t, int reg)
718 {
719 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
720 }
721
722 static inline void gen_store_spr(int reg, TCGv t)
723 {
724 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
725 }
726
727 /* Invalid instruction */
728 static void gen_invalid(DisasContext *ctx)
729 {
730 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
731 }
732
733 static opc_handler_t invalid_handler = {
734 .inval1 = 0xFFFFFFFF,
735 .inval2 = 0xFFFFFFFF,
736 .type = PPC_NONE,
737 .type2 = PPC_NONE,
738 .handler = gen_invalid,
739 };
740
741 /*** Integer comparison ***/
742
743 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
744 {
745 TCGv t0 = tcg_temp_new();
746 TCGv_i32 t1 = tcg_temp_new_i32();
747
748 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
749
750 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
751 tcg_gen_trunc_tl_i32(t1, t0);
752 tcg_gen_shli_i32(t1, t1, CRF_LT);
753 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
754
755 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
756 tcg_gen_trunc_tl_i32(t1, t0);
757 tcg_gen_shli_i32(t1, t1, CRF_GT);
758 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
759
760 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
761 tcg_gen_trunc_tl_i32(t1, t0);
762 tcg_gen_shli_i32(t1, t1, CRF_EQ);
763 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
764
765 tcg_temp_free(t0);
766 tcg_temp_free_i32(t1);
767 }
768
769 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
770 {
771 TCGv t0 = tcg_const_tl(arg1);
772 gen_op_cmp(arg0, t0, s, crf);
773 tcg_temp_free(t0);
774 }
775
776 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
777 {
778 TCGv t0, t1;
779 t0 = tcg_temp_new();
780 t1 = tcg_temp_new();
781 if (s) {
782 tcg_gen_ext32s_tl(t0, arg0);
783 tcg_gen_ext32s_tl(t1, arg1);
784 } else {
785 tcg_gen_ext32u_tl(t0, arg0);
786 tcg_gen_ext32u_tl(t1, arg1);
787 }
788 gen_op_cmp(t0, t1, s, crf);
789 tcg_temp_free(t1);
790 tcg_temp_free(t0);
791 }
792
793 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
794 {
795 TCGv t0 = tcg_const_tl(arg1);
796 gen_op_cmp32(arg0, t0, s, crf);
797 tcg_temp_free(t0);
798 }
799
800 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
801 {
802 if (NARROW_MODE(ctx)) {
803 gen_op_cmpi32(reg, 0, 1, 0);
804 } else {
805 gen_op_cmpi(reg, 0, 1, 0);
806 }
807 }
808
809 /* cmp */
810 static void gen_cmp(DisasContext *ctx)
811 {
812 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
813 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
814 1, crfD(ctx->opcode));
815 } else {
816 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
817 1, crfD(ctx->opcode));
818 }
819 }
820
821 /* cmpi */
822 static void gen_cmpi(DisasContext *ctx)
823 {
824 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
825 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
826 1, crfD(ctx->opcode));
827 } else {
828 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
829 1, crfD(ctx->opcode));
830 }
831 }
832
833 /* cmpl */
834 static void gen_cmpl(DisasContext *ctx)
835 {
836 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
837 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
838 0, crfD(ctx->opcode));
839 } else {
840 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
841 0, crfD(ctx->opcode));
842 }
843 }
844
845 /* cmpli */
846 static void gen_cmpli(DisasContext *ctx)
847 {
848 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
849 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
850 0, crfD(ctx->opcode));
851 } else {
852 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
853 0, crfD(ctx->opcode));
854 }
855 }
856
857 /* cmprb - range comparison: isupper, isaplha, islower*/
858 static void gen_cmprb(DisasContext *ctx)
859 {
860 TCGv_i32 src1 = tcg_temp_new_i32();
861 TCGv_i32 src2 = tcg_temp_new_i32();
862 TCGv_i32 src2lo = tcg_temp_new_i32();
863 TCGv_i32 src2hi = tcg_temp_new_i32();
864 TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)];
865
866 tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]);
867 tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]);
868
869 tcg_gen_andi_i32(src1, src1, 0xFF);
870 tcg_gen_ext8u_i32(src2lo, src2);
871 tcg_gen_shri_i32(src2, src2, 8);
872 tcg_gen_ext8u_i32(src2hi, src2);
873
874 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
875 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
876 tcg_gen_and_i32(crf, src2lo, src2hi);
877
878 if (ctx->opcode & 0x00200000) {
879 tcg_gen_shri_i32(src2, src2, 8);
880 tcg_gen_ext8u_i32(src2lo, src2);
881 tcg_gen_shri_i32(src2, src2, 8);
882 tcg_gen_ext8u_i32(src2hi, src2);
883 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1);
884 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi);
885 tcg_gen_and_i32(src2lo, src2lo, src2hi);
886 tcg_gen_or_i32(crf, crf, src2lo);
887 }
888 tcg_gen_shli_i32(crf, crf, CRF_GT);
889 tcg_temp_free_i32(src1);
890 tcg_temp_free_i32(src2);
891 tcg_temp_free_i32(src2lo);
892 tcg_temp_free_i32(src2hi);
893 }
894
895 #if defined(TARGET_PPC64)
896 /* cmpeqb */
897 static void gen_cmpeqb(DisasContext *ctx)
898 {
899 gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
900 cpu_gpr[rB(ctx->opcode)]);
901 }
902 #endif
903
904 /* isel (PowerPC 2.03 specification) */
905 static void gen_isel(DisasContext *ctx)
906 {
907 uint32_t bi = rC(ctx->opcode);
908 uint32_t mask = 0x08 >> (bi & 0x03);
909 TCGv t0 = tcg_temp_new();
910 TCGv zr;
911
912 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
913 tcg_gen_andi_tl(t0, t0, mask);
914
915 zr = tcg_const_tl(0);
916 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
917 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
918 cpu_gpr[rB(ctx->opcode)]);
919 tcg_temp_free(zr);
920 tcg_temp_free(t0);
921 }
922
923 /* cmpb: PowerPC 2.05 specification */
924 static void gen_cmpb(DisasContext *ctx)
925 {
926 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
927 cpu_gpr[rB(ctx->opcode)]);
928 }
929
930 /*** Integer arithmetic ***/
931
932 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
933 TCGv arg1, TCGv arg2, int sub)
934 {
935 TCGv t0 = tcg_temp_new();
936
937 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
938 tcg_gen_xor_tl(t0, arg1, arg2);
939 if (sub) {
940 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
941 } else {
942 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
943 }
944 tcg_temp_free(t0);
945 if (NARROW_MODE(ctx)) {
946 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
947 }
948 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
949 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
950 }
951
952 /* Common add function */
953 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
954 TCGv arg2, bool add_ca, bool compute_ca,
955 bool compute_ov, bool compute_rc0)
956 {
957 TCGv t0 = ret;
958
959 if (compute_ca || compute_ov) {
960 t0 = tcg_temp_new();
961 }
962
963 if (compute_ca) {
964 if (NARROW_MODE(ctx)) {
965 /* Caution: a non-obvious corner case of the spec is that we
966 must produce the *entire* 64-bit addition, but produce the
967 carry into bit 32. */
968 TCGv t1 = tcg_temp_new();
969 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
970 tcg_gen_add_tl(t0, arg1, arg2);
971 if (add_ca) {
972 tcg_gen_add_tl(t0, t0, cpu_ca);
973 }
974 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
975 tcg_temp_free(t1);
976 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
977 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
978 } else {
979 TCGv zero = tcg_const_tl(0);
980 if (add_ca) {
981 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
982 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
983 } else {
984 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
985 }
986 tcg_temp_free(zero);
987 }
988 } else {
989 tcg_gen_add_tl(t0, arg1, arg2);
990 if (add_ca) {
991 tcg_gen_add_tl(t0, t0, cpu_ca);
992 }
993 }
994
995 if (compute_ov) {
996 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
997 }
998 if (unlikely(compute_rc0)) {
999 gen_set_Rc0(ctx, t0);
1000 }
1001
1002 if (!TCGV_EQUAL(t0, ret)) {
1003 tcg_gen_mov_tl(ret, t0);
1004 tcg_temp_free(t0);
1005 }
1006 }
1007 /* Add functions with two operands */
1008 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
1009 static void glue(gen_, name)(DisasContext *ctx) \
1010 { \
1011 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1012 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1013 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1014 }
1015 /* Add functions with one operand and one immediate */
1016 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
1017 add_ca, compute_ca, compute_ov) \
1018 static void glue(gen_, name)(DisasContext *ctx) \
1019 { \
1020 TCGv t0 = tcg_const_tl(const_val); \
1021 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
1022 cpu_gpr[rA(ctx->opcode)], t0, \
1023 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1024 tcg_temp_free(t0); \
1025 }
1026
1027 /* add add. addo addo. */
1028 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1029 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1030 /* addc addc. addco addco. */
1031 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1032 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1033 /* adde adde. addeo addeo. */
1034 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1035 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1036 /* addme addme. addmeo addmeo. */
1037 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1038 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1039 /* addze addze. addzeo addzeo.*/
1040 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1041 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1042 /* addi */
1043 static void gen_addi(DisasContext *ctx)
1044 {
1045 target_long simm = SIMM(ctx->opcode);
1046
1047 if (rA(ctx->opcode) == 0) {
1048 /* li case */
1049 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1050 } else {
1051 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1052 cpu_gpr[rA(ctx->opcode)], simm);
1053 }
1054 }
1055 /* addic addic.*/
1056 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
1057 {
1058 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1059 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1060 c, 0, 1, 0, compute_rc0);
1061 tcg_temp_free(c);
1062 }
1063
1064 static void gen_addic(DisasContext *ctx)
1065 {
1066 gen_op_addic(ctx, 0);
1067 }
1068
1069 static void gen_addic_(DisasContext *ctx)
1070 {
1071 gen_op_addic(ctx, 1);
1072 }
1073
1074 /* addis */
1075 static void gen_addis(DisasContext *ctx)
1076 {
1077 target_long simm = SIMM(ctx->opcode);
1078
1079 if (rA(ctx->opcode) == 0) {
1080 /* lis case */
1081 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1082 } else {
1083 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
1084 cpu_gpr[rA(ctx->opcode)], simm << 16);
1085 }
1086 }
1087
1088 /* addpcis */
1089 static void gen_addpcis(DisasContext *ctx)
1090 {
1091 target_long d = DX(ctx->opcode);
1092
1093 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16));
1094 }
1095
1096 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
1097 TCGv arg2, int sign, int compute_ov)
1098 {
1099 TCGLabel *l1 = gen_new_label();
1100 TCGLabel *l2 = gen_new_label();
1101 TCGv_i32 t0 = tcg_temp_local_new_i32();
1102 TCGv_i32 t1 = tcg_temp_local_new_i32();
1103
1104 tcg_gen_trunc_tl_i32(t0, arg1);
1105 tcg_gen_trunc_tl_i32(t1, arg2);
1106 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1107 if (sign) {
1108 TCGLabel *l3 = gen_new_label();
1109 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1110 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1111 gen_set_label(l3);
1112 tcg_gen_div_i32(t0, t0, t1);
1113 } else {
1114 tcg_gen_divu_i32(t0, t0, t1);
1115 }
1116 if (compute_ov) {
1117 tcg_gen_movi_tl(cpu_ov, 0);
1118 }
1119 tcg_gen_br(l2);
1120 gen_set_label(l1);
1121 if (sign) {
1122 tcg_gen_sari_i32(t0, t0, 31);
1123 } else {
1124 tcg_gen_movi_i32(t0, 0);
1125 }
1126 if (compute_ov) {
1127 tcg_gen_movi_tl(cpu_ov, 1);
1128 tcg_gen_movi_tl(cpu_so, 1);
1129 }
1130 gen_set_label(l2);
1131 tcg_gen_extu_i32_tl(ret, t0);
1132 tcg_temp_free_i32(t0);
1133 tcg_temp_free_i32(t1);
1134 if (unlikely(Rc(ctx->opcode) != 0))
1135 gen_set_Rc0(ctx, ret);
1136 }
1137 /* Div functions */
1138 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1139 static void glue(gen_, name)(DisasContext *ctx) \
1140 { \
1141 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1142 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1143 sign, compute_ov); \
1144 }
1145 /* divwu divwu. divwuo divwuo. */
1146 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1147 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1148 /* divw divw. divwo divwo. */
1149 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1150 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1151
1152 /* div[wd]eu[o][.] */
1153 #define GEN_DIVE(name, hlpr, compute_ov) \
1154 static void gen_##name(DisasContext *ctx) \
1155 { \
1156 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1157 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1158 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1159 tcg_temp_free_i32(t0); \
1160 if (unlikely(Rc(ctx->opcode) != 0)) { \
1161 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1162 } \
1163 }
1164
1165 GEN_DIVE(divweu, divweu, 0);
1166 GEN_DIVE(divweuo, divweu, 1);
1167 GEN_DIVE(divwe, divwe, 0);
1168 GEN_DIVE(divweo, divwe, 1);
1169
1170 #if defined(TARGET_PPC64)
1171 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1172 TCGv arg2, int sign, int compute_ov)
1173 {
1174 TCGLabel *l1 = gen_new_label();
1175 TCGLabel *l2 = gen_new_label();
1176
1177 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1178 if (sign) {
1179 TCGLabel *l3 = gen_new_label();
1180 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1181 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1182 gen_set_label(l3);
1183 tcg_gen_div_i64(ret, arg1, arg2);
1184 } else {
1185 tcg_gen_divu_i64(ret, arg1, arg2);
1186 }
1187 if (compute_ov) {
1188 tcg_gen_movi_tl(cpu_ov, 0);
1189 }
1190 tcg_gen_br(l2);
1191 gen_set_label(l1);
1192 if (sign) {
1193 tcg_gen_sari_i64(ret, arg1, 63);
1194 } else {
1195 tcg_gen_movi_i64(ret, 0);
1196 }
1197 if (compute_ov) {
1198 tcg_gen_movi_tl(cpu_ov, 1);
1199 tcg_gen_movi_tl(cpu_so, 1);
1200 }
1201 gen_set_label(l2);
1202 if (unlikely(Rc(ctx->opcode) != 0))
1203 gen_set_Rc0(ctx, ret);
1204 }
1205 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1206 static void glue(gen_, name)(DisasContext *ctx) \
1207 { \
1208 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1209 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1210 sign, compute_ov); \
1211 }
1212 /* divwu divwu. divwuo divwuo. */
1213 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1214 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1215 /* divw divw. divwo divwo. */
1216 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1217 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1218
1219 GEN_DIVE(divdeu, divdeu, 0);
1220 GEN_DIVE(divdeuo, divdeu, 1);
1221 GEN_DIVE(divde, divde, 0);
1222 GEN_DIVE(divdeo, divde, 1);
1223 #endif
1224
1225 static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
1226 TCGv arg2, int sign)
1227 {
1228 TCGv_i32 t0 = tcg_temp_new_i32();
1229 TCGv_i32 t1 = tcg_temp_new_i32();
1230
1231 tcg_gen_trunc_tl_i32(t0, arg1);
1232 tcg_gen_trunc_tl_i32(t1, arg2);
1233 if (sign) {
1234 TCGv_i32 t2 = tcg_temp_new_i32();
1235 TCGv_i32 t3 = tcg_temp_new_i32();
1236 tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN);
1237 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1);
1238 tcg_gen_and_i32(t2, t2, t3);
1239 tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0);
1240 tcg_gen_or_i32(t2, t2, t3);
1241 tcg_gen_movi_i32(t3, 0);
1242 tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1);
1243 tcg_gen_rem_i32(t3, t0, t1);
1244 tcg_gen_ext_i32_tl(ret, t3);
1245 tcg_temp_free_i32(t2);
1246 tcg_temp_free_i32(t3);
1247 } else {
1248 TCGv_i32 t2 = tcg_const_i32(1);
1249 TCGv_i32 t3 = tcg_const_i32(0);
1250 tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
1251 tcg_gen_remu_i32(t3, t0, t1);
1252 tcg_gen_extu_i32_tl(ret, t3);
1253 tcg_temp_free_i32(t2);
1254 tcg_temp_free_i32(t3);
1255 }
1256 tcg_temp_free_i32(t0);
1257 tcg_temp_free_i32(t1);
1258 }
1259
1260 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1261 static void glue(gen_, name)(DisasContext *ctx) \
1262 { \
1263 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1264 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1265 sign); \
1266 }
1267
1268 GEN_INT_ARITH_MODW(moduw, 0x08, 0);
1269 GEN_INT_ARITH_MODW(modsw, 0x18, 1);
1270
1271 #if defined(TARGET_PPC64)
1272 static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
1273 TCGv arg2, int sign)
1274 {
1275 TCGv_i64 t0 = tcg_temp_new_i64();
1276 TCGv_i64 t1 = tcg_temp_new_i64();
1277
1278 tcg_gen_mov_i64(t0, arg1);
1279 tcg_gen_mov_i64(t1, arg2);
1280 if (sign) {
1281 TCGv_i64 t2 = tcg_temp_new_i64();
1282 TCGv_i64 t3 = tcg_temp_new_i64();
1283 tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN);
1284 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1);
1285 tcg_gen_and_i64(t2, t2, t3);
1286 tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0);
1287 tcg_gen_or_i64(t2, t2, t3);
1288 tcg_gen_movi_i64(t3, 0);
1289 tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
1290 tcg_gen_rem_i64(ret, t0, t1);
1291 tcg_temp_free_i64(t2);
1292 tcg_temp_free_i64(t3);
1293 } else {
1294 TCGv_i64 t2 = tcg_const_i64(1);
1295 TCGv_i64 t3 = tcg_const_i64(0);
1296 tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
1297 tcg_gen_remu_i64(ret, t0, t1);
1298 tcg_temp_free_i64(t2);
1299 tcg_temp_free_i64(t3);
1300 }
1301 tcg_temp_free_i64(t0);
1302 tcg_temp_free_i64(t1);
1303 }
1304
1305 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1306 static void glue(gen_, name)(DisasContext *ctx) \
1307 { \
1308 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1309 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1310 sign); \
1311 }
1312
1313 GEN_INT_ARITH_MODD(modud, 0x08, 0);
1314 GEN_INT_ARITH_MODD(modsd, 0x18, 1);
1315 #endif
1316
1317 /* mulhw mulhw. */
1318 static void gen_mulhw(DisasContext *ctx)
1319 {
1320 TCGv_i32 t0 = tcg_temp_new_i32();
1321 TCGv_i32 t1 = tcg_temp_new_i32();
1322
1323 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1324 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1325 tcg_gen_muls2_i32(t0, t1, t0, t1);
1326 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1327 tcg_temp_free_i32(t0);
1328 tcg_temp_free_i32(t1);
1329 if (unlikely(Rc(ctx->opcode) != 0))
1330 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1331 }
1332
1333 /* mulhwu mulhwu. */
1334 static void gen_mulhwu(DisasContext *ctx)
1335 {
1336 TCGv_i32 t0 = tcg_temp_new_i32();
1337 TCGv_i32 t1 = tcg_temp_new_i32();
1338
1339 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1340 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1341 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1342 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1343 tcg_temp_free_i32(t0);
1344 tcg_temp_free_i32(t1);
1345 if (unlikely(Rc(ctx->opcode) != 0))
1346 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1347 }
1348
1349 /* mullw mullw. */
1350 static void gen_mullw(DisasContext *ctx)
1351 {
1352 #if defined(TARGET_PPC64)
1353 TCGv_i64 t0, t1;
1354 t0 = tcg_temp_new_i64();
1355 t1 = tcg_temp_new_i64();
1356 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1357 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1358 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1359 tcg_temp_free(t0);
1360 tcg_temp_free(t1);
1361 #else
1362 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1363 cpu_gpr[rB(ctx->opcode)]);
1364 #endif
1365 if (unlikely(Rc(ctx->opcode) != 0))
1366 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1367 }
1368
1369 /* mullwo mullwo. */
1370 static void gen_mullwo(DisasContext *ctx)
1371 {
1372 TCGv_i32 t0 = tcg_temp_new_i32();
1373 TCGv_i32 t1 = tcg_temp_new_i32();
1374
1375 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1376 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1377 tcg_gen_muls2_i32(t0, t1, t0, t1);
1378 #if defined(TARGET_PPC64)
1379 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1380 #else
1381 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1382 #endif
1383
1384 tcg_gen_sari_i32(t0, t0, 31);
1385 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1386 tcg_gen_extu_i32_tl(cpu_ov, t0);
1387 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1388
1389 tcg_temp_free_i32(t0);
1390 tcg_temp_free_i32(t1);
1391 if (unlikely(Rc(ctx->opcode) != 0))
1392 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1393 }
1394
1395 /* mulli */
1396 static void gen_mulli(DisasContext *ctx)
1397 {
1398 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1399 SIMM(ctx->opcode));
1400 }
1401
1402 #if defined(TARGET_PPC64)
1403 /* mulhd mulhd. */
1404 static void gen_mulhd(DisasContext *ctx)
1405 {
1406 TCGv lo = tcg_temp_new();
1407 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1408 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1409 tcg_temp_free(lo);
1410 if (unlikely(Rc(ctx->opcode) != 0)) {
1411 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1412 }
1413 }
1414
1415 /* mulhdu mulhdu. */
1416 static void gen_mulhdu(DisasContext *ctx)
1417 {
1418 TCGv lo = tcg_temp_new();
1419 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1420 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1421 tcg_temp_free(lo);
1422 if (unlikely(Rc(ctx->opcode) != 0)) {
1423 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1424 }
1425 }
1426
1427 /* mulld mulld. */
1428 static void gen_mulld(DisasContext *ctx)
1429 {
1430 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1431 cpu_gpr[rB(ctx->opcode)]);
1432 if (unlikely(Rc(ctx->opcode) != 0))
1433 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1434 }
1435
1436 /* mulldo mulldo. */
1437 static void gen_mulldo(DisasContext *ctx)
1438 {
1439 TCGv_i64 t0 = tcg_temp_new_i64();
1440 TCGv_i64 t1 = tcg_temp_new_i64();
1441
1442 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1443 cpu_gpr[rB(ctx->opcode)]);
1444 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1445
1446 tcg_gen_sari_i64(t0, t0, 63);
1447 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1448 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1449
1450 tcg_temp_free_i64(t0);
1451 tcg_temp_free_i64(t1);
1452
1453 if (unlikely(Rc(ctx->opcode) != 0)) {
1454 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1455 }
1456 }
1457 #endif
1458
1459 /* Common subf function */
1460 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1461 TCGv arg2, bool add_ca, bool compute_ca,
1462 bool compute_ov, bool compute_rc0)
1463 {
1464 TCGv t0 = ret;
1465
1466 if (compute_ca || compute_ov) {
1467 t0 = tcg_temp_new();
1468 }
1469
1470 if (compute_ca) {
1471 /* dest = ~arg1 + arg2 [+ ca]. */
1472 if (NARROW_MODE(ctx)) {
1473 /* Caution: a non-obvious corner case of the spec is that we
1474 must produce the *entire* 64-bit addition, but produce the
1475 carry into bit 32. */
1476 TCGv inv1 = tcg_temp_new();
1477 TCGv t1 = tcg_temp_new();
1478 tcg_gen_not_tl(inv1, arg1);
1479 if (add_ca) {
1480 tcg_gen_add_tl(t0, arg2, cpu_ca);
1481 } else {
1482 tcg_gen_addi_tl(t0, arg2, 1);
1483 }
1484 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1485 tcg_gen_add_tl(t0, t0, inv1);
1486 tcg_temp_free(inv1);
1487 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1488 tcg_temp_free(t1);
1489 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1490 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1491 } else if (add_ca) {
1492 TCGv zero, inv1 = tcg_temp_new();
1493 tcg_gen_not_tl(inv1, arg1);
1494 zero = tcg_const_tl(0);
1495 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1496 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1497 tcg_temp_free(zero);
1498 tcg_temp_free(inv1);
1499 } else {
1500 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1501 tcg_gen_sub_tl(t0, arg2, arg1);
1502 }
1503 } else if (add_ca) {
1504 /* Since we're ignoring carry-out, we can simplify the
1505 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1506 tcg_gen_sub_tl(t0, arg2, arg1);
1507 tcg_gen_add_tl(t0, t0, cpu_ca);
1508 tcg_gen_subi_tl(t0, t0, 1);
1509 } else {
1510 tcg_gen_sub_tl(t0, arg2, arg1);
1511 }
1512
1513 if (compute_ov) {
1514 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1515 }
1516 if (unlikely(compute_rc0)) {
1517 gen_set_Rc0(ctx, t0);
1518 }
1519
1520 if (!TCGV_EQUAL(t0, ret)) {
1521 tcg_gen_mov_tl(ret, t0);
1522 tcg_temp_free(t0);
1523 }
1524 }
1525 /* Sub functions with Two operands functions */
1526 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1527 static void glue(gen_, name)(DisasContext *ctx) \
1528 { \
1529 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1530 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1531 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1532 }
1533 /* Sub functions with one operand and one immediate */
1534 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1535 add_ca, compute_ca, compute_ov) \
1536 static void glue(gen_, name)(DisasContext *ctx) \
1537 { \
1538 TCGv t0 = tcg_const_tl(const_val); \
1539 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1540 cpu_gpr[rA(ctx->opcode)], t0, \
1541 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1542 tcg_temp_free(t0); \
1543 }
1544 /* subf subf. subfo subfo. */
1545 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1546 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1547 /* subfc subfc. subfco subfco. */
1548 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1549 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1550 /* subfe subfe. subfeo subfo. */
1551 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1552 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1553 /* subfme subfme. subfmeo subfmeo. */
1554 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1555 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1556 /* subfze subfze. subfzeo subfzeo.*/
1557 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1558 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1559
1560 /* subfic */
1561 static void gen_subfic(DisasContext *ctx)
1562 {
1563 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1564 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1565 c, 0, 1, 0, 0);
1566 tcg_temp_free(c);
1567 }
1568
1569 /* neg neg. nego nego. */
1570 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1571 {
1572 TCGv zero = tcg_const_tl(0);
1573 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1574 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1575 tcg_temp_free(zero);
1576 }
1577
1578 static void gen_neg(DisasContext *ctx)
1579 {
1580 gen_op_arith_neg(ctx, 0);
1581 }
1582
1583 static void gen_nego(DisasContext *ctx)
1584 {
1585 gen_op_arith_neg(ctx, 1);
1586 }
1587
1588 /*** Integer logical ***/
1589 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1590 static void glue(gen_, name)(DisasContext *ctx) \
1591 { \
1592 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1593 cpu_gpr[rB(ctx->opcode)]); \
1594 if (unlikely(Rc(ctx->opcode) != 0)) \
1595 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1596 }
1597
1598 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1599 static void glue(gen_, name)(DisasContext *ctx) \
1600 { \
1601 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1602 if (unlikely(Rc(ctx->opcode) != 0)) \
1603 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1604 }
1605
1606 /* and & and. */
1607 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1608 /* andc & andc. */
1609 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1610
1611 /* andi. */
1612 static void gen_andi_(DisasContext *ctx)
1613 {
1614 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1615 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1616 }
1617
1618 /* andis. */
1619 static void gen_andis_(DisasContext *ctx)
1620 {
1621 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1622 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1623 }
1624
1625 /* cntlzw */
1626 static void gen_cntlzw(DisasContext *ctx)
1627 {
1628 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1629 if (unlikely(Rc(ctx->opcode) != 0))
1630 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1631 }
1632
1633 /* cnttzw */
1634 static void gen_cnttzw(DisasContext *ctx)
1635 {
1636 gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1637 if (unlikely(Rc(ctx->opcode) != 0)) {
1638 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1639 }
1640 }
1641
1642 /* eqv & eqv. */
1643 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1644 /* extsb & extsb. */
1645 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1646 /* extsh & extsh. */
1647 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1648 /* nand & nand. */
1649 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1650 /* nor & nor. */
1651 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1652
1653 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1654 static void gen_pause(DisasContext *ctx)
1655 {
1656 TCGv_i32 t0 = tcg_const_i32(0);
1657 tcg_gen_st_i32(t0, cpu_env,
1658 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1659 tcg_temp_free_i32(t0);
1660
1661 /* Stop translation, this gives other CPUs a chance to run */
1662 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
1663 }
1664 #endif /* defined(TARGET_PPC64) */
1665
1666 /* or & or. */
1667 static void gen_or(DisasContext *ctx)
1668 {
1669 int rs, ra, rb;
1670
1671 rs = rS(ctx->opcode);
1672 ra = rA(ctx->opcode);
1673 rb = rB(ctx->opcode);
1674 /* Optimisation for mr. ri case */
1675 if (rs != ra || rs != rb) {
1676 if (rs != rb)
1677 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1678 else
1679 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1680 if (unlikely(Rc(ctx->opcode) != 0))
1681 gen_set_Rc0(ctx, cpu_gpr[ra]);
1682 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1683 gen_set_Rc0(ctx, cpu_gpr[rs]);
1684 #if defined(TARGET_PPC64)
1685 } else if (rs != 0) { /* 0 is nop */
1686 int prio = 0;
1687
1688 switch (rs) {
1689 case 1:
1690 /* Set process priority to low */
1691 prio = 2;
1692 break;
1693 case 6:
1694 /* Set process priority to medium-low */
1695 prio = 3;
1696 break;
1697 case 2:
1698 /* Set process priority to normal */
1699 prio = 4;
1700 break;
1701 #if !defined(CONFIG_USER_ONLY)
1702 case 31:
1703 if (!ctx->pr) {
1704 /* Set process priority to very low */
1705 prio = 1;
1706 }
1707 break;
1708 case 5:
1709 if (!ctx->pr) {
1710 /* Set process priority to medium-hight */
1711 prio = 5;
1712 }
1713 break;
1714 case 3:
1715 if (!ctx->pr) {
1716 /* Set process priority to high */
1717 prio = 6;
1718 }
1719 break;
1720 case 7:
1721 if (ctx->hv && !ctx->pr) {
1722 /* Set process priority to very high */
1723 prio = 7;
1724 }
1725 break;
1726 #endif
1727 default:
1728 break;
1729 }
1730 if (prio) {
1731 TCGv t0 = tcg_temp_new();
1732 gen_load_spr(t0, SPR_PPR);
1733 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1734 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1735 gen_store_spr(SPR_PPR, t0);
1736 tcg_temp_free(t0);
1737 }
1738 #if !defined(CONFIG_USER_ONLY)
1739 /* Pause out of TCG otherwise spin loops with smt_low eat too much
1740 * CPU and the kernel hangs. This applies to all encodings other
1741 * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30),
1742 * and all currently undefined.
1743 */
1744 gen_pause(ctx);
1745 #endif
1746 #endif
1747 }
1748 }
1749 /* orc & orc. */
1750 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1751
1752 /* xor & xor. */
1753 static void gen_xor(DisasContext *ctx)
1754 {
1755 /* Optimisation for "set to zero" case */
1756 if (rS(ctx->opcode) != rB(ctx->opcode))
1757 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1758 else
1759 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1760 if (unlikely(Rc(ctx->opcode) != 0))
1761 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1762 }
1763
1764 /* ori */
1765 static void gen_ori(DisasContext *ctx)
1766 {
1767 target_ulong uimm = UIMM(ctx->opcode);
1768
1769 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1770 return;
1771 }
1772 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1773 }
1774
1775 /* oris */
1776 static void gen_oris(DisasContext *ctx)
1777 {
1778 target_ulong uimm = UIMM(ctx->opcode);
1779
1780 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1781 /* NOP */
1782 return;
1783 }
1784 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1785 }
1786
1787 /* xori */
1788 static void gen_xori(DisasContext *ctx)
1789 {
1790 target_ulong uimm = UIMM(ctx->opcode);
1791
1792 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1793 /* NOP */
1794 return;
1795 }
1796 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1797 }
1798
1799 /* xoris */
1800 static void gen_xoris(DisasContext *ctx)
1801 {
1802 target_ulong uimm = UIMM(ctx->opcode);
1803
1804 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1805 /* NOP */
1806 return;
1807 }
1808 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1809 }
1810
1811 /* popcntb : PowerPC 2.03 specification */
1812 static void gen_popcntb(DisasContext *ctx)
1813 {
1814 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1815 }
1816
1817 static void gen_popcntw(DisasContext *ctx)
1818 {
1819 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1820 }
1821
1822 #if defined(TARGET_PPC64)
1823 /* popcntd: PowerPC 2.06 specification */
1824 static void gen_popcntd(DisasContext *ctx)
1825 {
1826 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1827 }
1828 #endif
1829
1830 /* prtyw: PowerPC 2.05 specification */
1831 static void gen_prtyw(DisasContext *ctx)
1832 {
1833 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1834 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1835 TCGv t0 = tcg_temp_new();
1836 tcg_gen_shri_tl(t0, rs, 16);
1837 tcg_gen_xor_tl(ra, rs, t0);
1838 tcg_gen_shri_tl(t0, ra, 8);
1839 tcg_gen_xor_tl(ra, ra, t0);
1840 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1841 tcg_temp_free(t0);
1842 }
1843
1844 #if defined(TARGET_PPC64)
1845 /* prtyd: PowerPC 2.05 specification */
1846 static void gen_prtyd(DisasContext *ctx)
1847 {
1848 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1849 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1850 TCGv t0 = tcg_temp_new();
1851 tcg_gen_shri_tl(t0, rs, 32);
1852 tcg_gen_xor_tl(ra, rs, t0);
1853 tcg_gen_shri_tl(t0, ra, 16);
1854 tcg_gen_xor_tl(ra, ra, t0);
1855 tcg_gen_shri_tl(t0, ra, 8);
1856 tcg_gen_xor_tl(ra, ra, t0);
1857 tcg_gen_andi_tl(ra, ra, 1);
1858 tcg_temp_free(t0);
1859 }
1860 #endif
1861
1862 #if defined(TARGET_PPC64)
1863 /* bpermd */
1864 static void gen_bpermd(DisasContext *ctx)
1865 {
1866 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1867 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1868 }
1869 #endif
1870
1871 #if defined(TARGET_PPC64)
1872 /* extsw & extsw. */
1873 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1874
1875 /* cntlzd */
1876 static void gen_cntlzd(DisasContext *ctx)
1877 {
1878 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1879 if (unlikely(Rc(ctx->opcode) != 0))
1880 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1881 }
1882
1883 /* cnttzd */
1884 static void gen_cnttzd(DisasContext *ctx)
1885 {
1886 gen_helper_cnttzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1887 if (unlikely(Rc(ctx->opcode) != 0)) {
1888 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1889 }
1890 }
1891 #endif
1892
1893 /*** Integer rotate ***/
1894
1895 /* rlwimi & rlwimi. */
1896 static void gen_rlwimi(DisasContext *ctx)
1897 {
1898 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1899 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1900 uint32_t sh = SH(ctx->opcode);
1901 uint32_t mb = MB(ctx->opcode);
1902 uint32_t me = ME(ctx->opcode);
1903
1904 if (sh == (31-me) && mb <= me) {
1905 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1906 } else {
1907 target_ulong mask;
1908 TCGv t1;
1909
1910 #if defined(TARGET_PPC64)
1911 mb += 32;
1912 me += 32;
1913 #endif
1914 mask = MASK(mb, me);
1915
1916 t1 = tcg_temp_new();
1917 if (mask <= 0xffffffffu) {
1918 TCGv_i32 t0 = tcg_temp_new_i32();
1919 tcg_gen_trunc_tl_i32(t0, t_rs);
1920 tcg_gen_rotli_i32(t0, t0, sh);
1921 tcg_gen_extu_i32_tl(t1, t0);
1922 tcg_temp_free_i32(t0);
1923 } else {
1924 #if defined(TARGET_PPC64)
1925 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1926 tcg_gen_rotli_i64(t1, t1, sh);
1927 #else
1928 g_assert_not_reached();
1929 #endif
1930 }
1931
1932 tcg_gen_andi_tl(t1, t1, mask);
1933 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1934 tcg_gen_or_tl(t_ra, t_ra, t1);
1935 tcg_temp_free(t1);
1936 }
1937 if (unlikely(Rc(ctx->opcode) != 0)) {
1938 gen_set_Rc0(ctx, t_ra);
1939 }
1940 }
1941
1942 /* rlwinm & rlwinm. */
1943 static void gen_rlwinm(DisasContext *ctx)
1944 {
1945 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1946 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1947 uint32_t sh = SH(ctx->opcode);
1948 uint32_t mb = MB(ctx->opcode);
1949 uint32_t me = ME(ctx->opcode);
1950
1951 if (mb == 0 && me == (31 - sh)) {
1952 tcg_gen_shli_tl(t_ra, t_rs, sh);
1953 tcg_gen_ext32u_tl(t_ra, t_ra);
1954 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1955 tcg_gen_ext32u_tl(t_ra, t_rs);
1956 tcg_gen_shri_tl(t_ra, t_ra, mb);
1957 } else {
1958 target_ulong mask;
1959 #if defined(TARGET_PPC64)
1960 mb += 32;
1961 me += 32;
1962 #endif
1963 mask = MASK(mb, me);
1964
1965 if (mask <= 0xffffffffu) {
1966 TCGv_i32 t0 = tcg_temp_new_i32();
1967 tcg_gen_trunc_tl_i32(t0, t_rs);
1968 tcg_gen_rotli_i32(t0, t0, sh);
1969 tcg_gen_andi_i32(t0, t0, mask);
1970 tcg_gen_extu_i32_tl(t_ra, t0);
1971 tcg_temp_free_i32(t0);
1972 } else {
1973 #if defined(TARGET_PPC64)
1974 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1975 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1976 tcg_gen_andi_i64(t_ra, t_ra, mask);
1977 #else
1978 g_assert_not_reached();
1979 #endif
1980 }
1981 }
1982 if (unlikely(Rc(ctx->opcode) != 0)) {
1983 gen_set_Rc0(ctx, t_ra);
1984 }
1985 }
1986
1987 /* rlwnm & rlwnm. */
1988 static void gen_rlwnm(DisasContext *ctx)
1989 {
1990 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1991 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1992 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1993 uint32_t mb = MB(ctx->opcode);
1994 uint32_t me = ME(ctx->opcode);
1995 target_ulong mask;
1996
1997 #if defined(TARGET_PPC64)
1998 mb += 32;
1999 me += 32;
2000 #endif
2001 mask = MASK(mb, me);
2002
2003 if (mask <= 0xffffffffu) {
2004 TCGv_i32 t0 = tcg_temp_new_i32();
2005 TCGv_i32 t1 = tcg_temp_new_i32();
2006 tcg_gen_trunc_tl_i32(t0, t_rb);
2007 tcg_gen_trunc_tl_i32(t1, t_rs);
2008 tcg_gen_andi_i32(t0, t0, 0x1f);
2009 tcg_gen_rotl_i32(t1, t1, t0);
2010 tcg_gen_extu_i32_tl(t_ra, t1);
2011 tcg_temp_free_i32(t0);
2012 tcg_temp_free_i32(t1);
2013 } else {
2014 #if defined(TARGET_PPC64)
2015 TCGv_i64 t0 = tcg_temp_new_i64();
2016 tcg_gen_andi_i64(t0, t_rb, 0x1f);
2017 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
2018 tcg_gen_rotl_i64(t_ra, t_ra, t0);
2019 tcg_temp_free_i64(t0);
2020 #else
2021 g_assert_not_reached();
2022 #endif
2023 }
2024
2025 tcg_gen_andi_tl(t_ra, t_ra, mask);
2026
2027 if (unlikely(Rc(ctx->opcode) != 0)) {
2028 gen_set_Rc0(ctx, t_ra);
2029 }
2030 }
2031
2032 #if defined(TARGET_PPC64)
2033 #define GEN_PPC64_R2(name, opc1, opc2) \
2034 static void glue(gen_, name##0)(DisasContext *ctx) \
2035 { \
2036 gen_##name(ctx, 0); \
2037 } \
2038 \
2039 static void glue(gen_, name##1)(DisasContext *ctx) \
2040 { \
2041 gen_##name(ctx, 1); \
2042 }
2043 #define GEN_PPC64_R4(name, opc1, opc2) \
2044 static void glue(gen_, name##0)(DisasContext *ctx) \
2045 { \
2046 gen_##name(ctx, 0, 0); \
2047 } \
2048 \
2049 static void glue(gen_, name##1)(DisasContext *ctx) \
2050 { \
2051 gen_##name(ctx, 0, 1); \
2052 } \
2053 \
2054 static void glue(gen_, name##2)(DisasContext *ctx) \
2055 { \
2056 gen_##name(ctx, 1, 0); \
2057 } \
2058 \
2059 static void glue(gen_, name##3)(DisasContext *ctx) \
2060 { \
2061 gen_##name(ctx, 1, 1); \
2062 }
2063
2064 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
2065 {
2066 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2067 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2068
2069 if (sh != 0 && mb == 0 && me == (63 - sh)) {
2070 tcg_gen_shli_tl(t_ra, t_rs, sh);
2071 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
2072 tcg_gen_shri_tl(t_ra, t_rs, mb);
2073 } else {
2074 tcg_gen_rotli_tl(t_ra, t_rs, sh);
2075 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2076 }
2077 if (unlikely(Rc(ctx->opcode) != 0)) {
2078 gen_set_Rc0(ctx, t_ra);
2079 }
2080 }
2081
2082 /* rldicl - rldicl. */
2083 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
2084 {
2085 uint32_t sh, mb;
2086
2087 sh = SH(ctx->opcode) | (shn << 5);
2088 mb = MB(ctx->opcode) | (mbn << 5);
2089 gen_rldinm(ctx, mb, 63, sh);
2090 }
2091 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
2092
2093 /* rldicr - rldicr. */
2094 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
2095 {
2096 uint32_t sh, me;
2097
2098 sh = SH(ctx->opcode) | (shn << 5);
2099 me = MB(ctx->opcode) | (men << 5);
2100 gen_rldinm(ctx, 0, me, sh);
2101 }
2102 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
2103
2104 /* rldic - rldic. */
2105 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
2106 {
2107 uint32_t sh, mb;
2108
2109 sh = SH(ctx->opcode) | (shn << 5);
2110 mb = MB(ctx->opcode) | (mbn << 5);
2111 gen_rldinm(ctx, mb, 63 - sh, sh);
2112 }
2113 GEN_PPC64_R4(rldic, 0x1E, 0x04);
2114
2115 static void gen_rldnm(DisasContext *ctx, int mb, int me)
2116 {
2117 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2118 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2119 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
2120 TCGv t0;
2121
2122 t0 = tcg_temp_new();
2123 tcg_gen_andi_tl(t0, t_rb, 0x3f);
2124 tcg_gen_rotl_tl(t_ra, t_rs, t0);
2125 tcg_temp_free(t0);
2126
2127 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
2128 if (unlikely(Rc(ctx->opcode) != 0)) {
2129 gen_set_Rc0(ctx, t_ra);
2130 }
2131 }
2132
2133 /* rldcl - rldcl. */
2134 static inline void gen_rldcl(DisasContext *ctx, int mbn)
2135 {
2136 uint32_t mb;
2137
2138 mb = MB(ctx->opcode) | (mbn << 5);
2139 gen_rldnm(ctx, mb, 63);
2140 }
2141 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
2142
2143 /* rldcr - rldcr. */
2144 static inline void gen_rldcr(DisasContext *ctx, int men)
2145 {
2146 uint32_t me;
2147
2148 me = MB(ctx->opcode) | (men << 5);
2149 gen_rldnm(ctx, 0, me);
2150 }
2151 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
2152
2153 /* rldimi - rldimi. */
2154 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
2155 {
2156 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
2157 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
2158 uint32_t sh = SH(ctx->opcode) | (shn << 5);
2159 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
2160 uint32_t me = 63 - sh;
2161
2162 if (mb <= me) {
2163 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
2164 } else {
2165 target_ulong mask = MASK(mb, me);
2166 TCGv t1 = tcg_temp_new();
2167
2168 tcg_gen_rotli_tl(t1, t_rs, sh);
2169 tcg_gen_andi_tl(t1, t1, mask);
2170 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
2171 tcg_gen_or_tl(t_ra, t_ra, t1);
2172 tcg_temp_free(t1);
2173 }
2174 if (unlikely(Rc(ctx->opcode) != 0)) {
2175 gen_set_Rc0(ctx, t_ra);
2176 }
2177 }
2178 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
2179 #endif
2180
2181 /*** Integer shift ***/
2182
2183 /* slw & slw. */
2184 static void gen_slw(DisasContext *ctx)
2185 {
2186 TCGv t0, t1;
2187
2188 t0 = tcg_temp_new();
2189 /* AND rS with a mask that is 0 when rB >= 0x20 */
2190 #if defined(TARGET_PPC64)
2191 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2192 tcg_gen_sari_tl(t0, t0, 0x3f);
2193 #else
2194 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2195 tcg_gen_sari_tl(t0, t0, 0x1f);
2196 #endif
2197 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2198 t1 = tcg_temp_new();
2199 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2200 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2201 tcg_temp_free(t1);
2202 tcg_temp_free(t0);
2203 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
2204 if (unlikely(Rc(ctx->opcode) != 0))
2205 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2206 }
2207
2208 /* sraw & sraw. */
2209 static void gen_sraw(DisasContext *ctx)
2210 {
2211 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
2212 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2213 if (unlikely(Rc(ctx->opcode) != 0))
2214 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2215 }
2216
2217 /* srawi & srawi. */
2218 static void gen_srawi(DisasContext *ctx)
2219 {
2220 int sh = SH(ctx->opcode);
2221 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2222 TCGv src = cpu_gpr[rS(ctx->opcode)];
2223 if (sh == 0) {
2224 tcg_gen_ext32s_tl(dst, src);
2225 tcg_gen_movi_tl(cpu_ca, 0);
2226 } else {
2227 TCGv t0;
2228 tcg_gen_ext32s_tl(dst, src);
2229 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
2230 t0 = tcg_temp_new();
2231 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
2232 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2233 tcg_temp_free(t0);
2234 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2235 tcg_gen_sari_tl(dst, dst, sh);
2236 }
2237 if (unlikely(Rc(ctx->opcode) != 0)) {
2238 gen_set_Rc0(ctx, dst);
2239 }
2240 }
2241
2242 /* srw & srw. */
2243 static void gen_srw(DisasContext *ctx)
2244 {
2245 TCGv t0, t1;
2246
2247 t0 = tcg_temp_new();
2248 /* AND rS with a mask that is 0 when rB >= 0x20 */
2249 #if defined(TARGET_PPC64)
2250 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
2251 tcg_gen_sari_tl(t0, t0, 0x3f);
2252 #else
2253 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
2254 tcg_gen_sari_tl(t0, t0, 0x1f);
2255 #endif
2256 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2257 tcg_gen_ext32u_tl(t0, t0);
2258 t1 = tcg_temp_new();
2259 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
2260 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2261 tcg_temp_free(t1);
2262 tcg_temp_free(t0);
2263 if (unlikely(Rc(ctx->opcode) != 0))
2264 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2265 }
2266
2267 #if defined(TARGET_PPC64)
2268 /* sld & sld. */
2269 static void gen_sld(DisasContext *ctx)
2270 {
2271 TCGv t0, t1;
2272
2273 t0 = tcg_temp_new();
2274 /* AND rS with a mask that is 0 when rB >= 0x40 */
2275 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2276 tcg_gen_sari_tl(t0, t0, 0x3f);
2277 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2278 t1 = tcg_temp_new();
2279 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2280 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2281 tcg_temp_free(t1);
2282 tcg_temp_free(t0);
2283 if (unlikely(Rc(ctx->opcode) != 0))
2284 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2285 }
2286
2287 /* srad & srad. */
2288 static void gen_srad(DisasContext *ctx)
2289 {
2290 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2291 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2292 if (unlikely(Rc(ctx->opcode) != 0))
2293 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2294 }
2295 /* sradi & sradi. */
2296 static inline void gen_sradi(DisasContext *ctx, int n)
2297 {
2298 int sh = SH(ctx->opcode) + (n << 5);
2299 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2300 TCGv src = cpu_gpr[rS(ctx->opcode)];
2301 if (sh == 0) {
2302 tcg_gen_mov_tl(dst, src);
2303 tcg_gen_movi_tl(cpu_ca, 0);
2304 } else {
2305 TCGv t0;
2306 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2307 t0 = tcg_temp_new();
2308 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2309 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2310 tcg_temp_free(t0);
2311 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2312 tcg_gen_sari_tl(dst, src, sh);
2313 }
2314 if (unlikely(Rc(ctx->opcode) != 0)) {
2315 gen_set_Rc0(ctx, dst);
2316 }
2317 }
2318
2319 static void gen_sradi0(DisasContext *ctx)
2320 {
2321 gen_sradi(ctx, 0);
2322 }
2323
2324 static void gen_sradi1(DisasContext *ctx)
2325 {
2326 gen_sradi(ctx, 1);
2327 }
2328
2329 /* srd & srd. */
2330 static void gen_srd(DisasContext *ctx)
2331 {
2332 TCGv t0, t1;
2333
2334 t0 = tcg_temp_new();
2335 /* AND rS with a mask that is 0 when rB >= 0x40 */
2336 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2337 tcg_gen_sari_tl(t0, t0, 0x3f);
2338 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2339 t1 = tcg_temp_new();
2340 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2341 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2342 tcg_temp_free(t1);
2343 tcg_temp_free(t0);
2344 if (unlikely(Rc(ctx->opcode) != 0))
2345 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2346 }
2347 #endif
2348
2349 /*** Addressing modes ***/
2350 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2351 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2352 target_long maskl)
2353 {
2354 target_long simm = SIMM(ctx->opcode);
2355
2356 simm &= ~maskl;
2357 if (rA(ctx->opcode) == 0) {
2358 if (NARROW_MODE(ctx)) {
2359 simm = (uint32_t)simm;
2360 }
2361 tcg_gen_movi_tl(EA, simm);
2362 } else if (likely(simm != 0)) {
2363 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2364 if (NARROW_MODE(ctx)) {
2365 tcg_gen_ext32u_tl(EA, EA);
2366 }
2367 } else {
2368 if (NARROW_MODE(ctx)) {
2369 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2370 } else {
2371 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2372 }
2373 }
2374 }
2375
2376 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2377 {
2378 if (rA(ctx->opcode) == 0) {
2379 if (NARROW_MODE(ctx)) {
2380 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2381 } else {
2382 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2383 }
2384 } else {
2385 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2386 if (NARROW_MODE(ctx)) {
2387 tcg_gen_ext32u_tl(EA, EA);
2388 }
2389 }
2390 }
2391
2392 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2393 {
2394 if (rA(ctx->opcode) == 0) {
2395 tcg_gen_movi_tl(EA, 0);
2396 } else if (NARROW_MODE(ctx)) {
2397 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2398 } else {
2399 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2400 }
2401 }
2402
2403 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2404 target_long val)
2405 {
2406 tcg_gen_addi_tl(ret, arg1, val);
2407 if (NARROW_MODE(ctx)) {
2408 tcg_gen_ext32u_tl(ret, ret);
2409 }
2410 }
2411
2412 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2413 {
2414 TCGLabel *l1 = gen_new_label();
2415 TCGv t0 = tcg_temp_new();
2416 TCGv_i32 t1, t2;
2417 /* NIP cannot be restored if the memory exception comes from an helper */
2418 gen_update_nip(ctx, ctx->nip - 4);
2419 tcg_gen_andi_tl(t0, EA, mask);
2420 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2421 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2422 t2 = tcg_const_i32(0);
2423 gen_helper_raise_exception_err(cpu_env, t1, t2);
2424 tcg_temp_free_i32(t1);
2425 tcg_temp_free_i32(t2);
2426 gen_set_label(l1);
2427 tcg_temp_free(t0);
2428 }
2429
2430 /*** Integer load ***/
2431 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2432 {
2433 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2434 }
2435
2436 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2437 {
2438 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2439 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2440 }
2441
2442 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2443 {
2444 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2445 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2446 }
2447
2448 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2449 {
2450 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2451 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2452 }
2453
2454 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2455 {
2456 TCGv tmp = tcg_temp_new();
2457 gen_qemu_ld32u(ctx, tmp, addr);
2458 tcg_gen_extu_tl_i64(val, tmp);
2459 tcg_temp_free(tmp);
2460 }
2461
2462 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2463 {
2464 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2465 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2466 }
2467
2468 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2469 {
2470 TCGv tmp = tcg_temp_new();
2471 gen_qemu_ld32s(ctx, tmp, addr);
2472 tcg_gen_ext_tl_i64(val, tmp);
2473 tcg_temp_free(tmp);
2474 }
2475
2476 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2477 {
2478 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2479 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2480 }
2481
2482 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2483 {
2484 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2485 }
2486
2487 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2488 {
2489 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2490 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2491 }
2492
2493 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2494 {
2495 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2496 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2497 }
2498
2499 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2500 {
2501 TCGv tmp = tcg_temp_new();
2502 tcg_gen_trunc_i64_tl(tmp, val);
2503 gen_qemu_st32(ctx, tmp, addr);
2504 tcg_temp_free(tmp);
2505 }
2506
2507 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2508 {
2509 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2510 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2511 }
2512
2513 #define GEN_LD(name, ldop, opc, type) \
2514 static void glue(gen_, name)(DisasContext *ctx) \
2515 { \
2516 TCGv EA; \
2517 gen_set_access_type(ctx, ACCESS_INT); \
2518 EA = tcg_temp_new(); \
2519 gen_addr_imm_index(ctx, EA, 0); \
2520 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2521 tcg_temp_free(EA); \
2522 }
2523
2524 #define GEN_LDU(name, ldop, opc, type) \
2525 static void glue(gen_, name##u)(DisasContext *ctx) \
2526 { \
2527 TCGv EA; \
2528 if (unlikely(rA(ctx->opcode) == 0 || \
2529 rA(ctx->opcode) == rD(ctx->opcode))) { \
2530 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2531 return; \
2532 } \
2533 gen_set_access_type(ctx, ACCESS_INT); \
2534 EA = tcg_temp_new(); \
2535 if (type == PPC_64B) \
2536 gen_addr_imm_index(ctx, EA, 0x03); \
2537 else \
2538 gen_addr_imm_index(ctx, EA, 0); \
2539 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2540 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2541 tcg_temp_free(EA); \
2542 }
2543
2544 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2545 static void glue(gen_, name##ux)(DisasContext *ctx) \
2546 { \
2547 TCGv EA; \
2548 if (unlikely(rA(ctx->opcode) == 0 || \
2549 rA(ctx->opcode) == rD(ctx->opcode))) { \
2550 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2551 return; \
2552 } \
2553 gen_set_access_type(ctx, ACCESS_INT); \
2554 EA = tcg_temp_new(); \
2555 gen_addr_reg_index(ctx, EA); \
2556 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2557 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2558 tcg_temp_free(EA); \
2559 }
2560
2561 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2562 static void glue(gen_, name##x)(DisasContext *ctx) \
2563 { \
2564 TCGv EA; \
2565 chk; \
2566 gen_set_access_type(ctx, ACCESS_INT); \
2567 EA = tcg_temp_new(); \
2568 gen_addr_reg_index(ctx, EA); \
2569 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2570 tcg_temp_free(EA); \
2571 }
2572
2573 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2574 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2575
2576 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2577 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2578
2579 #define GEN_LDS(name, ldop, op, type) \
2580 GEN_LD(name, ldop, op | 0x20, type); \
2581 GEN_LDU(name, ldop, op | 0x21, type); \
2582 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2583 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2584
2585 /* lbz lbzu lbzux lbzx */
2586 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2587 /* lha lhau lhaux lhax */
2588 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2589 /* lhz lhzu lhzux lhzx */
2590 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2591 /* lwz lwzu lwzux lwzx */
2592 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2593 #if defined(TARGET_PPC64)
2594 /* lwaux */
2595 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2596 /* lwax */
2597 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2598 /* ldux */
2599 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2600 /* ldx */
2601 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2602
2603 /* CI load/store variants */
2604 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
2605 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST)
2606 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
2607 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
2608
2609 static void gen_ld(DisasContext *ctx)
2610 {
2611 TCGv EA;
2612 if (Rc(ctx->opcode)) {
2613 if (unlikely(rA(ctx->opcode) == 0 ||
2614 rA(ctx->opcode) == rD(ctx->opcode))) {
2615 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2616 return;
2617 }
2618 }
2619 gen_set_access_type(ctx, ACCESS_INT);
2620 EA = tcg_temp_new();
2621 gen_addr_imm_index(ctx, EA, 0x03);
2622 if (ctx->opcode & 0x02) {
2623 /* lwa (lwau is undefined) */
2624 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2625 } else {
2626 /* ld - ldu */
2627 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2628 }
2629 if (Rc(ctx->opcode))
2630 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2631 tcg_temp_free(EA);
2632 }
2633
2634 /* lq */
2635 static void gen_lq(DisasContext *ctx)
2636 {
2637 int ra, rd;
2638 TCGv EA;
2639
2640 /* lq is a legal user mode instruction starting in ISA 2.07 */
2641 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2642 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2643
2644 if (!legal_in_user_mode && ctx->pr) {
2645 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2646 return;
2647 }
2648
2649 if (!le_is_supported && ctx->le_mode) {
2650 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2651 return;
2652 }
2653
2654 ra = rA(ctx->opcode);
2655 rd = rD(ctx->opcode);
2656 if (unlikely((rd & 1) || rd == ra)) {
2657 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2658 return;
2659 }
2660
2661 gen_set_access_type(ctx, ACCESS_INT);
2662 EA = tcg_temp_new();
2663 gen_addr_imm_index(ctx, EA, 0x0F);
2664
2665 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2666 64-bit byteswap already. */
2667 if (unlikely(ctx->le_mode)) {
2668 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2669 gen_addr_add(ctx, EA, EA, 8);
2670 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2671 } else {
2672 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2673 gen_addr_add(ctx, EA, EA, 8);
2674 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2675 }
2676 tcg_temp_free(EA);
2677 }
2678 #endif
2679
2680 /*** Integer store ***/
2681 #define GEN_ST(name, stop, opc, type) \
2682 static void glue(gen_, name)(DisasContext *ctx) \
2683 { \
2684 TCGv EA; \
2685 gen_set_access_type(ctx, ACCESS_INT); \
2686 EA = tcg_temp_new(); \
2687 gen_addr_imm_index(ctx, EA, 0); \
2688 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2689 tcg_temp_free(EA); \
2690 }
2691
2692 #define GEN_STU(name, stop, opc, type) \
2693 static void glue(gen_, stop##u)(DisasContext *ctx) \
2694 { \
2695 TCGv EA; \
2696 if (unlikely(rA(ctx->opcode) == 0)) { \
2697 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2698 return; \
2699 } \
2700 gen_set_access_type(ctx, ACCESS_INT); \
2701 EA = tcg_temp_new(); \
2702 if (type == PPC_64B) \
2703 gen_addr_imm_index(ctx, EA, 0x03); \
2704 else \
2705 gen_addr_imm_index(ctx, EA, 0); \
2706 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2707 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2708 tcg_temp_free(EA); \
2709 }
2710
2711 #define GEN_STUX(name, stop, opc2, opc3, type) \
2712 static void glue(gen_, name##ux)(DisasContext *ctx) \
2713 { \
2714 TCGv EA; \
2715 if (unlikely(rA(ctx->opcode) == 0)) { \
2716 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2717 return; \
2718 } \
2719 gen_set_access_type(ctx, ACCESS_INT); \
2720 EA = tcg_temp_new(); \
2721 gen_addr_reg_index(ctx, EA); \
2722 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2723 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2724 tcg_temp_free(EA); \
2725 }
2726
2727 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2728 static void glue(gen_, name##x)(DisasContext *ctx) \
2729 { \
2730 TCGv EA; \
2731 chk; \
2732 gen_set_access_type(ctx, ACCESS_INT); \
2733 EA = tcg_temp_new(); \
2734 gen_addr_reg_index(ctx, EA); \
2735 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2736 tcg_temp_free(EA); \
2737 }
2738 #define GEN_STX(name, stop, opc2, opc3, type) \
2739 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2740
2741 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2742 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2743
2744 #define GEN_STS(name, stop, op, type) \
2745 GEN_ST(name, stop, op | 0x20, type); \
2746 GEN_STU(name, stop, op | 0x21, type); \
2747 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2748 GEN_STX(name, stop, 0x17, op | 0x00, type)
2749
2750 /* stb stbu stbux stbx */
2751 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2752 /* sth sthu sthux sthx */
2753 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2754 /* stw stwu stwux stwx */
2755 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2756 #if defined(TARGET_PPC64)
2757 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2758 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2759 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
2760 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
2761 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
2762 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
2763
2764 static void gen_std(DisasContext *ctx)
2765 {
2766 int rs;
2767 TCGv EA;
2768
2769 rs = rS(ctx->opcode);
2770 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
2771 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2772 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2773
2774 if (!(ctx->insns_flags & PPC_64BX)) {
2775 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2776 }
2777
2778 if (!legal_in_user_mode && ctx->pr) {
2779 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2780 return;
2781 }
2782
2783 if (!le_is_supported && ctx->le_mode) {
2784 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2785 return;
2786 }
2787
2788 if (unlikely(rs & 1)) {
2789 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2790 return;
2791 }
2792 gen_set_access_type(ctx, ACCESS_INT);
2793 EA = tcg_temp_new();
2794 gen_addr_imm_index(ctx, EA, 0x03);
2795
2796 /* We only need to swap high and low halves. gen_qemu_st64 does
2797 necessary 64-bit byteswap already. */
2798 if (unlikely(ctx->le_mode)) {
2799 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2800 gen_addr_add(ctx, EA, EA, 8);
2801 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2802 } else {
2803 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2804 gen_addr_add(ctx, EA, EA, 8);
2805 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2806 }
2807 tcg_temp_free(EA);
2808 } else {
2809 /* std / stdu*/
2810 if (Rc(ctx->opcode)) {
2811 if (unlikely(rA(ctx->opcode) == 0)) {
2812 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2813 return;
2814 }
2815 }
2816 gen_set_access_type(ctx, ACCESS_INT);
2817 EA = tcg_temp_new();
2818 gen_addr_imm_index(ctx, EA, 0x03);
2819 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2820 if (Rc(ctx->opcode))
2821 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2822 tcg_temp_free(EA);
2823 }
2824 }
2825 #endif
2826 /*** Integer load and store with byte reverse ***/
2827
2828 /* lhbrx */
2829 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2830 {
2831 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2832 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2833 }
2834 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2835
2836 /* lwbrx */
2837 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2838 {
2839 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2840 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2841 }
2842 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2843
2844 #if defined(TARGET_PPC64)
2845 /* ldbrx */
2846 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2847 {
2848 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2849 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2850 }
2851 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE);
2852 #endif /* TARGET_PPC64 */
2853
2854 /* sthbrx */
2855 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2856 {
2857 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2858 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2859 }
2860 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2861
2862 /* stwbrx */
2863 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2864 {
2865 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2866 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2867 }
2868 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2869
2870 #if defined(TARGET_PPC64)
2871 /* stdbrx */
2872 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2873 {
2874 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
2875 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2876 }
2877 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE);
2878 #endif /* TARGET_PPC64 */
2879
2880 /*** Integer load and store multiple ***/
2881
2882 /* lmw */
2883 static void gen_lmw(DisasContext *ctx)
2884 {
2885 TCGv t0;
2886 TCGv_i32 t1;
2887 gen_set_access_type(ctx, ACCESS_INT);
2888 t0 = tcg_temp_new();
2889 t1 = tcg_const_i32(rD(ctx->opcode));
2890 gen_addr_imm_index(ctx, t0, 0);
2891 gen_helper_lmw(cpu_env, t0, t1);
2892 tcg_temp_free(t0);
2893 tcg_temp_free_i32(t1);
2894 }
2895
2896 /* stmw */
2897 static void gen_stmw(DisasContext *ctx)
2898 {
2899 TCGv t0;
2900 TCGv_i32 t1;
2901 gen_set_access_type(ctx, ACCESS_INT);
2902 t0 = tcg_temp_new();
2903 t1 = tcg_const_i32(rS(ctx->opcode));
2904 gen_addr_imm_index(ctx, t0, 0);
2905 gen_helper_stmw(cpu_env, t0, t1);
2906 tcg_temp_free(t0);
2907 tcg_temp_free_i32(t1);
2908 }
2909
2910 /*** Integer load and store strings ***/
2911
2912 /* lswi */
2913 /* PowerPC32 specification says we must generate an exception if
2914 * rA is in the range of registers to be loaded.
2915 * In an other hand, IBM says this is valid, but rA won't be loaded.
2916 * For now, I'll follow the spec...
2917 */
2918 static void gen_lswi(DisasContext *ctx)
2919 {
2920 TCGv t0;
2921 TCGv_i32 t1, t2;
2922 int nb = NB(ctx->opcode);
2923 int start = rD(ctx->opcode);
2924 int ra = rA(ctx->opcode);
2925 int nr;
2926
2927 if (nb == 0)
2928 nb = 32;
2929 nr = (nb + 3) / 4;
2930 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
2931 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2932 return;
2933 }
2934 gen_set_access_type(ctx, ACCESS_INT);
2935 t0 = tcg_temp_new();
2936 gen_addr_register(ctx, t0);
2937 t1 = tcg_const_i32(nb);
2938 t2 = tcg_const_i32(start);
2939 gen_helper_lsw(cpu_env, t0, t1, t2);
2940 tcg_temp_free(t0);
2941 tcg_temp_free_i32(t1);
2942 tcg_temp_free_i32(t2);
2943 }
2944
2945 /* lswx */
2946 static void gen_lswx(DisasContext *ctx)
2947 {
2948 TCGv t0;
2949 TCGv_i32 t1, t2, t3;
2950 gen_set_access_type(ctx, ACCESS_INT);
2951 t0 = tcg_temp_new();
2952 gen_addr_reg_index(ctx, t0);
2953 t1 = tcg_const_i32(rD(ctx->opcode));
2954 t2 = tcg_const_i32(rA(ctx->opcode));
2955 t3 = tcg_const_i32(rB(ctx->opcode));
2956 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2957 tcg_temp_free(t0);
2958 tcg_temp_free_i32(t1);
2959 tcg_temp_free_i32(t2);
2960 tcg_temp_free_i32(t3);
2961 }
2962
2963 /* stswi */
2964 static void gen_stswi(DisasContext *ctx)
2965 {
2966 TCGv t0;
2967 TCGv_i32 t1, t2;
2968 int nb = NB(ctx->opcode);
2969 gen_set_access_type(ctx, ACCESS_INT);
2970 t0 = tcg_temp_new();
2971 gen_addr_register(ctx, t0);
2972 if (nb == 0)
2973 nb = 32;
2974 t1 = tcg_const_i32(nb);
2975 t2 = tcg_const_i32(rS(ctx->opcode));
2976 gen_helper_stsw(cpu_env, t0, t1, t2);
2977 tcg_temp_free(t0);
2978 tcg_temp_free_i32(t1);
2979 tcg_temp_free_i32(t2);
2980 }
2981
2982 /* stswx */
2983 static void gen_stswx(DisasContext *ctx)
2984 {
2985 TCGv t0;
2986 TCGv_i32 t1, t2;
2987 gen_set_access_type(ctx, ACCESS_INT);
2988 t0 = tcg_temp_new();
2989 gen_addr_reg_index(ctx, t0);
2990 t1 = tcg_temp_new_i32();
2991 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2992 tcg_gen_andi_i32(t1, t1, 0x7F);
2993 t2 = tcg_const_i32(rS(ctx->opcode));
2994 gen_helper_stsw(cpu_env, t0, t1, t2);
2995 tcg_temp_free(t0);
2996 tcg_temp_free_i32(t1);
2997 tcg_temp_free_i32(t2);
2998 }
2999
3000 /*** Memory synchronisation ***/
3001 /* eieio */
3002 static void gen_eieio(DisasContext *ctx)
3003 {
3004 }
3005
3006 #if !defined(CONFIG_USER_ONLY)
3007 static inline void gen_check_tlb_flush(DisasContext *ctx)
3008 {
3009 TCGv_i32 t;
3010 TCGLabel *l;
3011
3012 if (!ctx->lazy_tlb_flush) {
3013 return;
3014 }
3015 l = gen_new_label();
3016 t = tcg_temp_new_i32();
3017 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3018 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3019 gen_helper_check_tlb_flush(cpu_env);
3020 gen_set_label(l);
3021 tcg_temp_free_i32(t);
3022 }
3023 #else
3024 static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3025 #endif
3026
3027 /* isync */
3028 static void gen_isync(DisasContext *ctx)
3029 {
3030 /*
3031 * We need to check for a pending TLB flush. This can only happen in
3032 * kernel mode however so check MSR_PR
3033 */
3034 if (!ctx->pr) {
3035 gen_check_tlb_flush(ctx);
3036 }
3037 gen_stop_exception(ctx);
3038 }
3039
3040 #define LARX(name, len, loadop) \
3041 static void gen_##name(DisasContext *ctx) \
3042 { \
3043 TCGv t0; \
3044 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3045 gen_set_access_type(ctx, ACCESS_RES); \
3046 t0 = tcg_temp_local_new(); \
3047 gen_addr_reg_index(ctx, t0); \
3048 if ((len) > 1) { \
3049 gen_check_align(ctx, t0, (len)-1); \
3050 } \
3051 gen_qemu_##loadop(ctx, gpr, t0); \
3052 tcg_gen_mov_tl(cpu_reserve, t0); \
3053 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3054 tcg_temp_free(t0); \
3055 }
3056
3057 /* lwarx */
3058 LARX(lbarx, 1, ld8u);
3059 LARX(lharx, 2, ld16u);
3060 LARX(lwarx, 4, ld32u);
3061
3062
3063 #if defined(CONFIG_USER_ONLY)
3064 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3065 int reg, int size)
3066 {
3067 TCGv t0 = tcg_temp_new();
3068
3069 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3070 tcg_gen_movi_tl(t0, (size << 5) | reg);
3071 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3072 tcg_temp_free(t0);
3073 gen_exception_err(ctx, POWERPC_EXCP_STCX, 0);
3074 }
3075 #else
3076 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3077 int reg, int size)
3078 {
3079 TCGLabel *l1;
3080
3081 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3082 l1 = gen_new_label();
3083 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3084 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3085 #if defined(TARGET_PPC64)
3086 if (size == 8) {
3087 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3088 } else
3089 #endif
3090 if (size == 4) {
3091 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3092 } else if (size == 2) {
3093 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3094 #if defined(TARGET_PPC64)
3095 } else if (size == 16) {
3096 TCGv gpr1, gpr2 , EA8;
3097 if (unlikely(ctx->le_mode)) {
3098 gpr1 = cpu_gpr[reg+1];
3099 gpr2 = cpu_gpr[reg];
3100 } else {
3101 gpr1 = cpu_gpr[reg];
3102 gpr2 = cpu_gpr[reg+1];
3103 }
3104 gen_qemu_st64(ctx, gpr1, EA);
3105 EA8 = tcg_temp_local_new();
3106 gen_addr_add(ctx, EA8, EA, 8);
3107 gen_qemu_st64(ctx, gpr2, EA8);
3108 tcg_temp_free(EA8);
3109 #endif
3110 } else {
3111 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3112 }
3113 gen_set_label(l1);
3114 tcg_gen_movi_tl(cpu_reserve, -1);
3115 }
3116 #endif
3117
3118 #define STCX(name, len) \
3119 static void gen_##name(DisasContext *ctx) \
3120 { \
3121 TCGv t0; \
3122 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3123 gen_inval_exception(ctx, \
3124 POWERPC_EXCP_INVAL_INVAL); \
3125 return; \
3126 } \
3127 gen_set_access_type(ctx, ACCESS_RES); \
3128 t0 = tcg_temp_local_new(); \
3129 gen_addr_reg_index(ctx, t0); \
3130 if (len > 1) { \
3131 gen_check_align(ctx, t0, (len)-1); \
3132 } \
3133 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3134 tcg_temp_free(t0); \
3135 }
3136
3137 STCX(stbcx_, 1);
3138 STCX(sthcx_, 2);
3139 STCX(stwcx_, 4);
3140
3141 #if defined(TARGET_PPC64)
3142 /* ldarx */
3143 LARX(ldarx, 8, ld64);
3144
3145 /* lqarx */
3146 static void gen_lqarx(DisasContext *ctx)
3147 {
3148 TCGv EA;
3149 int rd = rD(ctx->opcode);
3150 TCGv gpr1, gpr2;
3151
3152 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3153 (rd == rB(ctx->opcode)))) {
3154 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3155 return;
3156 }
3157
3158 gen_set_access_type(ctx, ACCESS_RES);
3159 EA = tcg_temp_local_new();
3160 gen_addr_reg_index(ctx, EA);
3161 gen_check_align(ctx, EA, 15);
3162 if (unlikely(ctx->le_mode)) {
3163 gpr1 = cpu_gpr[rd+1];
3164 gpr2 = cpu_gpr[rd];
3165 } else {
3166 gpr1 = cpu_gpr[rd];
3167 gpr2 = cpu_gpr[rd+1];
3168 }
3169 gen_qemu_ld64(ctx, gpr1, EA);
3170 tcg_gen_mov_tl(cpu_reserve, EA);
3171
3172 gen_addr_add(ctx, EA, EA, 8);
3173 gen_qemu_ld64(ctx, gpr2, EA);
3174
3175 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3176 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3177
3178 tcg_temp_free(EA);
3179 }
3180
3181 /* stdcx. */
3182 STCX(stdcx_, 8);
3183 STCX(stqcx_, 16);
3184 #endif /* defined(TARGET_PPC64) */
3185
3186 /* sync */
3187 static void gen_sync(DisasContext *ctx)
3188 {
3189 uint32_t l = (ctx->opcode >> 21) & 3;
3190
3191 /*
3192 * We may need to check for a pending TLB flush.
3193 *
3194 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3195 *
3196 * Additionally, this can only happen in kernel mode however so
3197 * check MSR_PR as well.
3198 */
3199 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3200 gen_check_tlb_flush(ctx);
3201 }
3202 }
3203
3204 /* wait */
3205 static void gen_wait(DisasContext *ctx)
3206 {
3207 TCGv_i32 t0 = tcg_const_i32(1);
3208 tcg_gen_st_i32(t0, cpu_env,
3209 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3210 tcg_temp_free_i32(t0);
3211 /* Stop translation, as the CPU is supposed to sleep from now */
3212 gen_exception_nip(ctx, EXCP_HLT, ctx->nip);
3213 }
3214
3215 #if defined(TARGET_PPC64)
3216 static void gen_doze(DisasContext *ctx)
3217 {
3218 #if defined(CONFIG_USER_ONLY)
3219 GEN_PRIV;
3220 #else
3221 TCGv_i32 t;
3222
3223 CHK_HV;
3224 t = tcg_const_i32(PPC_PM_DOZE);
3225 gen_helper_pminsn(cpu_env, t);
3226 tcg_temp_free_i32(t);
3227 gen_stop_exception(ctx);
3228 #endif /* defined(CONFIG_USER_ONLY) */
3229 }
3230
3231 static void gen_nap(DisasContext *ctx)
3232 {
3233 #if defined(CONFIG_USER_ONLY)
3234 GEN_PRIV;
3235 #else
3236 TCGv_i32 t;
3237
3238 CHK_HV;
3239 t = tcg_const_i32(PPC_PM_NAP);
3240 gen_helper_pminsn(cpu_env, t);
3241 tcg_temp_free_i32(t);
3242 gen_stop_exception(ctx);
3243 #endif /* defined(CONFIG_USER_ONLY) */
3244 }
3245
3246 static void gen_sleep(DisasContext *ctx)
3247 {
3248 #if defined(CONFIG_USER_ONLY)
3249 GEN_PRIV;
3250 #else
3251 TCGv_i32 t;
3252
3253 CHK_HV;
3254 t = tcg_const_i32(PPC_PM_SLEEP);
3255 gen_helper_pminsn(cpu_env, t);
3256 tcg_temp_free_i32(t);
3257 gen_stop_exception(ctx);
3258 #endif /* defined(CONFIG_USER_ONLY) */
3259 }
3260
3261 static void gen_rvwinkle(DisasContext *ctx)
3262 {
3263 #if defined(CONFIG_USER_ONLY)
3264 GEN_PRIV;
3265 #else
3266 TCGv_i32 t;
3267
3268 CHK_HV;
3269 t = tcg_const_i32(PPC_PM_RVWINKLE);
3270 gen_helper_pminsn(cpu_env, t);
3271 tcg_temp_free_i32(t);
3272 gen_stop_exception(ctx);
3273 #endif /* defined(CONFIG_USER_ONLY) */
3274 }
3275 #endif /* #if defined(TARGET_PPC64) */
3276
3277 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3278 {
3279 #if defined(TARGET_PPC64)
3280 if (ctx->has_cfar)
3281 tcg_gen_movi_tl(cpu_cfar, nip);
3282 #endif
3283 }
3284
3285 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3286 {
3287 if (unlikely(ctx->singlestep_enabled)) {
3288 return false;
3289 }
3290
3291 #ifndef CONFIG_USER_ONLY
3292 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3293 #else
3294 return true;
3295 #endif
3296 }
3297
3298 /*** Branch ***/
3299 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3300 {
3301 if (NARROW_MODE(ctx)) {
3302 dest = (uint32_t) dest;
3303 }
3304 if (use_goto_tb(ctx, dest)) {
3305 tcg_gen_goto_tb(n);
3306 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3307 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3308 } else {
3309 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3310 if (unlikely(ctx->singlestep_enabled)) {
3311 if ((ctx->singlestep_enabled &
3312 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3313 (ctx->exception == POWERPC_EXCP_BRANCH ||
3314 ctx->exception == POWERPC_EXCP_TRACE)) {
3315 gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest);
3316 }
3317 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3318 gen_debug_exception(ctx);
3319 }
3320 }
3321 tcg_gen_exit_tb(0);
3322 }
3323 }
3324
3325 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3326 {
3327 if (NARROW_MODE(ctx)) {
3328 nip = (uint32_t)nip;
3329 }
3330 tcg_gen_movi_tl(cpu_lr, nip);
3331 }
3332
3333 /* b ba bl bla */
3334 static void gen_b(DisasContext *ctx)
3335 {
3336 target_ulong li, target;
3337
3338 ctx->exception = POWERPC_EXCP_BRANCH;
3339 /* sign extend LI */
3340 li = LI(ctx->opcode);
3341 li = (li ^ 0x02000000) - 0x02000000;
3342 if (likely(AA(ctx->opcode) == 0)) {
3343 target = ctx->nip + li - 4;
3344 } else {
3345 target = li;
3346 }
3347 if (LK(ctx->opcode)) {
3348 gen_setlr(ctx, ctx->nip);
3349 }
3350 gen_update_cfar(ctx, ctx->nip);
3351 gen_goto_tb(ctx, 0, target);
3352 }
3353
3354 #define BCOND_IM 0
3355 #define BCOND_LR 1
3356 #define BCOND_CTR 2
3357 #define BCOND_TAR 3
3358
3359 static inline void gen_bcond(DisasContext *ctx, int type)
3360 {
3361 uint32_t bo = BO(ctx->opcode);
3362 TCGLabel *l1;
3363 TCGv target;
3364
3365 ctx->exception = POWERPC_EXCP_BRANCH;
3366 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3367 target = tcg_temp_local_new();
3368 if (type == BCOND_CTR)
3369 tcg_gen_mov_tl(target, cpu_ctr);
3370 else if (type == BCOND_TAR)
3371 gen_load_spr(target, SPR_TAR);
3372 else
3373 tcg_gen_mov_tl(target, cpu_lr);
3374 } else {
3375 TCGV_UNUSED(target);
3376 }
3377 if (LK(ctx->opcode))
3378 gen_setlr(ctx, ctx->nip);
3379 l1 = gen_new_label();
3380 if ((bo & 0x4) == 0) {
3381 /* Decrement and test CTR */
3382 TCGv temp = tcg_temp_new();
3383 if (unlikely(type == BCOND_CTR)) {
3384 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3385 return;
3386 }
3387 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3388 if (NARROW_MODE(ctx)) {
3389 tcg_gen_ext32u_tl(temp, cpu_ctr);
3390 } else {
3391 tcg_gen_mov_tl(temp, cpu_ctr);
3392 }
3393 if (bo & 0x2) {
3394 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3395 } else {
3396 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3397 }
3398 tcg_temp_free(temp);
3399 }
3400 if ((bo & 0x10) == 0) {
3401 /* Test CR */
3402 uint32_t bi = BI(ctx->opcode);
3403 uint32_t mask = 0x08 >> (bi & 0x03);
3404 TCGv_i32 temp = tcg_temp_new_i32();
3405
3406 if (bo & 0x8) {
3407 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3408 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3409 } else {
3410 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3411 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3412 }
3413 tcg_temp_free_i32(temp);
3414 }
3415 gen_update_cfar(ctx, ctx->nip);
3416 if (type == BCOND_IM) {
3417 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3418 if (likely(AA(ctx->opcode) == 0)) {
3419 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3420 } else {
3421 gen_goto_tb(ctx, 0, li);
3422 }
3423 gen_set_label(l1);
3424 gen_goto_tb(ctx, 1, ctx->nip);
3425 } else {
3426 if (NARROW_MODE(ctx)) {
3427 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3428 } else {
3429 tcg_gen_andi_tl(cpu_nip, target, ~3);
3430 }
3431 tcg_gen_exit_tb(0);
3432 gen_set_label(l1);
3433 gen_update_nip(ctx, ctx->nip);
3434 tcg_gen_exit_tb(0);
3435 }
3436 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3437 tcg_temp_free(target);
3438 }
3439 }
3440
3441 static void gen_bc(DisasContext *ctx)
3442 {
3443 gen_bcond(ctx, BCOND_IM);
3444 }
3445
3446 static void gen_bcctr(DisasContext *ctx)
3447 {
3448 gen_bcond(ctx, BCOND_CTR);
3449 }
3450
3451 static void gen_bclr(DisasContext *ctx)
3452 {
3453 gen_bcond(ctx, BCOND_LR);
3454 }
3455
3456 static void gen_bctar(DisasContext *ctx)
3457 {
3458 gen_bcond(ctx, BCOND_TAR);
3459 }
3460
3461 /*** Condition register logical ***/
3462 #define GEN_CRLOGIC(name, tcg_op, opc) \
3463 static void glue(gen_, name)(DisasContext *ctx) \
3464 { \
3465 uint8_t bitmask; \
3466 int sh; \
3467 TCGv_i32 t0, t1; \
3468 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3469 t0 = tcg_temp_new_i32(); \
3470 if (sh > 0) \
3471 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3472 else if (sh < 0) \
3473 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3474 else \
3475 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3476 t1 = tcg_temp_new_i32(); \
3477 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3478 if (sh > 0) \
3479 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3480 else if (sh < 0) \
3481 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3482 else \
3483 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3484 tcg_op(t0, t0, t1); \
3485 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3486 tcg_gen_andi_i32(t0, t0, bitmask); \
3487 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3488 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3489 tcg_temp_free_i32(t0); \
3490 tcg_temp_free_i32(t1); \
3491 }
3492
3493 /* crand */
3494 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3495 /* crandc */
3496 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3497 /* creqv */
3498 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3499 /* crnand */
3500 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3501 /* crnor */
3502 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3503 /* cror */
3504 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3505 /* crorc */
3506 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3507 /* crxor */
3508 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3509
3510 /* mcrf */
3511 static void gen_mcrf(DisasContext *ctx)
3512 {
3513 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3514 }
3515
3516 /*** System linkage ***/
3517
3518 /* rfi (supervisor only) */
3519 static void gen_rfi(DisasContext *ctx)
3520 {
3521 #if defined(CONFIG_USER_ONLY)
3522 GEN_PRIV;
3523 #else
3524 /* FIXME: This instruction doesn't exist anymore on 64-bit server
3525 * processors compliant with arch 2.x, we should remove it there,
3526 * but we need to fix OpenBIOS not to use it on 970 first
3527 */
3528 /* Restore CPU state */
3529 CHK_SV;
3530 gen_update_cfar(ctx, ctx->nip);
3531 gen_helper_rfi(cpu_env);
3532 gen_sync_exception(ctx);
3533 #endif
3534 }
3535
3536 #if defined(TARGET_PPC64)
3537 static void gen_rfid(DisasContext *ctx)
3538 {
3539 #if defined(CONFIG_USER_ONLY)
3540 GEN_PRIV;
3541 #else
3542 /* Restore CPU state */
3543 CHK_SV;
3544 gen_update_cfar(ctx, ctx->nip);
3545 gen_helper_rfid(cpu_env);
3546 gen_sync_exception(ctx);
3547 #endif
3548 }
3549
3550 static void gen_hrfid(DisasContext *ctx)
3551 {
3552 #if defined(CONFIG_USER_ONLY)
3553 GEN_PRIV;
3554 #else
3555 /* Restore CPU state */
3556 CHK_HV;
3557 gen_helper_hrfid(cpu_env);
3558 gen_sync_exception(ctx);
3559 #endif
3560 }
3561 #endif
3562
3563 /* sc */
3564 #if defined(CONFIG_USER_ONLY)
3565 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3566 #else
3567 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3568 #endif
3569 static void gen_sc(DisasContext *ctx)
3570 {
3571 uint32_t lev;
3572
3573 lev = (ctx->opcode >> 5) & 0x7F;
3574 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3575 }
3576
3577 /*** Trap ***/
3578
3579 /* tw */
3580 static void gen_tw(DisasContext *ctx)
3581 {
3582 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3583 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3584 t0);
3585 tcg_temp_free_i32(t0);
3586 }
3587
3588 /* twi */
3589 static void gen_twi(DisasContext *ctx)
3590 {
3591 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3592 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3593 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3594 tcg_temp_free(t0);
3595 tcg_temp_free_i32(t1);
3596 }
3597
3598 #if defined(TARGET_PPC64)
3599 /* td */
3600 static void gen_td(DisasContext *ctx)
3601 {
3602 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3603 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3604 t0);
3605 tcg_temp_free_i32(t0);
3606 }
3607
3608 /* tdi */
3609 static void gen_tdi(DisasContext *ctx)
3610 {
3611 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3612 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3613 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3614 tcg_temp_free(t0);
3615 tcg_temp_free_i32(t1);
3616 }
3617 #endif
3618
3619 /*** Processor control ***/
3620
3621 static void gen_read_xer(TCGv dst)
3622 {
3623 TCGv t0 = tcg_temp_new();
3624 TCGv t1 = tcg_temp_new();
3625 TCGv t2 = tcg_temp_new();
3626 tcg_gen_mov_tl(dst, cpu_xer);
3627 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3628 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3629 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3630 tcg_gen_or_tl(t0, t0, t1);
3631 tcg_gen_or_tl(dst, dst, t2);
3632 tcg_gen_or_tl(dst, dst, t0);
3633 tcg_temp_free(t0);
3634 tcg_temp_free(t1);
3635 tcg_temp_free(t2);
3636 }
3637
3638 static void gen_write_xer(TCGv src)
3639 {
3640 tcg_gen_andi_tl(cpu_xer, src,
3641 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3642 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3643 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3644 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3645 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3646 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3647 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3648 }
3649
3650 /* mcrxr */
3651 static void gen_mcrxr(DisasContext *ctx)
3652 {
3653 TCGv_i32 t0 = tcg_temp_new_i32();
3654 TCGv_i32 t1 = tcg_temp_new_i32();
3655 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3656
3657 tcg_gen_trunc_tl_i32(t0, cpu_so);
3658 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3659 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3660 tcg_gen_shli_i32(t0, t0, 3);
3661 tcg_gen_shli_i32(t1, t1, 2);
3662 tcg_gen_shli_i32(dst, dst, 1);
3663 tcg_gen_or_i32(dst, dst, t0);
3664 tcg_gen_or_i32(dst, dst, t1);
3665 tcg_temp_free_i32(t0);
3666 tcg_temp_free_i32(t1);
3667
3668 tcg_gen_movi_tl(cpu_so, 0);
3669 tcg_gen_movi_tl(cpu_ov, 0);
3670 tcg_gen_movi_tl(cpu_ca, 0);
3671 }
3672
3673 /* mfcr mfocrf */
3674 static void gen_mfcr(DisasContext *ctx)
3675 {
3676 uint32_t crm, crn;
3677
3678 if (likely(ctx->opcode & 0x00100000)) {
3679 crm = CRM(ctx->opcode);
3680 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3681 crn = ctz32 (crm);
3682 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3683 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3684 cpu_gpr[rD(ctx->opcode)], crn * 4);
3685 }
3686 } else {
3687 TCGv_i32 t0 = tcg_temp_new_i32();
3688 tcg_gen_mov_i32(t0, cpu_crf[0]);
3689 tcg_gen_shli_i32(t0, t0, 4);
3690 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3691 tcg_gen_shli_i32(t0, t0, 4);
3692 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3693 tcg_gen_shli_i32(t0, t0, 4);
3694 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3695 tcg_gen_shli_i32(t0, t0, 4);
3696 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3697 tcg_gen_shli_i32(t0, t0, 4);
3698 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3699 tcg_gen_shli_i32(t0, t0, 4);
3700 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3701 tcg_gen_shli_i32(t0, t0, 4);
3702 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3703 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3704 tcg_temp_free_i32(t0);
3705 }
3706 }
3707
3708 /* mfmsr */
3709 static void gen_mfmsr(DisasContext *ctx)
3710 {
3711 CHK_SV;
3712 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3713 }
3714
3715 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
3716 {
3717 #if 0
3718 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3719 printf("ERROR: try to access SPR %d !\n", sprn);
3720 #endif
3721 }
3722 #define SPR_NOACCESS (&spr_noaccess)
3723
3724 /* mfspr */
3725 static inline void gen_op_mfspr(DisasContext *ctx)
3726 {
3727 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
3728 uint32_t sprn = SPR(ctx->opcode);
3729
3730 #if defined(CONFIG_USER_ONLY)
3731 read_cb = ctx->spr_cb[sprn].uea_read;
3732 #else
3733 if (ctx->pr) {
3734 read_cb = ctx->spr_cb[sprn].uea_read;
3735 } else if (ctx->hv) {
3736 read_cb = ctx->spr_cb[sprn].hea_read;
3737 } else {
3738 read_cb = ctx->spr_cb[sprn].oea_read;
3739 }
3740 #endif
3741 if (likely(read_cb != NULL)) {
3742 if (likely(read_cb != SPR_NOACCESS)) {
3743 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3744 } else {
3745 /* Privilege exception */
3746 /* This is a hack to avoid warnings when running Linux:
3747 * this OS breaks the PowerPC virtualisation model,
3748 * allowing userland application to read the PVR
3749 */
3750 if (sprn != SPR_PVR) {
3751 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
3752 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3753 if (qemu_log_separate()) {
3754 qemu_log("Trying to read privileged spr %d (0x%03x) at "
3755 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3756 }
3757 }
3758 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3759 }
3760 } else {
3761 /* ISA 2.07 defines these as no-ops */
3762 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3763 (sprn >= 808 && sprn <= 811)) {
3764 /* This is a nop */
3765 return;
3766 }
3767 /* Not defined */
3768 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
3769 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3770 if (qemu_log_separate()) {
3771 qemu_log("Trying to read invalid spr %d (0x%03x) at "
3772 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3773 }
3774
3775 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3776 * it can generate a priv, a hv emu or a no-op
3777 */
3778 if (sprn & 0x10) {
3779 if (ctx->pr) {
3780 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3781 }
3782 } else {
3783 if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
3784 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3785 }
3786 }
3787 }
3788 }
3789
3790 static void gen_mfspr(DisasContext *ctx)
3791 {
3792 gen_op_mfspr(ctx);
3793 }
3794
3795 /* mftb */
3796 static void gen_mftb(DisasContext *ctx)
3797 {
3798 gen_op_mfspr(ctx);
3799 }
3800
3801 /* mtcrf mtocrf*/
3802 static void gen_mtcrf(DisasContext *ctx)
3803 {
3804 uint32_t crm, crn;
3805
3806 crm = CRM(ctx->opcode);
3807 if (likely((ctx->opcode & 0x00100000))) {
3808 if (crm && ((crm & (crm - 1)) == 0)) {
3809 TCGv_i32 temp = tcg_temp_new_i32();
3810 crn = ctz32 (crm);
3811 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3812 tcg_gen_shri_i32(temp, temp, crn * 4);
3813 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3814 tcg_temp_free_i32(temp);
3815 }
3816 } else {
3817 TCGv_i32 temp = tcg_temp_new_i32();
3818 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3819 for (crn = 0 ; crn < 8 ; crn++) {
3820 if (crm & (1 << crn)) {
3821 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3822 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3823 }
3824 }
3825 tcg_temp_free_i32(temp);
3826 }
3827 }
3828
3829 /* mtmsr */
3830 #if defined(TARGET_PPC64)
3831 static void gen_mtmsrd(DisasContext *ctx)
3832 {
3833 CHK_SV;
3834
3835 #if !defined(CONFIG_USER_ONLY)
3836 if (ctx->opcode & 0x00010000) {
3837 /* Special form that does not need any synchronisation */
3838 TCGv t0 = tcg_temp_new();
3839 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3840 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3841 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3842 tcg_temp_free(t0);
3843 } else {
3844 /* XXX: we need to update nip before the store
3845 * if we enter power saving mode, we will exit the loop
3846 * directly from ppc_store_msr
3847 */
3848 gen_update_nip(ctx, ctx->nip);
3849 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3850 /* Must stop the translation as machine state (may have) changed */
3851 /* Note that mtmsr is not always defined as context-synchronizing */
3852 gen_stop_exception(ctx);
3853 }
3854 #endif /* !defined(CONFIG_USER_ONLY) */
3855 }
3856 #endif /* defined(TARGET_PPC64) */
3857
3858 static void gen_mtmsr(DisasContext *ctx)
3859 {
3860 CHK_SV;
3861
3862 #if !defined(CONFIG_USER_ONLY)
3863 if (ctx->opcode & 0x00010000) {
3864 /* Special form that does not need any synchronisation */
3865 TCGv t0 = tcg_temp_new();
3866 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3867 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
3868 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3869 tcg_temp_free(t0);
3870 } else {
3871 TCGv msr = tcg_temp_new();
3872
3873 /* XXX: we need to update nip before the store
3874 * if we enter power saving mode, we will exit the loop
3875 * directly from ppc_store_msr
3876 */
3877 gen_update_nip(ctx, ctx->nip);
3878 #if defined(TARGET_PPC64)
3879 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3880 #else
3881 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3882 #endif
3883 gen_helper_store_msr(cpu_env, msr);
3884 tcg_temp_free(msr);
3885 /* Must stop the translation as machine state (may have) changed */
3886 /* Note that mtmsr is not always defined as context-synchronizing */
3887 gen_stop_exception(ctx);
3888 }
3889 #endif
3890 }
3891
3892 /* mtspr */
3893 static void gen_mtspr(DisasContext *ctx)
3894 {
3895 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
3896 uint32_t sprn = SPR(ctx->opcode);
3897
3898 #if defined(CONFIG_USER_ONLY)
3899 write_cb = ctx->spr_cb[sprn].uea_write;
3900 #else
3901 if (ctx->pr) {
3902 write_cb = ctx->spr_cb[sprn].uea_write;
3903 } else if (ctx->hv) {
3904 write_cb = ctx->spr_cb[sprn].hea_write;
3905 } else {
3906 write_cb = ctx->spr_cb[sprn].oea_write;
3907 }
3908 #endif
3909 if (likely(write_cb != NULL)) {
3910 if (likely(write_cb != SPR_NOACCESS)) {
3911 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3912 } else {
3913 /* Privilege exception */
3914 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
3915 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3916 if (qemu_log_separate()) {
3917 qemu_log("Trying to write privileged spr %d (0x%03x) at "
3918 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3919 }
3920 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
3921 }
3922 } else {
3923 /* ISA 2.07 defines these as no-ops */
3924 if ((ctx->insns_flags2 & PPC2_ISA207S) &&
3925 (sprn >= 808 && sprn <= 811)) {
3926 /* This is a nop */
3927 return;
3928 }
3929
3930 /* Not defined */
3931 if (qemu_log_separate()) {
3932 qemu_log("Trying to write invalid spr %d (0x%03x) at "
3933 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3934 }
3935 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
3936 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
3937
3938
3939 /* The behaviour depends on MSR:PR and SPR# bit 0x10,
3940 * it can generate a priv, a hv emu or a no-op
3941 */
3942 if (sprn & 0x10) {
3943 if (ctx->pr) {
3944 gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3945 }
3946 } else {
3947 if (ctx->pr || sprn == 0) {
3948 gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3949 }
3950 }
3951 }
3952 }
3953
3954 #if defined(TARGET_PPC64)
3955 /* setb */
3956 static void gen_setb(DisasContext *ctx)
3957 {
3958 TCGv_i32 t0 = tcg_temp_new_i32();
3959 TCGv_i32 t8 = tcg_temp_new_i32();
3960 TCGv_i32 tm1 = tcg_temp_new_i32();
3961 int crf = crfS(ctx->opcode);
3962
3963 tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4);
3964 tcg_gen_movi_i32(t8, 8);
3965 tcg_gen_movi_i32(tm1, -1);
3966 tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0);
3967 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3968
3969 tcg_temp_free_i32(t0);
3970 tcg_temp_free_i32(t8);
3971 tcg_temp_free_i32(tm1);
3972 }
3973 #endif
3974
3975 /*** Cache management ***/
3976
3977 /* dcbf */
3978 static void gen_dcbf(DisasContext *ctx)
3979 {
3980 /* XXX: specification says this is treated as a load by the MMU */
3981 TCGv t0;
3982 gen_set_access_type(ctx, ACCESS_CACHE);
3983 t0 = tcg_temp_new();
3984 gen_addr_reg_index(ctx, t0);
3985 gen_qemu_ld8u(ctx, t0, t0);
3986 tcg_temp_free(t0);
3987 }
3988
3989 /* dcbi (Supervisor only) */
3990 static void gen_dcbi(DisasContext *ctx)
3991 {
3992 #if defined(CONFIG_USER_ONLY)
3993 GEN_PRIV;
3994 #else
3995 TCGv EA, val;
3996
3997 CHK_SV;
3998 EA = tcg_temp_new();
3999 gen_set_access_type(ctx, ACCESS_CACHE);
4000 gen_addr_reg_index(ctx, EA);
4001 val = tcg_temp_new();
4002 /* XXX: specification says this should be treated as a store by the MMU */
4003 gen_qemu_ld8u(ctx, val, EA);
4004 gen_qemu_st8(ctx, val, EA);
4005 tcg_temp_free(val);
4006 tcg_temp_free(EA);
4007 #endif /* defined(CONFIG_USER_ONLY) */
4008 }
4009
4010 /* dcdst */
4011 static void gen_dcbst(DisasContext *ctx)
4012 {
4013 /* XXX: specification say this is treated as a load by the MMU */
4014 TCGv t0;
4015 gen_set_access_type(ctx, ACCESS_CACHE);
4016 t0 = tcg_temp_new();
4017 gen_addr_reg_index(ctx, t0);
4018 gen_qemu_ld8u(ctx, t0, t0);
4019 tcg_temp_free(t0);
4020 }
4021
4022 /* dcbt */
4023 static void gen_dcbt(DisasContext *ctx)
4024 {
4025 /* interpreted as no-op */
4026 /* XXX: specification say this is treated as a load by the MMU
4027 * but does not generate any exception
4028 */
4029 }
4030
4031 /* dcbtst */
4032 static void gen_dcbtst(DisasContext *ctx)
4033 {
4034 /* interpreted as no-op */
4035 /* XXX: specification say this is treated as a load by the MMU
4036 * but does not generate any exception
4037 */
4038 }
4039
4040 /* dcbtls */
4041 static void gen_dcbtls(DisasContext *ctx)
4042 {
4043 /* Always fails locking the cache */
4044 TCGv t0 = tcg_temp_new();
4045 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4046 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4047 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4048 tcg_temp_free(t0);
4049 }
4050
4051 /* dcbz */
4052 static void gen_dcbz(DisasContext *ctx)
4053 {
4054 TCGv tcgv_addr;
4055 TCGv_i32 tcgv_is_dcbzl;
4056 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4057
4058 gen_set_access_type(ctx, ACCESS_CACHE);
4059 /* NIP cannot be restored if the memory exception comes from an helper */
4060 gen_update_nip(ctx, ctx->nip - 4);
4061 tcgv_addr = tcg_temp_new();
4062 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4063
4064 gen_addr_reg_index(ctx, tcgv_addr);
4065 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4066
4067 tcg_temp_free(tcgv_addr);
4068 tcg_temp_free_i32(tcgv_is_dcbzl);
4069 }
4070
4071 /* dst / dstt */
4072 static void gen_dst(DisasContext *ctx)
4073 {
4074 if (rA(ctx->opcode) == 0) {
4075 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4076 } else {
4077 /* interpreted as no-op */
4078 }
4079 }
4080
4081 /* dstst /dststt */
4082 static void gen_dstst(DisasContext *ctx)
4083 {
4084 if (rA(ctx->opcode) == 0) {
4085 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
4086 } else {
4087 /* interpreted as no-op */
4088 }
4089
4090 }
4091
4092 /* dss / dssall */
4093 static void gen_dss(DisasContext *ctx)
4094 {
4095 /* interpreted as no-op */
4096 }
4097
4098 /* icbi */
4099 static void gen_icbi(DisasContext *ctx)
4100 {
4101 TCGv t0;
4102 gen_set_access_type(ctx, ACCESS_CACHE);
4103 t0 = tcg_temp_new();
4104 gen_addr_reg_index(ctx, t0);
4105 gen_helper_icbi(cpu_env, t0);
4106 tcg_temp_free(t0);
4107 }
4108
4109 /* Optional: */
4110 /* dcba */
4111 static void gen_dcba(DisasContext *ctx)
4112 {
4113 /* interpreted as no-op */
4114 /* XXX: specification say this is treated as a store by the MMU
4115 * but does not generate any exception
4116 */
4117 }
4118
4119 /*** Segment register manipulation ***/
4120 /* Supervisor only: */
4121
4122 /* mfsr */
4123 static void gen_mfsr(DisasContext *ctx)
4124 {
4125 #if defined(CONFIG_USER_ONLY)
4126 GEN_PRIV;
4127 #else
4128 TCGv t0;
4129
4130 CHK_SV;
4131 t0 = tcg_const_tl(SR(ctx->opcode));
4132 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4133 tcg_temp_free(t0);
4134 #endif /* defined(CONFIG_USER_ONLY) */
4135 }
4136
4137 /* mfsrin */
4138 static void gen_mfsrin(DisasContext *ctx)
4139 {
4140 #if defined(CONFIG_USER_ONLY)
4141 GEN_PRIV;
4142 #else
4143 TCGv t0;
4144
4145 CHK_SV;
4146 t0 = tcg_temp_new();
4147 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4148 tcg_gen_andi_tl(t0, t0, 0xF);
4149 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4150 tcg_temp_free(t0);
4151 #endif /* defined(CONFIG_USER_ONLY) */
4152 }
4153
4154 /* mtsr */
4155 static void gen_mtsr(DisasContext *ctx)
4156 {
4157 #if defined(CONFIG_USER_ONLY)
4158 GEN_PRIV;
4159 #else
4160 TCGv t0;
4161
4162 CHK_SV;
4163 t0 = tcg_const_tl(SR(ctx->opcode));
4164 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4165 tcg_temp_free(t0);
4166 #endif /* defined(CONFIG_USER_ONLY) */
4167 }
4168
4169 /* mtsrin */
4170 static void gen_mtsrin(DisasContext *ctx)
4171 {
4172 #if defined(CONFIG_USER_ONLY)
4173 GEN_PRIV;
4174 #else
4175 TCGv t0;
4176 CHK_SV;
4177
4178 t0 = tcg_temp_new();
4179 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4180 tcg_gen_andi_tl(t0, t0, 0xF);
4181 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4182 tcg_temp_free(t0);
4183 #endif /* defined(CONFIG_USER_ONLY) */
4184 }
4185
4186 #if defined(TARGET_PPC64)
4187 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4188
4189 /* mfsr */
4190 static void gen_mfsr_64b(DisasContext *ctx)
4191 {
4192 #if defined(CONFIG_USER_ONLY)
4193 GEN_PRIV;
4194 #else
4195 TCGv t0;
4196
4197 CHK_SV;
4198 t0 = tcg_const_tl(SR(ctx->opcode));
4199 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4200 tcg_temp_free(t0);
4201 #endif /* defined(CONFIG_USER_ONLY) */
4202 }
4203
4204 /* mfsrin */
4205 static void gen_mfsrin_64b(DisasContext *ctx)
4206 {
4207 #if defined(CONFIG_USER_ONLY)
4208 GEN_PRIV;
4209 #else
4210 TCGv t0;
4211
4212 CHK_SV;
4213 t0 = tcg_temp_new();
4214 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4215 tcg_gen_andi_tl(t0, t0, 0xF);
4216 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4217 tcg_temp_free(t0);
4218 #endif /* defined(CONFIG_USER_ONLY) */
4219 }
4220
4221 /* mtsr */
4222 static void gen_mtsr_64b(DisasContext *ctx)
4223 {
4224 #if defined(CONFIG_USER_ONLY)
4225 GEN_PRIV;
4226 #else
4227 TCGv t0;
4228
4229 CHK_SV;
4230 t0 = tcg_const_tl(SR(ctx->opcode));
4231 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4232 tcg_temp_free(t0);
4233 #endif /* defined(CONFIG_USER_ONLY) */
4234 }
4235
4236 /* mtsrin */
4237 static void gen_mtsrin_64b(DisasContext *ctx)
4238 {
4239 #if defined(CONFIG_USER_ONLY)
4240 GEN_PRIV;
4241 #else
4242 TCGv t0;
4243
4244 CHK_SV;
4245 t0 = tcg_temp_new();
4246 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4247 tcg_gen_andi_tl(t0, t0, 0xF);
4248 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4249 tcg_temp_free(t0);
4250 #endif /* defined(CONFIG_USER_ONLY) */
4251 }
4252
4253 /* slbmte */
4254 static void gen_slbmte(DisasContext *ctx)
4255 {
4256 #if defined(CONFIG_USER_ONLY)
4257 GEN_PRIV;
4258 #else
4259 CHK_SV;
4260
4261 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4262 cpu_gpr[rS(ctx->opcode)]);
4263 #endif /* defined(CONFIG_USER_ONLY) */
4264 }
4265
4266 static void gen_slbmfee(DisasContext *ctx)
4267 {
4268 #if defined(CONFIG_USER_ONLY)
4269 GEN_PRIV;
4270 #else
4271 CHK_SV;
4272
4273 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4274 cpu_gpr[rB(ctx->opcode)]);
4275 #endif /* defined(CONFIG_USER_ONLY) */
4276 }
4277
4278 static void gen_slbmfev(DisasContext *ctx)
4279 {
4280 #if defined(CONFIG_USER_ONLY)
4281 GEN_PRIV;
4282 #else
4283 CHK_SV;
4284
4285 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4286 cpu_gpr[rB(ctx->opcode)]);
4287 #endif /* defined(CONFIG_USER_ONLY) */
4288 }
4289
4290 static void gen_slbfee_(DisasContext *ctx)
4291 {
4292 #if defined(CONFIG_USER_ONLY)
4293 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4294 #else
4295 TCGLabel *l1, *l2;
4296
4297 if (unlikely(ctx->pr)) {
4298 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4299 return;
4300 }
4301 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4302 cpu_gpr[rB(ctx->opcode)]);
4303 l1 = gen_new_label();
4304 l2 = gen_new_label();
4305 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4306 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4307 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
4308 tcg_gen_br(l2);
4309 gen_set_label(l1);
4310 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4311 gen_set_label(l2);
4312 #endif
4313 }
4314 #endif /* defined(TARGET_PPC64) */
4315
4316 /*** Lookaside buffer management ***/
4317 /* Optional & supervisor only: */
4318
4319 /* tlbia */
4320 static void gen_tlbia(DisasContext *ctx)
4321 {
4322 #if defined(CONFIG_USER_ONLY)
4323 GEN_PRIV;
4324 #else
4325 CHK_HV;
4326
4327 gen_helper_tlbia(cpu_env);
4328 #endif /* defined(CONFIG_USER_ONLY) */
4329 }
4330
4331 /* tlbiel */
4332 static void gen_tlbiel(DisasContext *ctx)
4333 {
4334 #if defined(CONFIG_USER_ONLY)
4335 GEN_PRIV;
4336 #else
4337 CHK_SV;
4338
4339 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4340 #endif /* defined(CONFIG_USER_ONLY) */
4341 }
4342
4343 /* tlbie */
4344 static void gen_tlbie(DisasContext *ctx)
4345 {
4346 #if defined(CONFIG_USER_ONLY)
4347 GEN_PRIV;
4348 #else
4349 CHK_HV;
4350
4351 if (NARROW_MODE(ctx)) {
4352 TCGv t0 = tcg_temp_new();
4353 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4354 gen_helper_tlbie(cpu_env, t0);
4355 tcg_temp_free(t0);
4356 } else {
4357 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4358 }
4359 #endif /* defined(CONFIG_USER_ONLY) */
4360 }
4361
4362 /* tlbsync */
4363 static void gen_tlbsync(DisasContext *ctx)
4364 {
4365 #if defined(CONFIG_USER_ONLY)
4366 GEN_PRIV;
4367 #else
4368 CHK_HV;
4369
4370 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4371 * embedded however needs to deal with tlbsync. We don't try to be
4372 * fancy and swallow the overhead of checking for both.
4373 */
4374 gen_check_tlb_flush(ctx);
4375 #endif /* defined(CONFIG_USER_ONLY) */
4376 }
4377
4378 #if defined(TARGET_PPC64)
4379 /* slbia */
4380 static void gen_slbia(DisasContext *ctx)
4381 {
4382 #if defined(CONFIG_USER_ONLY)
4383 GEN_PRIV;
4384 #else
4385 CHK_SV;
4386
4387 gen_helper_slbia(cpu_env);
4388 #endif /* defined(CONFIG_USER_ONLY) */
4389 }
4390
4391 /* slbie */
4392 static void gen_slbie(DisasContext *ctx)
4393 {
4394 #if defined(CONFIG_USER_ONLY)
4395 GEN_PRIV;
4396 #else
4397 CHK_SV;
4398
4399 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4400 #endif /* defined(CONFIG_USER_ONLY) */
4401 }
4402 #endif /* defined(TARGET_PPC64) */
4403
4404 /*** External control ***/
4405 /* Optional: */
4406
4407 /* eciwx */
4408 static void gen_eciwx(DisasContext *ctx)
4409 {
4410 TCGv t0;
4411 /* Should check EAR[E] ! */
4412 gen_set_access_type(ctx, ACCESS_EXT);
4413 t0 = tcg_temp_new();
4414 gen_addr_reg_index(ctx, t0);
4415 gen_check_align(ctx, t0, 0x03);
4416 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4417 tcg_temp_free(t0);
4418 }
4419
4420 /* ecowx */
4421 static void gen_ecowx(DisasContext *ctx)
4422 {
4423 TCGv t0;
4424 /* Should check EAR[E] ! */
4425 gen_set_access_type(ctx, ACCESS_EXT);
4426 t0 = tcg_temp_new();
4427 gen_addr_reg_index(ctx, t0);
4428 gen_check_align(ctx, t0, 0x03);
4429 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4430 tcg_temp_free(t0);
4431 }
4432
4433 /* PowerPC 601 specific instructions */
4434
4435 /* abs - abs. */
4436 static void gen_abs(DisasContext *ctx)
4437 {
4438 TCGLabel *l1 = gen_new_label();
4439 TCGLabel *l2 = gen_new_label();
4440 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4441 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4442 tcg_gen_br(l2);
4443 gen_set_label(l1);
4444 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4445 gen_set_label(l2);
4446 if (unlikely(Rc(ctx->opcode) != 0))
4447 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4448 }
4449
4450 /* abso - abso. */
4451 static void gen_abso(DisasContext *ctx)
4452 {
4453 TCGLabel *l1 = gen_new_label();
4454 TCGLabel *l2 = gen_new_label();
4455 TCGLabel *l3 = gen_new_label();
4456 /* Start with XER OV disabled, the most likely case */
4457 tcg_gen_movi_tl(cpu_ov, 0);
4458 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4459 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4460 tcg_gen_movi_tl(cpu_ov, 1);
4461 tcg_gen_movi_tl(cpu_so, 1);
4462 tcg_gen_br(l2);
4463 gen_set_label(l1);
4464 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4465 tcg_gen_br(l3);
4466 gen_set_label(l2);
4467 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4468 gen_set_label(l3);
4469 if (unlikely(Rc(ctx->opcode) != 0))
4470 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4471 }
4472
4473 /* clcs */
4474 static void gen_clcs(DisasContext *ctx)
4475 {
4476 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4477 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4478 tcg_temp_free_i32(t0);
4479 /* Rc=1 sets CR0 to an undefined state */
4480 }
4481
4482 /* div - div. */
4483 static void gen_div(DisasContext *ctx)
4484 {
4485 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4486 cpu_gpr[rB(ctx->opcode)]);
4487 if (unlikely(Rc(ctx->opcode) != 0))
4488 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4489 }
4490
4491 /* divo - divo. */
4492 static void gen_divo(DisasContext *ctx)
4493 {
4494 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4495 cpu_gpr[rB(ctx->opcode)]);
4496 if (unlikely(Rc(ctx->opcode) != 0))
4497 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4498 }
4499
4500 /* divs - divs. */
4501 static void gen_divs(DisasContext *ctx)
4502 {
4503 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4504 cpu_gpr[rB(ctx->opcode)]);
4505 if (unlikely(Rc(ctx->opcode) != 0))
4506 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4507 }
4508
4509 /* divso - divso. */
4510 static void gen_divso(DisasContext *ctx)
4511 {
4512 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4513 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4514 if (unlikely(Rc(ctx->opcode) != 0))
4515 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4516 }
4517
4518 /* doz - doz. */
4519 static void gen_doz(DisasContext *ctx)
4520 {
4521 TCGLabel *l1 = gen_new_label();
4522 TCGLabel *l2 = gen_new_label();
4523 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4524 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4525 tcg_gen_br(l2);
4526 gen_set_label(l1);
4527 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4528 gen_set_label(l2);
4529 if (unlikely(Rc(ctx->opcode) != 0))
4530 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4531 }
4532
4533 /* dozo - dozo. */
4534 static void gen_dozo(DisasContext *ctx)
4535 {
4536 TCGLabel *l1 = gen_new_label();
4537 TCGLabel *l2 = gen_new_label();
4538 TCGv t0 = tcg_temp_new();
4539 TCGv t1 = tcg_temp_new();
4540 TCGv t2 = tcg_temp_new();
4541 /* Start with XER OV disabled, the most likely case */
4542 tcg_gen_movi_tl(cpu_ov, 0);
4543 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4544 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4545 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4546 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4547 tcg_gen_andc_tl(t1, t1, t2);
4548 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4549 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4550 tcg_gen_movi_tl(cpu_ov, 1);
4551 tcg_gen_movi_tl(cpu_so, 1);
4552 tcg_gen_br(l2);
4553 gen_set_label(l1);
4554 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4555 gen_set_label(l2);
4556 tcg_temp_free(t0);
4557 tcg_temp_free(t1);
4558 tcg_temp_free(t2);
4559 if (unlikely(Rc(ctx->opcode) != 0))
4560 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4561 }
4562
4563 /* dozi */
4564 static void gen_dozi(DisasContext *ctx)
4565 {
4566 target_long simm = SIMM(ctx->opcode);
4567 TCGLabel *l1 = gen_new_label();
4568 TCGLabel *l2 = gen_new_label();
4569 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4570 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4571 tcg_gen_br(l2);
4572 gen_set_label(l1);
4573 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4574 gen_set_label(l2);
4575 if (unlikely(Rc(ctx->opcode) != 0))
4576 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4577 }
4578
4579 /* lscbx - lscbx. */
4580 static void gen_lscbx(DisasContext *ctx)
4581 {
4582 TCGv t0 = tcg_temp_new();
4583 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4584 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4585 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4586
4587 gen_addr_reg_index(ctx, t0);
4588 /* NIP cannot be restored if the memory exception comes from an helper */
4589 gen_update_nip(ctx, ctx->nip - 4);
4590 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4591 tcg_temp_free_i32(t1);
4592 tcg_temp_free_i32(t2);
4593 tcg_temp_free_i32(t3);
4594 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4595 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4596 if (unlikely(Rc(ctx->opcode) != 0))
4597 gen_set_Rc0(ctx, t0);
4598 tcg_temp_free(t0);
4599 }
4600
4601 /* maskg - maskg. */
4602 static void gen_maskg(DisasContext *ctx)
4603 {
4604 TCGLabel *l1 = gen_new_label();
4605 TCGv t0 = tcg_temp_new();
4606 TCGv t1 = tcg_temp_new();
4607 TCGv t2 = tcg_temp_new();
4608 TCGv t3 = tcg_temp_new();
4609 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4610 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4611 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4612 tcg_gen_addi_tl(t2, t0, 1);
4613 tcg_gen_shr_tl(t2, t3, t2);
4614 tcg_gen_shr_tl(t3, t3, t1);
4615 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4616 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4617 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4618 gen_set_label(l1);
4619 tcg_temp_free(t0);
4620 tcg_temp_free(t1);
4621 tcg_temp_free(t2);
4622 tcg_temp_free(t3);
4623 if (unlikely(Rc(ctx->opcode) != 0))
4624 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4625 }
4626
4627 /* maskir - maskir. */
4628 static void gen_maskir(DisasContext *ctx)
4629 {
4630 TCGv t0 = tcg_temp_new();
4631 TCGv t1 = tcg_temp_new();
4632 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4633 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4634 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4635 tcg_temp_free(t0);
4636 tcg_temp_free(t1);
4637 if (unlikely(Rc(ctx->opcode) != 0))
4638 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4639 }
4640
4641 /* mul - mul. */
4642 static void gen_mul(DisasContext *ctx)
4643 {
4644 TCGv_i64 t0 = tcg_temp_new_i64();
4645 TCGv_i64 t1 = tcg_temp_new_i64();
4646 TCGv t2 = tcg_temp_new();
4647 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4648 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4649 tcg_gen_mul_i64(t0, t0, t1);
4650 tcg_gen_trunc_i64_tl(t2, t0);
4651 gen_store_spr(SPR_MQ, t2);
4652 tcg_gen_shri_i64(t1, t0, 32);
4653 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4654 tcg_temp_free_i64(t0);
4655 tcg_temp_free_i64(t1);
4656 tcg_temp_free(t2);
4657 if (unlikely(Rc(ctx->opcode) != 0))
4658 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4659 }
4660
4661 /* mulo - mulo. */
4662 static void gen_mulo(DisasContext *ctx)
4663 {
4664 TCGLabel *l1 = gen_new_label();
4665 TCGv_i64 t0 = tcg_temp_new_i64();
4666 TCGv_i64 t1 = tcg_temp_new_i64();
4667 TCGv t2 = tcg_temp_new();
4668 /* Start with XER OV disabled, the most likely case */
4669 tcg_gen_movi_tl(cpu_ov, 0);
4670 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4671 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4672 tcg_gen_mul_i64(t0, t0, t1);
4673 tcg_gen_trunc_i64_tl(t2, t0);
4674 gen_store_spr(SPR_MQ, t2);
4675 tcg_gen_shri_i64(t1, t0, 32);
4676 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4677 tcg_gen_ext32s_i64(t1, t0);
4678 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4679 tcg_gen_movi_tl(cpu_ov, 1);
4680 tcg_gen_movi_tl(cpu_so, 1);
4681 gen_set_label(l1);
4682 tcg_temp_free_i64(t0);
4683 tcg_temp_free_i64(t1);
4684 tcg_temp_free(t2);
4685 if (unlikely(Rc(ctx->opcode) != 0))
4686 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4687 }
4688
4689 /* nabs - nabs. */
4690 static void gen_nabs(DisasContext *ctx)
4691 {
4692 TCGLabel *l1 = gen_new_label();
4693 TCGLabel *l2 = gen_new_label();
4694 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4695 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4696 tcg_gen_br(l2);
4697 gen_set_label(l1);
4698 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4699 gen_set_label(l2);
4700 if (unlikely(Rc(ctx->opcode) != 0))
4701 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4702 }
4703
4704 /* nabso - nabso. */
4705 static void gen_nabso(DisasContext *ctx)
4706 {
4707 TCGLabel *l1 = gen_new_label();
4708 TCGLabel *l2 = gen_new_label();
4709 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4710 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4711 tcg_gen_br(l2);
4712 gen_set_label(l1);
4713 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4714 gen_set_label(l2);
4715 /* nabs never overflows */
4716 tcg_gen_movi_tl(cpu_ov, 0);
4717 if (unlikely(Rc(ctx->opcode) != 0))
4718 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4719 }
4720
4721 /* rlmi - rlmi. */
4722 static void gen_rlmi(DisasContext *ctx)
4723 {
4724 uint32_t mb = MB(ctx->opcode);
4725 uint32_t me = ME(ctx->opcode);
4726 TCGv t0 = tcg_temp_new();
4727 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4728 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4729 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4730 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4731 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4732 tcg_temp_free(t0);
4733 if (unlikely(Rc(ctx->opcode) != 0))
4734 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4735 }
4736
4737 /* rrib - rrib. */
4738 static void gen_rrib(DisasContext *ctx)
4739 {
4740 TCGv t0 = tcg_temp_new();
4741 TCGv t1 = tcg_temp_new();
4742 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4743 tcg_gen_movi_tl(t1, 0x80000000);
4744 tcg_gen_shr_tl(t1, t1, t0);
4745 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4746 tcg_gen_and_tl(t0, t0, t1);
4747 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4748 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4749 tcg_temp_free(t0);
4750 tcg_temp_free(t1);
4751 if (unlikely(Rc(ctx->opcode) != 0))
4752 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4753 }
4754
4755 /* sle - sle. */
4756 static void gen_sle(DisasContext *ctx)
4757 {
4758 TCGv t0 = tcg_temp_new();
4759 TCGv t1 = tcg_temp_new();
4760 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4761 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4762 tcg_gen_subfi_tl(t1, 32, t1);
4763 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4764 tcg_gen_or_tl(t1, t0, t1);
4765 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4766 gen_store_spr(SPR_MQ, t1);
4767 tcg_temp_free(t0);
4768 tcg_temp_free(t1);
4769 if (unlikely(Rc(ctx->opcode) != 0))
4770 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4771 }
4772
4773 /* sleq - sleq. */
4774 static void gen_sleq(DisasContext *ctx)
4775 {
4776 TCGv t0 = tcg_temp_new();
4777 TCGv t1 = tcg_temp_new();
4778 TCGv t2 = tcg_temp_new();
4779 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4780 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4781 tcg_gen_shl_tl(t2, t2, t0);
4782 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4783 gen_load_spr(t1, SPR_MQ);
4784 gen_store_spr(SPR_MQ, t0);
4785 tcg_gen_and_tl(t0, t0, t2);
4786 tcg_gen_andc_tl(t1, t1, t2);
4787 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4788 tcg_temp_free(t0);
4789 tcg_temp_free(t1);
4790 tcg_temp_free(t2);
4791 if (unlikely(Rc(ctx->opcode) != 0))
4792 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4793 }
4794
4795 /* sliq - sliq. */
4796 static void gen_sliq(DisasContext *ctx)
4797 {
4798 int sh = SH(ctx->opcode);
4799 TCGv t0 = tcg_temp_new();
4800 TCGv t1 = tcg_temp_new();
4801 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4802 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4803 tcg_gen_or_tl(t1, t0, t1);
4804 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4805 gen_store_spr(SPR_MQ, t1);
4806 tcg_temp_free(t0);
4807 tcg_temp_free(t1);
4808 if (unlikely(Rc(ctx->opcode) != 0))
4809 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4810 }
4811
4812 /* slliq - slliq. */
4813 static void gen_slliq(DisasContext *ctx)
4814 {
4815 int sh = SH(ctx->opcode);
4816 TCGv t0 = tcg_temp_new();
4817 TCGv t1 = tcg_temp_new();
4818 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4819 gen_load_spr(t1, SPR_MQ);
4820 gen_store_spr(SPR_MQ, t0);
4821 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4822 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4823 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4824 tcg_temp_free(t0);
4825 tcg_temp_free(t1);
4826 if (unlikely(Rc(ctx->opcode) != 0))
4827 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4828 }
4829
4830 /* sllq - sllq. */
4831 static void gen_sllq(DisasContext *ctx)
4832 {
4833 TCGLabel *l1 = gen_new_label();
4834 TCGLabel *l2 = gen_new_label();
4835 TCGv t0 = tcg_temp_local_new();
4836 TCGv t1 = tcg_temp_local_new();
4837 TCGv t2 = tcg_temp_local_new();
4838 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4839 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4840 tcg_gen_shl_tl(t1, t1, t2);
4841 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4842 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4843 gen_load_spr(t0, SPR_MQ);
4844 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4845 tcg_gen_br(l2);
4846 gen_set_label(l1);
4847 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4848 gen_load_spr(t2, SPR_MQ);
4849 tcg_gen_andc_tl(t1, t2, t1);
4850 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4851 gen_set_label(l2);
4852 tcg_temp_free(t0);
4853 tcg_temp_free(t1);
4854 tcg_temp_free(t2);
4855 if (unlikely(Rc(ctx->opcode) != 0))
4856 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4857 }
4858
4859 /* slq - slq. */
4860 static void gen_slq(DisasContext *ctx)
4861 {
4862 TCGLabel *l1 = gen_new_label();
4863 TCGv t0 = tcg_temp_new();
4864 TCGv t1 = tcg_temp_new();
4865 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4866 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4867 tcg_gen_subfi_tl(t1, 32, t1);
4868 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4869 tcg_gen_or_tl(t1, t0, t1);
4870 gen_store_spr(SPR_MQ, t1);
4871 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4872 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4873 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4874 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4875 gen_set_label(l1);
4876 tcg_temp_free(t0);
4877 tcg_temp_free(t1);
4878 if (unlikely(Rc(ctx->opcode) != 0))
4879 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4880 }
4881
4882 /* sraiq - sraiq. */
4883 static void gen_sraiq(DisasContext *ctx)
4884 {
4885 int sh = SH(ctx->opcode);
4886 TCGLabel *l1 = gen_new_label();
4887 TCGv t0 = tcg_temp_new();
4888 TCGv t1 = tcg_temp_new();
4889 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4890 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4891 tcg_gen_or_tl(t0, t0, t1);
4892 gen_store_spr(SPR_MQ, t0);
4893 tcg_gen_movi_tl(cpu_ca, 0);
4894 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4895 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4896 tcg_gen_movi_tl(cpu_ca, 1);
4897 gen_set_label(l1);
4898 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4899 tcg_temp_free(t0);
4900 tcg_temp_free(t1);
4901 if (unlikely(Rc(ctx->opcode) != 0))
4902 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4903 }
4904
4905 /* sraq - sraq. */
4906 static void gen_sraq(DisasContext *ctx)
4907 {
4908 TCGLabel *l1 = gen_new_label();
4909 TCGLabel *l2 = gen_new_label();
4910 TCGv t0 = tcg_temp_new();
4911 TCGv t1 = tcg_temp_local_new();
4912 TCGv t2 = tcg_temp_local_new();
4913 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4914 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4915 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4916 tcg_gen_subfi_tl(t2, 32, t2);
4917 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4918 tcg_gen_or_tl(t0, t0, t2);
4919 gen_store_spr(SPR_MQ, t0);
4920 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4921 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4922 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4923 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4924 gen_set_label(l1);
4925 tcg_temp_free(t0);
4926 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4927 tcg_gen_movi_tl(cpu_ca, 0);
4928 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4929 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4930 tcg_gen_movi_tl(cpu_ca, 1);
4931 gen_set_label(l2);
4932 tcg_temp_free(t1);
4933 tcg_temp_free(t2);
4934 if (unlikely(Rc(ctx->opcode) != 0))
4935 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4936 }
4937
4938 /* sre - sre. */
4939 static void gen_sre(DisasContext *ctx)
4940 {
4941 TCGv t0 = tcg_temp_new();
4942 TCGv t1 = tcg_temp_new();
4943 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4944 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4945 tcg_gen_subfi_tl(t1, 32, t1);
4946 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4947 tcg_gen_or_tl(t1, t0, t1);
4948 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4949 gen_store_spr(SPR_MQ, t1);
4950 tcg_temp_free(t0);
4951 tcg_temp_free(t1);
4952 if (unlikely(Rc(ctx->opcode) != 0))
4953 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4954 }
4955
4956 /* srea - srea. */
4957 static void gen_srea(DisasContext *ctx)
4958 {
4959 TCGv t0 = tcg_temp_new();
4960 TCGv t1 = tcg_temp_new();
4961 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4962 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4963 gen_store_spr(SPR_MQ, t0);
4964 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4965 tcg_temp_free(t0);
4966 tcg_temp_free(t1);
4967 if (unlikely(Rc(ctx->opcode) != 0))
4968 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4969 }
4970
4971 /* sreq */
4972 static void gen_sreq(DisasContext *ctx)
4973 {
4974 TCGv t0 = tcg_temp_new();
4975 TCGv t1 = tcg_temp_new();
4976 TCGv t2 = tcg_temp_new();
4977 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4978 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4979 tcg_gen_shr_tl(t1, t1, t0);
4980 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4981 gen_load_spr(t2, SPR_MQ);
4982 gen_store_spr(SPR_MQ, t0);
4983 tcg_gen_and_tl(t0, t0, t1);
4984 tcg_gen_andc_tl(t2, t2, t1);
4985 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4986 tcg_temp_free(t0);
4987 tcg_temp_free(t1);
4988 tcg_temp_free(t2);
4989 if (unlikely(Rc(ctx->opcode) != 0))
4990 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4991 }
4992
4993 /* sriq */
4994 static void gen_sriq(DisasContext *ctx)
4995 {
4996 int sh = SH(ctx->opcode);
4997 TCGv t0 = tcg_temp_new();
4998 TCGv t1 = tcg_temp_new();
4999 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5000 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5001 tcg_gen_or_tl(t1, t0, t1);
5002 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5003 gen_store_spr(SPR_MQ, t1);
5004 tcg_temp_free(t0);
5005 tcg_temp_free(t1);
5006 if (unlikely(Rc(ctx->opcode) != 0))
5007 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5008 }
5009
5010 /* srliq */
5011 static void gen_srliq(DisasContext *ctx)
5012 {
5013 int sh = SH(ctx->opcode);
5014 TCGv t0 = tcg_temp_new();
5015 TCGv t1 = tcg_temp_new();
5016 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5017 gen_load_spr(t1, SPR_MQ);
5018 gen_store_spr(SPR_MQ, t0);
5019 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5020 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5021 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5022 tcg_temp_free(t0);
5023 tcg_temp_free(t1);
5024 if (unlikely(Rc(ctx->opcode) != 0))
5025 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5026 }
5027
5028 /* srlq */
5029 static void gen_srlq(DisasContext *ctx)
5030 {
5031 TCGLabel *l1 = gen_new_label();
5032 TCGLabel *l2 = gen_new_label();
5033 TCGv t0 = tcg_temp_local_new();
5034 TCGv t1 = tcg_temp_local_new();
5035 TCGv t2 = tcg_temp_local_new();
5036 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5037 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5038 tcg_gen_shr_tl(t2, t1, t2);
5039 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5040 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5041 gen_load_spr(t0, SPR_MQ);
5042 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5043 tcg_gen_br(l2);
5044 gen_set_label(l1);
5045 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5046 tcg_gen_and_tl(t0, t0, t2);
5047 gen_load_spr(t1, SPR_MQ);
5048 tcg_gen_andc_tl(t1, t1, t2);
5049 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5050 gen_set_label(l2);
5051 tcg_temp_free(t0);
5052 tcg_temp_free(t1);
5053 tcg_temp_free(t2);
5054 if (unlikely(Rc(ctx->opcode) != 0))
5055 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5056 }
5057
5058 /* srq */
5059 static void gen_srq(DisasContext *ctx)
5060 {
5061 TCGLabel *l1 = gen_new_label();
5062 TCGv t0 = tcg_temp_new();
5063 TCGv t1 = tcg_temp_new();
5064 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5065 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5066 tcg_gen_subfi_tl(t1, 32, t1);
5067 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5068 tcg_gen_or_tl(t1, t0, t1);
5069 gen_store_spr(SPR_MQ, t1);
5070 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5071 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5072 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5073 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5074 gen_set_label(l1);
5075 tcg_temp_free(t0);
5076 tcg_temp_free(t1);
5077 if (unlikely(Rc(ctx->opcode) != 0))
5078 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5079 }
5080
5081 /* PowerPC 602 specific instructions */
5082
5083 /* dsa */
5084 static void gen_dsa(DisasContext *ctx)
5085 {
5086 /* XXX: TODO */
5087 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5088 }
5089
5090 /* esa */
5091 static void gen_esa(DisasContext *ctx)
5092 {
5093 /* XXX: TODO */
5094 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5095 }
5096
5097 /* mfrom */
5098 static void gen_mfrom(DisasContext *ctx)
5099 {
5100 #if defined(CONFIG_USER_ONLY)
5101 GEN_PRIV;
5102 #else
5103 CHK_SV;
5104 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5105 #endif /* defined(CONFIG_USER_ONLY) */
5106 }
5107
5108 /* 602 - 603 - G2 TLB management */
5109
5110 /* tlbld */
5111 static void gen_tlbld_6xx(DisasContext *ctx)
5112 {
5113 #if defined(CONFIG_USER_ONLY)
5114 GEN_PRIV;
5115 #else
5116 CHK_SV;
5117 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5118 #endif /* defined(CONFIG_USER_ONLY) */
5119 }
5120
5121 /* tlbli */
5122 static void gen_tlbli_6xx(DisasContext *ctx)
5123 {
5124 #if defined(CONFIG_USER_ONLY)
5125 GEN_PRIV;
5126 #else
5127 CHK_SV;
5128 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5129 #endif /* defined(CONFIG_USER_ONLY) */
5130 }
5131
5132 /* 74xx TLB management */
5133
5134 /* tlbld */
5135 static void gen_tlbld_74xx(DisasContext *ctx)
5136 {
5137 #if defined(CONFIG_USER_ONLY)
5138 GEN_PRIV;
5139 #else
5140 CHK_SV;
5141 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5142 #endif /* defined(CONFIG_USER_ONLY) */
5143 }
5144
5145 /* tlbli */
5146 static void gen_tlbli_74xx(DisasContext *ctx)
5147 {
5148 #if defined(CONFIG_USER_ONLY)
5149 GEN_PRIV;
5150 #else
5151 CHK_SV;
5152 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5153 #endif /* defined(CONFIG_USER_ONLY) */
5154 }
5155
5156 /* POWER instructions not in PowerPC 601 */
5157
5158 /* clf */
5159 static void gen_clf(DisasContext *ctx)
5160 {
5161 /* Cache line flush: implemented as no-op */
5162 }
5163
5164 /* cli */
5165 static void gen_cli(DisasContext *ctx)
5166 {
5167 #if defined(CONFIG_USER_ONLY)
5168 GEN_PRIV;
5169 #else
5170 /* Cache line invalidate: privileged and treated as no-op */
5171 CHK_SV;
5172 #endif /* defined(CONFIG_USER_ONLY) */
5173 }
5174
5175 /* dclst */
5176 static void gen_dclst(DisasContext *ctx)
5177 {
5178 /* Data cache line store: treated as no-op */
5179 }
5180
5181 static void gen_mfsri(DisasContext *ctx)
5182 {
5183 #if defined(CONFIG_USER_ONLY)
5184 GEN_PRIV;
5185 #else
5186 int ra = rA(ctx->opcode);
5187 int rd = rD(ctx->opcode);
5188 TCGv t0;
5189
5190 CHK_SV;
5191 t0 = tcg_temp_new();
5192 gen_addr_reg_index(ctx, t0);
5193 tcg_gen_shri_tl(t0, t0, 28);
5194 tcg_gen_andi_tl(t0, t0, 0xF);
5195 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5196 tcg_temp_free(t0);
5197 if (ra != 0 && ra != rd)
5198 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5199 #endif /* defined(CONFIG_USER_ONLY) */
5200 }
5201
5202 static void gen_rac(DisasContext *ctx)
5203 {
5204 #if defined(CONFIG_USER_ONLY)
5205 GEN_PRIV;
5206 #else
5207 TCGv t0;
5208
5209 CHK_SV;
5210 t0 = tcg_temp_new();
5211 gen_addr_reg_index(ctx, t0);
5212 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5213 tcg_temp_free(t0);
5214 #endif /* defined(CONFIG_USER_ONLY) */
5215 }
5216
5217 static void gen_rfsvc(DisasContext *ctx)
5218 {
5219 #if defined(CONFIG_USER_ONLY)
5220 GEN_PRIV;
5221 #else
5222 CHK_SV;
5223
5224 gen_helper_rfsvc(cpu_env);
5225 gen_sync_exception(ctx);
5226 #endif /* defined(CONFIG_USER_ONLY) */
5227 }
5228
5229 #include "translate/fp-impl.c"
5230
5231 #include "translate/vmx-impl.c"
5232
5233 #include "translate/vsx-impl.c"
5234
5235 /* svc is not implemented for now */
5236
5237 /* BookE specific instructions */
5238
5239 /* XXX: not implemented on 440 ? */
5240 static void gen_mfapidi(DisasContext *ctx)
5241 {
5242 /* XXX: TODO */
5243 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5244 }
5245
5246 /* XXX: not implemented on 440 ? */
5247 static void gen_tlbiva(DisasContext *ctx)
5248 {
5249 #if defined(CONFIG_USER_ONLY)
5250 GEN_PRIV;
5251 #else
5252 TCGv t0;
5253
5254 CHK_SV;
5255 t0 = tcg_temp_new();
5256 gen_addr_reg_index(ctx, t0);
5257 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5258 tcg_temp_free(t0);
5259 #endif /* defined(CONFIG_USER_ONLY) */
5260 }
5261
5262 /* All 405 MAC instructions are translated here */
5263 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5264 int ra, int rb, int rt, int Rc)
5265 {
5266 TCGv t0, t1;
5267
5268 t0 = tcg_temp_local_new();
5269 t1 = tcg_temp_local_new();
5270
5271 switch (opc3 & 0x0D) {
5272 case 0x05:
5273 /* macchw - macchw. - macchwo - macchwo. */
5274 /* macchws - macchws. - macchwso - macchwso. */
5275 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5276 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5277 /* mulchw - mulchw. */
5278 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5279 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5280 tcg_gen_ext16s_tl(t1, t1);
5281 break;
5282 case 0x04:
5283 /* macchwu - macchwu. - macchwuo - macchwuo. */
5284 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5285 /* mulchwu - mulchwu. */
5286 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5287 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5288 tcg_gen_ext16u_tl(t1, t1);
5289 break;
5290 case 0x01:
5291 /* machhw - machhw. - machhwo - machhwo. */
5292 /* machhws - machhws. - machhwso - machhwso. */
5293 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5294 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5295 /* mulhhw - mulhhw. */
5296 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5297 tcg_gen_ext16s_tl(t0, t0);
5298 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5299 tcg_gen_ext16s_tl(t1, t1);
5300 break;
5301 case 0x00:
5302 /* machhwu - machhwu. - machhwuo - machhwuo. */
5303 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5304 /* mulhhwu - mulhhwu. */
5305 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5306 tcg_gen_ext16u_tl(t0, t0);
5307 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5308 tcg_gen_ext16u_tl(t1, t1);
5309 break;
5310 case 0x0D:
5311 /* maclhw - maclhw. - maclhwo - maclhwo. */
5312 /* maclhws - maclhws. - maclhwso - maclhwso. */
5313 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5314 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5315 /* mullhw - mullhw. */
5316 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5317 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5318 break;
5319 case 0x0C:
5320 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5321 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5322 /* mullhwu - mullhwu. */
5323 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5324 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5325 break;
5326 }
5327 if (opc2 & 0x04) {
5328 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5329 tcg_gen_mul_tl(t1, t0, t1);
5330 if (opc2 & 0x02) {
5331 /* nmultiply-and-accumulate (0x0E) */
5332 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5333 } else {
5334 /* multiply-and-accumulate (0x0C) */
5335 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5336 }
5337
5338 if (opc3 & 0x12) {
5339 /* Check overflow and/or saturate */
5340 TCGLabel *l1 = gen_new_label();
5341
5342 if (opc3 & 0x10) {
5343 /* Start with XER OV disabled, the most likely case */
5344 tcg_gen_movi_tl(cpu_ov, 0);
5345 }
5346 if (opc3 & 0x01) {
5347 /* Signed */
5348 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5349 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5350 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5351 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5352 if (opc3 & 0x02) {
5353 /* Saturate */
5354 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5355 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5356 }
5357 } else {
5358 /* Unsigned */
5359 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5360 if (opc3 & 0x02) {
5361 /* Saturate */
5362 tcg_gen_movi_tl(t0, UINT32_MAX);
5363 }
5364 }
5365 if (opc3 & 0x10) {
5366 /* Check overflow */
5367 tcg_gen_movi_tl(cpu_ov, 1);
5368 tcg_gen_movi_tl(cpu_so, 1);
5369 }
5370 gen_set_label(l1);
5371 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5372 }
5373 } else {
5374 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5375 }
5376 tcg_temp_free(t0);
5377 tcg_temp_free(t1);
5378 if (unlikely(Rc) != 0) {
5379 /* Update Rc0 */
5380 gen_set_Rc0(ctx, cpu_gpr[rt]);
5381 }
5382 }
5383
5384 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5385 static void glue(gen_, name)(DisasContext *ctx) \
5386 { \
5387 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5388 rD(ctx->opcode), Rc(ctx->opcode)); \
5389 }
5390
5391 /* macchw - macchw. */
5392 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5393 /* macchwo - macchwo. */
5394 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5395 /* macchws - macchws. */
5396 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5397 /* macchwso - macchwso. */
5398 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5399 /* macchwsu - macchwsu. */
5400 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5401 /* macchwsuo - macchwsuo. */
5402 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5403 /* macchwu - macchwu. */
5404 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5405 /* macchwuo - macchwuo. */
5406 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5407 /* machhw - machhw. */
5408 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5409 /* machhwo - machhwo. */
5410 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5411 /* machhws - machhws. */
5412 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5413 /* machhwso - machhwso. */
5414 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5415 /* machhwsu - machhwsu. */
5416 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5417 /* machhwsuo - machhwsuo. */
5418 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5419 /* machhwu - machhwu. */
5420 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5421 /* machhwuo - machhwuo. */
5422 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5423 /* maclhw - maclhw. */
5424 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5425 /* maclhwo - maclhwo. */
5426 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5427 /* maclhws - maclhws. */
5428 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5429 /* maclhwso - maclhwso. */
5430 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5431 /* maclhwu - maclhwu. */
5432 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5433 /* maclhwuo - maclhwuo. */
5434 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5435 /* maclhwsu - maclhwsu. */
5436 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5437 /* maclhwsuo - maclhwsuo. */
5438 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5439 /* nmacchw - nmacchw. */
5440 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5441 /* nmacchwo - nmacchwo. */
5442 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5443 /* nmacchws - nmacchws. */
5444 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5445 /* nmacchwso - nmacchwso. */
5446 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5447 /* nmachhw - nmachhw. */
5448 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5449 /* nmachhwo - nmachhwo. */
5450 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5451 /* nmachhws - nmachhws. */
5452 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5453 /* nmachhwso - nmachhwso. */
5454 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5455 /* nmaclhw - nmaclhw. */
5456 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5457 /* nmaclhwo - nmaclhwo. */
5458 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5459 /* nmaclhws - nmaclhws. */
5460 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5461 /* nmaclhwso - nmaclhwso. */
5462 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5463
5464 /* mulchw - mulchw. */
5465 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5466 /* mulchwu - mulchwu. */
5467 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5468 /* mulhhw - mulhhw. */
5469 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5470 /* mulhhwu - mulhhwu. */
5471 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5472 /* mullhw - mullhw. */
5473 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5474 /* mullhwu - mullhwu. */
5475 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5476
5477 /* mfdcr */
5478 static void gen_mfdcr(DisasContext *ctx)
5479 {
5480 #if defined(CONFIG_USER_ONLY)
5481 GEN_PRIV;
5482 #else
5483 TCGv dcrn;
5484
5485 CHK_SV;
5486 dcrn = tcg_const_tl(SPR(ctx->opcode));
5487 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5488 tcg_temp_free(dcrn);
5489 #endif /* defined(CONFIG_USER_ONLY) */
5490 }
5491
5492 /* mtdcr */
5493 static void gen_mtdcr(DisasContext *ctx)
5494 {
5495 #if defined(CONFIG_USER_ONLY)
5496 GEN_PRIV;
5497 #else
5498 TCGv dcrn;
5499
5500 CHK_SV;
5501 dcrn = tcg_const_tl(SPR(ctx->opcode));
5502 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5503 tcg_temp_free(dcrn);
5504 #endif /* defined(CONFIG_USER_ONLY) */
5505 }
5506
5507 /* mfdcrx */
5508 /* XXX: not implemented on 440 ? */
5509 static void gen_mfdcrx(DisasContext *ctx)
5510 {
5511 #if defined(CONFIG_USER_ONLY)
5512 GEN_PRIV;
5513 #else
5514 CHK_SV;
5515 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5516 cpu_gpr[rA(ctx->opcode)]);
5517 /* Note: Rc update flag set leads to undefined state of Rc0 */
5518 #endif /* defined(CONFIG_USER_ONLY) */
5519 }
5520
5521 /* mtdcrx */
5522 /* XXX: not implemented on 440 ? */
5523 static void gen_mtdcrx(DisasContext *ctx)
5524 {
5525 #if defined(CONFIG_USER_ONLY)
5526 GEN_PRIV;
5527 #else
5528 CHK_SV;
5529 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5530 cpu_gpr[rS(ctx->opcode)]);
5531 /* Note: Rc update flag set leads to undefined state of Rc0 */
5532 #endif /* defined(CONFIG_USER_ONLY) */
5533 }
5534
5535 /* mfdcrux (PPC 460) : user-mode access to DCR */
5536 static void gen_mfdcrux(DisasContext *ctx)
5537 {
5538 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5539 cpu_gpr[rA(ctx->opcode)]);
5540 /* Note: Rc update flag set leads to undefined state of Rc0 */
5541 }
5542
5543 /* mtdcrux (PPC 460) : user-mode access to DCR */
5544 static void gen_mtdcrux(DisasContext *ctx)
5545 {
5546 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5547 cpu_gpr[rS(ctx->opcode)]);
5548 /* Note: Rc update flag set leads to undefined state of Rc0 */
5549 }
5550
5551 /* dccci */
5552 static void gen_dccci(DisasContext *ctx)
5553 {
5554 CHK_SV;
5555 /* interpreted as no-op */
5556 }
5557
5558 /* dcread */
5559 static void gen_dcread(DisasContext *ctx)
5560 {
5561 #if defined(CONFIG_USER_ONLY)
5562 GEN_PRIV;
5563 #else
5564 TCGv EA, val;
5565
5566 CHK_SV;
5567 gen_set_access_type(ctx, ACCESS_CACHE);
5568 EA = tcg_temp_new();
5569 gen_addr_reg_index(ctx, EA);
5570 val = tcg_temp_new();
5571 gen_qemu_ld32u(ctx, val, EA);
5572 tcg_temp_free(val);
5573 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5574 tcg_temp_free(EA);
5575 #endif /* defined(CONFIG_USER_ONLY) */
5576 }
5577
5578 /* icbt */
5579 static void gen_icbt_40x(DisasContext *ctx)
5580 {
5581 /* interpreted as no-op */
5582 /* XXX: specification say this is treated as a load by the MMU
5583 * but does not generate any exception
5584 */
5585 }
5586
5587 /* iccci */
5588 static void gen_iccci(DisasContext *ctx)
5589 {
5590 CHK_SV;
5591 /* interpreted as no-op */
5592 }
5593
5594 /* icread */
5595 static void gen_icread(DisasContext *ctx)
5596 {
5597 CHK_SV;
5598 /* interpreted as no-op */
5599 }
5600
5601 /* rfci (supervisor only) */
5602 static void gen_rfci_40x(DisasContext *ctx)
5603 {
5604 #if defined(CONFIG_USER_ONLY)
5605 GEN_PRIV;
5606 #else
5607 CHK_SV;
5608 /* Restore CPU state */
5609 gen_helper_40x_rfci(cpu_env);
5610 gen_sync_exception(ctx);
5611 #endif /* defined(CONFIG_USER_ONLY) */
5612 }
5613
5614 static void gen_rfci(DisasContext *ctx)
5615 {
5616 #if defined(CONFIG_USER_ONLY)
5617 GEN_PRIV;
5618 #else
5619 CHK_SV;
5620 /* Restore CPU state */
5621 gen_helper_rfci(cpu_env);
5622 gen_sync_exception(ctx);
5623 #endif /* defined(CONFIG_USER_ONLY) */
5624 }
5625
5626 /* BookE specific */
5627
5628 /* XXX: not implemented on 440 ? */
5629 static void gen_rfdi(DisasContext *ctx)
5630 {
5631 #if defined(CONFIG_USER_ONLY)
5632 GEN_PRIV;
5633 #else
5634 CHK_SV;
5635 /* Restore CPU state */
5636 gen_helper_rfdi(cpu_env);
5637 gen_sync_exception(ctx);
5638 #endif /* defined(CONFIG_USER_ONLY) */
5639 }
5640
5641 /* XXX: not implemented on 440 ? */
5642 static void gen_rfmci(DisasContext *ctx)
5643 {
5644 #if defined(CONFIG_USER_ONLY)
5645 GEN_PRIV;
5646 #else
5647 CHK_SV;
5648 /* Restore CPU state */
5649 gen_helper_rfmci(cpu_env);
5650 gen_sync_exception(ctx);
5651 #endif /* defined(CONFIG_USER_ONLY) */
5652 }
5653
5654 /* TLB management - PowerPC 405 implementation */
5655
5656 /* tlbre */
5657 static void gen_tlbre_40x(DisasContext *ctx)
5658 {
5659 #if defined(CONFIG_USER_ONLY)
5660 GEN_PRIV;
5661 #else
5662 CHK_SV;
5663 switch (rB(ctx->opcode)) {
5664 case 0:
5665 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5666 cpu_gpr[rA(ctx->opcode)]);
5667 break;
5668 case 1:
5669 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5670 cpu_gpr[rA(ctx->opcode)]);
5671 break;
5672 default:
5673 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5674 break;
5675 }
5676 #endif /* defined(CONFIG_USER_ONLY) */
5677 }
5678
5679 /* tlbsx - tlbsx. */
5680 static void gen_tlbsx_40x(DisasContext *ctx)
5681 {
5682 #if defined(CONFIG_USER_ONLY)
5683 GEN_PRIV;
5684 #else
5685 TCGv t0;
5686
5687 CHK_SV;
5688 t0 = tcg_temp_new();
5689 gen_addr_reg_index(ctx, t0);
5690 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5691 tcg_temp_free(t0);
5692 if (Rc(ctx->opcode)) {
5693 TCGLabel *l1 = gen_new_label();
5694 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5695 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5696 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5697 gen_set_label(l1);
5698 }
5699 #endif /* defined(CONFIG_USER_ONLY) */
5700 }
5701
5702 /* tlbwe */
5703 static void gen_tlbwe_40x(DisasContext *ctx)
5704 {
5705 #if defined(CONFIG_USER_ONLY)
5706 GEN_PRIV;
5707 #else
5708 CHK_SV;
5709
5710 switch (rB(ctx->opcode)) {
5711 case 0:
5712 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5713 cpu_gpr[rS(ctx->opcode)]);
5714 break;
5715 case 1:
5716 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5717 cpu_gpr[rS(ctx->opcode)]);
5718 break;
5719 default:
5720 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5721 break;
5722 }
5723 #endif /* defined(CONFIG_USER_ONLY) */
5724 }
5725
5726 /* TLB management - PowerPC 440 implementation */
5727
5728 /* tlbre */
5729 static void gen_tlbre_440(DisasContext *ctx)
5730 {
5731 #if defined(CONFIG_USER_ONLY)
5732 GEN_PRIV;
5733 #else
5734 CHK_SV;
5735
5736 switch (rB(ctx->opcode)) {
5737 case 0:
5738 case 1:
5739 case 2:
5740 {
5741 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5742 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5743 t0, cpu_gpr[rA(ctx->opcode)]);
5744 tcg_temp_free_i32(t0);
5745 }
5746 break;
5747 default:
5748 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5749 break;
5750 }
5751 #endif /* defined(CONFIG_USER_ONLY) */
5752 }
5753
5754 /* tlbsx - tlbsx. */
5755 static void gen_tlbsx_440(DisasContext *ctx)
5756 {
5757 #if defined(CONFIG_USER_ONLY)
5758 GEN_PRIV;
5759 #else
5760 TCGv t0;
5761
5762 CHK_SV;
5763 t0 = tcg_temp_new();
5764 gen_addr_reg_index(ctx, t0);
5765 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5766 tcg_temp_free(t0);
5767 if (Rc(ctx->opcode)) {
5768 TCGLabel *l1 = gen_new_label();
5769 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5770 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5771 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5772 gen_set_label(l1);
5773 }
5774 #endif /* defined(CONFIG_USER_ONLY) */
5775 }
5776
5777 /* tlbwe */
5778 static void gen_tlbwe_440(DisasContext *ctx)
5779 {
5780 #if defined(CONFIG_USER_ONLY)
5781 GEN_PRIV;
5782 #else
5783 CHK_SV;
5784 switch (rB(ctx->opcode)) {
5785 case 0:
5786 case 1:
5787 case 2:
5788 {
5789 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5790 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5791 cpu_gpr[rS(ctx->opcode)]);
5792 tcg_temp_free_i32(t0);
5793 }
5794 break;
5795 default:
5796 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5797 break;
5798 }
5799 #endif /* defined(CONFIG_USER_ONLY) */
5800 }
5801
5802 /* TLB management - PowerPC BookE 2.06 implementation */
5803
5804 /* tlbre */
5805 static void gen_tlbre_booke206(DisasContext *ctx)
5806 {
5807 #if defined(CONFIG_USER_ONLY)
5808 GEN_PRIV;
5809 #else
5810 CHK_SV;
5811 gen_helper_booke206_tlbre(cpu_env);
5812 #endif /* defined(CONFIG_USER_ONLY) */
5813 }
5814
5815 /* tlbsx - tlbsx. */
5816 static void gen_tlbsx_booke206(DisasContext *ctx)
5817 {
5818 #if defined(CONFIG_USER_ONLY)
5819 GEN_PRIV;
5820 #else
5821 TCGv t0;
5822
5823 CHK_SV;
5824 if (rA(ctx->opcode)) {
5825 t0 = tcg_temp_new();
5826 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
5827 } else {
5828 t0 = tcg_const_tl(0);
5829 }
5830
5831 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
5832 gen_helper_booke206_tlbsx(cpu_env, t0);
5833 tcg_temp_free(t0);
5834 #endif /* defined(CONFIG_USER_ONLY) */
5835 }
5836
5837 /* tlbwe */
5838 static void gen_tlbwe_booke206(DisasContext *ctx)
5839 {
5840 #if defined(CONFIG_USER_ONLY)
5841 GEN_PRIV;
5842 #else
5843 CHK_SV;
5844 gen_helper_booke206_tlbwe(cpu_env);
5845 #endif /* defined(CONFIG_USER_ONLY) */
5846 }
5847
5848 static void gen_tlbivax_booke206(DisasContext *ctx)
5849 {
5850 #if defined(CONFIG_USER_ONLY)
5851 GEN_PRIV;
5852 #else
5853 TCGv t0;
5854
5855 CHK_SV;
5856 t0 = tcg_temp_new();
5857 gen_addr_reg_index(ctx, t0);
5858 gen_helper_booke206_tlbivax(cpu_env, t0);
5859 tcg_temp_free(t0);
5860 #endif /* defined(CONFIG_USER_ONLY) */
5861 }
5862
5863 static void gen_tlbilx_booke206(DisasContext *ctx)
5864 {
5865 #if defined(CONFIG_USER_ONLY)
5866 GEN_PRIV;
5867 #else
5868 TCGv t0;
5869
5870 CHK_SV;
5871 t0 = tcg_temp_new();
5872 gen_addr_reg_index(ctx, t0);
5873
5874 switch((ctx->opcode >> 21) & 0x3) {
5875 case 0:
5876 gen_helper_booke206_tlbilx0(cpu_env, t0);
5877 break;
5878 case 1:
5879 gen_helper_booke206_tlbilx1(cpu_env, t0);
5880 break;
5881 case 3:
5882 gen_helper_booke206_tlbilx3(cpu_env, t0);
5883 break;
5884 default:
5885 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5886 break;
5887 }
5888
5889 tcg_temp_free(t0);
5890 #endif /* defined(CONFIG_USER_ONLY) */
5891 }
5892
5893
5894 /* wrtee */
5895 static void gen_wrtee(DisasContext *ctx)
5896 {
5897 #if defined(CONFIG_USER_ONLY)
5898 GEN_PRIV;
5899 #else
5900 TCGv t0;
5901
5902 CHK_SV;
5903 t0 = tcg_temp_new();
5904 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
5905 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5906 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
5907 tcg_temp_free(t0);
5908 /* Stop translation to have a chance to raise an exception
5909 * if we just set msr_ee to 1
5910 */
5911 gen_stop_exception(ctx);
5912 #endif /* defined(CONFIG_USER_ONLY) */
5913 }
5914
5915 /* wrteei */
5916 static void gen_wrteei(DisasContext *ctx)
5917 {
5918 #if defined(CONFIG_USER_ONLY)
5919 GEN_PRIV;
5920 #else
5921 CHK_SV;
5922 if (ctx->opcode & 0x00008000) {
5923 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
5924 /* Stop translation to have a chance to raise an exception */
5925 gen_stop_exception(ctx);
5926 } else {
5927 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
5928 }
5929 #endif /* defined(CONFIG_USER_ONLY) */
5930 }
5931
5932 /* PowerPC 440 specific instructions */
5933
5934 /* dlmzb */
5935 static void gen_dlmzb(DisasContext *ctx)
5936 {
5937 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
5938 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
5939 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
5940 tcg_temp_free_i32(t0);
5941 }
5942
5943 /* mbar replaces eieio on 440 */
5944 static void gen_mbar(DisasContext *ctx)
5945 {
5946 /* interpreted as no-op */
5947 }
5948
5949 /* msync replaces sync on 440 */
5950 static void gen_msync_4xx(DisasContext *ctx)
5951 {
5952 /* interpreted as no-op */
5953 }
5954
5955 /* icbt */
5956 static void gen_icbt_440(DisasContext *ctx)
5957 {
5958 /* interpreted as no-op */
5959 /* XXX: specification say this is treated as a load by the MMU
5960 * but does not generate any exception
5961 */
5962 }
5963
5964 /* Embedded.Processor Control */
5965
5966 static void gen_msgclr(DisasContext *ctx)
5967 {
5968 #if defined(CONFIG_USER_ONLY)
5969 GEN_PRIV;
5970 #else
5971 CHK_SV;
5972 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5973 #endif /* defined(CONFIG_USER_ONLY) */
5974 }
5975
5976 static void gen_msgsnd(DisasContext *ctx)
5977 {
5978 #if defined(CONFIG_USER_ONLY)
5979 GEN_PRIV;
5980 #else
5981 CHK_SV;
5982 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
5983 #endif /* defined(CONFIG_USER_ONLY) */
5984 }
5985
5986
5987 #if defined(TARGET_PPC64)
5988 static void gen_maddld(DisasContext *ctx)
5989 {
5990 TCGv_i64 t1 = tcg_temp_new_i64();
5991
5992 tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5993 tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]);
5994 tcg_temp_free_i64(t1);
5995 }
5996
5997 /* maddhd maddhdu */
5998 static void gen_maddhd_maddhdu(DisasContext *ctx)
5999 {
6000 TCGv_i64 lo = tcg_temp_new_i64();
6001 TCGv_i64 hi = tcg_temp_new_i64();
6002 TCGv_i64 t1 = tcg_temp_new_i64();
6003
6004 if (Rc(ctx->opcode)) {
6005 tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6006 cpu_gpr[rB(ctx->opcode)]);
6007 tcg_gen_movi_i64(t1, 0);
6008 } else {
6009 tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)],
6010 cpu_gpr[rB(ctx->opcode)]);
6011 tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63);
6012 }
6013 tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi,
6014 cpu_gpr[rC(ctx->opcode)], t1);
6015 tcg_temp_free_i64(lo);
6016 tcg_temp_free_i64(hi);
6017 tcg_temp_free_i64(t1);
6018 }
6019 #endif /* defined(TARGET_PPC64) */
6020
6021 #include "translate/dfp-impl.c"
6022
6023 #include "translate/spe-impl.c"
6024
6025 static void gen_tbegin(DisasContext *ctx)
6026 {
6027 if (unlikely(!ctx->tm_enabled)) {
6028 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6029 return;
6030 }
6031 gen_helper_tbegin(cpu_env);
6032 }
6033
6034 #define GEN_TM_NOOP(name) \
6035 static inline void gen_##name(DisasContext *ctx) \
6036 { \
6037 if (unlikely(!ctx->tm_enabled)) { \
6038 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6039 return; \
6040 } \
6041 /* Because tbegin always fails in QEMU, these user \
6042 * space instructions all have a simple implementation: \
6043 * \
6044 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6045 * = 0b0 || 0b00 || 0b0 \
6046 */ \
6047 tcg_gen_movi_i32(cpu_crf[0], 0); \
6048 }
6049
6050 GEN_TM_NOOP(tend);
6051 GEN_TM_NOOP(tabort);
6052 GEN_TM_NOOP(tabortwc);
6053 GEN_TM_NOOP(tabortwci);
6054 GEN_TM_NOOP(tabortdc);
6055 GEN_TM_NOOP(tabortdci);
6056 GEN_TM_NOOP(tsr);
6057
6058 static void gen_tcheck(DisasContext *ctx)
6059 {
6060 if (unlikely(!ctx->tm_enabled)) {
6061 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
6062 return;
6063 }
6064 /* Because tbegin always fails, the tcheck implementation
6065 * is simple:
6066 *
6067 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6068 * = 0b1 || 0b00 || 0b0
6069 */
6070 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
6071 }
6072
6073 #if defined(CONFIG_USER_ONLY)
6074 #define GEN_TM_PRIV_NOOP(name) \
6075 static inline void gen_##name(DisasContext *ctx) \
6076 { \
6077 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6078 }
6079
6080 #else
6081
6082 #define GEN_TM_PRIV_NOOP(name) \
6083 static inline void gen_##name(DisasContext *ctx) \
6084 { \
6085 CHK_SV; \
6086 if (unlikely(!ctx->tm_enabled)) { \
6087 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6088 return; \
6089 } \
6090 /* Because tbegin always fails, the implementation is \
6091 * simple: \
6092 * \
6093 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6094 * = 0b0 || 0b00 | 0b0 \
6095 */ \
6096 tcg_gen_movi_i32(cpu_crf[0], 0); \
6097 }
6098
6099 #endif
6100
6101 GEN_TM_PRIV_NOOP(treclaim);
6102 GEN_TM_PRIV_NOOP(trechkpt);
6103
6104 static opcode_t opcodes[] = {
6105 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
6106 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
6107 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6108 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
6109 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
6110 #if defined(TARGET_PPC64)
6111 GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
6112 #endif
6113 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
6114 GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300),
6115 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
6116 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6117 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6118 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6119 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6120 GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6121 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
6122 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
6123 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
6124 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
6125 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6126 #if defined(TARGET_PPC64)
6127 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
6128 #endif
6129 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
6130 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
6131 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6132 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6133 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6134 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
6135 GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
6136 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
6137 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
6138 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6139 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6140 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6141 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6142 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
6143 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
6144 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
6145 #if defined(TARGET_PPC64)
6146 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
6147 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
6148 GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
6149 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
6150 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
6151 #endif
6152 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6153 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6154 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6155 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
6156 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
6157 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
6158 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
6159 #if defined(TARGET_PPC64)
6160 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
6161 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
6162 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
6163 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
6164 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
6165 #endif
6166 #if defined(TARGET_PPC64)
6167 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
6168 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
6169 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
6170 #endif
6171 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6172 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
6173 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
6174 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
6175 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
6176 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
6177 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
6178 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
6179 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6180 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6181 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
6182 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6183 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
6184 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
6185 #if defined(TARGET_PPC64)
6186 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
6187 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
6188 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
6189 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
6190 #endif
6191 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
6192 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
6193 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6194 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6195 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
6196 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
6197 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
6198 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
6199 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
6200 #if defined(TARGET_PPC64)
6201 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
6202 GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6203 GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6204 GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6205 GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
6206 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
6207 #endif
6208 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
6209 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
6210 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
6211 #if defined(TARGET_PPC64)
6212 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
6213 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
6214 #endif
6215 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
6216 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
6217 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
6218 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
6219 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
6220 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
6221 #if defined(TARGET_PPC64)
6222 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
6223 GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
6224 #endif
6225 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
6226 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
6227 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
6228 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
6229 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
6230 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
6231 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
6232 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
6233 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
6234 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
6235 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
6236 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
6237 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
6238 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
6239 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
6240 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
6241 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
6242 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
6243 #if defined(TARGET_PPC64)
6244 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
6245 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
6246 PPC_SEGMENT_64B),
6247 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
6248 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
6249 PPC_SEGMENT_64B),
6250 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
6251 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
6252 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
6253 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
6254 #endif
6255 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
6256 /* XXX Those instructions will need to be handled differently for
6257 * different ISA versions */
6258 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
6259 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
6260 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
6261 #if defined(TARGET_PPC64)
6262 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
6263 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
6264 #endif
6265 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
6266 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
6267 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
6268 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
6269 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
6270 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
6271 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
6272 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
6273 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
6274 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
6275 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
6276 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6277 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
6278 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
6279 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
6280 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
6281 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
6282 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
6283 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
6284 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
6285 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
6286 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
6287 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
6288 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
6289 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
6290 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
6291 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
6292 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
6293 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
6294 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
6295 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
6296 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
6297 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
6298 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
6299 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
6300 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
6301 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
6302 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
6303 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
6304 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
6305 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
6306 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
6307 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
6308 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
6309 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
6310 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
6311 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
6312 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
6313 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
6314 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6315 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6316 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
6317 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
6318 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6319 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
6320 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
6321 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
6322 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
6323 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
6324 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
6325 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
6326 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
6327 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
6328 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
6329 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
6330 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
6331 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
6332 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
6333 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
6334 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
6335 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
6336 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
6337 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
6338 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
6339 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
6340 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
6341 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
6342 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
6343 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
6344 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
6345 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
6346 PPC_NONE, PPC2_BOOKE206),
6347 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
6348 PPC_NONE, PPC2_BOOKE206),
6349 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
6350 PPC_NONE, PPC2_BOOKE206),
6351 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
6352 PPC_NONE, PPC2_BOOKE206),
6353 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
6354 PPC_NONE, PPC2_BOOKE206),
6355 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
6356 PPC_NONE, PPC2_PRCNTL),
6357 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
6358 PPC_NONE, PPC2_PRCNTL),
6359 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
6360 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
6361 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
6362 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
6363 PPC_BOOKE, PPC2_BOOKE206),
6364 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
6365 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
6366 PPC_BOOKE, PPC2_BOOKE206),
6367 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
6368 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
6369 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
6370 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
6371 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
6372 #if defined(TARGET_PPC64)
6373 GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE,
6374 PPC2_ISA300),
6375 GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300),
6376 #endif
6377
6378 #undef GEN_INT_ARITH_ADD
6379 #undef GEN_INT_ARITH_ADD_CONST
6380 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
6381 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
6382 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
6383 add_ca, compute_ca, compute_ov) \
6384 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
6385 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
6386 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
6387 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
6388 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
6389 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
6390 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
6391 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
6392 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
6393 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
6394 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
6395
6396 #undef GEN_INT_ARITH_DIVW
6397 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
6398 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
6399 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
6400 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
6401 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
6402 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
6403 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6404 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6405 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6406 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6407 GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6408 GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6409
6410 #if defined(TARGET_PPC64)
6411 #undef GEN_INT_ARITH_DIVD
6412 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
6413 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6414 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
6415 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
6416 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
6417 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
6418
6419 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6420 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
6421 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6422 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
6423 GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
6424 GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
6425
6426 #undef GEN_INT_ARITH_MUL_HELPER
6427 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
6428 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
6429 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
6430 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
6431 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
6432 #endif
6433
6434 #undef GEN_INT_ARITH_SUBF
6435 #undef GEN_INT_ARITH_SUBF_CONST
6436 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
6437 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
6438 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
6439 add_ca, compute_ca, compute_ov) \
6440 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
6441 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
6442 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
6443 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
6444 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
6445 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
6446 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
6447 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
6448 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
6449 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
6450 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
6451
6452 #undef GEN_LOGICAL1
6453 #undef GEN_LOGICAL2
6454 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
6455 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
6456 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
6457 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
6458 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
6459 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
6460 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
6461 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
6462 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
6463 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
6464 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
6465 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
6466 #if defined(TARGET_PPC64)
6467 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
6468 #endif
6469
6470 #if defined(TARGET_PPC64)
6471 #undef GEN_PPC64_R2
6472 #undef GEN_PPC64_R4
6473 #define GEN_PPC64_R2(name, opc1, opc2) \
6474 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6475 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6476 PPC_64B)
6477 #define GEN_PPC64_R4(name, opc1, opc2) \
6478 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
6479 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
6480 PPC_64B), \
6481 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
6482 PPC_64B), \
6483 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
6484 PPC_64B)
6485 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
6486 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
6487 GEN_PPC64_R4(rldic, 0x1E, 0x04),
6488 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
6489 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
6490 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
6491 #endif
6492
6493 #undef GEN_LD
6494 #undef GEN_LDU
6495 #undef GEN_LDUX
6496 #undef GEN_LDX_E
6497 #undef GEN_LDS
6498 #define GEN_LD(name, ldop, opc, type) \
6499 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6500 #define GEN_LDU(name, ldop, opc, type) \
6501 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
6502 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
6503 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6504 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
6505 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6506 #define GEN_LDS(name, ldop, op, type) \
6507 GEN_LD(name, ldop, op | 0x20, type) \
6508 GEN_LDU(name, ldop, op | 0x21, type) \
6509 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
6510 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
6511
6512 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
6513 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
6514 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
6515 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
6516 #if defined(TARGET_PPC64)
6517 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
6518 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
6519 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
6520 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
6521 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE)
6522
6523 /* HV/P7 and later only */
6524 GEN_LDX_HVRM(ldcix, ld64, 0x15, 0x1b, PPC_CILDST)
6525 GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST)
6526 GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST)
6527 GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
6528 #endif
6529 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
6530 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
6531
6532 #undef GEN_ST
6533 #undef GEN_STU
6534 #undef GEN_STUX
6535 #undef GEN_STX_E
6536 #undef GEN_STS
6537 #define GEN_ST(name, stop, opc, type) \
6538 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
6539 #define GEN_STU(name, stop, opc, type) \
6540 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
6541 #define GEN_STUX(name, stop, opc2, opc3, type) \
6542 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
6543 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
6544 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
6545 #define GEN_STS(name, stop, op, type) \
6546 GEN_ST(name, stop, op | 0x20, type) \
6547 GEN_STU(name, stop, op | 0x21, type) \
6548 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
6549 GEN_STX(name, stop, 0x17, op | 0x00, type)
6550
6551 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
6552 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
6553 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
6554 #if defined(TARGET_PPC64)
6555 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
6556 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
6557 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE)
6558 GEN_STX_HVRM(stdcix, st64, 0x15, 0x1f, PPC_CILDST)
6559 GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST)
6560 GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST)
6561 GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST)
6562 #endif
6563 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
6564 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
6565
6566 #undef GEN_CRLOGIC
6567 #define GEN_CRLOGIC(name, tcg_op, opc) \
6568 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
6569 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
6570 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
6571 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
6572 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
6573 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
6574 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
6575 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
6576 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
6577
6578 #undef GEN_MAC_HANDLER
6579 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6580 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
6581 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
6582 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
6583 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
6584 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
6585 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
6586 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
6587 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
6588 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
6589 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
6590 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
6591 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
6592 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
6593 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
6594 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
6595 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
6596 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
6597 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
6598 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
6599 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
6600 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
6601 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
6602 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
6603 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
6604 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
6605 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
6606 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
6607 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
6608 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
6609 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
6610 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
6611 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
6612 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
6613 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
6614 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
6615 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
6616 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
6617 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
6618 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
6619 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
6620 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
6621 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
6622 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
6623
6624 #include "translate/fp-ops.c"
6625
6626 #include "translate/vmx-ops.c"
6627
6628 #include "translate/vsx-ops.c"
6629
6630 #include "translate/dfp-ops.c"
6631
6632 #include "translate/spe-ops.c"
6633
6634 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
6635 PPC_NONE, PPC2_TM),
6636 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
6637 PPC_NONE, PPC2_TM),
6638 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
6639 PPC_NONE, PPC2_TM),
6640 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
6641 PPC_NONE, PPC2_TM),
6642 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
6643 PPC_NONE, PPC2_TM),
6644 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
6645 PPC_NONE, PPC2_TM),
6646 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
6647 PPC_NONE, PPC2_TM),
6648 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
6649 PPC_NONE, PPC2_TM),
6650 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
6651 PPC_NONE, PPC2_TM),
6652 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
6653 PPC_NONE, PPC2_TM),
6654 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
6655 PPC_NONE, PPC2_TM),
6656 };
6657
6658 #include "helper_regs.h"
6659 #include "translate_init.c"
6660
6661 /*****************************************************************************/
6662 /* Misc PowerPC helpers */
6663 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
6664 int flags)
6665 {
6666 #define RGPL 4
6667 #define RFPL 4
6668
6669 PowerPCCPU *cpu = POWERPC_CPU(cs);
6670 CPUPPCState *env = &cpu->env;
6671 int i;
6672
6673 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
6674 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
6675 env->nip, env->lr, env->ctr, cpu_read_xer(env),
6676 cs->cpu_index);
6677 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
6678 TARGET_FMT_lx " iidx %d didx %d\n",
6679 env->msr, env->spr[SPR_HID0],
6680 env->hflags, env->immu_idx, env->dmmu_idx);
6681 #if !defined(NO_TIMER_DUMP)
6682 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
6683 #if !defined(CONFIG_USER_ONLY)
6684 " DECR %08" PRIu32
6685 #endif
6686 "\n",
6687 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
6688 #if !defined(CONFIG_USER_ONLY)
6689 , cpu_ppc_load_decr(env)
6690 #endif
6691 );
6692 #endif
6693 for (i = 0; i < 32; i++) {
6694 if ((i & (RGPL - 1)) == 0)
6695 cpu_fprintf(f, "GPR%02d", i);
6696 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
6697 if ((i & (RGPL - 1)) == (RGPL - 1))
6698 cpu_fprintf(f, "\n");
6699 }
6700 cpu_fprintf(f, "CR ");
6701 for (i = 0; i < 8; i++)
6702 cpu_fprintf(f, "%01x", env->crf[i]);
6703 cpu_fprintf(f, " [");
6704 for (i = 0; i < 8; i++) {
6705 char a = '-';
6706 if (env->crf[i] & 0x08)
6707 a = 'L';
6708 else if (env->crf[i] & 0x04)
6709 a = 'G';
6710 else if (env->crf[i] & 0x02)
6711 a = 'E';
6712 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
6713 }
6714 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
6715 env->reserve_addr);
6716 for (i = 0; i < 32; i++) {
6717 if ((i & (RFPL - 1)) == 0)
6718 cpu_fprintf(f, "FPR%02d", i);
6719 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
6720 if ((i & (RFPL - 1)) == (RFPL - 1))
6721 cpu_fprintf(f, "\n");
6722 }
6723 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
6724 #if !defined(CONFIG_USER_ONLY)
6725 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
6726 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
6727 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
6728 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
6729
6730 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
6731 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
6732 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
6733 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
6734
6735 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
6736 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
6737 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
6738 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
6739
6740 #if defined(TARGET_PPC64)
6741 if (env->excp_model == POWERPC_EXCP_POWER7 ||
6742 env->excp_model == POWERPC_EXCP_POWER8) {
6743 cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
6744 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
6745 }
6746 #endif
6747 if (env->excp_model == POWERPC_EXCP_BOOKE) {
6748 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
6749 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
6750 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
6751 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
6752
6753 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
6754 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
6755 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
6756 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
6757
6758 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
6759 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
6760 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
6761 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
6762
6763 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
6764 " EPR " TARGET_FMT_lx "\n",
6765 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
6766 env->spr[SPR_BOOKE_EPR]);
6767
6768 /* FSL-specific */
6769 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
6770 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
6771 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
6772 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
6773
6774 /*
6775 * IVORs are left out as they are large and do not change often --
6776 * they can be read with "p $ivor0", "p $ivor1", etc.
6777 */
6778 }
6779
6780 #if defined(TARGET_PPC64)
6781 if (env->flags & POWERPC_FLAG_CFAR) {
6782 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
6783 }
6784 #endif
6785
6786 switch (env->mmu_model) {
6787 case POWERPC_MMU_32B:
6788 case POWERPC_MMU_601:
6789 case POWERPC_MMU_SOFT_6xx:
6790 case POWERPC_MMU_SOFT_74xx:
6791 #if defined(TARGET_PPC64)
6792 case POWERPC_MMU_64B:
6793 case POWERPC_MMU_2_03:
6794 case POWERPC_MMU_2_06:
6795 case POWERPC_MMU_2_06a:
6796 case POWERPC_MMU_2_07:
6797 case POWERPC_MMU_2_07a:
6798 #endif
6799 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
6800 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
6801 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
6802 break;
6803 case POWERPC_MMU_BOOKE206:
6804 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
6805 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
6806 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
6807 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
6808
6809 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
6810 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
6811 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
6812 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
6813
6814 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
6815 " TLB1CFG " TARGET_FMT_lx "\n",
6816 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
6817 env->spr[SPR_BOOKE_TLB1CFG]);
6818 break;
6819 default:
6820 break;
6821 }
6822 #endif
6823
6824 #undef RGPL
6825 #undef RFPL
6826 }
6827
6828 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
6829 fprintf_function cpu_fprintf, int flags)
6830 {
6831 #if defined(DO_PPC_STATISTICS)
6832 PowerPCCPU *cpu = POWERPC_CPU(cs);
6833 opc_handler_t **t1, **t2, **t3, *handler;
6834 int op1, op2, op3;
6835
6836 t1 = cpu->env.opcodes;
6837 for (op1 = 0; op1 < 64; op1++) {
6838 handler = t1[op1];
6839 if (is_indirect_opcode(handler)) {
6840 t2 = ind_table(handler);
6841 for (op2 = 0; op2 < 32; op2++) {
6842 handler = t2[op2];
6843 if (is_indirect_opcode(handler)) {
6844 t3 = ind_table(handler);
6845 for (op3 = 0; op3 < 32; op3++) {
6846 handler = t3[op3];
6847 if (handler->count == 0)
6848 continue;
6849 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6850 "%016" PRIx64 " %" PRId64 "\n",
6851 op1, op2, op3, op1, (op3 << 5) | op2,
6852 handler->oname,
6853 handler->count, handler->count);
6854 }
6855 } else {
6856 if (handler->count == 0)
6857 continue;
6858 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6859 "%016" PRIx64 " %" PRId64 "\n",
6860 op1, op2, op1, op2, handler->oname,
6861 handler->count, handler->count);
6862 }
6863 }
6864 } else {
6865 if (handler->count == 0)
6866 continue;
6867 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
6868 " %" PRId64 "\n",
6869 op1, op1, handler->oname,
6870 handler->count, handler->count);
6871 }
6872 }
6873 #endif
6874 }
6875
6876 /*****************************************************************************/
6877 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
6878 {
6879 PowerPCCPU *cpu = ppc_env_get_cpu(env);
6880 CPUState *cs = CPU(cpu);
6881 DisasContext ctx, *ctxp = &ctx;
6882 opc_handler_t **table, *handler;
6883 target_ulong pc_start;
6884 int num_insns;
6885 int max_insns;
6886
6887 pc_start = tb->pc;
6888 ctx.nip = pc_start;
6889 ctx.tb = tb;
6890 ctx.exception = POWERPC_EXCP_NONE;
6891 ctx.spr_cb = env->spr_cb;
6892 ctx.pr = msr_pr;
6893 ctx.mem_idx = env->dmmu_idx;
6894 ctx.dr = msr_dr;
6895 #if !defined(CONFIG_USER_ONLY)
6896 ctx.hv = msr_hv || !env->has_hv_mode;
6897 #endif
6898 ctx.insns_flags = env->insns_flags;
6899 ctx.insns_flags2 = env->insns_flags2;
6900 ctx.access_type = -1;
6901 ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
6902 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
6903 #if defined(TARGET_PPC64)
6904 ctx.sf_mode = msr_is_64bit(env, env->msr);
6905 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
6906 #endif
6907 if (env->mmu_model == POWERPC_MMU_32B ||
6908 env->mmu_model == POWERPC_MMU_601 ||
6909 (env->mmu_model & POWERPC_MMU_64B))
6910 ctx.lazy_tlb_flush = true;
6911
6912 ctx.fpu_enabled = !!msr_fp;
6913 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
6914 ctx.spe_enabled = !!msr_spe;
6915 else
6916 ctx.spe_enabled = false;
6917 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6918 ctx.altivec_enabled = !!msr_vr;
6919 else
6920 ctx.altivec_enabled = false;
6921 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
6922 ctx.vsx_enabled = !!msr_vsx;
6923 } else {
6924 ctx.vsx_enabled = false;
6925 }
6926 #if defined(TARGET_PPC64)
6927 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
6928 ctx.tm_enabled = !!msr_tm;
6929 } else {
6930 ctx.tm_enabled = false;
6931 }
6932 #endif
6933 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
6934 ctx.singlestep_enabled = CPU_SINGLE_STEP;
6935 else
6936 ctx.singlestep_enabled = 0;
6937 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
6938 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
6939 if (unlikely(cs->singlestep_enabled)) {
6940 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
6941 }
6942 #if defined (DO_SINGLE_STEP) && 0
6943 /* Single step trace mode */
6944 msr_se = 1;
6945 #endif
6946 num_insns = 0;
6947 max_insns = tb->cflags & CF_COUNT_MASK;
6948 if (max_insns == 0) {
6949 max_insns = CF_COUNT_MASK;
6950 }
6951 if (max_insns > TCG_MAX_INSNS) {
6952 max_insns = TCG_MAX_INSNS;
6953 }
6954
6955 gen_tb_start(tb);
6956 tcg_clear_temp_count();
6957 /* Set env in case of segfault during code fetch */
6958 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
6959 tcg_gen_insn_start(ctx.nip);
6960 num_insns++;
6961
6962 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
6963 gen_debug_exception(ctxp);
6964 /* The address covered by the breakpoint must be included in
6965 [tb->pc, tb->pc + tb->size) in order to for it to be
6966 properly cleared -- thus we increment the PC here so that
6967 the logic setting tb->size below does the right thing. */
6968 ctx.nip += 4;
6969 break;
6970 }
6971
6972 LOG_DISAS("----------------\n");
6973 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
6974 ctx.nip, ctx.mem_idx, (int)msr_ir);
6975 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
6976 gen_io_start();
6977 if (unlikely(need_byteswap(&ctx))) {
6978 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
6979 } else {
6980 ctx.opcode = cpu_ldl_code(env, ctx.nip);
6981 }
6982 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
6983 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
6984 opc3(ctx.opcode), opc4(ctx.opcode),
6985 ctx.le_mode ? "little" : "big");
6986 ctx.nip += 4;
6987 table = env->opcodes;
6988 handler = table[opc1(ctx.opcode)];
6989 if (is_indirect_opcode(handler)) {
6990 table = ind_table(handler);
6991 handler = table[opc2(ctx.opcode)];
6992 if (is_indirect_opcode(handler)) {
6993 table = ind_table(handler);
6994 handler = table[opc3(ctx.opcode)];
6995 if (is_indirect_opcode(handler)) {
6996 table = ind_table(handler);
6997 handler = table[opc4(ctx.opcode)];
6998 }
6999 }
7000 }
7001 /* Is opcode *REALLY* valid ? */
7002 if (unlikely(handler->handler == &gen_invalid)) {
7003 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
7004 "%02x - %02x - %02x - %02x (%08x) "
7005 TARGET_FMT_lx " %d\n",
7006 opc1(ctx.opcode), opc2(ctx.opcode),
7007 opc3(ctx.opcode), opc4(ctx.opcode),
7008 ctx.opcode, ctx.nip - 4, (int)msr_ir);
7009 } else {
7010 uint32_t inval;
7011
7012 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
7013 inval = handler->inval2;
7014 } else {
7015 inval = handler->inval1;
7016 }
7017
7018 if (unlikely((ctx.opcode & inval) != 0)) {
7019 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
7020 "%02x - %02x - %02x - %02x (%08x) "
7021 TARGET_FMT_lx "\n", ctx.opcode & inval,
7022 opc1(ctx.opcode), opc2(ctx.opcode),
7023 opc3(ctx.opcode), opc4(ctx.opcode),
7024 ctx.opcode, ctx.nip - 4);
7025 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
7026 break;
7027 }
7028 }
7029 (*(handler->handler))(&ctx);
7030 #if defined(DO_PPC_STATISTICS)
7031 handler->count++;
7032 #endif
7033 /* Check trace mode exceptions */
7034 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
7035 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
7036 ctx.exception != POWERPC_SYSCALL &&
7037 ctx.exception != POWERPC_EXCP_TRAP &&
7038 ctx.exception != POWERPC_EXCP_BRANCH)) {
7039 gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip);
7040 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7041 (cs->singlestep_enabled) ||
7042 singlestep ||
7043 num_insns >= max_insns)) {
7044 /* if we reach a page boundary or are single stepping, stop
7045 * generation
7046 */
7047 break;
7048 }
7049 if (tcg_check_temp_count()) {
7050 fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked "
7051 "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode),
7052 opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode);
7053 exit(1);
7054 }
7055 }
7056 if (tb->cflags & CF_LAST_IO)
7057 gen_io_end();
7058 if (ctx.exception == POWERPC_EXCP_NONE) {
7059 gen_goto_tb(&ctx, 0, ctx.nip);
7060 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
7061 if (unlikely(cs->singlestep_enabled)) {
7062 gen_debug_exception(ctxp);
7063 }
7064 /* Generate the return instruction */
7065 tcg_gen_exit_tb(0);
7066 }
7067 gen_tb_end(tb, num_insns);
7068
7069 tb->size = ctx.nip - pc_start;
7070 tb->icount = num_insns;
7071
7072 #if defined(DEBUG_DISAS)
7073 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
7074 && qemu_log_in_addr_range(pc_start)) {
7075 int flags;
7076 flags = env->bfd_mach;
7077 flags |= ctx.le_mode << 16;
7078 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7079 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
7080 qemu_log("\n");
7081 }
7082 #endif
7083 }
7084
7085 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
7086 target_ulong *data)
7087 {
7088 env->nip = data[0];
7089 }
QEmu