4 * Copyright (c) 2008 OK Labs
5 * Copyright (c) 2011 NICTA Pty Ltd
6 * Originally written by Hans Jiang
7 * Updated by Peter Chubb
8 * Updated by Jean-Christophe Dubois
10 * This code is licensed under GPL version 2 or later. See
11 * the COPYING file in the top-level directory.
16 #include "qemu/bitops.h"
17 #include "qemu/timer.h"
18 #include "hw/ptimer.h"
19 #include "hw/sysbus.h"
20 #include "hw/arm/imx.h"
21 #include "qemu/main-loop.h"
23 #define TYPE_IMX_EPIT "imx.epit"
28 static char const *imx_epit_reg_name(uint32_t reg
)
46 # define DPRINTF(fmt, args...) \
47 do { fprintf(stderr, "%s: " fmt , __func__, ##args); } while (0)
49 # define DPRINTF(fmt, args...) do {} while (0)
53 * Define to 1 for messages about attempts to
54 * access unimplemented registers or similar.
56 #define DEBUG_IMPLEMENTATION 1
57 #if DEBUG_IMPLEMENTATION
58 # define IPRINTF(fmt, args...) \
59 do { fprintf(stderr, "%s: " fmt, __func__, ##args); } while (0)
61 # define IPRINTF(fmt, args...) do {} while (0)
64 #define IMX_EPIT(obj) \
65 OBJECT_CHECK(IMXEPITState, (obj), TYPE_IMX_EPIT)
68 * EPIT: Enhanced periodic interrupt timer
71 #define CR_EN (1 << 0)
72 #define CR_ENMOD (1 << 1)
73 #define CR_OCIEN (1 << 2)
74 #define CR_RLD (1 << 3)
75 #define CR_PRESCALE_SHIFT (4)
76 #define CR_PRESCALE_MASK (0xfff)
77 #define CR_SWR (1 << 16)
78 #define CR_IOVW (1 << 17)
79 #define CR_DBGEN (1 << 18)
80 #define CR_WAITEN (1 << 19)
81 #define CR_DOZEN (1 << 20)
82 #define CR_STOPEN (1 << 21)
83 #define CR_CLKSRC_SHIFT (24)
84 #define CR_CLKSRC_MASK (0x3 << CR_CLKSRC_SHIFT)
86 #define TIMER_MAX 0XFFFFFFFFUL
89 * Exact clock frequencies vary from board to board.
92 static const IMXClk imx_epit_clocks
[] = {
94 IPG
, /* 01 ipg_clk, ~532MHz */
95 IPG
, /* 10 ipg_clk_highfreq */
96 CLK_32k
, /* 11 ipg_clk_32k -- ~32kHz */
101 ptimer_state
*timer_reload
;
102 ptimer_state
*timer_cmp
;
117 * Update interrupt status
119 static void imx_epit_update_int(IMXEPITState
*s
)
121 if (s
->sr
&& (s
->cr
& CR_OCIEN
) && (s
->cr
& CR_EN
)) {
122 qemu_irq_raise(s
->irq
);
124 qemu_irq_lower(s
->irq
);
128 static void imx_epit_set_freq(IMXEPITState
*s
)
134 clksrc
= extract32(s
->cr
, CR_CLKSRC_SHIFT
, 2);
135 prescaler
= 1 + extract32(s
->cr
, CR_PRESCALE_SHIFT
, 12);
137 freq
= imx_clock_frequency(s
->ccm
, imx_epit_clocks
[clksrc
]) / prescaler
;
141 DPRINTF("Setting ptimer frequency to %u\n", freq
);
144 ptimer_set_freq(s
->timer_reload
, freq
);
145 ptimer_set_freq(s
->timer_cmp
, freq
);
149 static void imx_epit_reset(DeviceState
*dev
)
151 IMXEPITState
*s
= IMX_EPIT(dev
);
154 * Soft reset doesn't touch some bits; hard reset clears them
156 s
->cr
&= (CR_EN
|CR_ENMOD
|CR_STOPEN
|CR_DOZEN
|CR_WAITEN
|CR_DBGEN
);
161 /* stop both timers */
162 ptimer_stop(s
->timer_cmp
);
163 ptimer_stop(s
->timer_reload
);
164 /* compute new frequency */
165 imx_epit_set_freq(s
);
166 /* init both timers to TIMER_MAX */
167 ptimer_set_limit(s
->timer_cmp
, TIMER_MAX
, 1);
168 ptimer_set_limit(s
->timer_reload
, TIMER_MAX
, 1);
169 if (s
->freq
&& (s
->cr
& CR_EN
)) {
170 /* if the timer is still enabled, restart it */
171 ptimer_run(s
->timer_reload
, 0);
175 static uint32_t imx_epit_update_count(IMXEPITState
*s
)
177 s
->cnt
= ptimer_get_count(s
->timer_reload
);
182 static uint64_t imx_epit_read(void *opaque
, hwaddr offset
, unsigned size
)
184 IMXEPITState
*s
= IMX_EPIT(opaque
);
185 uint32_t reg_value
= 0;
186 uint32_t reg
= offset
>> 2;
189 case 0: /* Control Register */
193 case 1: /* Status Register */
197 case 2: /* LR - ticks*/
206 imx_epit_update_count(s
);
211 IPRINTF("Bad offset %x\n", reg
);
215 DPRINTF("(%s) = 0x%08x\n", imx_epit_reg_name(reg
), reg_value
);
220 static void imx_epit_reload_compare_timer(IMXEPITState
*s
)
222 if ((s
->cr
& (CR_EN
| CR_OCIEN
)) == (CR_EN
| CR_OCIEN
)) {
223 /* if the compare feature is on and timers are running */
224 uint32_t tmp
= imx_epit_update_count(s
);
227 /* It'll fire in this round of the timer */
229 } else { /* catch it next time around */
230 next
= tmp
- s
->cmp
+ ((s
->cr
& CR_RLD
) ? TIMER_MAX
: s
->lr
);
232 ptimer_set_count(s
->timer_cmp
, next
);
236 static void imx_epit_write(void *opaque
, hwaddr offset
, uint64_t value
,
239 IMXEPITState
*s
= IMX_EPIT(opaque
);
240 uint32_t reg
= offset
>> 2;
243 DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(reg
), (uint32_t)value
);
249 s
->cr
= value
& 0x03ffffff;
250 if (s
->cr
& CR_SWR
) {
251 /* handle the reset */
252 imx_epit_reset(DEVICE(s
));
254 imx_epit_set_freq(s
);
257 if (s
->freq
&& (s
->cr
& CR_EN
) && !(oldcr
& CR_EN
)) {
258 if (s
->cr
& CR_ENMOD
) {
259 if (s
->cr
& CR_RLD
) {
260 ptimer_set_limit(s
->timer_reload
, s
->lr
, 1);
261 ptimer_set_limit(s
->timer_cmp
, s
->lr
, 1);
263 ptimer_set_limit(s
->timer_reload
, TIMER_MAX
, 1);
264 ptimer_set_limit(s
->timer_cmp
, TIMER_MAX
, 1);
268 imx_epit_reload_compare_timer(s
);
269 ptimer_run(s
->timer_reload
, 0);
270 if (s
->cr
& CR_OCIEN
) {
271 ptimer_run(s
->timer_cmp
, 0);
273 ptimer_stop(s
->timer_cmp
);
275 } else if (!(s
->cr
& CR_EN
)) {
276 /* stop both timers */
277 ptimer_stop(s
->timer_reload
);
278 ptimer_stop(s
->timer_cmp
);
279 } else if (s
->cr
& CR_OCIEN
) {
280 if (!(oldcr
& CR_OCIEN
)) {
281 imx_epit_reload_compare_timer(s
);
282 ptimer_run(s
->timer_cmp
, 0);
285 ptimer_stop(s
->timer_cmp
);
289 case 1: /* SR - ACK*/
290 /* writing 1 to OCIF clear the OCIF bit */
293 imx_epit_update_int(s
);
297 case 2: /* LR - set ticks */
300 if (s
->cr
& CR_RLD
) {
301 /* Also set the limit if the LRD bit is set */
302 /* If IOVW bit is set then set the timer value */
303 ptimer_set_limit(s
->timer_reload
, s
->lr
, s
->cr
& CR_IOVW
);
304 ptimer_set_limit(s
->timer_cmp
, s
->lr
, 0);
305 } else if (s
->cr
& CR_IOVW
) {
306 /* If IOVW bit is set then set the timer value */
307 ptimer_set_count(s
->timer_reload
, s
->lr
);
310 imx_epit_reload_compare_timer(s
);
316 imx_epit_reload_compare_timer(s
);
321 IPRINTF("Bad offset %x\n", reg
);
326 static void imx_epit_cmp(void *opaque
)
328 IMXEPITState
*s
= IMX_EPIT(opaque
);
330 DPRINTF("sr was %d\n", s
->sr
);
333 imx_epit_update_int(s
);
336 void imx_timerp_create(const hwaddr addr
, qemu_irq irq
, DeviceState
*ccm
)
341 dev
= sysbus_create_simple(TYPE_IMX_EPIT
, addr
, irq
);
346 static const MemoryRegionOps imx_epit_ops
= {
347 .read
= imx_epit_read
,
348 .write
= imx_epit_write
,
349 .endianness
= DEVICE_NATIVE_ENDIAN
,
352 static const VMStateDescription vmstate_imx_timer_epit
= {
355 .minimum_version_id
= 2,
356 .fields
= (VMStateField
[]) {
357 VMSTATE_UINT32(cr
, IMXEPITState
),
358 VMSTATE_UINT32(sr
, IMXEPITState
),
359 VMSTATE_UINT32(lr
, IMXEPITState
),
360 VMSTATE_UINT32(cmp
, IMXEPITState
),
361 VMSTATE_UINT32(cnt
, IMXEPITState
),
362 VMSTATE_UINT32(freq
, IMXEPITState
),
363 VMSTATE_PTIMER(timer_reload
, IMXEPITState
),
364 VMSTATE_PTIMER(timer_cmp
, IMXEPITState
),
365 VMSTATE_END_OF_LIST()
369 static void imx_epit_realize(DeviceState
*dev
, Error
**errp
)
371 IMXEPITState
*s
= IMX_EPIT(dev
);
372 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
377 sysbus_init_irq(sbd
, &s
->irq
);
378 memory_region_init_io(&s
->iomem
, OBJECT(s
), &imx_epit_ops
, s
, TYPE_IMX_EPIT
,
380 sysbus_init_mmio(sbd
, &s
->iomem
);
382 s
->timer_reload
= ptimer_init(NULL
);
384 bh
= qemu_bh_new(imx_epit_cmp
, s
);
385 s
->timer_cmp
= ptimer_init(bh
);
388 static void imx_epit_class_init(ObjectClass
*klass
, void *data
)
390 DeviceClass
*dc
= DEVICE_CLASS(klass
);
392 dc
->realize
= imx_epit_realize
;
393 dc
->reset
= imx_epit_reset
;
394 dc
->vmsd
= &vmstate_imx_timer_epit
;
395 dc
->desc
= "i.MX periodic timer";
398 static const TypeInfo imx_epit_info
= {
399 .name
= TYPE_IMX_EPIT
,
400 .parent
= TYPE_SYS_BUS_DEVICE
,
401 .instance_size
= sizeof(IMXEPITState
),
402 .class_init
= imx_epit_class_init
,
405 static void imx_epit_register_types(void)
407 type_register_static(&imx_epit_info
);
410 type_init(imx_epit_register_types
)