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aspeed/smc: Add default reset values
[qemu.git] / hw / ssi / aspeed_smc.c
blob8cc7ccf45591fa61236e70c83e6bbfa701e5543a
1 /*
2 * ASPEED AST2400 SMC Controller (SPI Flash Only)
3 *
4 * Copyright (C) 2016 IBM Corp.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
27 #include "migration/vmstate.h"
28 #include "qemu/log.h"
29 #include "qemu/module.h"
30 #include "qemu/error-report.h"
31 #include "qapi/error.h"
32 #include "qemu/units.h"
33 #include "trace.h"
34
35 #include "hw/irq.h"
36 #include "hw/qdev-properties.h"
37 #include "hw/ssi/aspeed_smc.h"
38
39 /* CE Type Setting Register */
40 #define R_CONF (0x00 / 4)
41 #define CONF_LEGACY_DISABLE (1 << 31)
42 #define CONF_ENABLE_W4 20
43 #define CONF_ENABLE_W3 19
44 #define CONF_ENABLE_W2 18
45 #define CONF_ENABLE_W1 17
46 #define CONF_ENABLE_W0 16
47 #define CONF_FLASH_TYPE4 8
48 #define CONF_FLASH_TYPE3 6
49 #define CONF_FLASH_TYPE2 4
50 #define CONF_FLASH_TYPE1 2
51 #define CONF_FLASH_TYPE0 0
52 #define CONF_FLASH_TYPE_NOR 0x0
53 #define CONF_FLASH_TYPE_NAND 0x1
54 #define CONF_FLASH_TYPE_SPI 0x2 /* AST2600 is SPI only */
55
56 /* CE Control Register */
57 #define R_CE_CTRL (0x04 / 4)
58 #define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */
59 #define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */
60 #define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */
61 #define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */
62 #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */
63
64 /* Interrupt Control and Status Register */
65 #define R_INTR_CTRL (0x08 / 4)
66 #define INTR_CTRL_DMA_STATUS (1 << 11)
67 #define INTR_CTRL_CMD_ABORT_STATUS (1 << 10)
68 #define INTR_CTRL_WRITE_PROTECT_STATUS (1 << 9)
69 #define INTR_CTRL_DMA_EN (1 << 3)
70 #define INTR_CTRL_CMD_ABORT_EN (1 << 2)
71 #define INTR_CTRL_WRITE_PROTECT_EN (1 << 1)
72
73 /* Command Control Register */
74 #define R_CE_CMD_CTRL (0x0C / 4)
75 #define CTRL_ADDR_BYTE0_DISABLE_SHIFT 4
76 #define CTRL_DATA_BYTE0_DISABLE_SHIFT 0
77
78 #define aspeed_smc_addr_byte_enabled(s, i) \
79 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i)))))
80 #define aspeed_smc_data_byte_enabled(s, i) \
81 (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i)))))
82
83 /* CEx Control Register */
84 #define R_CTRL0 (0x10 / 4)
85 #define CTRL_IO_QPI (1 << 31)
86 #define CTRL_IO_QUAD_DATA (1 << 30)
87 #define CTRL_IO_DUAL_DATA (1 << 29)
88 #define CTRL_IO_DUAL_ADDR_DATA (1 << 28) /* Includes dummies */
89 #define CTRL_IO_QUAD_ADDR_DATA (1 << 28) /* Includes dummies */
90 #define CTRL_CMD_SHIFT 16
91 #define CTRL_CMD_MASK 0xff
92 #define CTRL_DUMMY_HIGH_SHIFT 14
93 #define CTRL_AST2400_SPI_4BYTE (1 << 13)
94 #define CE_CTRL_CLOCK_FREQ_SHIFT 8
95 #define CE_CTRL_CLOCK_FREQ_MASK 0xf
96 #define CE_CTRL_CLOCK_FREQ(div) \
97 (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT)
98 #define CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */
99 #define CTRL_CE_STOP_ACTIVE (1 << 2)
100 #define CTRL_CMD_MODE_MASK 0x3
101 #define CTRL_READMODE 0x0
102 #define CTRL_FREADMODE 0x1
103 #define CTRL_WRITEMODE 0x2
104 #define CTRL_USERMODE 0x3
105 #define R_CTRL1 (0x14 / 4)
106 #define R_CTRL2 (0x18 / 4)
107 #define R_CTRL3 (0x1C / 4)
108 #define R_CTRL4 (0x20 / 4)
109
110 /* CEx Segment Address Register */
111 #define R_SEG_ADDR0 (0x30 / 4)
112 #define SEG_END_SHIFT 24 /* 8MB units */
113 #define SEG_END_MASK 0xff
114 #define SEG_START_SHIFT 16 /* address bit [A29-A23] */
115 #define SEG_START_MASK 0xff
116 #define R_SEG_ADDR1 (0x34 / 4)
117 #define R_SEG_ADDR2 (0x38 / 4)
118 #define R_SEG_ADDR3 (0x3C / 4)
119 #define R_SEG_ADDR4 (0x40 / 4)
120
121 /* Misc Control Register #1 */
122 #define R_MISC_CTRL1 (0x50 / 4)
123
124 /* SPI dummy cycle data */
125 #define R_DUMMY_DATA (0x54 / 4)
126
127 /* FMC_WDT2 Control/Status Register for Alternate Boot (AST2600) */
128 #define R_FMC_WDT2_CTRL (0x64 / 4)
129 #define FMC_WDT2_CTRL_ALT_BOOT_MODE BIT(6) /* O: 2 chips 1: 1 chip */
130 #define FMC_WDT2_CTRL_SINGLE_BOOT_MODE BIT(5)
131 #define FMC_WDT2_CTRL_BOOT_SOURCE BIT(4) /* O: primary 1: alternate */
132 #define FMC_WDT2_CTRL_EN BIT(0)
133
134 /* DMA Control/Status Register */
135 #define R_DMA_CTRL (0x80 / 4)
136 #define DMA_CTRL_REQUEST (1 << 31)
137 #define DMA_CTRL_GRANT (1 << 30)
138 #define DMA_CTRL_DELAY_MASK 0xf
139 #define DMA_CTRL_DELAY_SHIFT 8
140 #define DMA_CTRL_FREQ_MASK 0xf
141 #define DMA_CTRL_FREQ_SHIFT 4
142 #define DMA_CTRL_CALIB (1 << 3)
143 #define DMA_CTRL_CKSUM (1 << 2)
144 #define DMA_CTRL_WRITE (1 << 1)
145 #define DMA_CTRL_ENABLE (1 << 0)
146
147 /* DMA Flash Side Address */
148 #define R_DMA_FLASH_ADDR (0x84 / 4)
149
150 /* DMA DRAM Side Address */
151 #define R_DMA_DRAM_ADDR (0x88 / 4)
152
153 /* DMA Length Register */
154 #define R_DMA_LEN (0x8C / 4)
155
156 /* Checksum Calculation Result */
157 #define R_DMA_CHECKSUM (0x90 / 4)
158
159 /* Read Timing Compensation Register */
160 #define R_TIMINGS (0x94 / 4)
161
162 /* SPI controller registers and bits (AST2400) */
163 #define R_SPI_CONF (0x00 / 4)
164 #define SPI_CONF_ENABLE_W0 0
165 #define R_SPI_CTRL0 (0x4 / 4)
166 #define R_SPI_MISC_CTRL (0x10 / 4)
167 #define R_SPI_TIMINGS (0x14 / 4)
168
169 #define ASPEED_SMC_R_SPI_MAX (0x20 / 4)
170 #define ASPEED_SMC_R_SMC_MAX (0x20 / 4)
171
172 /*
173 * DMA DRAM addresses should be 4 bytes aligned and the valid address
174 * range is 0x40000000 - 0x5FFFFFFF (AST2400)
175 * 0x80000000 - 0xBFFFFFFF (AST2500)
176 *
177 * DMA flash addresses should be 4 bytes aligned and the valid address
178 * range is 0x20000000 - 0x2FFFFFFF.
179 *
180 * DMA length is from 4 bytes to 32MB
181 * 0: 4 bytes
182 * 0x7FFFFF: 32M bytes
183 */
184 #define DMA_DRAM_ADDR(asc, val) ((val) & (asc)->dma_dram_mask)
185 #define DMA_FLASH_ADDR(asc, val) ((val) & (asc)->dma_flash_mask)
186 #define DMA_LENGTH(val) ((val) & 0x01FFFFFC)
187
188 /* Flash opcodes. */
189 #define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */
190
191 #define SNOOP_OFF 0xFF
192 #define SNOOP_START 0x0
193
194 /*
195 * Default segments mapping addresses and size for each peripheral per
196 * controller. These can be changed when board is initialized with the
197 * Segment Address Registers.
198 */
199 static const AspeedSegments aspeed_2400_spi1_segments[];
200 static const AspeedSegments aspeed_2500_spi1_segments[];
201 static const AspeedSegments aspeed_2500_spi2_segments[];
202
203 #define ASPEED_SMC_FEATURE_DMA 0x1
204 #define ASPEED_SMC_FEATURE_DMA_GRANT 0x2
205 #define ASPEED_SMC_FEATURE_WDT_CONTROL 0x4
206
207 static inline bool aspeed_smc_has_dma(const AspeedSMCClass *asc)
208 {
209 return !!(asc->features & ASPEED_SMC_FEATURE_DMA);
210 }
211
212 static inline bool aspeed_smc_has_wdt_control(const AspeedSMCClass *asc)
213 {
214 return !!(asc->features & ASPEED_SMC_FEATURE_WDT_CONTROL);
215 }
216
217 #define aspeed_smc_error(fmt, ...) \
218 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt "\n", __func__, ## __VA_ARGS__)
219
220 static bool aspeed_smc_flash_overlap(const AspeedSMCState *s,
221 const AspeedSegments *new,
222 int cs)
223 {
224 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
225 AspeedSegments seg;
226 int i;
227
228 for (i = 0; i < asc->max_peripherals; i++) {
229 if (i == cs) {
230 continue;
231 }
232
233 asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + i], &seg);
234
235 if (new->addr + new->size > seg.addr &&
236 new->addr < seg.addr + seg.size) {
237 aspeed_smc_error("new segment CS%d [ 0x%"
238 HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with "
239 "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
240 cs, new->addr, new->addr + new->size,
241 i, seg.addr, seg.addr + seg.size);
242 return true;
243 }
244 }
245 return false;
246 }
247
248 static void aspeed_smc_flash_set_segment_region(AspeedSMCState *s, int cs,
249 uint64_t regval)
250 {
251 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
252 AspeedSMCFlash *fl = &s->flashes[cs];
253 AspeedSegments seg;
254
255 asc->reg_to_segment(s, regval, &seg);
256
257 memory_region_transaction_begin();
258 memory_region_set_size(&fl->mmio, seg.size);
259 memory_region_set_address(&fl->mmio, seg.addr - asc->flash_window_base);
260 memory_region_set_enabled(&fl->mmio, !!seg.size);
261 memory_region_transaction_commit();
262
263 s->regs[R_SEG_ADDR0 + cs] = regval;
264 }
265
266 static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
267 uint64_t new)
268 {
269 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
270 AspeedSegments seg;
271
272 asc->reg_to_segment(s, new, &seg);
273
274 trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size);
275
276 /* The start address of CS0 is read-only */
277 if (cs == 0 && seg.addr != asc->flash_window_base) {
278 aspeed_smc_error("Tried to change CS0 start address to 0x%"
279 HWADDR_PRIx, seg.addr);
280 seg.addr = asc->flash_window_base;
281 new = asc->segment_to_reg(s, &seg);
282 }
283
284 /*
285 * The end address of the AST2500 spi controllers is also
286 * read-only.
287 */
288 if ((asc->segments == aspeed_2500_spi1_segments ||
289 asc->segments == aspeed_2500_spi2_segments) &&
290 cs == asc->max_peripherals &&
291 seg.addr + seg.size != asc->segments[cs].addr +
292 asc->segments[cs].size) {
293 aspeed_smc_error("Tried to change CS%d end address to 0x%"
294 HWADDR_PRIx, cs, seg.addr + seg.size);
295 seg.size = asc->segments[cs].addr + asc->segments[cs].size -
296 seg.addr;
297 new = asc->segment_to_reg(s, &seg);
298 }
299
300 /* Keep the segment in the overall flash window */
301 if (seg.size &&
302 (seg.addr + seg.size <= asc->flash_window_base ||
303 seg.addr > asc->flash_window_base + asc->flash_window_size)) {
304 aspeed_smc_error("new segment for CS%d is invalid : "
305 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
306 cs, seg.addr, seg.addr + seg.size);
307 return;
308 }
309
310 /* Check start address vs. alignment */
311 if (seg.size && !QEMU_IS_ALIGNED(seg.addr, seg.size)) {
312 aspeed_smc_error("new segment for CS%d is not "
313 "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
314 cs, seg.addr, seg.addr + seg.size);
315 }
316
317 /* And segments should not overlap (in the specs) */
318 aspeed_smc_flash_overlap(s, &seg, cs);
319
320 /* All should be fine now to move the region */
321 aspeed_smc_flash_set_segment_region(s, cs, new);
322 }
323
324 static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr,
325 unsigned size)
326 {
327 aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u" PRIx64, addr, size);
328 return 0;
329 }
330
331 static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr,
332 uint64_t data, unsigned size)
333 {
334 aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u: 0x%" PRIx64,
335 addr, size, data);
336 }
337
338 static const MemoryRegionOps aspeed_smc_flash_default_ops = {
339 .read = aspeed_smc_flash_default_read,
340 .write = aspeed_smc_flash_default_write,
341 .endianness = DEVICE_LITTLE_ENDIAN,
342 .valid = {
343 .min_access_size = 1,
344 .max_access_size = 4,
345 },
346 };
347
348 static inline int aspeed_smc_flash_mode(const AspeedSMCFlash *fl)
349 {
350 const AspeedSMCState *s = fl->controller;
351
352 return s->regs[s->r_ctrl0 + fl->cs] & CTRL_CMD_MODE_MASK;
353 }
354
355 static inline bool aspeed_smc_is_writable(const AspeedSMCFlash *fl)
356 {
357 const AspeedSMCState *s = fl->controller;
358
359 return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + fl->cs));
360 }
361
362 static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl)
363 {
364 const AspeedSMCState *s = fl->controller;
365 int cmd = (s->regs[s->r_ctrl0 + fl->cs] >> CTRL_CMD_SHIFT) & CTRL_CMD_MASK;
366
367 /*
368 * In read mode, the default SPI command is READ (0x3). In other
369 * modes, the command should necessarily be defined
370 *
371 * TODO: add support for READ4 (0x13) on AST2600
372 */
373 if (aspeed_smc_flash_mode(fl) == CTRL_READMODE) {
374 cmd = SPI_OP_READ;
375 }
376
377 if (!cmd) {
378 aspeed_smc_error("no command defined for mode %d",
379 aspeed_smc_flash_mode(fl));
380 }
381
382 return cmd;
383 }
384
385 static inline int aspeed_smc_flash_is_4byte(const AspeedSMCFlash *fl)
386 {
387 const AspeedSMCState *s = fl->controller;
388 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
389
390 if (asc->segments == aspeed_2400_spi1_segments) {
391 return s->regs[s->r_ctrl0] & CTRL_AST2400_SPI_4BYTE;
392 } else {
393 return s->regs[s->r_ce_ctrl] & (1 << (CTRL_EXTENDED0 + fl->cs));
394 }
395 }
396
397 static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect)
398 {
399 AspeedSMCState *s = fl->controller;
400
401 trace_aspeed_smc_flash_select(fl->cs, unselect ? "un" : "");
402
403 qemu_set_irq(s->cs_lines[fl->cs], unselect);
404 }
405
406 static void aspeed_smc_flash_select(AspeedSMCFlash *fl)
407 {
408 aspeed_smc_flash_do_select(fl, false);
409 }
410
411 static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl)
412 {
413 aspeed_smc_flash_do_select(fl, true);
414 }
415
416 static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
417 uint32_t addr)
418 {
419 const AspeedSMCState *s = fl->controller;
420 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
421 AspeedSegments seg;
422
423 asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->cs], &seg);
424 if ((addr % seg.size) != addr) {
425 aspeed_smc_error("invalid address 0x%08x for CS%d segment : "
426 "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]",
427 addr, fl->cs, seg.addr, seg.addr + seg.size);
428 addr %= seg.size;
429 }
430
431 return addr;
432 }
433
434 static int aspeed_smc_flash_dummies(const AspeedSMCFlash *fl)
435 {
436 const AspeedSMCState *s = fl->controller;
437 uint32_t r_ctrl0 = s->regs[s->r_ctrl0 + fl->cs];
438 uint32_t dummy_high = (r_ctrl0 >> CTRL_DUMMY_HIGH_SHIFT) & 0x1;
439 uint32_t dummy_low = (r_ctrl0 >> CTRL_DUMMY_LOW_SHIFT) & 0x3;
440 uint32_t dummies = ((dummy_high << 2) | dummy_low) * 8;
441
442 if (r_ctrl0 & CTRL_IO_DUAL_ADDR_DATA) {
443 dummies /= 2;
444 }
445
446 return dummies;
447 }
448
449 static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr)
450 {
451 const AspeedSMCState *s = fl->controller;
452 uint8_t cmd = aspeed_smc_flash_cmd(fl);
453 int i = aspeed_smc_flash_is_4byte(fl) ? 4 : 3;
454
455 /* Flash access can not exceed CS segment */
456 addr = aspeed_smc_check_segment_addr(fl, addr);
457
458 ssi_transfer(s->spi, cmd);
459 while (i--) {
460 if (aspeed_smc_addr_byte_enabled(s, i)) {
461 ssi_transfer(s->spi, (addr >> (i * 8)) & 0xff);
462 }
463 }
464
465 /*
466 * Use fake transfers to model dummy bytes. The value should
467 * be configured to some non-zero value in fast read mode and
468 * zero in read mode. But, as the HW allows inconsistent
469 * settings, let's check for fast read mode.
470 */
471 if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) {
472 for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) {
473 ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff);
474 }
475 }
476 }
477
478 static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size)
479 {
480 AspeedSMCFlash *fl = opaque;
481 AspeedSMCState *s = fl->controller;
482 uint64_t ret = 0;
483 int i;
484
485 switch (aspeed_smc_flash_mode(fl)) {
486 case CTRL_USERMODE:
487 for (i = 0; i < size; i++) {
488 ret |= ssi_transfer(s->spi, 0x0) << (8 * i);
489 }
490 break;
491 case CTRL_READMODE:
492 case CTRL_FREADMODE:
493 aspeed_smc_flash_select(fl);
494 aspeed_smc_flash_setup(fl, addr);
495
496 for (i = 0; i < size; i++) {
497 ret |= ssi_transfer(s->spi, 0x0) << (8 * i);
498 }
499
500 aspeed_smc_flash_unselect(fl);
501 break;
502 default:
503 aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl));
504 }
505
506 trace_aspeed_smc_flash_read(fl->cs, addr, size, ret,
507 aspeed_smc_flash_mode(fl));
508 return ret;
509 }
510
511 /*
512 * TODO (clg@kaod.org): stolen from xilinx_spips.c. Should move to a
513 * common include header.
514 */
515 typedef enum {
516 READ = 0x3, READ_4 = 0x13,
517 FAST_READ = 0xb, FAST_READ_4 = 0x0c,
518 DOR = 0x3b, DOR_4 = 0x3c,
519 QOR = 0x6b, QOR_4 = 0x6c,
520 DIOR = 0xbb, DIOR_4 = 0xbc,
521 QIOR = 0xeb, QIOR_4 = 0xec,
522
523 PP = 0x2, PP_4 = 0x12,
524 DPP = 0xa2,
525 QPP = 0x32, QPP_4 = 0x34,
526 } FlashCMD;
527
528 static int aspeed_smc_num_dummies(uint8_t command)
529 {
530 switch (command) { /* check for dummies */
531 case READ: /* no dummy bytes/cycles */
532 case PP:
533 case DPP:
534 case QPP:
535 case READ_4:
536 case PP_4:
537 case QPP_4:
538 return 0;
539 case FAST_READ:
540 case DOR:
541 case QOR:
542 case FAST_READ_4:
543 case DOR_4:
544 case QOR_4:
545 return 1;
546 case DIOR:
547 case DIOR_4:
548 return 2;
549 case QIOR:
550 case QIOR_4:
551 return 4;
552 default:
553 return -1;
554 }
555 }
556
557 static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data,
558 unsigned size)
559 {
560 AspeedSMCState *s = fl->controller;
561 uint8_t addr_width = aspeed_smc_flash_is_4byte(fl) ? 4 : 3;
562
563 trace_aspeed_smc_do_snoop(fl->cs, s->snoop_index, s->snoop_dummies,
564 (uint8_t) data & 0xff);
565
566 if (s->snoop_index == SNOOP_OFF) {
567 return false; /* Do nothing */
568
569 } else if (s->snoop_index == SNOOP_START) {
570 uint8_t cmd = data & 0xff;
571 int ndummies = aspeed_smc_num_dummies(cmd);
572
573 /*
574 * No dummy cycles are expected with the current command. Turn
575 * off snooping and let the transfer proceed normally.
576 */
577 if (ndummies <= 0) {
578 s->snoop_index = SNOOP_OFF;
579 return false;
580 }
581
582 s->snoop_dummies = ndummies * 8;
583
584 } else if (s->snoop_index >= addr_width + 1) {
585
586 /* The SPI transfer has reached the dummy cycles sequence */
587 for (; s->snoop_dummies; s->snoop_dummies--) {
588 ssi_transfer(s->spi, s->regs[R_DUMMY_DATA] & 0xff);
589 }
590
591 /* If no more dummy cycles are expected, turn off snooping */
592 if (!s->snoop_dummies) {
593 s->snoop_index = SNOOP_OFF;
594 } else {
595 s->snoop_index += size;
596 }
597
598 /*
599 * Dummy cycles have been faked already. Ignore the current
600 * SPI transfer
601 */
602 return true;
603 }
604
605 s->snoop_index += size;
606 return false;
607 }
608
609 static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data,
610 unsigned size)
611 {
612 AspeedSMCFlash *fl = opaque;
613 AspeedSMCState *s = fl->controller;
614 int i;
615
616 trace_aspeed_smc_flash_write(fl->cs, addr, size, data,
617 aspeed_smc_flash_mode(fl));
618
619 if (!aspeed_smc_is_writable(fl)) {
620 aspeed_smc_error("flash is not writable at 0x%" HWADDR_PRIx, addr);
621 return;
622 }
623
624 switch (aspeed_smc_flash_mode(fl)) {
625 case CTRL_USERMODE:
626 if (aspeed_smc_do_snoop(fl, data, size)) {
627 break;
628 }
629
630 for (i = 0; i < size; i++) {
631 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
632 }
633 break;
634 case CTRL_WRITEMODE:
635 aspeed_smc_flash_select(fl);
636 aspeed_smc_flash_setup(fl, addr);
637
638 for (i = 0; i < size; i++) {
639 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff);
640 }
641
642 aspeed_smc_flash_unselect(fl);
643 break;
644 default:
645 aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl));
646 }
647 }
648
649 static const MemoryRegionOps aspeed_smc_flash_ops = {
650 .read = aspeed_smc_flash_read,
651 .write = aspeed_smc_flash_write,
652 .endianness = DEVICE_LITTLE_ENDIAN,
653 .valid = {
654 .min_access_size = 1,
655 .max_access_size = 4,
656 },
657 };
658
659 static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value)
660 {
661 AspeedSMCState *s = fl->controller;
662 bool unselect;
663
664 /* User mode selects the CS, other modes unselect */
665 unselect = (value & CTRL_CMD_MODE_MASK) != CTRL_USERMODE;
666
667 /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */
668 if (!(s->regs[s->r_ctrl0 + fl->cs] & CTRL_CE_STOP_ACTIVE) &&
669 value & CTRL_CE_STOP_ACTIVE) {
670 unselect = true;
671 }
672
673 s->regs[s->r_ctrl0 + fl->cs] = value;
674
675 s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START;
676
677 aspeed_smc_flash_do_select(fl, unselect);
678 }
679
680 static void aspeed_smc_reset(DeviceState *d)
681 {
682 AspeedSMCState *s = ASPEED_SMC(d);
683 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
684 int i;
685
686 if (asc->resets) {
687 memcpy(s->regs, asc->resets, sizeof s->regs);
688 } else {
689 memset(s->regs, 0, sizeof s->regs);
690 }
691
692 /* Unselect all peripherals */
693 for (i = 0; i < s->num_cs; ++i) {
694 s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE;
695 qemu_set_irq(s->cs_lines[i], true);
696 }
697
698 /* setup the default segment register values and regions for all */
699 for (i = 0; i < asc->max_peripherals; ++i) {
700 aspeed_smc_flash_set_segment_region(s, i,
701 asc->segment_to_reg(s, &asc->segments[i]));
702 }
703
704 s->snoop_index = SNOOP_OFF;
705 s->snoop_dummies = 0;
706 }
707
708 static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
709 {
710 AspeedSMCState *s = ASPEED_SMC(opaque);
711 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(opaque);
712
713 addr >>= 2;
714
715 if (addr == s->r_conf ||
716 (addr >= s->r_timings &&
717 addr < s->r_timings + asc->nregs_timings) ||
718 addr == s->r_ce_ctrl ||
719 addr == R_CE_CMD_CTRL ||
720 addr == R_INTR_CTRL ||
721 addr == R_DUMMY_DATA ||
722 (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) ||
723 (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) ||
724 (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR) ||
725 (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR) ||
726 (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN) ||
727 (aspeed_smc_has_dma(asc) && addr == R_DMA_CHECKSUM) ||
728 (addr >= R_SEG_ADDR0 &&
729 addr < R_SEG_ADDR0 + asc->max_peripherals) ||
730 (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->max_peripherals)) {
731
732 trace_aspeed_smc_read(addr, size, s->regs[addr]);
733
734 return s->regs[addr];
735 } else {
736 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
737 __func__, addr);
738 return -1;
739 }
740 }
741
742 static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_mask)
743 {
744 /* HCLK/1 .. HCLK/16 */
745 const uint8_t hclk_divisors[] = {
746 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0
747 };
748 int i;
749
750 for (i = 0; i < ARRAY_SIZE(hclk_divisors); i++) {
751 if (hclk_mask == hclk_divisors[i]) {
752 return i + 1;
753 }
754 }
755
756 aspeed_smc_error("invalid HCLK mask %x", hclk_mask);
757 return 0;
758 }
759
760 /*
761 * When doing calibration, the SPI clock rate in the CE0 Control
762 * Register and the read delay cycles in the Read Timing Compensation
763 * Register are set using bit[11:4] of the DMA Control Register.
764 */
765 static void aspeed_smc_dma_calibration(AspeedSMCState *s)
766 {
767 uint8_t delay =
768 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK;
769 uint8_t hclk_mask =
770 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK;
771 uint8_t hclk_div = aspeed_smc_hclk_divisor(hclk_mask);
772 uint32_t hclk_shift = (hclk_div - 1) << 2;
773 uint8_t cs;
774
775 /*
776 * The Read Timing Compensation Register values apply to all CS on
777 * the SPI bus and only HCLK/1 - HCLK/5 can have tunable delays
778 */
779 if (hclk_div && hclk_div < 6) {
780 s->regs[s->r_timings] &= ~(0xf << hclk_shift);
781 s->regs[s->r_timings] |= delay << hclk_shift;
782 }
783
784 /*
785 * TODO: compute the CS from the DMA address and the segment
786 * registers. This is not really a problem for now because the
787 * Timing Register values apply to all CS and software uses CS0 to
788 * do calibration.
789 */
790 cs = 0;
791 s->regs[s->r_ctrl0 + cs] &=
792 ~(CE_CTRL_CLOCK_FREQ_MASK << CE_CTRL_CLOCK_FREQ_SHIFT);
793 s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div);
794 }
795
796 /*
797 * Emulate read errors in the DMA Checksum Register for high
798 * frequencies and optimistic settings of the Read Timing Compensation
799 * Register. This will help in tuning the SPI timing calibration
800 * algorithm.
801 */
802 static bool aspeed_smc_inject_read_failure(AspeedSMCState *s)
803 {
804 uint8_t delay =
805 (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK;
806 uint8_t hclk_mask =
807 (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK;
808
809 /*
810 * Typical values of a palmetto-bmc machine.
811 */
812 switch (aspeed_smc_hclk_divisor(hclk_mask)) {
813 case 4 ... 16:
814 return false;
815 case 3: /* at least one HCLK cycle delay */
816 return (delay & 0x7) < 1;
817 case 2: /* at least two HCLK cycle delay */
818 return (delay & 0x7) < 2;
819 case 1: /* (> 100MHz) is above the max freq of the controller */
820 return true;
821 default:
822 g_assert_not_reached();
823 }
824 }
825
826 /*
827 * Accumulate the result of the reads to provide a checksum that will
828 * be used to validate the read timing settings.
829 */
830 static void aspeed_smc_dma_checksum(AspeedSMCState *s)
831 {
832 MemTxResult result;
833 uint32_t data;
834
835 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
836 aspeed_smc_error("invalid direction for DMA checksum");
837 return;
838 }
839
840 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) {
841 aspeed_smc_dma_calibration(s);
842 }
843
844 while (s->regs[R_DMA_LEN]) {
845 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
846 MEMTXATTRS_UNSPECIFIED, &result);
847 if (result != MEMTX_OK) {
848 aspeed_smc_error("Flash read failed @%08x",
849 s->regs[R_DMA_FLASH_ADDR]);
850 return;
851 }
852 trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data);
853
854 /*
855 * When the DMA is on-going, the DMA registers are updated
856 * with the current working addresses and length.
857 */
858 s->regs[R_DMA_CHECKSUM] += data;
859 s->regs[R_DMA_FLASH_ADDR] += 4;
860 s->regs[R_DMA_LEN] -= 4;
861 }
862
863 if (s->inject_failure && aspeed_smc_inject_read_failure(s)) {
864 s->regs[R_DMA_CHECKSUM] = 0xbadc0de;
865 }
866
867 }
868
869 static void aspeed_smc_dma_rw(AspeedSMCState *s)
870 {
871 MemTxResult result;
872 uint32_t data;
873
874 trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ?
875 "write" : "read",
876 s->regs[R_DMA_FLASH_ADDR],
877 s->regs[R_DMA_DRAM_ADDR],
878 s->regs[R_DMA_LEN]);
879 while (s->regs[R_DMA_LEN]) {
880 if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
881 data = address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],
882 MEMTXATTRS_UNSPECIFIED, &result);
883 if (result != MEMTX_OK) {
884 aspeed_smc_error("DRAM read failed @%08x",
885 s->regs[R_DMA_DRAM_ADDR]);
886 return;
887 }
888
889 address_space_stl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
890 data, MEMTXATTRS_UNSPECIFIED, &result);
891 if (result != MEMTX_OK) {
892 aspeed_smc_error("Flash write failed @%08x",
893 s->regs[R_DMA_FLASH_ADDR]);
894 return;
895 }
896 } else {
897 data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
898 MEMTXATTRS_UNSPECIFIED, &result);
899 if (result != MEMTX_OK) {
900 aspeed_smc_error("Flash read failed @%08x",
901 s->regs[R_DMA_FLASH_ADDR]);
902 return;
903 }
904
905 address_space_stl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],
906 data, MEMTXATTRS_UNSPECIFIED, &result);
907 if (result != MEMTX_OK) {
908 aspeed_smc_error("DRAM write failed @%08x",
909 s->regs[R_DMA_DRAM_ADDR]);
910 return;
911 }
912 }
913
914 /*
915 * When the DMA is on-going, the DMA registers are updated
916 * with the current working addresses and length.
917 */
918 s->regs[R_DMA_FLASH_ADDR] += 4;
919 s->regs[R_DMA_DRAM_ADDR] += 4;
920 s->regs[R_DMA_LEN] -= 4;
921 s->regs[R_DMA_CHECKSUM] += data;
922 }
923 }
924
925 static void aspeed_smc_dma_stop(AspeedSMCState *s)
926 {
927 /*
928 * When the DMA is disabled, INTR_CTRL_DMA_STATUS=0 means the
929 * engine is idle
930 */
931 s->regs[R_INTR_CTRL] &= ~INTR_CTRL_DMA_STATUS;
932 s->regs[R_DMA_CHECKSUM] = 0;
933
934 /*
935 * Lower the DMA irq in any case. The IRQ control register could
936 * have been cleared before disabling the DMA.
937 */
938 qemu_irq_lower(s->irq);
939 }
940
941 /*
942 * When INTR_CTRL_DMA_STATUS=1, the DMA has completed and a new DMA
943 * can start even if the result of the previous was not collected.
944 */
945 static bool aspeed_smc_dma_in_progress(AspeedSMCState *s)
946 {
947 return s->regs[R_DMA_CTRL] & DMA_CTRL_ENABLE &&
948 !(s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_STATUS);
949 }
950
951 static void aspeed_smc_dma_done(AspeedSMCState *s)
952 {
953 s->regs[R_INTR_CTRL] |= INTR_CTRL_DMA_STATUS;
954 if (s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_EN) {
955 qemu_irq_raise(s->irq);
956 }
957 }
958
959 static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl)
960 {
961 if (!(dma_ctrl & DMA_CTRL_ENABLE)) {
962 s->regs[R_DMA_CTRL] = dma_ctrl;
963
964 aspeed_smc_dma_stop(s);
965 return;
966 }
967
968 if (aspeed_smc_dma_in_progress(s)) {
969 aspeed_smc_error("DMA in progress !");
970 return;
971 }
972
973 s->regs[R_DMA_CTRL] = dma_ctrl;
974
975 if (s->regs[R_DMA_CTRL] & DMA_CTRL_CKSUM) {
976 aspeed_smc_dma_checksum(s);
977 } else {
978 aspeed_smc_dma_rw(s);
979 }
980
981 aspeed_smc_dma_done(s);
982 }
983
984 static inline bool aspeed_smc_dma_granted(AspeedSMCState *s)
985 {
986 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
987
988 if (!(asc->features & ASPEED_SMC_FEATURE_DMA_GRANT)) {
989 return true;
990 }
991
992 if (!(s->regs[R_DMA_CTRL] & DMA_CTRL_GRANT)) {
993 aspeed_smc_error("DMA not granted");
994 return false;
995 }
996
997 return true;
998 }
999
1000 static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl)
1001 {
1002 /* Preserve DMA bits */
1003 dma_ctrl |= s->regs[R_DMA_CTRL] & (DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
1004
1005 if (dma_ctrl == 0xAEED0000) {
1006 /* automatically grant request */
1007 s->regs[R_DMA_CTRL] |= (DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
1008 return;
1009 }
1010
1011 /* clear request */
1012 if (dma_ctrl == 0xDEEA0000) {
1013 s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
1014 return;
1015 }
1016
1017 if (!aspeed_smc_dma_granted(s)) {
1018 aspeed_smc_error("DMA not granted");
1019 return;
1020 }
1021
1022 aspeed_smc_dma_ctrl(s, dma_ctrl);
1023 s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT);
1024 }
1025
1026 static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
1027 unsigned int size)
1028 {
1029 AspeedSMCState *s = ASPEED_SMC(opaque);
1030 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1031 uint32_t value = data;
1032
1033 addr >>= 2;
1034
1035 trace_aspeed_smc_write(addr, size, data);
1036
1037 if (addr == s->r_conf ||
1038 (addr >= s->r_timings &&
1039 addr < s->r_timings + asc->nregs_timings) ||
1040 addr == s->r_ce_ctrl) {
1041 s->regs[addr] = value;
1042 } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) {
1043 int cs = addr - s->r_ctrl0;
1044 aspeed_smc_flash_update_ctrl(&s->flashes[cs], value);
1045 } else if (addr >= R_SEG_ADDR0 &&
1046 addr < R_SEG_ADDR0 + asc->max_peripherals) {
1047 int cs = addr - R_SEG_ADDR0;
1048
1049 if (value != s->regs[R_SEG_ADDR0 + cs]) {
1050 aspeed_smc_flash_set_segment(s, cs, value);
1051 }
1052 } else if (addr == R_CE_CMD_CTRL) {
1053 s->regs[addr] = value & 0xff;
1054 } else if (addr == R_DUMMY_DATA) {
1055 s->regs[addr] = value & 0xff;
1056 } else if (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) {
1057 s->regs[addr] = value & FMC_WDT2_CTRL_EN;
1058 } else if (addr == R_INTR_CTRL) {
1059 s->regs[addr] = value;
1060 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) {
1061 asc->dma_ctrl(s, value);
1062 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR &&
1063 aspeed_smc_dma_granted(s)) {
1064 s->regs[addr] = DMA_DRAM_ADDR(asc, value);
1065 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR &&
1066 aspeed_smc_dma_granted(s)) {
1067 s->regs[addr] = DMA_FLASH_ADDR(asc, value);
1068 } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN &&
1069 aspeed_smc_dma_granted(s)) {
1070 s->regs[addr] = DMA_LENGTH(value);
1071 } else {
1072 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
1073 __func__, addr);
1074 return;
1075 }
1076 }
1077
1078 static const MemoryRegionOps aspeed_smc_ops = {
1079 .read = aspeed_smc_read,
1080 .write = aspeed_smc_write,
1081 .endianness = DEVICE_LITTLE_ENDIAN,
1082 };
1083
1084 static void aspeed_smc_instance_init(Object *obj)
1085 {
1086 AspeedSMCState *s = ASPEED_SMC(obj);
1087 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1088 int i;
1089
1090 for (i = 0; i < asc->max_peripherals; i++) {
1091 object_initialize_child(obj, "flash[*]", &s->flashes[i],
1092 TYPE_ASPEED_SMC_FLASH);
1093 }
1094 }
1095
1096 /*
1097 * Initialize the custom address spaces for DMAs
1098 */
1099 static void aspeed_smc_dma_setup(AspeedSMCState *s, Error **errp)
1100 {
1101 if (!s->dram_mr) {
1102 error_setg(errp, TYPE_ASPEED_SMC ": 'dram' link not set");
1103 return;
1104 }
1105
1106 address_space_init(&s->flash_as, &s->mmio_flash,
1107 TYPE_ASPEED_SMC ".dma-flash");
1108 address_space_init(&s->dram_as, s->dram_mr,
1109 TYPE_ASPEED_SMC ".dma-dram");
1110 }
1111
1112 static void aspeed_smc_realize(DeviceState *dev, Error **errp)
1113 {
1114 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1115 AspeedSMCState *s = ASPEED_SMC(dev);
1116 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1117 int i;
1118 hwaddr offset = 0;
1119
1120 /* keep a copy under AspeedSMCState to speed up accesses */
1121 s->r_conf = asc->r_conf;
1122 s->r_ce_ctrl = asc->r_ce_ctrl;
1123 s->r_ctrl0 = asc->r_ctrl0;
1124 s->r_timings = asc->r_timings;
1125 s->conf_enable_w0 = asc->conf_enable_w0;
1126
1127 /* Enforce some real HW limits */
1128 if (s->num_cs > asc->max_peripherals) {
1129 aspeed_smc_error("num_cs cannot exceed: %d", asc->max_peripherals);
1130 s->num_cs = asc->max_peripherals;
1131 }
1132
1133 /* DMA irq. Keep it first for the initialization in the SoC */
1134 sysbus_init_irq(sbd, &s->irq);
1135
1136 s->spi = ssi_create_bus(dev, "spi");
1137
1138 /* Setup cs_lines for peripherals */
1139 s->cs_lines = g_new0(qemu_irq, s->num_cs);
1140
1141 for (i = 0; i < s->num_cs; ++i) {
1142 sysbus_init_irq(sbd, &s->cs_lines[i]);
1143 }
1144
1145 /* The memory region for the controller registers */
1146 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s,
1147 TYPE_ASPEED_SMC, asc->nregs * 4);
1148 sysbus_init_mmio(sbd, &s->mmio);
1149
1150 /*
1151 * The container memory region representing the address space
1152 * window in which the flash modules are mapped. The size and
1153 * address depends on the SoC model and controller type.
1154 */
1155 memory_region_init_io(&s->mmio_flash, OBJECT(s),
1156 &aspeed_smc_flash_default_ops, s,
1157 TYPE_ASPEED_SMC ".flash",
1158 asc->flash_window_size);
1159 memory_region_init_alias(&s->mmio_flash_alias, OBJECT(s),
1160 TYPE_ASPEED_SMC ".flash",
1161 &s->mmio_flash, 0, asc->flash_window_size);
1162 sysbus_init_mmio(sbd, &s->mmio_flash_alias);
1163
1164 /*
1165 * Let's create a sub memory region for each possible peripheral. All
1166 * have a configurable memory segment in the overall flash mapping
1167 * window of the controller but, there is not necessarily a flash
1168 * module behind to handle the memory accesses. This depends on
1169 * the board configuration.
1170 */
1171 for (i = 0; i < asc->max_peripherals; ++i) {
1172 AspeedSMCFlash *fl = &s->flashes[i];
1173
1174 if (!object_property_set_link(OBJECT(fl), "controller", OBJECT(s),
1175 errp)) {
1176 return;
1177 }
1178 if (!object_property_set_uint(OBJECT(fl), "cs", i, errp)) {
1179 return;
1180 }
1181 if (!sysbus_realize(SYS_BUS_DEVICE(fl), errp)) {
1182 return;
1183 }
1184
1185 memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio);
1186 offset += asc->segments[i].size;
1187 }
1188
1189 /* DMA support */
1190 if (aspeed_smc_has_dma(asc)) {
1191 aspeed_smc_dma_setup(s, errp);
1192 }
1193 }
1194
1195 static const VMStateDescription vmstate_aspeed_smc = {
1196 .name = "aspeed.smc",
1197 .version_id = 2,
1198 .minimum_version_id = 2,
1199 .fields = (VMStateField[]) {
1200 VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX),
1201 VMSTATE_UINT8(snoop_index, AspeedSMCState),
1202 VMSTATE_UINT8(snoop_dummies, AspeedSMCState),
1203 VMSTATE_END_OF_LIST()
1204 }
1205 };
1206
1207 static Property aspeed_smc_properties[] = {
1208 DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1),
1209 DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false),
1210 DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr,
1211 TYPE_MEMORY_REGION, MemoryRegion *),
1212 DEFINE_PROP_END_OF_LIST(),
1213 };
1214
1215 static void aspeed_smc_class_init(ObjectClass *klass, void *data)
1216 {
1217 DeviceClass *dc = DEVICE_CLASS(klass);
1218
1219 dc->realize = aspeed_smc_realize;
1220 dc->reset = aspeed_smc_reset;
1221 device_class_set_props(dc, aspeed_smc_properties);
1222 dc->vmsd = &vmstate_aspeed_smc;
1223 }
1224
1225 static const TypeInfo aspeed_smc_info = {
1226 .name = TYPE_ASPEED_SMC,
1227 .parent = TYPE_SYS_BUS_DEVICE,
1228 .instance_init = aspeed_smc_instance_init,
1229 .instance_size = sizeof(AspeedSMCState),
1230 .class_size = sizeof(AspeedSMCClass),
1231 .class_init = aspeed_smc_class_init,
1232 .abstract = true,
1233 };
1234
1235 static void aspeed_smc_flash_realize(DeviceState *dev, Error **errp)
1236 {
1237 AspeedSMCFlash *s = ASPEED_SMC_FLASH(dev);
1238 AspeedSMCClass *asc;
1239 g_autofree char *name = g_strdup_printf(TYPE_ASPEED_SMC_FLASH ".%d", s->cs);
1240
1241 if (!s->controller) {
1242 error_setg(errp, TYPE_ASPEED_SMC_FLASH ": 'controller' link not set");
1243 return;
1244 }
1245
1246 asc = ASPEED_SMC_GET_CLASS(s->controller);
1247
1248 /*
1249 * Use the default segment value to size the memory region. This
1250 * can be changed by FW at runtime.
1251 */
1252 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_flash_ops,
1253 s, name, asc->segments[s->cs].size);
1254 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
1255 }
1256
1257 static Property aspeed_smc_flash_properties[] = {
1258 DEFINE_PROP_UINT8("cs", AspeedSMCFlash, cs, 0),
1259 DEFINE_PROP_LINK("controller", AspeedSMCFlash, controller, TYPE_ASPEED_SMC,
1260 AspeedSMCState *),
1261 DEFINE_PROP_END_OF_LIST(),
1262 };
1263
1264 static void aspeed_smc_flash_class_init(ObjectClass *klass, void *data)
1265 {
1266 DeviceClass *dc = DEVICE_CLASS(klass);
1267
1268 dc->desc = "Aspeed SMC Flash device region";
1269 dc->realize = aspeed_smc_flash_realize;
1270 device_class_set_props(dc, aspeed_smc_flash_properties);
1271 }
1272
1273 static const TypeInfo aspeed_smc_flash_info = {
1274 .name = TYPE_ASPEED_SMC_FLASH,
1275 .parent = TYPE_SYS_BUS_DEVICE,
1276 .instance_size = sizeof(AspeedSMCFlash),
1277 .class_init = aspeed_smc_flash_class_init,
1278 };
1279
1280 /*
1281 * The Segment Registers of the AST2400 and AST2500 have a 8MB
1282 * unit. The address range of a flash SPI peripheral is encoded with
1283 * absolute addresses which should be part of the overall controller
1284 * window.
1285 */
1286 static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s,
1287 const AspeedSegments *seg)
1288 {
1289 uint32_t reg = 0;
1290 reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT;
1291 reg |= (((seg->addr + seg->size) >> 23) & SEG_END_MASK) << SEG_END_SHIFT;
1292 return reg;
1293 }
1294
1295 static void aspeed_smc_reg_to_segment(const AspeedSMCState *s,
1296 uint32_t reg, AspeedSegments *seg)
1297 {
1298 seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23;
1299 seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr;
1300 }
1301
1302 static const AspeedSegments aspeed_2400_smc_segments[] = {
1303 { 0x10000000, 32 * MiB },
1304 };
1305
1306 static void aspeed_2400_smc_class_init(ObjectClass *klass, void *data)
1307 {
1308 DeviceClass *dc = DEVICE_CLASS(klass);
1309 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1310
1311 dc->desc = "Aspeed 2400 SMC Controller";
1312 asc->r_conf = R_CONF;
1313 asc->r_ce_ctrl = R_CE_CTRL;
1314 asc->r_ctrl0 = R_CTRL0;
1315 asc->r_timings = R_TIMINGS;
1316 asc->nregs_timings = 1;
1317 asc->conf_enable_w0 = CONF_ENABLE_W0;
1318 asc->max_peripherals = 1;
1319 asc->segments = aspeed_2400_smc_segments;
1320 asc->flash_window_base = 0x10000000;
1321 asc->flash_window_size = 0x6000000;
1322 asc->features = 0x0;
1323 asc->nregs = ASPEED_SMC_R_SMC_MAX;
1324 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1325 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1326 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1327 }
1328
1329 static const TypeInfo aspeed_2400_smc_info = {
1330 .name = "aspeed.smc-ast2400",
1331 .parent = TYPE_ASPEED_SMC,
1332 .class_init = aspeed_2400_smc_class_init,
1333 };
1334
1335 static const uint32_t aspeed_2400_fmc_resets[ASPEED_SMC_R_MAX] = {
1336 /*
1337 * CE0 and CE1 types are HW strapped in SCU70. Do it here to
1338 * simplify the model.
1339 */
1340 [R_CONF] = CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0,
1341 };
1342
1343 static const AspeedSegments aspeed_2400_fmc_segments[] = {
1344 { 0x20000000, 64 * MiB }, /* start address is readonly */
1345 { 0x24000000, 32 * MiB },
1346 { 0x26000000, 32 * MiB },
1347 { 0x28000000, 32 * MiB },
1348 { 0x2A000000, 32 * MiB }
1349 };
1350
1351 static void aspeed_2400_fmc_class_init(ObjectClass *klass, void *data)
1352 {
1353 DeviceClass *dc = DEVICE_CLASS(klass);
1354 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1355
1356 dc->desc = "Aspeed 2400 FMC Controller";
1357 asc->r_conf = R_CONF;
1358 asc->r_ce_ctrl = R_CE_CTRL;
1359 asc->r_ctrl0 = R_CTRL0;
1360 asc->r_timings = R_TIMINGS;
1361 asc->nregs_timings = 1;
1362 asc->conf_enable_w0 = CONF_ENABLE_W0;
1363 asc->max_peripherals = 5;
1364 asc->segments = aspeed_2400_fmc_segments;
1365 asc->resets = aspeed_2400_fmc_resets;
1366 asc->flash_window_base = 0x20000000;
1367 asc->flash_window_size = 0x10000000;
1368 asc->features = ASPEED_SMC_FEATURE_DMA;
1369 asc->dma_flash_mask = 0x0FFFFFFC;
1370 asc->dma_dram_mask = 0x1FFFFFFC;
1371 asc->nregs = ASPEED_SMC_R_MAX;
1372 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1373 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1374 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1375 }
1376
1377 static const TypeInfo aspeed_2400_fmc_info = {
1378 .name = "aspeed.fmc-ast2400",
1379 .parent = TYPE_ASPEED_SMC,
1380 .class_init = aspeed_2400_fmc_class_init,
1381 };
1382
1383 static const AspeedSegments aspeed_2400_spi1_segments[] = {
1384 { 0x30000000, 64 * MiB },
1385 };
1386
1387 static void aspeed_2400_spi1_class_init(ObjectClass *klass, void *data)
1388 {
1389 DeviceClass *dc = DEVICE_CLASS(klass);
1390 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1391
1392 dc->desc = "Aspeed 2400 SPI1 Controller";
1393 asc->r_conf = R_SPI_CONF;
1394 asc->r_ce_ctrl = 0xff;
1395 asc->r_ctrl0 = R_SPI_CTRL0;
1396 asc->r_timings = R_SPI_TIMINGS;
1397 asc->nregs_timings = 1;
1398 asc->conf_enable_w0 = SPI_CONF_ENABLE_W0;
1399 asc->max_peripherals = 1;
1400 asc->segments = aspeed_2400_spi1_segments;
1401 asc->flash_window_base = 0x30000000;
1402 asc->flash_window_size = 0x10000000;
1403 asc->features = 0x0;
1404 asc->nregs = ASPEED_SMC_R_SPI_MAX;
1405 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1406 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1407 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1408 }
1409
1410 static const TypeInfo aspeed_2400_spi1_info = {
1411 .name = "aspeed.spi1-ast2400",
1412 .parent = TYPE_ASPEED_SMC,
1413 .class_init = aspeed_2400_spi1_class_init,
1414 };
1415
1416 static const uint32_t aspeed_2500_fmc_resets[ASPEED_SMC_R_MAX] = {
1417 [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |
1418 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1),
1419 };
1420
1421 static const AspeedSegments aspeed_2500_fmc_segments[] = {
1422 { 0x20000000, 128 * MiB }, /* start address is readonly */
1423 { 0x28000000, 32 * MiB },
1424 { 0x2A000000, 32 * MiB },
1425 };
1426
1427 static void aspeed_2500_fmc_class_init(ObjectClass *klass, void *data)
1428 {
1429 DeviceClass *dc = DEVICE_CLASS(klass);
1430 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1431
1432 dc->desc = "Aspeed 2600 FMC Controller";
1433 asc->r_conf = R_CONF;
1434 asc->r_ce_ctrl = R_CE_CTRL;
1435 asc->r_ctrl0 = R_CTRL0;
1436 asc->r_timings = R_TIMINGS;
1437 asc->nregs_timings = 1;
1438 asc->conf_enable_w0 = CONF_ENABLE_W0;
1439 asc->max_peripherals = 3;
1440 asc->segments = aspeed_2500_fmc_segments;
1441 asc->resets = aspeed_2500_fmc_resets;
1442 asc->flash_window_base = 0x20000000;
1443 asc->flash_window_size = 0x10000000;
1444 asc->features = ASPEED_SMC_FEATURE_DMA;
1445 asc->dma_flash_mask = 0x0FFFFFFC;
1446 asc->dma_dram_mask = 0x3FFFFFFC;
1447 asc->nregs = ASPEED_SMC_R_MAX;
1448 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1449 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1450 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1451 }
1452
1453 static const TypeInfo aspeed_2500_fmc_info = {
1454 .name = "aspeed.fmc-ast2500",
1455 .parent = TYPE_ASPEED_SMC,
1456 .class_init = aspeed_2500_fmc_class_init,
1457 };
1458
1459 static const AspeedSegments aspeed_2500_spi1_segments[] = {
1460 { 0x30000000, 32 * MiB }, /* start address is readonly */
1461 { 0x32000000, 96 * MiB }, /* end address is readonly */
1462 };
1463
1464 static void aspeed_2500_spi1_class_init(ObjectClass *klass, void *data)
1465 {
1466 DeviceClass *dc = DEVICE_CLASS(klass);
1467 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1468
1469 dc->desc = "Aspeed 2600 SPI1 Controller";
1470 asc->r_conf = R_CONF;
1471 asc->r_ce_ctrl = R_CE_CTRL;
1472 asc->r_ctrl0 = R_CTRL0;
1473 asc->r_timings = R_TIMINGS;
1474 asc->nregs_timings = 1;
1475 asc->conf_enable_w0 = CONF_ENABLE_W0;
1476 asc->max_peripherals = 2;
1477 asc->segments = aspeed_2500_spi1_segments;
1478 asc->flash_window_base = 0x30000000;
1479 asc->flash_window_size = 0x8000000;
1480 asc->features = 0x0;
1481 asc->nregs = ASPEED_SMC_R_MAX;
1482 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1483 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1484 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1485 }
1486
1487 static const TypeInfo aspeed_2500_spi1_info = {
1488 .name = "aspeed.spi1-ast2500",
1489 .parent = TYPE_ASPEED_SMC,
1490 .class_init = aspeed_2500_spi1_class_init,
1491 };
1492
1493 static const AspeedSegments aspeed_2500_spi2_segments[] = {
1494 { 0x38000000, 32 * MiB }, /* start address is readonly */
1495 { 0x3A000000, 96 * MiB }, /* end address is readonly */
1496 };
1497
1498 static void aspeed_2500_spi2_class_init(ObjectClass *klass, void *data)
1499 {
1500 DeviceClass *dc = DEVICE_CLASS(klass);
1501 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1502
1503 dc->desc = "Aspeed 2600 SPI2 Controller";
1504 asc->r_conf = R_CONF;
1505 asc->r_ce_ctrl = R_CE_CTRL;
1506 asc->r_ctrl0 = R_CTRL0;
1507 asc->r_timings = R_TIMINGS;
1508 asc->nregs_timings = 1;
1509 asc->conf_enable_w0 = CONF_ENABLE_W0;
1510 asc->max_peripherals = 2;
1511 asc->segments = aspeed_2500_spi2_segments;
1512 asc->flash_window_base = 0x38000000;
1513 asc->flash_window_size = 0x8000000;
1514 asc->features = 0x0;
1515 asc->nregs = ASPEED_SMC_R_MAX;
1516 asc->segment_to_reg = aspeed_smc_segment_to_reg;
1517 asc->reg_to_segment = aspeed_smc_reg_to_segment;
1518 asc->dma_ctrl = aspeed_smc_dma_ctrl;
1519 }
1520
1521 static const TypeInfo aspeed_2500_spi2_info = {
1522 .name = "aspeed.spi2-ast2500",
1523 .parent = TYPE_ASPEED_SMC,
1524 .class_init = aspeed_2500_spi2_class_init,
1525 };
1526
1527 /*
1528 * The Segment Registers of the AST2600 have a 1MB unit. The address
1529 * range of a flash SPI peripheral is encoded with offsets in the overall
1530 * controller window. The previous SoC AST2400 and AST2500 used
1531 * absolute addresses. Only bits [27:20] are relevant and the end
1532 * address is an upper bound limit.
1533 */
1534 #define AST2600_SEG_ADDR_MASK 0x0ff00000
1535
1536 static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s,
1537 const AspeedSegments *seg)
1538 {
1539 uint32_t reg = 0;
1540
1541 /* Disabled segments have a nil register */
1542 if (!seg->size) {
1543 return 0;
1544 }
1545
1546 reg |= (seg->addr & AST2600_SEG_ADDR_MASK) >> 16; /* start offset */
1547 reg |= (seg->addr + seg->size - 1) & AST2600_SEG_ADDR_MASK; /* end offset */
1548 return reg;
1549 }
1550
1551 static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s,
1552 uint32_t reg, AspeedSegments *seg)
1553 {
1554 uint32_t start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK;
1555 uint32_t end_offset = reg & AST2600_SEG_ADDR_MASK;
1556 AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s);
1557
1558 if (reg) {
1559 seg->addr = asc->flash_window_base + start_offset;
1560 seg->size = end_offset + MiB - start_offset;
1561 } else {
1562 seg->addr = asc->flash_window_base;
1563 seg->size = 0;
1564 }
1565 }
1566
1567 static const uint32_t aspeed_2600_fmc_resets[ASPEED_SMC_R_MAX] = {
1568 [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |
1569 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1 |
1570 CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE2),
1571 };
1572
1573 static const AspeedSegments aspeed_2600_fmc_segments[] = {
1574 { 0x0, 128 * MiB }, /* start address is readonly */
1575 { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */
1576 { 0x0, 0 }, /* disabled */
1577 };
1578
1579 static void aspeed_2600_fmc_class_init(ObjectClass *klass, void *data)
1580 {
1581 DeviceClass *dc = DEVICE_CLASS(klass);
1582 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1583
1584 dc->desc = "Aspeed 2600 FMC Controller";
1585 asc->r_conf = R_CONF;
1586 asc->r_ce_ctrl = R_CE_CTRL;
1587 asc->r_ctrl0 = R_CTRL0;
1588 asc->r_timings = R_TIMINGS;
1589 asc->nregs_timings = 1;
1590 asc->conf_enable_w0 = CONF_ENABLE_W0;
1591 asc->max_peripherals = 3;
1592 asc->segments = aspeed_2600_fmc_segments;
1593 asc->resets = aspeed_2600_fmc_resets;
1594 asc->flash_window_base = 0x20000000;
1595 asc->flash_window_size = 0x10000000;
1596 asc->features = ASPEED_SMC_FEATURE_DMA |
1597 ASPEED_SMC_FEATURE_WDT_CONTROL;
1598 asc->dma_flash_mask = 0x0FFFFFFC;
1599 asc->dma_dram_mask = 0x3FFFFFFC;
1600 asc->nregs = ASPEED_SMC_R_MAX;
1601 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
1602 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
1603 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
1604 }
1605
1606 static const TypeInfo aspeed_2600_fmc_info = {
1607 .name = "aspeed.fmc-ast2600",
1608 .parent = TYPE_ASPEED_SMC,
1609 .class_init = aspeed_2600_fmc_class_init,
1610 };
1611
1612 static const AspeedSegments aspeed_2600_spi1_segments[] = {
1613 { 0x0, 128 * MiB }, /* start address is readonly */
1614 { 0x0, 0 }, /* disabled */
1615 };
1616
1617 static void aspeed_2600_spi1_class_init(ObjectClass *klass, void *data)
1618 {
1619 DeviceClass *dc = DEVICE_CLASS(klass);
1620 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1621
1622 dc->desc = "Aspeed 2600 SPI1 Controller";
1623 asc->r_conf = R_CONF;
1624 asc->r_ce_ctrl = R_CE_CTRL;
1625 asc->r_ctrl0 = R_CTRL0;
1626 asc->r_timings = R_TIMINGS;
1627 asc->nregs_timings = 2;
1628 asc->conf_enable_w0 = CONF_ENABLE_W0;
1629 asc->max_peripherals = 2;
1630 asc->segments = aspeed_2600_spi1_segments;
1631 asc->flash_window_base = 0x30000000;
1632 asc->flash_window_size = 0x10000000;
1633 asc->features = ASPEED_SMC_FEATURE_DMA |
1634 ASPEED_SMC_FEATURE_DMA_GRANT;
1635 asc->dma_flash_mask = 0x0FFFFFFC;
1636 asc->dma_dram_mask = 0x3FFFFFFC;
1637 asc->nregs = ASPEED_SMC_R_MAX;
1638 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
1639 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
1640 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
1641 }
1642
1643 static const TypeInfo aspeed_2600_spi1_info = {
1644 .name = "aspeed.spi1-ast2600",
1645 .parent = TYPE_ASPEED_SMC,
1646 .class_init = aspeed_2600_spi1_class_init,
1647 };
1648
1649 static const AspeedSegments aspeed_2600_spi2_segments[] = {
1650 { 0x0, 128 * MiB }, /* start address is readonly */
1651 { 0x0, 0 }, /* disabled */
1652 { 0x0, 0 }, /* disabled */
1653 };
1654
1655 static void aspeed_2600_spi2_class_init(ObjectClass *klass, void *data)
1656 {
1657 DeviceClass *dc = DEVICE_CLASS(klass);
1658 AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass);
1659
1660 dc->desc = "Aspeed 2600 SPI2 Controller";
1661 asc->r_conf = R_CONF;
1662 asc->r_ce_ctrl = R_CE_CTRL;
1663 asc->r_ctrl0 = R_CTRL0;
1664 asc->r_timings = R_TIMINGS;
1665 asc->nregs_timings = 3;
1666 asc->conf_enable_w0 = CONF_ENABLE_W0;
1667 asc->max_peripherals = 3;
1668 asc->segments = aspeed_2600_spi2_segments;
1669 asc->flash_window_base = 0x50000000;
1670 asc->flash_window_size = 0x10000000;
1671 asc->features = ASPEED_SMC_FEATURE_DMA |
1672 ASPEED_SMC_FEATURE_DMA_GRANT;
1673 asc->dma_flash_mask = 0x0FFFFFFC;
1674 asc->dma_dram_mask = 0x3FFFFFFC;
1675 asc->nregs = ASPEED_SMC_R_MAX;
1676 asc->segment_to_reg = aspeed_2600_smc_segment_to_reg;
1677 asc->reg_to_segment = aspeed_2600_smc_reg_to_segment;
1678 asc->dma_ctrl = aspeed_2600_smc_dma_ctrl;
1679 }
1680
1681 static const TypeInfo aspeed_2600_spi2_info = {
1682 .name = "aspeed.spi2-ast2600",
1683 .parent = TYPE_ASPEED_SMC,
1684 .class_init = aspeed_2600_spi2_class_init,
1685 };
1686
1687 static void aspeed_smc_register_types(void)
1688 {
1689 type_register_static(&aspeed_smc_flash_info);
1690 type_register_static(&aspeed_smc_info);
1691 type_register_static(&aspeed_2400_smc_info);
1692 type_register_static(&aspeed_2400_fmc_info);
1693 type_register_static(&aspeed_2400_spi1_info);
1694 type_register_static(&aspeed_2500_fmc_info);
1695 type_register_static(&aspeed_2500_spi1_info);
1696 type_register_static(&aspeed_2500_spi2_info);
1697 type_register_static(&aspeed_2600_fmc_info);
1698 type_register_static(&aspeed_2600_spi1_info);
1699 type_register_static(&aspeed_2600_spi2_info);
1700 }
1701
1702 type_init(aspeed_smc_register_types)
QEmu