s390x: introduce 2.11 compat machine
[qemu.git] / target / arm / helper-a64.c
blobd9df82cff55a61eb5466328db2e2a0f4fc958d35
1 /*
2 * AArch64 specific helpers
4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/gdbstub.h"
23 #include "exec/helper-proto.h"
24 #include "qemu/host-utils.h"
25 #include "qemu/log.h"
26 #include "sysemu/sysemu.h"
27 #include "qemu/bitops.h"
28 #include "internals.h"
29 #include "qemu/crc32c.h"
30 #include "exec/exec-all.h"
31 #include "exec/cpu_ldst.h"
32 #include "qemu/int128.h"
33 #include "tcg.h"
34 #include <zlib.h> /* For crc32 */
36 /* C2.4.7 Multiply and divide */
37 /* special cases for 0 and LLONG_MIN are mandated by the standard */
38 uint64_t HELPER(udiv64)(uint64_t num, uint64_t den)
40 if (den == 0) {
41 return 0;
43 return num / den;
46 int64_t HELPER(sdiv64)(int64_t num, int64_t den)
48 if (den == 0) {
49 return 0;
51 if (num == LLONG_MIN && den == -1) {
52 return LLONG_MIN;
54 return num / den;
57 uint64_t HELPER(rbit64)(uint64_t x)
59 return revbit64(x);
62 /* Convert a softfloat float_relation_ (as returned by
63 * the float*_compare functions) to the correct ARM
64 * NZCV flag state.
66 static inline uint32_t float_rel_to_flags(int res)
68 uint64_t flags;
69 switch (res) {
70 case float_relation_equal:
71 flags = PSTATE_Z | PSTATE_C;
72 break;
73 case float_relation_less:
74 flags = PSTATE_N;
75 break;
76 case float_relation_greater:
77 flags = PSTATE_C;
78 break;
79 case float_relation_unordered:
80 default:
81 flags = PSTATE_C | PSTATE_V;
82 break;
84 return flags;
87 uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
89 return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
92 uint64_t HELPER(vfp_cmpes_a64)(float32 x, float32 y, void *fp_status)
94 return float_rel_to_flags(float32_compare(x, y, fp_status));
97 uint64_t HELPER(vfp_cmpd_a64)(float64 x, float64 y, void *fp_status)
99 return float_rel_to_flags(float64_compare_quiet(x, y, fp_status));
102 uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, void *fp_status)
104 return float_rel_to_flags(float64_compare(x, y, fp_status));
107 float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp)
109 float_status *fpst = fpstp;
111 a = float32_squash_input_denormal(a, fpst);
112 b = float32_squash_input_denormal(b, fpst);
114 if ((float32_is_zero(a) && float32_is_infinity(b)) ||
115 (float32_is_infinity(a) && float32_is_zero(b))) {
116 /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
117 return make_float32((1U << 30) |
118 ((float32_val(a) ^ float32_val(b)) & (1U << 31)));
120 return float32_mul(a, b, fpst);
123 float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
125 float_status *fpst = fpstp;
127 a = float64_squash_input_denormal(a, fpst);
128 b = float64_squash_input_denormal(b, fpst);
130 if ((float64_is_zero(a) && float64_is_infinity(b)) ||
131 (float64_is_infinity(a) && float64_is_zero(b))) {
132 /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
133 return make_float64((1ULL << 62) |
134 ((float64_val(a) ^ float64_val(b)) & (1ULL << 63)));
136 return float64_mul(a, b, fpst);
139 uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t indices,
140 uint32_t rn, uint32_t numregs)
142 /* Helper function for SIMD TBL and TBX. We have to do the table
143 * lookup part for the 64 bits worth of indices we're passed in.
144 * result is the initial results vector (either zeroes for TBL
145 * or some guest values for TBX), rn the register number where
146 * the table starts, and numregs the number of registers in the table.
147 * We return the results of the lookups.
149 int shift;
151 for (shift = 0; shift < 64; shift += 8) {
152 int index = extract64(indices, shift, 8);
153 if (index < 16 * numregs) {
154 /* Convert index (a byte offset into the virtual table
155 * which is a series of 128-bit vectors concatenated)
156 * into the correct vfp.regs[] element plus a bit offset
157 * into that element, bearing in mind that the table
158 * can wrap around from V31 to V0.
160 int elt = (rn * 2 + (index >> 3)) % 64;
161 int bitidx = (index & 7) * 8;
162 uint64_t val = extract64(env->vfp.regs[elt], bitidx, 8);
164 result = deposit64(result, shift, 8, val);
167 return result;
170 /* 64bit/double versions of the neon float compare functions */
171 uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp)
173 float_status *fpst = fpstp;
174 return -float64_eq_quiet(a, b, fpst);
177 uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, void *fpstp)
179 float_status *fpst = fpstp;
180 return -float64_le(b, a, fpst);
183 uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
185 float_status *fpst = fpstp;
186 return -float64_lt(b, a, fpst);
189 /* Reciprocal step and sqrt step. Note that unlike the A32/T32
190 * versions, these do a fully fused multiply-add or
191 * multiply-add-and-halve.
193 #define float32_two make_float32(0x40000000)
194 #define float32_three make_float32(0x40400000)
195 #define float32_one_point_five make_float32(0x3fc00000)
197 #define float64_two make_float64(0x4000000000000000ULL)
198 #define float64_three make_float64(0x4008000000000000ULL)
199 #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
201 float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
203 float_status *fpst = fpstp;
205 a = float32_squash_input_denormal(a, fpst);
206 b = float32_squash_input_denormal(b, fpst);
208 a = float32_chs(a);
209 if ((float32_is_infinity(a) && float32_is_zero(b)) ||
210 (float32_is_infinity(b) && float32_is_zero(a))) {
211 return float32_two;
213 return float32_muladd(a, b, float32_two, 0, fpst);
216 float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
218 float_status *fpst = fpstp;
220 a = float64_squash_input_denormal(a, fpst);
221 b = float64_squash_input_denormal(b, fpst);
223 a = float64_chs(a);
224 if ((float64_is_infinity(a) && float64_is_zero(b)) ||
225 (float64_is_infinity(b) && float64_is_zero(a))) {
226 return float64_two;
228 return float64_muladd(a, b, float64_two, 0, fpst);
231 float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
233 float_status *fpst = fpstp;
235 a = float32_squash_input_denormal(a, fpst);
236 b = float32_squash_input_denormal(b, fpst);
238 a = float32_chs(a);
239 if ((float32_is_infinity(a) && float32_is_zero(b)) ||
240 (float32_is_infinity(b) && float32_is_zero(a))) {
241 return float32_one_point_five;
243 return float32_muladd(a, b, float32_three, float_muladd_halve_result, fpst);
246 float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
248 float_status *fpst = fpstp;
250 a = float64_squash_input_denormal(a, fpst);
251 b = float64_squash_input_denormal(b, fpst);
253 a = float64_chs(a);
254 if ((float64_is_infinity(a) && float64_is_zero(b)) ||
255 (float64_is_infinity(b) && float64_is_zero(a))) {
256 return float64_one_point_five;
258 return float64_muladd(a, b, float64_three, float_muladd_halve_result, fpst);
261 /* Pairwise long add: add pairs of adjacent elements into
262 * double-width elements in the result (eg _s8 is an 8x8->16 op)
264 uint64_t HELPER(neon_addlp_s8)(uint64_t a)
266 uint64_t nsignmask = 0x0080008000800080ULL;
267 uint64_t wsignmask = 0x8000800080008000ULL;
268 uint64_t elementmask = 0x00ff00ff00ff00ffULL;
269 uint64_t tmp1, tmp2;
270 uint64_t res, signres;
272 /* Extract odd elements, sign extend each to a 16 bit field */
273 tmp1 = a & elementmask;
274 tmp1 ^= nsignmask;
275 tmp1 |= wsignmask;
276 tmp1 = (tmp1 - nsignmask) ^ wsignmask;
277 /* Ditto for the even elements */
278 tmp2 = (a >> 8) & elementmask;
279 tmp2 ^= nsignmask;
280 tmp2 |= wsignmask;
281 tmp2 = (tmp2 - nsignmask) ^ wsignmask;
283 /* calculate the result by summing bits 0..14, 16..22, etc,
284 * and then adjusting the sign bits 15, 23, etc manually.
285 * This ensures the addition can't overflow the 16 bit field.
287 signres = (tmp1 ^ tmp2) & wsignmask;
288 res = (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask);
289 res ^= signres;
291 return res;
294 uint64_t HELPER(neon_addlp_u8)(uint64_t a)
296 uint64_t tmp;
298 tmp = a & 0x00ff00ff00ff00ffULL;
299 tmp += (a >> 8) & 0x00ff00ff00ff00ffULL;
300 return tmp;
303 uint64_t HELPER(neon_addlp_s16)(uint64_t a)
305 int32_t reslo, reshi;
307 reslo = (int32_t)(int16_t)a + (int32_t)(int16_t)(a >> 16);
308 reshi = (int32_t)(int16_t)(a >> 32) + (int32_t)(int16_t)(a >> 48);
310 return (uint32_t)reslo | (((uint64_t)reshi) << 32);
313 uint64_t HELPER(neon_addlp_u16)(uint64_t a)
315 uint64_t tmp;
317 tmp = a & 0x0000ffff0000ffffULL;
318 tmp += (a >> 16) & 0x0000ffff0000ffffULL;
319 return tmp;
322 /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
323 float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
325 float_status *fpst = fpstp;
326 uint32_t val32, sbit;
327 int32_t exp;
329 if (float32_is_any_nan(a)) {
330 float32 nan = a;
331 if (float32_is_signaling_nan(a, fpst)) {
332 float_raise(float_flag_invalid, fpst);
333 nan = float32_maybe_silence_nan(a, fpst);
335 if (fpst->default_nan_mode) {
336 nan = float32_default_nan(fpst);
338 return nan;
341 val32 = float32_val(a);
342 sbit = 0x80000000ULL & val32;
343 exp = extract32(val32, 23, 8);
345 if (exp == 0) {
346 return make_float32(sbit | (0xfe << 23));
347 } else {
348 return make_float32(sbit | (~exp & 0xff) << 23);
352 float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
354 float_status *fpst = fpstp;
355 uint64_t val64, sbit;
356 int64_t exp;
358 if (float64_is_any_nan(a)) {
359 float64 nan = a;
360 if (float64_is_signaling_nan(a, fpst)) {
361 float_raise(float_flag_invalid, fpst);
362 nan = float64_maybe_silence_nan(a, fpst);
364 if (fpst->default_nan_mode) {
365 nan = float64_default_nan(fpst);
367 return nan;
370 val64 = float64_val(a);
371 sbit = 0x8000000000000000ULL & val64;
372 exp = extract64(float64_val(a), 52, 11);
374 if (exp == 0) {
375 return make_float64(sbit | (0x7feULL << 52));
376 } else {
377 return make_float64(sbit | (~exp & 0x7ffULL) << 52);
381 float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env)
383 /* Von Neumann rounding is implemented by using round-to-zero
384 * and then setting the LSB of the result if Inexact was raised.
386 float32 r;
387 float_status *fpst = &env->vfp.fp_status;
388 float_status tstat = *fpst;
389 int exflags;
391 set_float_rounding_mode(float_round_to_zero, &tstat);
392 set_float_exception_flags(0, &tstat);
393 r = float64_to_float32(a, &tstat);
394 r = float32_maybe_silence_nan(r, &tstat);
395 exflags = get_float_exception_flags(&tstat);
396 if (exflags & float_flag_inexact) {
397 r = make_float32(float32_val(r) | 1);
399 exflags |= get_float_exception_flags(fpst);
400 set_float_exception_flags(exflags, fpst);
401 return r;
404 /* 64-bit versions of the CRC helpers. Note that although the operation
405 * (and the prototypes of crc32c() and crc32() mean that only the bottom
406 * 32 bits of the accumulator and result are used, we pass and return
407 * uint64_t for convenience of the generated code. Unlike the 32-bit
408 * instruction set versions, val may genuinely have 64 bits of data in it.
409 * The upper bytes of val (above the number specified by 'bytes') must have
410 * been zeroed out by the caller.
412 uint64_t HELPER(crc32_64)(uint64_t acc, uint64_t val, uint32_t bytes)
414 uint8_t buf[8];
416 stq_le_p(buf, val);
418 /* zlib crc32 converts the accumulator and output to one's complement. */
419 return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
422 uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes)
424 uint8_t buf[8];
426 stq_le_p(buf, val);
428 /* Linux crc32c converts the output to one's complement. */
429 return crc32c(acc, buf, bytes) ^ 0xffffffff;
432 /* Returns 0 on success; 1 otherwise. */
433 uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
434 uint64_t new_lo, uint64_t new_hi)
436 uintptr_t ra = GETPC();
437 Int128 oldv, cmpv, newv;
438 bool success;
440 cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
441 newv = int128_make128(new_lo, new_hi);
443 if (parallel_cpus) {
444 #ifndef CONFIG_ATOMIC128
445 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
446 #else
447 int mem_idx = cpu_mmu_index(env, false);
448 TCGMemOpIdx oi = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
449 oldv = helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra);
450 success = int128_eq(oldv, cmpv);
451 #endif
452 } else {
453 uint64_t o0, o1;
455 #ifdef CONFIG_USER_ONLY
456 /* ??? Enforce alignment. */
457 uint64_t *haddr = g2h(addr);
458 o0 = ldq_le_p(haddr + 0);
459 o1 = ldq_le_p(haddr + 1);
460 oldv = int128_make128(o0, o1);
462 success = int128_eq(oldv, cmpv);
463 if (success) {
464 stq_le_p(haddr + 0, int128_getlo(newv));
465 stq_le_p(haddr + 1, int128_gethi(newv));
467 #else
468 int mem_idx = cpu_mmu_index(env, false);
469 TCGMemOpIdx oi0 = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
470 TCGMemOpIdx oi1 = make_memop_idx(MO_LEQ, mem_idx);
472 o0 = helper_le_ldq_mmu(env, addr + 0, oi0, ra);
473 o1 = helper_le_ldq_mmu(env, addr + 8, oi1, ra);
474 oldv = int128_make128(o0, o1);
476 success = int128_eq(oldv, cmpv);
477 if (success) {
478 helper_le_stq_mmu(env, addr + 0, int128_getlo(newv), oi1, ra);
479 helper_le_stq_mmu(env, addr + 8, int128_gethi(newv), oi1, ra);
481 #endif
484 return !success;
487 uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
488 uint64_t new_lo, uint64_t new_hi)
490 uintptr_t ra = GETPC();
491 Int128 oldv, cmpv, newv;
492 bool success;
494 cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
495 newv = int128_make128(new_lo, new_hi);
497 if (parallel_cpus) {
498 #ifndef CONFIG_ATOMIC128
499 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
500 #else
501 int mem_idx = cpu_mmu_index(env, false);
502 TCGMemOpIdx oi = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
503 oldv = helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra);
504 success = int128_eq(oldv, cmpv);
505 #endif
506 } else {
507 uint64_t o0, o1;
509 #ifdef CONFIG_USER_ONLY
510 /* ??? Enforce alignment. */
511 uint64_t *haddr = g2h(addr);
512 o1 = ldq_be_p(haddr + 0);
513 o0 = ldq_be_p(haddr + 1);
514 oldv = int128_make128(o0, o1);
516 success = int128_eq(oldv, cmpv);
517 if (success) {
518 stq_be_p(haddr + 0, int128_gethi(newv));
519 stq_be_p(haddr + 1, int128_getlo(newv));
521 #else
522 int mem_idx = cpu_mmu_index(env, false);
523 TCGMemOpIdx oi0 = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
524 TCGMemOpIdx oi1 = make_memop_idx(MO_BEQ, mem_idx);
526 o1 = helper_be_ldq_mmu(env, addr + 0, oi0, ra);
527 o0 = helper_be_ldq_mmu(env, addr + 8, oi1, ra);
528 oldv = int128_make128(o0, o1);
530 success = int128_eq(oldv, cmpv);
531 if (success) {
532 helper_be_stq_mmu(env, addr + 0, int128_gethi(newv), oi1, ra);
533 helper_be_stq_mmu(env, addr + 8, int128_getlo(newv), oi1, ra);
535 #endif
538 return !success;