target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/qmp/qerror.h"
  26 #if !defined(CONFIG_USER_ONLY)
  27 #include "hw/loader.h"
  28 #endif
  29 #include "hw/arm/arm.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/kvm.h"
  32 #include "kvm_arm.h"
  33
  34 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  35 {
  36     ARMCPU *cpu = ARM_CPU(cs);
  37
  38     cpu->env.regs[15] = value;
  39 }
  40
  41 static bool arm_cpu_has_work(CPUState *cs)
  42 {
  43     return cs->interrupt_request &
  44         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
  45 }
  46
  47 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  48 {
  49     /* Reset a single ARMCPRegInfo register */
  50     ARMCPRegInfo *ri = value;
  51     ARMCPU *cpu = opaque;
  52
  53     if (ri->type & ARM_CP_SPECIAL) {
  54         return;
  55     }
  56
  57     if (ri->resetfn) {
  58         ri->resetfn(&cpu->env, ri);
  59         return;
  60     }
  61
  62     /* A zero offset is never possible as it would be regs[0]
  63      * so we use it to indicate that reset is being handled elsewhere.
  64      * This is basically only used for fields in non-core coprocessors
  65      * (like the pxa2xx ones).
  66      */
  67     if (!ri->fieldoffset) {
  68         return;
  69     }
  70
  71     if (cpreg_field_is_64bit(ri)) {
  72         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  73     } else {
  74         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  75     }
  76 }
  77
  78 /* CPUClass::reset() */
  79 static void arm_cpu_reset(CPUState *s)
  80 {
  81     ARMCPU *cpu = ARM_CPU(s);
  82     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  83     CPUARMState *env = &cpu->env;
  84
  85     acc->parent_reset(s);
  86
  87     memset(env, 0, offsetof(CPUARMState, features));
  88     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  89     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  90     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  91     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  92     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
  93
  94     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  95         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  96     }
  97
  98     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
  99         /* 64 bit CPUs always start in 64 bit mode */
 100         env->aarch64 = 1;
 101 #if defined(CONFIG_USER_ONLY)
 102         env->pstate = PSTATE_MODE_EL0t;
 103         /* Userspace expects access to CTL_EL0 and the cache ops */
 104         env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI;
 105         /* and to the FP/Neon instructions */
 106         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
 107 #else
 108         env->pstate = PSTATE_MODE_EL1h;
 109         env->pc = cpu->rvbar;
 110 #endif
 111     } else {
 112 #if defined(CONFIG_USER_ONLY)
 113         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 114         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf);
 115 #endif
 116     }
 117
 118 #if defined(CONFIG_USER_ONLY)
 119     env->uncached_cpsr = ARM_CPU_MODE_USR;
 120     /* For user mode we must enable access to coprocessors */
 121     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 122     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 123         env->cp15.c15_cpar = 3;
 124     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 125         env->cp15.c15_cpar = 1;
 126     }
 127 #else
 128     /* SVC mode with interrupts disabled.  */
 129     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 130     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 131     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 132      * clear at reset. Initial SP and PC are loaded from ROM.
 133      */
 134     if (IS_M(env)) {
 135         uint32_t initial_msp; /* Loaded from 0x0 */
 136         uint32_t initial_pc; /* Loaded from 0x4 */
 137         uint8_t *rom;
 138
 139         env->daif &= ~PSTATE_I;
 140         rom = rom_ptr(0);
 141         if (rom) {
 142             /* Address zero is covered by ROM which hasn't yet been
 143              * copied into physical memory.
 144              */
 145             initial_msp = ldl_p(rom);
 146             initial_pc = ldl_p(rom + 4);
 147         } else {
 148             /* Address zero not covered by a ROM blob, or the ROM blob
 149              * is in non-modifiable memory and this is a second reset after
 150              * it got copied into memory. In the latter case, rom_ptr
 151              * will return a NULL pointer and we should use ldl_phys instead.
 152              */
 153             initial_msp = ldl_phys(s->as, 0);
 154             initial_pc = ldl_phys(s->as, 4);
 155         }
 156
 157         env->regs[13] = initial_msp & 0xFFFFFFFC;
 158         env->regs[15] = initial_pc & ~1;
 159         env->thumb = initial_pc & 1;
 160     }
 161
 162     if (env->cp15.c1_sys & SCTLR_V) {
 163         env->regs[15] = 0xFFFF0000;
 164     }
 165
 166     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 167 #endif
 168     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 169     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 170     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 171     set_float_detect_tininess(float_tininess_before_rounding,
 172                               &env->vfp.fp_status);
 173     set_float_detect_tininess(float_tininess_before_rounding,
 174                               &env->vfp.standard_fp_status);
 175     tlb_flush(s, 1);
 176     /* Reset is a state change for some CPUARMState fields which we
 177      * bake assumptions about into translated code, so we need to
 178      * tb_flush().
 179      */
 180     tb_flush(env);
 181
 182 #ifndef CONFIG_USER_ONLY
 183     if (kvm_enabled()) {
 184         kvm_arm_reset_vcpu(cpu);
 185     }
 186 #endif
 187
 188     hw_watchpoint_update_all(cpu);
 189 }
 190
 191 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 192 {
 193     CPUClass *cc = CPU_GET_CLASS(cs);
 194     ARMCPU *cpu = ARM_CPU(cs);
 195     CPUARMState *env = &cpu->env;
 196     bool ret = false;
 197
 198     if (interrupt_request & CPU_INTERRUPT_FIQ
 199         && !(env->daif & PSTATE_F)) {
 200         cs->exception_index = EXCP_FIQ;
 201         cc->do_interrupt(cs);
 202         ret = true;
 203     }
 204     /* ARMv7-M interrupt return works by loading a magic value
 205        into the PC.  On real hardware the load causes the
 206        return to occur.  The qemu implementation performs the
 207        jump normally, then does the exception return when the
 208        CPU tries to execute code at the magic address.
 209        This will cause the magic PC value to be pushed to
 210        the stack if an interrupt occurred at the wrong time.
 211        We avoid this by disabling interrupts when
 212        pc contains a magic address.  */
 213     if (interrupt_request & CPU_INTERRUPT_HARD
 214         && !(env->daif & PSTATE_I)
 215         && (!IS_M(env) || env->regs[15] < 0xfffffff0)) {
 216         cs->exception_index = EXCP_IRQ;
 217         cc->do_interrupt(cs);
 218         ret = true;
 219     }
 220
 221     return ret;
 222 }
 223
 224 #ifndef CONFIG_USER_ONLY
 225 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 226 {
 227     ARMCPU *cpu = opaque;
 228     CPUState *cs = CPU(cpu);
 229
 230     switch (irq) {
 231     case ARM_CPU_IRQ:
 232         if (level) {
 233             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 234         } else {
 235             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 236         }
 237         break;
 238     case ARM_CPU_FIQ:
 239         if (level) {
 240             cpu_interrupt(cs, CPU_INTERRUPT_FIQ);
 241         } else {
 242             cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
 243         }
 244         break;
 245     default:
 246         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 247     }
 248 }
 249
 250 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 251 {
 252 #ifdef CONFIG_KVM
 253     ARMCPU *cpu = opaque;
 254     CPUState *cs = CPU(cpu);
 255     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 256
 257     switch (irq) {
 258     case ARM_CPU_IRQ:
 259         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 260         break;
 261     case ARM_CPU_FIQ:
 262         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 263         break;
 264     default:
 265         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 266     }
 267     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 268     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 269 #endif
 270 }
 271 #endif
 272
 273 static inline void set_feature(CPUARMState *env, int feature)
 274 {
 275     env->features |= 1ULL << feature;
 276 }
 277
 278 static void arm_cpu_initfn(Object *obj)
 279 {
 280     CPUState *cs = CPU(obj);
 281     ARMCPU *cpu = ARM_CPU(obj);
 282     static bool inited;
 283
 284     cs->env_ptr = &cpu->env;
 285     cpu_exec_init(&cpu->env);
 286     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 287                                          g_free, g_free);
 288
 289 #ifndef CONFIG_USER_ONLY
 290     /* Our inbound IRQ and FIQ lines */
 291     if (kvm_enabled()) {
 292         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
 293     } else {
 294         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
 295     }
 296
 297     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 298                                                 arm_gt_ptimer_cb, cpu);
 299     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 300                                                 arm_gt_vtimer_cb, cpu);
 301     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 302                        ARRAY_SIZE(cpu->gt_timer_outputs));
 303 #endif
 304
 305     /* DTB consumers generally don't in fact care what the 'compatible'
 306      * string is, so always provide some string and trust that a hypothetical
 307      * picky DTB consumer will also provide a helpful error message.
 308      */
 309     cpu->dtb_compatible = "qemu,unknown";
 310     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 311     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 312
 313     if (tcg_enabled() && !inited) {
 314         inited = true;
 315         arm_translate_init();
 316     }
 317 }
 318
 319 static Property arm_cpu_reset_cbar_property =
 320             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 321
 322 static Property arm_cpu_reset_hivecs_property =
 323             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 324
 325 static Property arm_cpu_rvbar_property =
 326             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 327
 328 static void arm_cpu_post_init(Object *obj)
 329 {
 330     ARMCPU *cpu = ARM_CPU(obj);
 331
 332     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 333         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 334         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 335                                  &error_abort);
 336     }
 337
 338     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 339         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 340                                  &error_abort);
 341     }
 342
 343     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 344         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 345                                  &error_abort);
 346     }
 347 }
 348
 349 static void arm_cpu_finalizefn(Object *obj)
 350 {
 351     ARMCPU *cpu = ARM_CPU(obj);
 352     g_hash_table_destroy(cpu->cp_regs);
 353 }
 354
 355 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 356 {
 357     CPUState *cs = CPU(dev);
 358     ARMCPU *cpu = ARM_CPU(dev);
 359     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 360     CPUARMState *env = &cpu->env;
 361
 362     /* Some features automatically imply others: */
 363     if (arm_feature(env, ARM_FEATURE_V8)) {
 364         set_feature(env, ARM_FEATURE_V7);
 365         set_feature(env, ARM_FEATURE_ARM_DIV);
 366         set_feature(env, ARM_FEATURE_LPAE);
 367     }
 368     if (arm_feature(env, ARM_FEATURE_V7)) {
 369         set_feature(env, ARM_FEATURE_VAPA);
 370         set_feature(env, ARM_FEATURE_THUMB2);
 371         set_feature(env, ARM_FEATURE_MPIDR);
 372         if (!arm_feature(env, ARM_FEATURE_M)) {
 373             set_feature(env, ARM_FEATURE_V6K);
 374         } else {
 375             set_feature(env, ARM_FEATURE_V6);
 376         }
 377     }
 378     if (arm_feature(env, ARM_FEATURE_V6K)) {
 379         set_feature(env, ARM_FEATURE_V6);
 380         set_feature(env, ARM_FEATURE_MVFR);
 381     }
 382     if (arm_feature(env, ARM_FEATURE_V6)) {
 383         set_feature(env, ARM_FEATURE_V5);
 384         if (!arm_feature(env, ARM_FEATURE_M)) {
 385             set_feature(env, ARM_FEATURE_AUXCR);
 386         }
 387     }
 388     if (arm_feature(env, ARM_FEATURE_V5)) {
 389         set_feature(env, ARM_FEATURE_V4T);
 390     }
 391     if (arm_feature(env, ARM_FEATURE_M)) {
 392         set_feature(env, ARM_FEATURE_THUMB_DIV);
 393     }
 394     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 395         set_feature(env, ARM_FEATURE_THUMB_DIV);
 396     }
 397     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 398         set_feature(env, ARM_FEATURE_VFP3);
 399         set_feature(env, ARM_FEATURE_VFP_FP16);
 400     }
 401     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 402         set_feature(env, ARM_FEATURE_VFP);
 403     }
 404     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 405         set_feature(env, ARM_FEATURE_V7MP);
 406         set_feature(env, ARM_FEATURE_PXN);
 407     }
 408     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 409         set_feature(env, ARM_FEATURE_CBAR);
 410     }
 411
 412     if (cpu->reset_hivecs) {
 413             cpu->reset_sctlr |= (1 << 13);
 414     }
 415
 416     register_cp_regs_for_features(cpu);
 417     arm_cpu_register_gdb_regs_for_features(cpu);
 418
 419     init_cpreg_list(cpu);
 420
 421     qemu_init_vcpu(cs);
 422     cpu_reset(cs);
 423
 424     acc->parent_realize(dev, errp);
 425 }
 426
 427 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 428 {
 429     ObjectClass *oc;
 430     char *typename;
 431
 432     if (!cpu_model) {
 433         return NULL;
 434     }
 435
 436     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 437     oc = object_class_by_name(typename);
 438     g_free(typename);
 439     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 440         object_class_is_abstract(oc)) {
 441         return NULL;
 442     }
 443     return oc;
 444 }
 445
 446 /* CPU models. These are not needed for the AArch64 linux-user build. */
 447 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 448
 449 static void arm926_initfn(Object *obj)
 450 {
 451     ARMCPU *cpu = ARM_CPU(obj);
 452
 453     cpu->dtb_compatible = "arm,arm926";
 454     set_feature(&cpu->env, ARM_FEATURE_V5);
 455     set_feature(&cpu->env, ARM_FEATURE_VFP);
 456     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 457     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 458     cpu->midr = 0x41069265;
 459     cpu->reset_fpsid = 0x41011090;
 460     cpu->ctr = 0x1dd20d2;
 461     cpu->reset_sctlr = 0x00090078;
 462 }
 463
 464 static void arm946_initfn(Object *obj)
 465 {
 466     ARMCPU *cpu = ARM_CPU(obj);
 467
 468     cpu->dtb_compatible = "arm,arm946";
 469     set_feature(&cpu->env, ARM_FEATURE_V5);
 470     set_feature(&cpu->env, ARM_FEATURE_MPU);
 471     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 472     cpu->midr = 0x41059461;
 473     cpu->ctr = 0x0f004006;
 474     cpu->reset_sctlr = 0x00000078;
 475 }
 476
 477 static void arm1026_initfn(Object *obj)
 478 {
 479     ARMCPU *cpu = ARM_CPU(obj);
 480
 481     cpu->dtb_compatible = "arm,arm1026";
 482     set_feature(&cpu->env, ARM_FEATURE_V5);
 483     set_feature(&cpu->env, ARM_FEATURE_VFP);
 484     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 485     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 486     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 487     cpu->midr = 0x4106a262;
 488     cpu->reset_fpsid = 0x410110a0;
 489     cpu->ctr = 0x1dd20d2;
 490     cpu->reset_sctlr = 0x00090078;
 491     cpu->reset_auxcr = 1;
 492     {
 493         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 494         ARMCPRegInfo ifar = {
 495             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 496             .access = PL1_RW,
 497             .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
 498             .resetvalue = 0
 499         };
 500         define_one_arm_cp_reg(cpu, &ifar);
 501     }
 502 }
 503
 504 static void arm1136_r2_initfn(Object *obj)
 505 {
 506     ARMCPU *cpu = ARM_CPU(obj);
 507     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 508      * older core than plain "arm1136". In particular this does not
 509      * have the v6K features.
 510      * These ID register values are correct for 1136 but may be wrong
 511      * for 1136_r2 (in particular r0p2 does not actually implement most
 512      * of the ID registers).
 513      */
 514
 515     cpu->dtb_compatible = "arm,arm1136";
 516     set_feature(&cpu->env, ARM_FEATURE_V6);
 517     set_feature(&cpu->env, ARM_FEATURE_VFP);
 518     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 519     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 520     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 521     cpu->midr = 0x4107b362;
 522     cpu->reset_fpsid = 0x410120b4;
 523     cpu->mvfr0 = 0x11111111;
 524     cpu->mvfr1 = 0x00000000;
 525     cpu->ctr = 0x1dd20d2;
 526     cpu->reset_sctlr = 0x00050078;
 527     cpu->id_pfr0 = 0x111;
 528     cpu->id_pfr1 = 0x1;
 529     cpu->id_dfr0 = 0x2;
 530     cpu->id_afr0 = 0x3;
 531     cpu->id_mmfr0 = 0x01130003;
 532     cpu->id_mmfr1 = 0x10030302;
 533     cpu->id_mmfr2 = 0x01222110;
 534     cpu->id_isar0 = 0x00140011;
 535     cpu->id_isar1 = 0x12002111;
 536     cpu->id_isar2 = 0x11231111;
 537     cpu->id_isar3 = 0x01102131;
 538     cpu->id_isar4 = 0x141;
 539     cpu->reset_auxcr = 7;
 540 }
 541
 542 static void arm1136_initfn(Object *obj)
 543 {
 544     ARMCPU *cpu = ARM_CPU(obj);
 545
 546     cpu->dtb_compatible = "arm,arm1136";
 547     set_feature(&cpu->env, ARM_FEATURE_V6K);
 548     set_feature(&cpu->env, ARM_FEATURE_V6);
 549     set_feature(&cpu->env, ARM_FEATURE_VFP);
 550     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 551     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 552     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 553     cpu->midr = 0x4117b363;
 554     cpu->reset_fpsid = 0x410120b4;
 555     cpu->mvfr0 = 0x11111111;
 556     cpu->mvfr1 = 0x00000000;
 557     cpu->ctr = 0x1dd20d2;
 558     cpu->reset_sctlr = 0x00050078;
 559     cpu->id_pfr0 = 0x111;
 560     cpu->id_pfr1 = 0x1;
 561     cpu->id_dfr0 = 0x2;
 562     cpu->id_afr0 = 0x3;
 563     cpu->id_mmfr0 = 0x01130003;
 564     cpu->id_mmfr1 = 0x10030302;
 565     cpu->id_mmfr2 = 0x01222110;
 566     cpu->id_isar0 = 0x00140011;
 567     cpu->id_isar1 = 0x12002111;
 568     cpu->id_isar2 = 0x11231111;
 569     cpu->id_isar3 = 0x01102131;
 570     cpu->id_isar4 = 0x141;
 571     cpu->reset_auxcr = 7;
 572 }
 573
 574 static void arm1176_initfn(Object *obj)
 575 {
 576     ARMCPU *cpu = ARM_CPU(obj);
 577
 578     cpu->dtb_compatible = "arm,arm1176";
 579     set_feature(&cpu->env, ARM_FEATURE_V6K);
 580     set_feature(&cpu->env, ARM_FEATURE_VFP);
 581     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 582     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 583     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 584     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 585     cpu->midr = 0x410fb767;
 586     cpu->reset_fpsid = 0x410120b5;
 587     cpu->mvfr0 = 0x11111111;
 588     cpu->mvfr1 = 0x00000000;
 589     cpu->ctr = 0x1dd20d2;
 590     cpu->reset_sctlr = 0x00050078;
 591     cpu->id_pfr0 = 0x111;
 592     cpu->id_pfr1 = 0x11;
 593     cpu->id_dfr0 = 0x33;
 594     cpu->id_afr0 = 0;
 595     cpu->id_mmfr0 = 0x01130003;
 596     cpu->id_mmfr1 = 0x10030302;
 597     cpu->id_mmfr2 = 0x01222100;
 598     cpu->id_isar0 = 0x0140011;
 599     cpu->id_isar1 = 0x12002111;
 600     cpu->id_isar2 = 0x11231121;
 601     cpu->id_isar3 = 0x01102131;
 602     cpu->id_isar4 = 0x01141;
 603     cpu->reset_auxcr = 7;
 604 }
 605
 606 static void arm11mpcore_initfn(Object *obj)
 607 {
 608     ARMCPU *cpu = ARM_CPU(obj);
 609
 610     cpu->dtb_compatible = "arm,arm11mpcore";
 611     set_feature(&cpu->env, ARM_FEATURE_V6K);
 612     set_feature(&cpu->env, ARM_FEATURE_VFP);
 613     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 614     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 615     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 616     cpu->midr = 0x410fb022;
 617     cpu->reset_fpsid = 0x410120b4;
 618     cpu->mvfr0 = 0x11111111;
 619     cpu->mvfr1 = 0x00000000;
 620     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 621     cpu->id_pfr0 = 0x111;
 622     cpu->id_pfr1 = 0x1;
 623     cpu->id_dfr0 = 0;
 624     cpu->id_afr0 = 0x2;
 625     cpu->id_mmfr0 = 0x01100103;
 626     cpu->id_mmfr1 = 0x10020302;
 627     cpu->id_mmfr2 = 0x01222000;
 628     cpu->id_isar0 = 0x00100011;
 629     cpu->id_isar1 = 0x12002111;
 630     cpu->id_isar2 = 0x11221011;
 631     cpu->id_isar3 = 0x01102131;
 632     cpu->id_isar4 = 0x141;
 633     cpu->reset_auxcr = 1;
 634 }
 635
 636 static void cortex_m3_initfn(Object *obj)
 637 {
 638     ARMCPU *cpu = ARM_CPU(obj);
 639     set_feature(&cpu->env, ARM_FEATURE_V7);
 640     set_feature(&cpu->env, ARM_FEATURE_M);
 641     cpu->midr = 0x410fc231;
 642 }
 643
 644 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 645 {
 646 #ifndef CONFIG_USER_ONLY
 647     CPUClass *cc = CPU_CLASS(oc);
 648
 649     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 650 #endif
 651 }
 652
 653 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 654     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 655       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 656     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 657       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 658     REGINFO_SENTINEL
 659 };
 660
 661 static void cortex_a8_initfn(Object *obj)
 662 {
 663     ARMCPU *cpu = ARM_CPU(obj);
 664
 665     cpu->dtb_compatible = "arm,cortex-a8";
 666     set_feature(&cpu->env, ARM_FEATURE_V7);
 667     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 668     set_feature(&cpu->env, ARM_FEATURE_NEON);
 669     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 670     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 671     cpu->midr = 0x410fc080;
 672     cpu->reset_fpsid = 0x410330c0;
 673     cpu->mvfr0 = 0x11110222;
 674     cpu->mvfr1 = 0x00011100;
 675     cpu->ctr = 0x82048004;
 676     cpu->reset_sctlr = 0x00c50078;
 677     cpu->id_pfr0 = 0x1031;
 678     cpu->id_pfr1 = 0x11;
 679     cpu->id_dfr0 = 0x400;
 680     cpu->id_afr0 = 0;
 681     cpu->id_mmfr0 = 0x31100003;
 682     cpu->id_mmfr1 = 0x20000000;
 683     cpu->id_mmfr2 = 0x01202000;
 684     cpu->id_mmfr3 = 0x11;
 685     cpu->id_isar0 = 0x00101111;
 686     cpu->id_isar1 = 0x12112111;
 687     cpu->id_isar2 = 0x21232031;
 688     cpu->id_isar3 = 0x11112131;
 689     cpu->id_isar4 = 0x00111142;
 690     cpu->dbgdidr = 0x15141000;
 691     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 692     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 693     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 694     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 695     cpu->reset_auxcr = 2;
 696     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 697 }
 698
 699 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 700     /* power_control should be set to maximum latency. Again,
 701      * default to 0 and set by private hook
 702      */
 703     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 704       .access = PL1_RW, .resetvalue = 0,
 705       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 706     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 707       .access = PL1_RW, .resetvalue = 0,
 708       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 709     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 710       .access = PL1_RW, .resetvalue = 0,
 711       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 712     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 713       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 714     /* TLB lockdown control */
 715     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 716       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 717     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 718       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 719     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 720       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 721     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 722       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 723     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 724       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 725     REGINFO_SENTINEL
 726 };
 727
 728 static void cortex_a9_initfn(Object *obj)
 729 {
 730     ARMCPU *cpu = ARM_CPU(obj);
 731
 732     cpu->dtb_compatible = "arm,cortex-a9";
 733     set_feature(&cpu->env, ARM_FEATURE_V7);
 734     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 735     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 736     set_feature(&cpu->env, ARM_FEATURE_NEON);
 737     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 738     /* Note that A9 supports the MP extensions even for
 739      * A9UP and single-core A9MP (which are both different
 740      * and valid configurations; we don't model A9UP).
 741      */
 742     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 743     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 744     cpu->midr = 0x410fc090;
 745     cpu->reset_fpsid = 0x41033090;
 746     cpu->mvfr0 = 0x11110222;
 747     cpu->mvfr1 = 0x01111111;
 748     cpu->ctr = 0x80038003;
 749     cpu->reset_sctlr = 0x00c50078;
 750     cpu->id_pfr0 = 0x1031;
 751     cpu->id_pfr1 = 0x11;
 752     cpu->id_dfr0 = 0x000;
 753     cpu->id_afr0 = 0;
 754     cpu->id_mmfr0 = 0x00100103;
 755     cpu->id_mmfr1 = 0x20000000;
 756     cpu->id_mmfr2 = 0x01230000;
 757     cpu->id_mmfr3 = 0x00002111;
 758     cpu->id_isar0 = 0x00101111;
 759     cpu->id_isar1 = 0x13112111;
 760     cpu->id_isar2 = 0x21232041;
 761     cpu->id_isar3 = 0x11112131;
 762     cpu->id_isar4 = 0x00111142;
 763     cpu->dbgdidr = 0x35141000;
 764     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 765     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
 766     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
 767     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 768 }
 769
 770 #ifndef CONFIG_USER_ONLY
 771 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 772 {
 773     /* Linux wants the number of processors from here.
 774      * Might as well set the interrupt-controller bit too.
 775      */
 776     return ((smp_cpus - 1) << 24) | (1 << 23);
 777 }
 778 #endif
 779
 780 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 781 #ifndef CONFIG_USER_ONLY
 782     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 783       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 784       .writefn = arm_cp_write_ignore, },
 785 #endif
 786     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 787       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 788     REGINFO_SENTINEL
 789 };
 790
 791 static void cortex_a15_initfn(Object *obj)
 792 {
 793     ARMCPU *cpu = ARM_CPU(obj);
 794
 795     cpu->dtb_compatible = "arm,cortex-a15";
 796     set_feature(&cpu->env, ARM_FEATURE_V7);
 797     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 798     set_feature(&cpu->env, ARM_FEATURE_NEON);
 799     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 800     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 801     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 802     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 803     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 804     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 805     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 806     cpu->midr = 0x412fc0f1;
 807     cpu->reset_fpsid = 0x410430f0;
 808     cpu->mvfr0 = 0x10110222;
 809     cpu->mvfr1 = 0x11111111;
 810     cpu->ctr = 0x8444c004;
 811     cpu->reset_sctlr = 0x00c50078;
 812     cpu->id_pfr0 = 0x00001131;
 813     cpu->id_pfr1 = 0x00011011;
 814     cpu->id_dfr0 = 0x02010555;
 815     cpu->id_afr0 = 0x00000000;
 816     cpu->id_mmfr0 = 0x10201105;
 817     cpu->id_mmfr1 = 0x20000000;
 818     cpu->id_mmfr2 = 0x01240000;
 819     cpu->id_mmfr3 = 0x02102211;
 820     cpu->id_isar0 = 0x02101110;
 821     cpu->id_isar1 = 0x13112111;
 822     cpu->id_isar2 = 0x21232041;
 823     cpu->id_isar3 = 0x11112131;
 824     cpu->id_isar4 = 0x10011142;
 825     cpu->dbgdidr = 0x3515f021;
 826     cpu->clidr = 0x0a200023;
 827     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 828     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 829     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 830     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 831 }
 832
 833 static void ti925t_initfn(Object *obj)
 834 {
 835     ARMCPU *cpu = ARM_CPU(obj);
 836     set_feature(&cpu->env, ARM_FEATURE_V4T);
 837     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 838     cpu->midr = ARM_CPUID_TI925T;
 839     cpu->ctr = 0x5109149;
 840     cpu->reset_sctlr = 0x00000070;
 841 }
 842
 843 static void sa1100_initfn(Object *obj)
 844 {
 845     ARMCPU *cpu = ARM_CPU(obj);
 846
 847     cpu->dtb_compatible = "intel,sa1100";
 848     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 849     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 850     cpu->midr = 0x4401A11B;
 851     cpu->reset_sctlr = 0x00000070;
 852 }
 853
 854 static void sa1110_initfn(Object *obj)
 855 {
 856     ARMCPU *cpu = ARM_CPU(obj);
 857     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 858     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 859     cpu->midr = 0x6901B119;
 860     cpu->reset_sctlr = 0x00000070;
 861 }
 862
 863 static void pxa250_initfn(Object *obj)
 864 {
 865     ARMCPU *cpu = ARM_CPU(obj);
 866
 867     cpu->dtb_compatible = "marvell,xscale";
 868     set_feature(&cpu->env, ARM_FEATURE_V5);
 869     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 870     cpu->midr = 0x69052100;
 871     cpu->ctr = 0xd172172;
 872     cpu->reset_sctlr = 0x00000078;
 873 }
 874
 875 static void pxa255_initfn(Object *obj)
 876 {
 877     ARMCPU *cpu = ARM_CPU(obj);
 878
 879     cpu->dtb_compatible = "marvell,xscale";
 880     set_feature(&cpu->env, ARM_FEATURE_V5);
 881     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 882     cpu->midr = 0x69052d00;
 883     cpu->ctr = 0xd172172;
 884     cpu->reset_sctlr = 0x00000078;
 885 }
 886
 887 static void pxa260_initfn(Object *obj)
 888 {
 889     ARMCPU *cpu = ARM_CPU(obj);
 890
 891     cpu->dtb_compatible = "marvell,xscale";
 892     set_feature(&cpu->env, ARM_FEATURE_V5);
 893     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 894     cpu->midr = 0x69052903;
 895     cpu->ctr = 0xd172172;
 896     cpu->reset_sctlr = 0x00000078;
 897 }
 898
 899 static void pxa261_initfn(Object *obj)
 900 {
 901     ARMCPU *cpu = ARM_CPU(obj);
 902
 903     cpu->dtb_compatible = "marvell,xscale";
 904     set_feature(&cpu->env, ARM_FEATURE_V5);
 905     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 906     cpu->midr = 0x69052d05;
 907     cpu->ctr = 0xd172172;
 908     cpu->reset_sctlr = 0x00000078;
 909 }
 910
 911 static void pxa262_initfn(Object *obj)
 912 {
 913     ARMCPU *cpu = ARM_CPU(obj);
 914
 915     cpu->dtb_compatible = "marvell,xscale";
 916     set_feature(&cpu->env, ARM_FEATURE_V5);
 917     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 918     cpu->midr = 0x69052d06;
 919     cpu->ctr = 0xd172172;
 920     cpu->reset_sctlr = 0x00000078;
 921 }
 922
 923 static void pxa270a0_initfn(Object *obj)
 924 {
 925     ARMCPU *cpu = ARM_CPU(obj);
 926
 927     cpu->dtb_compatible = "marvell,xscale";
 928     set_feature(&cpu->env, ARM_FEATURE_V5);
 929     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 930     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 931     cpu->midr = 0x69054110;
 932     cpu->ctr = 0xd172172;
 933     cpu->reset_sctlr = 0x00000078;
 934 }
 935
 936 static void pxa270a1_initfn(Object *obj)
 937 {
 938     ARMCPU *cpu = ARM_CPU(obj);
 939
 940     cpu->dtb_compatible = "marvell,xscale";
 941     set_feature(&cpu->env, ARM_FEATURE_V5);
 942     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 943     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 944     cpu->midr = 0x69054111;
 945     cpu->ctr = 0xd172172;
 946     cpu->reset_sctlr = 0x00000078;
 947 }
 948
 949 static void pxa270b0_initfn(Object *obj)
 950 {
 951     ARMCPU *cpu = ARM_CPU(obj);
 952
 953     cpu->dtb_compatible = "marvell,xscale";
 954     set_feature(&cpu->env, ARM_FEATURE_V5);
 955     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 956     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 957     cpu->midr = 0x69054112;
 958     cpu->ctr = 0xd172172;
 959     cpu->reset_sctlr = 0x00000078;
 960 }
 961
 962 static void pxa270b1_initfn(Object *obj)
 963 {
 964     ARMCPU *cpu = ARM_CPU(obj);
 965
 966     cpu->dtb_compatible = "marvell,xscale";
 967     set_feature(&cpu->env, ARM_FEATURE_V5);
 968     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 969     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 970     cpu->midr = 0x69054113;
 971     cpu->ctr = 0xd172172;
 972     cpu->reset_sctlr = 0x00000078;
 973 }
 974
 975 static void pxa270c0_initfn(Object *obj)
 976 {
 977     ARMCPU *cpu = ARM_CPU(obj);
 978
 979     cpu->dtb_compatible = "marvell,xscale";
 980     set_feature(&cpu->env, ARM_FEATURE_V5);
 981     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 982     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 983     cpu->midr = 0x69054114;
 984     cpu->ctr = 0xd172172;
 985     cpu->reset_sctlr = 0x00000078;
 986 }
 987
 988 static void pxa270c5_initfn(Object *obj)
 989 {
 990     ARMCPU *cpu = ARM_CPU(obj);
 991
 992     cpu->dtb_compatible = "marvell,xscale";
 993     set_feature(&cpu->env, ARM_FEATURE_V5);
 994     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 995     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 996     cpu->midr = 0x69054117;
 997     cpu->ctr = 0xd172172;
 998     cpu->reset_sctlr = 0x00000078;
 999 }
1000
1001 #ifdef CONFIG_USER_ONLY
1002 static void arm_any_initfn(Object *obj)
1003 {
1004     ARMCPU *cpu = ARM_CPU(obj);
1005     set_feature(&cpu->env, ARM_FEATURE_V8);
1006     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1007     set_feature(&cpu->env, ARM_FEATURE_NEON);
1008     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1009     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1010     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1011     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1012     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1013     set_feature(&cpu->env, ARM_FEATURE_CRC);
1014     cpu->midr = 0xffffffff;
1015 }
1016 #endif
1017
1018 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1019
1020 typedef struct ARMCPUInfo {
1021     const char *name;
1022     void (*initfn)(Object *obj);
1023     void (*class_init)(ObjectClass *oc, void *data);
1024 } ARMCPUInfo;
1025
1026 static const ARMCPUInfo arm_cpus[] = {
1027 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1028     { .name = "arm926",      .initfn = arm926_initfn },
1029     { .name = "arm946",      .initfn = arm946_initfn },
1030     { .name = "arm1026",     .initfn = arm1026_initfn },
1031     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1032      * older core than plain "arm1136". In particular this does not
1033      * have the v6K features.
1034      */
1035     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1036     { .name = "arm1136",     .initfn = arm1136_initfn },
1037     { .name = "arm1176",     .initfn = arm1176_initfn },
1038     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1039     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1040                              .class_init = arm_v7m_class_init },
1041     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1042     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1043     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1044     { .name = "ti925t",      .initfn = ti925t_initfn },
1045     { .name = "sa1100",      .initfn = sa1100_initfn },
1046     { .name = "sa1110",      .initfn = sa1110_initfn },
1047     { .name = "pxa250",      .initfn = pxa250_initfn },
1048     { .name = "pxa255",      .initfn = pxa255_initfn },
1049     { .name = "pxa260",      .initfn = pxa260_initfn },
1050     { .name = "pxa261",      .initfn = pxa261_initfn },
1051     { .name = "pxa262",      .initfn = pxa262_initfn },
1052     /* "pxa270" is an alias for "pxa270-a0" */
1053     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1054     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1055     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1056     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1057     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1058     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1059     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1060 #ifdef CONFIG_USER_ONLY
1061     { .name = "any",         .initfn = arm_any_initfn },
1062 #endif
1063 #endif
1064     { .name = NULL }
1065 };
1066
1067 static Property arm_cpu_properties[] = {
1068     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1069     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1070     DEFINE_PROP_END_OF_LIST()
1071 };
1072
1073 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1074 {
1075     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1076     CPUClass *cc = CPU_CLASS(acc);
1077     DeviceClass *dc = DEVICE_CLASS(oc);
1078
1079     acc->parent_realize = dc->realize;
1080     dc->realize = arm_cpu_realizefn;
1081     dc->props = arm_cpu_properties;
1082
1083     acc->parent_reset = cc->reset;
1084     cc->reset = arm_cpu_reset;
1085
1086     cc->class_by_name = arm_cpu_class_by_name;
1087     cc->has_work = arm_cpu_has_work;
1088     cc->do_interrupt = arm_cpu_do_interrupt;
1089     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1090     cc->dump_state = arm_cpu_dump_state;
1091     cc->set_pc = arm_cpu_set_pc;
1092     cc->gdb_read_register = arm_cpu_gdb_read_register;
1093     cc->gdb_write_register = arm_cpu_gdb_write_register;
1094 #ifdef CONFIG_USER_ONLY
1095     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1096 #else
1097     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1098     cc->vmsd = &vmstate_arm_cpu;
1099 #endif
1100     cc->gdb_num_core_regs = 26;
1101     cc->gdb_core_xml_file = "arm-core.xml";
1102     cc->debug_excp_handler = arm_debug_excp_handler;
1103 }
1104
1105 static void cpu_register(const ARMCPUInfo *info)
1106 {
1107     TypeInfo type_info = {
1108         .parent = TYPE_ARM_CPU,
1109         .instance_size = sizeof(ARMCPU),
1110         .instance_init = info->initfn,
1111         .class_size = sizeof(ARMCPUClass),
1112         .class_init = info->class_init,
1113     };
1114
1115     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1116     type_register(&type_info);
1117     g_free((void *)type_info.name);
1118 }
1119
1120 static const TypeInfo arm_cpu_type_info = {
1121     .name = TYPE_ARM_CPU,
1122     .parent = TYPE_CPU,
1123     .instance_size = sizeof(ARMCPU),
1124     .instance_init = arm_cpu_initfn,
1125     .instance_post_init = arm_cpu_post_init,
1126     .instance_finalize = arm_cpu_finalizefn,
1127     .abstract = true,
1128     .class_size = sizeof(ARMCPUClass),
1129     .class_init = arm_cpu_class_init,
1130 };
1131
1132 static void arm_cpu_register_types(void)
1133 {
1134     const ARMCPUInfo *info = arm_cpus;
1135
1136     type_register_static(&arm_cpu_type_info);
1137
1138     while (info->name) {
1139         cpu_register(info);
1140         info++;
1141     }
1142 }
1143
1144 type_init(arm_cpu_register_types)