2 * QEMU Sun4u/Sun4v System Emulator
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "qemu-timer.h"
34 #include "firmware_abi.h"
45 #define CPUIRQ_DPRINTF(fmt, ...) \
46 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
48 #define CPUIRQ_DPRINTF(fmt, ...)
52 #define EBUS_DPRINTF(fmt, ...) \
53 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
55 #define EBUS_DPRINTF(fmt, ...)
58 #define KERNEL_LOAD_ADDR 0x00404000
59 #define CMDLINE_ADDR 0x003ff000
60 #define INITRD_LOAD_ADDR 0x00300000
61 #define PROM_SIZE_MAX (4 * 1024 * 1024)
62 #define PROM_VADDR 0x000ffd00000ULL
63 #define APB_SPECIAL_BASE 0x1fe00000000ULL
64 #define APB_MEM_BASE 0x1ff00000000ULL
65 #define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
66 #define PROM_FILENAME "openbios-sparc64"
67 #define NVRAM_SIZE 0x2000
69 #define BIOS_CFG_IOPORT 0x510
70 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
71 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
72 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
76 #define TICK_MAX 0x7fffffffffffffffULL
79 const char * const default_cpu_model
;
82 uint64_t console_serial_base
;
85 int DMA_get_channel_mode (int nchan
)
89 int DMA_read_memory (int nchan
, void *buf
, int pos
, int size
)
93 int DMA_write_memory (int nchan
, void *buf
, int pos
, int size
)
97 void DMA_hold_DREQ (int nchan
) {}
98 void DMA_release_DREQ (int nchan
) {}
99 void DMA_schedule(int nchan
) {}
100 void DMA_init (int high_page_enable
) {}
101 void DMA_register_channel (int nchan
,
102 DMA_transfer_handler transfer_handler
,
107 static int fw_cfg_boot_set(void *opaque
, const char *boot_device
)
109 fw_cfg_add_i16(opaque
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
113 static int sun4u_NVRAM_set_params (m48t59_t
*nvram
, uint16_t NVRAM_size
,
116 const char *boot_devices
,
117 uint32_t kernel_image
, uint32_t kernel_size
,
119 uint32_t initrd_image
, uint32_t initrd_size
,
120 uint32_t NVRAM_image
,
121 int width
, int height
, int depth
,
122 const uint8_t *macaddr
)
126 uint8_t image
[0x1ff0];
127 struct OpenBIOS_nvpart_v1
*part_header
;
129 memset(image
, '\0', sizeof(image
));
133 // OpenBIOS nvram variables
134 // Variable partition
135 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
136 part_header
->signature
= OPENBIOS_PART_SYSTEM
;
137 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "system");
139 end
= start
+ sizeof(struct OpenBIOS_nvpart_v1
);
140 for (i
= 0; i
< nb_prom_envs
; i
++)
141 end
= OpenBIOS_set_var(image
, end
, prom_envs
[i
]);
146 end
= start
+ ((end
- start
+ 15) & ~15);
147 OpenBIOS_finish_partition(part_header
, end
- start
);
151 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
152 part_header
->signature
= OPENBIOS_PART_FREE
;
153 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "free");
156 OpenBIOS_finish_partition(part_header
, end
- start
);
158 Sun_init_header((struct Sun_nvram
*)&image
[0x1fd8], macaddr
, 0x80);
160 for (i
= 0; i
< sizeof(image
); i
++)
161 m48t59_write(nvram
, i
, image
[i
]);
165 static unsigned long sun4u_load_kernel(const char *kernel_filename
,
166 const char *initrd_filename
,
167 ram_addr_t RAM_size
, long *initrd_size
)
173 linux_boot
= (kernel_filename
!= NULL
);
184 kernel_size
= load_elf(kernel_filename
, 0, NULL
, NULL
, NULL
,
187 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
188 RAM_size
- KERNEL_LOAD_ADDR
, bswap_needed
,
191 kernel_size
= load_image_targphys(kernel_filename
,
193 RAM_size
- KERNEL_LOAD_ADDR
);
194 if (kernel_size
< 0) {
195 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
202 if (initrd_filename
) {
203 *initrd_size
= load_image_targphys(initrd_filename
,
205 RAM_size
- INITRD_LOAD_ADDR
);
206 if (*initrd_size
< 0) {
207 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
212 if (*initrd_size
> 0) {
213 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
214 if (ldl_phys(KERNEL_LOAD_ADDR
+ i
) == 0x48647253) { // HdrS
215 stl_phys(KERNEL_LOAD_ADDR
+ i
+ 16, INITRD_LOAD_ADDR
);
216 stl_phys(KERNEL_LOAD_ADDR
+ i
+ 20, *initrd_size
);
225 void pic_info(Monitor
*mon
)
229 void irq_info(Monitor
*mon
)
233 void cpu_check_irqs(CPUState
*env
)
235 uint32_t pil
= env
->pil_in
|
236 (env
->softint
& ~(SOFTINT_TIMER
| SOFTINT_STIMER
));
238 /* check if TM or SM in SOFTINT are set
239 setting these also causes interrupt 14 */
240 if (env
->softint
& (SOFTINT_TIMER
| SOFTINT_STIMER
)) {
245 if (env
->interrupt_request
& CPU_INTERRUPT_HARD
) {
246 CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
247 env
->interrupt_index
);
248 env
->interrupt_index
= 0;
249 cpu_reset_interrupt(env
, CPU_INTERRUPT_HARD
);
254 if (cpu_interrupts_enabled(env
)) {
258 for (i
= 15; i
> env
->psrpil
; i
--) {
259 if (pil
& (1 << i
)) {
260 int old_interrupt
= env
->interrupt_index
;
261 int new_interrupt
= TT_EXTINT
| i
;
263 if (env
->tl
> 0 && cpu_tsptr(env
)->tt
> new_interrupt
) {
264 CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
265 "current %x >= pending %x\n",
266 env
->tl
, cpu_tsptr(env
)->tt
, new_interrupt
);
267 } else if (old_interrupt
!= new_interrupt
) {
268 env
->interrupt_index
= new_interrupt
;
269 CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i
,
270 old_interrupt
, new_interrupt
);
271 cpu_interrupt(env
, CPU_INTERRUPT_HARD
);
277 CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
278 "current interrupt %x\n",
279 pil
, env
->pil_in
, env
->softint
, env
->interrupt_index
);
283 static void cpu_set_irq(void *opaque
, int irq
, int level
)
285 CPUState
*env
= opaque
;
288 CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq
);
290 env
->pil_in
|= 1 << irq
;
293 CPUIRQ_DPRINTF("Lower CPU IRQ %d\n", irq
);
294 env
->pil_in
&= ~(1 << irq
);
299 typedef struct ResetData
{
304 static void main_cpu_reset(void *opaque
)
306 ResetData
*s
= (ResetData
*)opaque
;
307 CPUState
*env
= s
->env
;
308 static unsigned int nr_resets
;
311 env
->tick_cmpr
= TICK_INT_DIS
| 0;
312 ptimer_set_limit(env
->tick
, TICK_MAX
, 1);
313 ptimer_run(env
->tick
, 1);
314 env
->stick_cmpr
= TICK_INT_DIS
| 0;
315 ptimer_set_limit(env
->stick
, TICK_MAX
, 1);
316 ptimer_run(env
->stick
, 1);
317 env
->hstick_cmpr
= TICK_INT_DIS
| 0;
318 ptimer_set_limit(env
->hstick
, TICK_MAX
, 1);
319 ptimer_run(env
->hstick
, 1);
320 env
->gregs
[1] = 0; // Memory start
321 env
->gregs
[2] = ram_size
; // Memory size
322 env
->gregs
[3] = 0; // Machine description XXX
323 if (nr_resets
++ == 0) {
325 env
->pc
= s
->prom_addr
+ 0x20ULL
;
327 env
->pc
= s
->prom_addr
+ 0x40ULL
;
329 env
->npc
= env
->pc
+ 4;
332 static void tick_irq(void *opaque
)
334 CPUState
*env
= opaque
;
336 if (!(env
->tick_cmpr
& TICK_INT_DIS
)) {
337 env
->softint
|= SOFTINT_TIMER
;
338 cpu_interrupt(env
, CPU_INTERRUPT_TIMER
);
342 static void stick_irq(void *opaque
)
344 CPUState
*env
= opaque
;
346 if (!(env
->stick_cmpr
& TICK_INT_DIS
)) {
347 env
->softint
|= SOFTINT_STIMER
;
348 cpu_interrupt(env
, CPU_INTERRUPT_TIMER
);
352 static void hstick_irq(void *opaque
)
354 CPUState
*env
= opaque
;
356 if (!(env
->hstick_cmpr
& TICK_INT_DIS
)) {
357 cpu_interrupt(env
, CPU_INTERRUPT_TIMER
);
361 void cpu_tick_set_count(void *opaque
, uint64_t count
)
363 ptimer_set_count(opaque
, -count
);
366 uint64_t cpu_tick_get_count(void *opaque
)
368 return -ptimer_get_count(opaque
);
371 void cpu_tick_set_limit(void *opaque
, uint64_t limit
)
373 ptimer_set_limit(opaque
, -limit
, 0);
376 static void ebus_mmio_mapfunc(PCIDevice
*pci_dev
, int region_num
,
377 pcibus_t addr
, pcibus_t size
, int type
)
379 EBUS_DPRINTF("Mapping region %d registers at %" FMT_PCIBUS
"\n",
381 switch (region_num
) {
383 isa_mmio_init(addr
, 0x1000000);
386 isa_mmio_init(addr
, 0x800000);
391 static void dummy_isa_irq_handler(void *opaque
, int n
, int level
)
395 /* EBUS (Eight bit bus) bridge */
397 pci_ebus_init(PCIBus
*bus
, int devfn
)
401 pci_create_simple(bus
, devfn
, "ebus");
402 isa_irq
= qemu_allocate_irqs(dummy_isa_irq_handler
, NULL
, 16);
403 isa_bus_irqs(isa_irq
);
407 pci_ebus_init1(PCIDevice
*s
)
409 isa_bus_new(&s
->qdev
);
411 pci_config_set_vendor_id(s
->config
, PCI_VENDOR_ID_SUN
);
412 pci_config_set_device_id(s
->config
, PCI_DEVICE_ID_SUN_EBUS
);
413 s
->config
[0x04] = 0x06; // command = bus master, pci mem
414 s
->config
[0x05] = 0x00;
415 s
->config
[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
416 s
->config
[0x07] = 0x03; // status = medium devsel
417 s
->config
[0x08] = 0x01; // revision
418 s
->config
[0x09] = 0x00; // programming i/f
419 pci_config_set_class(s
->config
, PCI_CLASS_BRIDGE_OTHER
);
420 s
->config
[0x0D] = 0x0a; // latency_timer
421 s
->config
[PCI_HEADER_TYPE
] = PCI_HEADER_TYPE_NORMAL
; // header_type
423 pci_register_bar(s
, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY
,
425 pci_register_bar(s
, 1, 0x800000, PCI_BASE_ADDRESS_SPACE_MEMORY
,
430 static PCIDeviceInfo ebus_info
= {
432 .qdev
.size
= sizeof(PCIDevice
),
433 .init
= pci_ebus_init1
,
436 static void pci_ebus_register(void)
438 pci_qdev_register(&ebus_info
);
441 device_init(pci_ebus_register
);
443 /* Boot PROM (OpenBIOS) */
444 static void prom_init(target_phys_addr_t addr
, const char *bios_name
)
451 dev
= qdev_create(NULL
, "openprom");
452 qdev_init_nofail(dev
);
453 s
= sysbus_from_qdev(dev
);
455 sysbus_mmio_map(s
, 0, addr
);
458 if (bios_name
== NULL
) {
459 bios_name
= PROM_FILENAME
;
461 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
463 ret
= load_elf(filename
, addr
- PROM_VADDR
, NULL
, NULL
, NULL
,
465 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
466 ret
= load_image_targphys(filename
, addr
, PROM_SIZE_MAX
);
472 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
473 fprintf(stderr
, "qemu: could not load prom '%s'\n", bios_name
);
478 static int prom_init1(SysBusDevice
*dev
)
480 ram_addr_t prom_offset
;
482 prom_offset
= qemu_ram_alloc(PROM_SIZE_MAX
);
483 sysbus_init_mmio(dev
, PROM_SIZE_MAX
, prom_offset
| IO_MEM_ROM
);
487 static SysBusDeviceInfo prom_info
= {
489 .qdev
.name
= "openprom",
490 .qdev
.size
= sizeof(SysBusDevice
),
491 .qdev
.props
= (Property
[]) {
492 {/* end of property list */}
496 static void prom_register_devices(void)
498 sysbus_register_withprop(&prom_info
);
501 device_init(prom_register_devices
);
504 typedef struct RamDevice
511 static int ram_init1(SysBusDevice
*dev
)
513 ram_addr_t RAM_size
, ram_offset
;
514 RamDevice
*d
= FROM_SYSBUS(RamDevice
, dev
);
518 ram_offset
= qemu_ram_alloc(RAM_size
);
519 sysbus_init_mmio(dev
, RAM_size
, ram_offset
);
523 static void ram_init(target_phys_addr_t addr
, ram_addr_t RAM_size
)
530 dev
= qdev_create(NULL
, "memory");
531 s
= sysbus_from_qdev(dev
);
533 d
= FROM_SYSBUS(RamDevice
, s
);
535 qdev_init_nofail(dev
);
537 sysbus_mmio_map(s
, 0, addr
);
540 static SysBusDeviceInfo ram_info
= {
542 .qdev
.name
= "memory",
543 .qdev
.size
= sizeof(RamDevice
),
544 .qdev
.props
= (Property
[]) {
545 DEFINE_PROP_UINT64("size", RamDevice
, size
, 0),
546 DEFINE_PROP_END_OF_LIST(),
550 static void ram_register_devices(void)
552 sysbus_register_withprop(&ram_info
);
555 device_init(ram_register_devices
);
557 static CPUState
*cpu_devinit(const char *cpu_model
, const struct hwdef
*hwdef
)
561 ResetData
*reset_info
;
564 cpu_model
= hwdef
->default_cpu_model
;
565 env
= cpu_init(cpu_model
);
567 fprintf(stderr
, "Unable to find Sparc CPU definition\n");
570 bh
= qemu_bh_new(tick_irq
, env
);
571 env
->tick
= ptimer_init(bh
);
572 ptimer_set_period(env
->tick
, 1ULL);
574 bh
= qemu_bh_new(stick_irq
, env
);
575 env
->stick
= ptimer_init(bh
);
576 ptimer_set_period(env
->stick
, 1ULL);
578 bh
= qemu_bh_new(hstick_irq
, env
);
579 env
->hstick
= ptimer_init(bh
);
580 ptimer_set_period(env
->hstick
, 1ULL);
582 reset_info
= qemu_mallocz(sizeof(ResetData
));
583 reset_info
->env
= env
;
584 reset_info
->prom_addr
= hwdef
->prom_addr
;
585 qemu_register_reset(main_cpu_reset
, reset_info
);
590 static void sun4uv_init(ram_addr_t RAM_size
,
591 const char *boot_devices
,
592 const char *kernel_filename
, const char *kernel_cmdline
,
593 const char *initrd_filename
, const char *cpu_model
,
594 const struct hwdef
*hwdef
)
599 long initrd_size
, kernel_size
;
600 PCIBus
*pci_bus
, *pci_bus2
, *pci_bus3
;
602 DriveInfo
*hd
[MAX_IDE_BUS
* MAX_IDE_DEVS
];
603 DriveInfo
*fd
[MAX_FD
];
607 env
= cpu_devinit(cpu_model
, hwdef
);
610 ram_init(0, RAM_size
);
612 prom_init(hwdef
->prom_addr
, bios_name
);
615 irq
= qemu_allocate_irqs(cpu_set_irq
, env
, MAX_PILS
);
616 pci_bus
= pci_apb_init(APB_SPECIAL_BASE
, APB_MEM_BASE
, irq
, &pci_bus2
,
618 isa_mem_base
= VGA_BASE
;
619 pci_vga_init(pci_bus
, 0, 0);
621 // XXX Should be pci_bus3
622 pci_ebus_init(pci_bus
, -1);
625 if (hwdef
->console_serial_base
) {
626 serial_mm_init(hwdef
->console_serial_base
, 0, NULL
, 115200,
630 for(; i
< MAX_SERIAL_PORTS
; i
++) {
632 serial_isa_init(i
, serial_hds
[i
]);
636 for(i
= 0; i
< MAX_PARALLEL_PORTS
; i
++) {
637 if (parallel_hds
[i
]) {
638 parallel_init(i
, parallel_hds
[i
]);
642 for(i
= 0; i
< nb_nics
; i
++)
643 pci_nic_init_nofail(&nd_table
[i
], "ne2k_pci", NULL
);
645 if (drive_get_max_bus(IF_IDE
) >= MAX_IDE_BUS
) {
646 fprintf(stderr
, "qemu: too many IDE bus\n");
649 for(i
= 0; i
< MAX_IDE_BUS
* MAX_IDE_DEVS
; i
++) {
650 hd
[i
] = drive_get(IF_IDE
, i
/ MAX_IDE_DEVS
,
654 pci_cmd646_ide_init(pci_bus
, hd
, 1);
656 isa_create_simple("i8042");
657 for(i
= 0; i
< MAX_FD
; i
++) {
658 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
661 nvram
= m48t59_init_isa(0x0074, NVRAM_SIZE
, 59);
664 kernel_size
= sun4u_load_kernel(kernel_filename
, initrd_filename
,
665 ram_size
, &initrd_size
);
667 sun4u_NVRAM_set_params(nvram
, NVRAM_SIZE
, "Sun4u", RAM_size
, boot_devices
,
668 KERNEL_LOAD_ADDR
, kernel_size
,
670 INITRD_LOAD_ADDR
, initrd_size
,
671 /* XXX: need an option to load a NVRAM image */
673 graphic_width
, graphic_height
, graphic_depth
,
674 (uint8_t *)&nd_table
[0].macaddr
);
676 fw_cfg
= fw_cfg_init(BIOS_CFG_IOPORT
, BIOS_CFG_IOPORT
+ 1, 0, 0);
677 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
678 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
679 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
680 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
681 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
682 if (kernel_cmdline
) {
683 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
,
684 strlen(kernel_cmdline
) + 1);
685 fw_cfg_add_bytes(fw_cfg
, FW_CFG_CMDLINE_DATA
,
686 (uint8_t*)strdup(kernel_cmdline
),
687 strlen(kernel_cmdline
) + 1);
689 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, 0);
691 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
692 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
693 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_devices
[0]);
695 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_WIDTH
, graphic_width
);
696 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_HEIGHT
, graphic_height
);
697 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_DEPTH
, graphic_depth
);
699 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
708 static const struct hwdef hwdefs
[] = {
709 /* Sun4u generic PC-like machine */
711 .default_cpu_model
= "TI UltraSparc II",
712 .machine_id
= sun4u_id
,
713 .prom_addr
= 0x1fff0000000ULL
,
714 .console_serial_base
= 0,
716 /* Sun4v generic PC-like machine */
718 .default_cpu_model
= "Sun UltraSparc T1",
719 .machine_id
= sun4v_id
,
720 .prom_addr
= 0x1fff0000000ULL
,
721 .console_serial_base
= 0,
723 /* Sun4v generic Niagara machine */
725 .default_cpu_model
= "Sun UltraSparc T1",
726 .machine_id
= niagara_id
,
727 .prom_addr
= 0xfff0000000ULL
,
728 .console_serial_base
= 0xfff0c2c000ULL
,
732 /* Sun4u hardware initialisation */
733 static void sun4u_init(ram_addr_t RAM_size
,
734 const char *boot_devices
,
735 const char *kernel_filename
, const char *kernel_cmdline
,
736 const char *initrd_filename
, const char *cpu_model
)
738 sun4uv_init(RAM_size
, boot_devices
, kernel_filename
,
739 kernel_cmdline
, initrd_filename
, cpu_model
, &hwdefs
[0]);
742 /* Sun4v hardware initialisation */
743 static void sun4v_init(ram_addr_t RAM_size
,
744 const char *boot_devices
,
745 const char *kernel_filename
, const char *kernel_cmdline
,
746 const char *initrd_filename
, const char *cpu_model
)
748 sun4uv_init(RAM_size
, boot_devices
, kernel_filename
,
749 kernel_cmdline
, initrd_filename
, cpu_model
, &hwdefs
[1]);
752 /* Niagara hardware initialisation */
753 static void niagara_init(ram_addr_t RAM_size
,
754 const char *boot_devices
,
755 const char *kernel_filename
, const char *kernel_cmdline
,
756 const char *initrd_filename
, const char *cpu_model
)
758 sun4uv_init(RAM_size
, boot_devices
, kernel_filename
,
759 kernel_cmdline
, initrd_filename
, cpu_model
, &hwdefs
[2]);
762 static QEMUMachine sun4u_machine
= {
764 .desc
= "Sun4u platform",
766 .max_cpus
= 1, // XXX for now
770 static QEMUMachine sun4v_machine
= {
772 .desc
= "Sun4v platform",
774 .max_cpus
= 1, // XXX for now
777 static QEMUMachine niagara_machine
= {
779 .desc
= "Sun4v platform, Niagara",
780 .init
= niagara_init
,
781 .max_cpus
= 1, // XXX for now
784 static void sun4u_machine_init(void)
786 qemu_register_machine(&sun4u_machine
);
787 qemu_register_machine(&sun4v_machine
);
788 qemu_register_machine(&niagara_machine
);
791 machine_init(sun4u_machine_init
);