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spice: connection events.
[qemu.git] / hw / pci.c
blob0c15b13037ae81f78ed44363ac051441c5f95441
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
28 #include "msix.h"
29 #include "msi.h"
30 #include "monitor.h"
31 #include "net.h"
32 #include "sysemu.h"
33 #include "loader.h"
34 #include "qemu-objects.h"
35 #include "range.h"
36
37 //#define DEBUG_PCI
38 #ifdef DEBUG_PCI
39 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
40 #else
41 # define PCI_DPRINTF(format, ...) do { } while (0)
42 #endif
43
44 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
45 static char *pcibus_get_dev_path(DeviceState *dev);
46 static int pcibus_reset(BusState *qbus);
47
48 struct BusInfo pci_bus_info = {
49 .name = "PCI",
50 .size = sizeof(PCIBus),
51 .print_dev = pcibus_dev_print,
52 .get_dev_path = pcibus_get_dev_path,
53 .reset = pcibus_reset,
54 .props = (Property[]) {
55 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
56 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
57 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
58 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
59 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
60 DEFINE_PROP_END_OF_LIST()
61 }
62 };
63
64 static void pci_update_mappings(PCIDevice *d);
65 static void pci_set_irq(void *opaque, int irq_num, int level);
66 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
67 static void pci_del_option_rom(PCIDevice *pdev);
68
69 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
70 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
71
72 struct PCIHostBus {
73 int domain;
74 struct PCIBus *bus;
75 QLIST_ENTRY(PCIHostBus) next;
76 };
77 static QLIST_HEAD(, PCIHostBus) host_buses;
78
79 static const VMStateDescription vmstate_pcibus = {
80 .name = "PCIBUS",
81 .version_id = 1,
82 .minimum_version_id = 1,
83 .minimum_version_id_old = 1,
84 .fields = (VMStateField []) {
85 VMSTATE_INT32_EQUAL(nirq, PCIBus),
86 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
87 VMSTATE_END_OF_LIST()
88 }
89 };
90
91 static int pci_bar(PCIDevice *d, int reg)
92 {
93 uint8_t type;
94
95 if (reg != PCI_ROM_SLOT)
96 return PCI_BASE_ADDRESS_0 + reg * 4;
97
98 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
99 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
100 }
101
102 static inline int pci_irq_state(PCIDevice *d, int irq_num)
103 {
104 return (d->irq_state >> irq_num) & 0x1;
105 }
106
107 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
108 {
109 d->irq_state &= ~(0x1 << irq_num);
110 d->irq_state |= level << irq_num;
111 }
112
113 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
114 {
115 PCIBus *bus;
116 for (;;) {
117 bus = pci_dev->bus;
118 irq_num = bus->map_irq(pci_dev, irq_num);
119 if (bus->set_irq)
120 break;
121 pci_dev = bus->parent_dev;
122 }
123 bus->irq_count[irq_num] += change;
124 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
125 }
126
127 /* Update interrupt status bit in config space on interrupt
128 * state change. */
129 static void pci_update_irq_status(PCIDevice *dev)
130 {
131 if (dev->irq_state) {
132 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
133 } else {
134 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
135 }
136 }
137
138 static void pci_device_reset(PCIDevice *dev)
139 {
140 int r;
141 /* TODO: call the below unconditionally once all pci devices
142 * are qdevified */
143 if (dev->qdev.info) {
144 qdev_reset_all(&dev->qdev);
145 }
146
147 dev->irq_state = 0;
148 pci_update_irq_status(dev);
149 /* Clear all writeable bits */
150 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
151 pci_get_word(dev->wmask + PCI_COMMAND) |
152 pci_get_word(dev->w1cmask + PCI_COMMAND));
153 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
154 pci_get_word(dev->wmask + PCI_STATUS) |
155 pci_get_word(dev->w1cmask + PCI_STATUS));
156 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
157 dev->config[PCI_INTERRUPT_LINE] = 0x0;
158 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
159 PCIIORegion *region = &dev->io_regions[r];
160 if (!region->size) {
161 continue;
162 }
163
164 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
165 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
166 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
167 } else {
168 pci_set_long(dev->config + pci_bar(dev, r), region->type);
169 }
170 }
171 pci_update_mappings(dev);
172 }
173
174 /*
175 * Trigger pci bus reset under a given bus.
176 * To be called on RST# assert.
177 */
178 void pci_bus_reset(PCIBus *bus)
179 {
180 int i;
181
182 for (i = 0; i < bus->nirq; i++) {
183 bus->irq_count[i] = 0;
184 }
185 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
186 if (bus->devices[i]) {
187 pci_device_reset(bus->devices[i]);
188 }
189 }
190 }
191
192 static int pcibus_reset(BusState *qbus)
193 {
194 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));
195
196 /* topology traverse is done by pci_bus_reset().
197 Tell qbus/qdev walker not to traverse the tree */
198 return 1;
199 }
200
201 static void pci_host_bus_register(int domain, PCIBus *bus)
202 {
203 struct PCIHostBus *host;
204 host = qemu_mallocz(sizeof(*host));
205 host->domain = domain;
206 host->bus = bus;
207 QLIST_INSERT_HEAD(&host_buses, host, next);
208 }
209
210 PCIBus *pci_find_root_bus(int domain)
211 {
212 struct PCIHostBus *host;
213
214 QLIST_FOREACH(host, &host_buses, next) {
215 if (host->domain == domain) {
216 return host->bus;
217 }
218 }
219
220 return NULL;
221 }
222
223 int pci_find_domain(const PCIBus *bus)
224 {
225 PCIDevice *d;
226 struct PCIHostBus *host;
227
228 /* obtain root bus */
229 while ((d = bus->parent_dev) != NULL) {
230 bus = d->bus;
231 }
232
233 QLIST_FOREACH(host, &host_buses, next) {
234 if (host->bus == bus) {
235 return host->domain;
236 }
237 }
238
239 abort(); /* should not be reached */
240 return -1;
241 }
242
243 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
244 const char *name, int devfn_min)
245 {
246 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
247 assert(PCI_FUNC(devfn_min) == 0);
248 bus->devfn_min = devfn_min;
249
250 /* host bridge */
251 QLIST_INIT(&bus->child);
252 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
253
254 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
255 }
256
257 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
258 {
259 PCIBus *bus;
260
261 bus = qemu_mallocz(sizeof(*bus));
262 bus->qbus.qdev_allocated = 1;
263 pci_bus_new_inplace(bus, parent, name, devfn_min);
264 return bus;
265 }
266
267 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
268 void *irq_opaque, int nirq)
269 {
270 bus->set_irq = set_irq;
271 bus->map_irq = map_irq;
272 bus->irq_opaque = irq_opaque;
273 bus->nirq = nirq;
274 bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
275 }
276
277 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
278 {
279 bus->qbus.allow_hotplug = 1;
280 bus->hotplug = hotplug;
281 bus->hotplug_qdev = qdev;
282 }
283
284 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
285 {
286 bus->mem_base = base;
287 }
288
289 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
290 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
291 void *irq_opaque, int devfn_min, int nirq)
292 {
293 PCIBus *bus;
294
295 bus = pci_bus_new(parent, name, devfn_min);
296 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
297 return bus;
298 }
299
300 int pci_bus_num(PCIBus *s)
301 {
302 if (!s->parent_dev)
303 return 0; /* pci host bridge */
304 return s->parent_dev->config[PCI_SECONDARY_BUS];
305 }
306
307 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
308 {
309 PCIDevice *s = container_of(pv, PCIDevice, config);
310 uint8_t *config;
311 int i;
312
313 assert(size == pci_config_size(s));
314 config = qemu_malloc(size);
315
316 qemu_get_buffer(f, config, size);
317 for (i = 0; i < size; ++i) {
318 if ((config[i] ^ s->config[i]) &
319 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
320 qemu_free(config);
321 return -EINVAL;
322 }
323 }
324 memcpy(s->config, config, size);
325
326 pci_update_mappings(s);
327
328 qemu_free(config);
329 return 0;
330 }
331
332 /* just put buffer */
333 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
334 {
335 const uint8_t **v = pv;
336 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
337 qemu_put_buffer(f, *v, size);
338 }
339
340 static VMStateInfo vmstate_info_pci_config = {
341 .name = "pci config",
342 .get = get_pci_config_device,
343 .put = put_pci_config_device,
344 };
345
346 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
347 {
348 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
349 uint32_t irq_state[PCI_NUM_PINS];
350 int i;
351 for (i = 0; i < PCI_NUM_PINS; ++i) {
352 irq_state[i] = qemu_get_be32(f);
353 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
354 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
355 irq_state[i]);
356 return -EINVAL;
357 }
358 }
359
360 for (i = 0; i < PCI_NUM_PINS; ++i) {
361 pci_set_irq_state(s, i, irq_state[i]);
362 }
363
364 return 0;
365 }
366
367 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
368 {
369 int i;
370 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
371
372 for (i = 0; i < PCI_NUM_PINS; ++i) {
373 qemu_put_be32(f, pci_irq_state(s, i));
374 }
375 }
376
377 static VMStateInfo vmstate_info_pci_irq_state = {
378 .name = "pci irq state",
379 .get = get_pci_irq_state,
380 .put = put_pci_irq_state,
381 };
382
383 const VMStateDescription vmstate_pci_device = {
384 .name = "PCIDevice",
385 .version_id = 2,
386 .minimum_version_id = 1,
387 .minimum_version_id_old = 1,
388 .fields = (VMStateField []) {
389 VMSTATE_INT32_LE(version_id, PCIDevice),
390 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
391 vmstate_info_pci_config,
392 PCI_CONFIG_SPACE_SIZE),
393 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
394 vmstate_info_pci_irq_state,
395 PCI_NUM_PINS * sizeof(int32_t)),
396 VMSTATE_END_OF_LIST()
397 }
398 };
399
400 const VMStateDescription vmstate_pcie_device = {
401 .name = "PCIDevice",
402 .version_id = 2,
403 .minimum_version_id = 1,
404 .minimum_version_id_old = 1,
405 .fields = (VMStateField []) {
406 VMSTATE_INT32_LE(version_id, PCIDevice),
407 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
408 vmstate_info_pci_config,
409 PCIE_CONFIG_SPACE_SIZE),
410 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
411 vmstate_info_pci_irq_state,
412 PCI_NUM_PINS * sizeof(int32_t)),
413 VMSTATE_END_OF_LIST()
414 }
415 };
416
417 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
418 {
419 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
420 }
421
422 void pci_device_save(PCIDevice *s, QEMUFile *f)
423 {
424 /* Clear interrupt status bit: it is implicit
425 * in irq_state which we are saving.
426 * This makes us compatible with old devices
427 * which never set or clear this bit. */
428 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
429 vmstate_save_state(f, pci_get_vmstate(s), s);
430 /* Restore the interrupt status bit. */
431 pci_update_irq_status(s);
432 }
433
434 int pci_device_load(PCIDevice *s, QEMUFile *f)
435 {
436 int ret;
437 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
438 /* Restore the interrupt status bit. */
439 pci_update_irq_status(s);
440 return ret;
441 }
442
443 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
444 {
445 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
446 pci_default_sub_vendor_id);
447 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
448 pci_default_sub_device_id);
449 }
450
451 /*
452 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
453 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
454 */
455 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
456 unsigned int *slotp, unsigned int *funcp)
457 {
458 const char *p;
459 char *e;
460 unsigned long val;
461 unsigned long dom = 0, bus = 0;
462 unsigned int slot = 0;
463 unsigned int func = 0;
464
465 p = addr;
466 val = strtoul(p, &e, 16);
467 if (e == p)
468 return -1;
469 if (*e == ':') {
470 bus = val;
471 p = e + 1;
472 val = strtoul(p, &e, 16);
473 if (e == p)
474 return -1;
475 if (*e == ':') {
476 dom = bus;
477 bus = val;
478 p = e + 1;
479 val = strtoul(p, &e, 16);
480 if (e == p)
481 return -1;
482 }
483 }
484
485 slot = val;
486
487 if (funcp != NULL) {
488 if (*e != '.')
489 return -1;
490
491 p = e + 1;
492 val = strtoul(p, &e, 16);
493 if (e == p)
494 return -1;
495
496 func = val;
497 }
498
499 /* if funcp == NULL func is 0 */
500 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
501 return -1;
502
503 if (*e)
504 return -1;
505
506 /* Note: QEMU doesn't implement domains other than 0 */
507 if (!pci_find_bus(pci_find_root_bus(dom), bus))
508 return -1;
509
510 *domp = dom;
511 *busp = bus;
512 *slotp = slot;
513 if (funcp != NULL)
514 *funcp = func;
515 return 0;
516 }
517
518 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
519 unsigned *slotp)
520 {
521 /* strip legacy tag */
522 if (!strncmp(addr, "pci_addr=", 9)) {
523 addr += 9;
524 }
525 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
526 monitor_printf(mon, "Invalid pci address\n");
527 return -1;
528 }
529 return 0;
530 }
531
532 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
533 {
534 int dom, bus;
535 unsigned slot;
536
537 if (!devaddr) {
538 *devfnp = -1;
539 return pci_find_bus(pci_find_root_bus(0), 0);
540 }
541
542 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
543 return NULL;
544 }
545
546 *devfnp = slot << 3;
547 return pci_find_bus(pci_find_root_bus(dom), bus);
548 }
549
550 static void pci_init_cmask(PCIDevice *dev)
551 {
552 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
553 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
554 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
555 dev->cmask[PCI_REVISION_ID] = 0xff;
556 dev->cmask[PCI_CLASS_PROG] = 0xff;
557 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
558 dev->cmask[PCI_HEADER_TYPE] = 0xff;
559 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
560 }
561
562 static void pci_init_wmask(PCIDevice *dev)
563 {
564 int config_size = pci_config_size(dev);
565
566 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
567 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
568 pci_set_word(dev->wmask + PCI_COMMAND,
569 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
570 PCI_COMMAND_INTX_DISABLE);
571
572 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
573 config_size - PCI_CONFIG_HEADER_SIZE);
574 }
575
576 static void pci_init_w1cmask(PCIDevice *dev)
577 {
578 /*
579 * Note: It's okay to set w1cmask even for readonly bits as
580 * long as their value is hardwired to 0.
581 */
582 pci_set_word(dev->w1cmask + PCI_STATUS,
583 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
584 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
585 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
586 }
587
588 static void pci_init_wmask_bridge(PCIDevice *d)
589 {
590 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
591 PCI_SEC_LETENCY_TIMER */
592 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
593
594 /* base and limit */
595 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
596 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
597 pci_set_word(d->wmask + PCI_MEMORY_BASE,
598 PCI_MEMORY_RANGE_MASK & 0xffff);
599 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
600 PCI_MEMORY_RANGE_MASK & 0xffff);
601 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
602 PCI_PREF_RANGE_MASK & 0xffff);
603 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
604 PCI_PREF_RANGE_MASK & 0xffff);
605
606 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
607 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
608
609 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
610 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
611 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
612 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
613 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
614 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
615 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
616 PCI_BRIDGE_CTL_PARITY |
617 PCI_BRIDGE_CTL_SERR |
618 PCI_BRIDGE_CTL_ISA |
619 PCI_BRIDGE_CTL_VGA |
620 PCI_BRIDGE_CTL_VGA_16BIT |
621 PCI_BRIDGE_CTL_MASTER_ABORT |
622 PCI_BRIDGE_CTL_BUS_RESET |
623 PCI_BRIDGE_CTL_FAST_BACK |
624 PCI_BRIDGE_CTL_DISCARD |
625 PCI_BRIDGE_CTL_SEC_DISCARD |
626 PCI_BRIDGE_CTL_DISCARD_STATUS |
627 PCI_BRIDGE_CTL_DISCARD_SERR);
628 /* Below does not do anything as we never set this bit, put here for
629 * completeness. */
630 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
631 PCI_BRIDGE_CTL_DISCARD_STATUS);
632 }
633
634 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
635 {
636 uint8_t slot = PCI_SLOT(dev->devfn);
637 uint8_t func;
638
639 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
640 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
641 }
642
643 /*
644 * multifunction bit is interpreted in two ways as follows.
645 * - all functions must set the bit to 1.
646 * Example: Intel X53
647 * - function 0 must set the bit, but the rest function (> 0)
648 * is allowed to leave the bit to 0.
649 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
650 *
651 * So OS (at least Linux) checks the bit of only function 0,
652 * and doesn't see the bit of function > 0.
653 *
654 * The below check allows both interpretation.
655 */
656 if (PCI_FUNC(dev->devfn)) {
657 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
658 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
659 /* function 0 should set multifunction bit */
660 error_report("PCI: single function device can't be populated "
661 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
662 return -1;
663 }
664 return 0;
665 }
666
667 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
668 return 0;
669 }
670 /* function 0 indicates single function, so function > 0 must be NULL */
671 for (func = 1; func < PCI_FUNC_MAX; ++func) {
672 if (bus->devices[PCI_DEVFN(slot, func)]) {
673 error_report("PCI: %x.0 indicates single function, "
674 "but %x.%x is already populated.",
675 slot, slot, func);
676 return -1;
677 }
678 }
679 return 0;
680 }
681
682 static void pci_config_alloc(PCIDevice *pci_dev)
683 {
684 int config_size = pci_config_size(pci_dev);
685
686 pci_dev->config = qemu_mallocz(config_size);
687 pci_dev->cmask = qemu_mallocz(config_size);
688 pci_dev->wmask = qemu_mallocz(config_size);
689 pci_dev->w1cmask = qemu_mallocz(config_size);
690 pci_dev->used = qemu_mallocz(config_size);
691 }
692
693 static void pci_config_free(PCIDevice *pci_dev)
694 {
695 qemu_free(pci_dev->config);
696 qemu_free(pci_dev->cmask);
697 qemu_free(pci_dev->wmask);
698 qemu_free(pci_dev->w1cmask);
699 qemu_free(pci_dev->used);
700 }
701
702 /* -1 for devfn means auto assign */
703 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
704 const char *name, int devfn,
705 PCIConfigReadFunc *config_read,
706 PCIConfigWriteFunc *config_write,
707 bool is_bridge)
708 {
709 if (devfn < 0) {
710 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
711 devfn += PCI_FUNC_MAX) {
712 if (!bus->devices[devfn])
713 goto found;
714 }
715 error_report("PCI: no slot/function available for %s, all in use", name);
716 return NULL;
717 found: ;
718 } else if (bus->devices[devfn]) {
719 error_report("PCI: slot %d function %d not available for %s, in use by %s",
720 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
721 return NULL;
722 }
723 pci_dev->bus = bus;
724 pci_dev->devfn = devfn;
725 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
726 pci_dev->irq_state = 0;
727 pci_config_alloc(pci_dev);
728
729 if (!is_bridge) {
730 pci_set_default_subsystem_id(pci_dev);
731 }
732 pci_init_cmask(pci_dev);
733 pci_init_wmask(pci_dev);
734 pci_init_w1cmask(pci_dev);
735 if (is_bridge) {
736 pci_init_wmask_bridge(pci_dev);
737 }
738 if (pci_init_multifunction(bus, pci_dev)) {
739 pci_config_free(pci_dev);
740 return NULL;
741 }
742
743 if (!config_read)
744 config_read = pci_default_read_config;
745 if (!config_write)
746 config_write = pci_default_write_config;
747 pci_dev->config_read = config_read;
748 pci_dev->config_write = config_write;
749 bus->devices[devfn] = pci_dev;
750 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
751 pci_dev->version_id = 2; /* Current pci device vmstate version */
752 return pci_dev;
753 }
754
755 static void do_pci_unregister_device(PCIDevice *pci_dev)
756 {
757 qemu_free_irqs(pci_dev->irq);
758 pci_dev->bus->devices[pci_dev->devfn] = NULL;
759 pci_config_free(pci_dev);
760 }
761
762 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
763 int instance_size, int devfn,
764 PCIConfigReadFunc *config_read,
765 PCIConfigWriteFunc *config_write)
766 {
767 PCIDevice *pci_dev;
768
769 pci_dev = qemu_mallocz(instance_size);
770 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
771 config_read, config_write,
772 PCI_HEADER_TYPE_NORMAL);
773 if (pci_dev == NULL) {
774 hw_error("PCI: can't register device\n");
775 }
776 return pci_dev;
777 }
778
779 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
780 target_phys_addr_t addr)
781 {
782 return addr + bus->mem_base;
783 }
784
785 static void pci_unregister_io_regions(PCIDevice *pci_dev)
786 {
787 PCIIORegion *r;
788 int i;
789
790 for(i = 0; i < PCI_NUM_REGIONS; i++) {
791 r = &pci_dev->io_regions[i];
792 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
793 continue;
794 if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
795 isa_unassign_ioport(r->addr, r->filtered_size);
796 } else {
797 cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
798 r->addr),
799 r->filtered_size,
800 IO_MEM_UNASSIGNED);
801 }
802 }
803 }
804
805 static int pci_unregister_device(DeviceState *dev)
806 {
807 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
808 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
809 int ret = 0;
810
811 if (info->exit)
812 ret = info->exit(pci_dev);
813 if (ret)
814 return ret;
815
816 pci_unregister_io_regions(pci_dev);
817 pci_del_option_rom(pci_dev);
818 do_pci_unregister_device(pci_dev);
819 return 0;
820 }
821
822 void pci_register_bar(PCIDevice *pci_dev, int region_num,
823 pcibus_t size, uint8_t type,
824 PCIMapIORegionFunc *map_func)
825 {
826 PCIIORegion *r;
827 uint32_t addr;
828 uint64_t wmask;
829
830 assert(region_num >= 0);
831 assert(region_num < PCI_NUM_REGIONS);
832 if (size & (size-1)) {
833 fprintf(stderr, "ERROR: PCI region size must be pow2 "
834 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
835 exit(1);
836 }
837
838 r = &pci_dev->io_regions[region_num];
839 r->addr = PCI_BAR_UNMAPPED;
840 r->size = size;
841 r->filtered_size = size;
842 r->type = type;
843 r->map_func = map_func;
844
845 wmask = ~(size - 1);
846 addr = pci_bar(pci_dev, region_num);
847 if (region_num == PCI_ROM_SLOT) {
848 /* ROM enable bit is writeable */
849 wmask |= PCI_ROM_ADDRESS_ENABLE;
850 }
851 pci_set_long(pci_dev->config + addr, type);
852 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
853 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
854 pci_set_quad(pci_dev->wmask + addr, wmask);
855 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
856 } else {
857 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
858 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
859 }
860 }
861
862 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
863 uint8_t type)
864 {
865 pcibus_t base = *addr;
866 pcibus_t limit = *addr + *size - 1;
867 PCIDevice *br;
868
869 for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
870 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
871
872 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
873 if (!(cmd & PCI_COMMAND_IO)) {
874 goto no_map;
875 }
876 } else {
877 if (!(cmd & PCI_COMMAND_MEMORY)) {
878 goto no_map;
879 }
880 }
881
882 base = MAX(base, pci_bridge_get_base(br, type));
883 limit = MIN(limit, pci_bridge_get_limit(br, type));
884 }
885
886 if (base > limit) {
887 goto no_map;
888 }
889 *addr = base;
890 *size = limit - base + 1;
891 return;
892 no_map:
893 *addr = PCI_BAR_UNMAPPED;
894 *size = 0;
895 }
896
897 static pcibus_t pci_bar_address(PCIDevice *d,
898 int reg, uint8_t type, pcibus_t size)
899 {
900 pcibus_t new_addr, last_addr;
901 int bar = pci_bar(d, reg);
902 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
903
904 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
905 if (!(cmd & PCI_COMMAND_IO)) {
906 return PCI_BAR_UNMAPPED;
907 }
908 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
909 last_addr = new_addr + size - 1;
910 /* NOTE: we have only 64K ioports on PC */
911 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
912 return PCI_BAR_UNMAPPED;
913 }
914 return new_addr;
915 }
916
917 if (!(cmd & PCI_COMMAND_MEMORY)) {
918 return PCI_BAR_UNMAPPED;
919 }
920 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
921 new_addr = pci_get_quad(d->config + bar);
922 } else {
923 new_addr = pci_get_long(d->config + bar);
924 }
925 /* the ROM slot has a specific enable bit */
926 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
927 return PCI_BAR_UNMAPPED;
928 }
929 new_addr &= ~(size - 1);
930 last_addr = new_addr + size - 1;
931 /* NOTE: we do not support wrapping */
932 /* XXX: as we cannot support really dynamic
933 mappings, we handle specific values as invalid
934 mappings. */
935 if (last_addr <= new_addr || new_addr == 0 ||
936 last_addr == PCI_BAR_UNMAPPED) {
937 return PCI_BAR_UNMAPPED;
938 }
939
940 /* Now pcibus_t is 64bit.
941 * Check if 32 bit BAR wraps around explicitly.
942 * Without this, PC ide doesn't work well.
943 * TODO: remove this work around.
944 */
945 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
946 return PCI_BAR_UNMAPPED;
947 }
948
949 /*
950 * OS is allowed to set BAR beyond its addressable
951 * bits. For example, 32 bit OS can set 64bit bar
952 * to >4G. Check it. TODO: we might need to support
953 * it in the future for e.g. PAE.
954 */
955 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
956 return PCI_BAR_UNMAPPED;
957 }
958
959 return new_addr;
960 }
961
962 static void pci_update_mappings(PCIDevice *d)
963 {
964 PCIIORegion *r;
965 int i;
966 pcibus_t new_addr, filtered_size;
967
968 for(i = 0; i < PCI_NUM_REGIONS; i++) {
969 r = &d->io_regions[i];
970
971 /* this region isn't registered */
972 if (!r->size)
973 continue;
974
975 new_addr = pci_bar_address(d, i, r->type, r->size);
976
977 /* bridge filtering */
978 filtered_size = r->size;
979 if (new_addr != PCI_BAR_UNMAPPED) {
980 pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
981 }
982
983 /* This bar isn't changed */
984 if (new_addr == r->addr && filtered_size == r->filtered_size)
985 continue;
986
987 /* now do the real mapping */
988 if (r->addr != PCI_BAR_UNMAPPED) {
989 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
990 int class;
991 /* NOTE: specific hack for IDE in PC case:
992 only one byte must be mapped. */
993 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
994 if (class == 0x0101 && r->size == 4) {
995 isa_unassign_ioport(r->addr + 2, 1);
996 } else {
997 isa_unassign_ioport(r->addr, r->filtered_size);
998 }
999 } else {
1000 cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
1001 r->filtered_size,
1002 IO_MEM_UNASSIGNED);
1003 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
1004 }
1005 }
1006 r->addr = new_addr;
1007 r->filtered_size = filtered_size;
1008 if (r->addr != PCI_BAR_UNMAPPED) {
1009 /*
1010 * TODO: currently almost all the map funcions assumes
1011 * filtered_size == size and addr & ~(size - 1) == addr.
1012 * However with bridge filtering, they aren't always true.
1013 * Teach them such cases, such that filtered_size < size and
1014 * addr & (size - 1) != 0.
1015 */
1016 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1017 r->map_func(d, i, r->addr, r->filtered_size, r->type);
1018 } else {
1019 r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
1020 r->filtered_size, r->type);
1021 }
1022 }
1023 }
1024 }
1025
1026 static inline int pci_irq_disabled(PCIDevice *d)
1027 {
1028 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1029 }
1030
1031 /* Called after interrupt disabled field update in config space,
1032 * assert/deassert interrupts if necessary.
1033 * Gets original interrupt disable bit value (before update). */
1034 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1035 {
1036 int i, disabled = pci_irq_disabled(d);
1037 if (disabled == was_irq_disabled)
1038 return;
1039 for (i = 0; i < PCI_NUM_PINS; ++i) {
1040 int state = pci_irq_state(d, i);
1041 pci_change_irq_level(d, i, disabled ? -state : state);
1042 }
1043 }
1044
1045 uint32_t pci_default_read_config(PCIDevice *d,
1046 uint32_t address, int len)
1047 {
1048 uint32_t val = 0;
1049 assert(len == 1 || len == 2 || len == 4);
1050 len = MIN(len, pci_config_size(d) - address);
1051 memcpy(&val, d->config + address, len);
1052 return le32_to_cpu(val);
1053 }
1054
1055 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1056 {
1057 int i, was_irq_disabled = pci_irq_disabled(d);
1058 uint32_t config_size = pci_config_size(d);
1059
1060 for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
1061 uint8_t wmask = d->wmask[addr + i];
1062 uint8_t w1cmask = d->w1cmask[addr + i];
1063 assert(!(wmask & w1cmask));
1064 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1065 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1066 }
1067 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1068 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1069 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1070 range_covers_byte(addr, l, PCI_COMMAND))
1071 pci_update_mappings(d);
1072
1073 if (range_covers_byte(addr, l, PCI_COMMAND))
1074 pci_update_irq_disabled(d, was_irq_disabled);
1075 }
1076
1077 /***********************************************************/
1078 /* generic PCI irq support */
1079
1080 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1081 static void pci_set_irq(void *opaque, int irq_num, int level)
1082 {
1083 PCIDevice *pci_dev = opaque;
1084 int change;
1085
1086 change = level - pci_irq_state(pci_dev, irq_num);
1087 if (!change)
1088 return;
1089
1090 pci_set_irq_state(pci_dev, irq_num, level);
1091 pci_update_irq_status(pci_dev);
1092 if (pci_irq_disabled(pci_dev))
1093 return;
1094 pci_change_irq_level(pci_dev, irq_num, change);
1095 }
1096
1097 bool pci_msi_enabled(PCIDevice *dev)
1098 {
1099 return msix_enabled(dev) || msi_enabled(dev);
1100 }
1101
1102 void pci_msi_notify(PCIDevice *dev, unsigned int vector)
1103 {
1104 if (msix_enabled(dev)) {
1105 msix_notify(dev, vector);
1106 } else if (msi_enabled(dev)) {
1107 msi_notify(dev, vector);
1108 } else {
1109 /* MSI/MSI-X must be enabled */
1110 abort();
1111 }
1112 }
1113
1114 /***********************************************************/
1115 /* monitor info on PCI */
1116
1117 typedef struct {
1118 uint16_t class;
1119 const char *desc;
1120 } pci_class_desc;
1121
1122 static const pci_class_desc pci_class_descriptions[] =
1123 {
1124 { 0x0100, "SCSI controller"},
1125 { 0x0101, "IDE controller"},
1126 { 0x0102, "Floppy controller"},
1127 { 0x0103, "IPI controller"},
1128 { 0x0104, "RAID controller"},
1129 { 0x0106, "SATA controller"},
1130 { 0x0107, "SAS controller"},
1131 { 0x0180, "Storage controller"},
1132 { 0x0200, "Ethernet controller"},
1133 { 0x0201, "Token Ring controller"},
1134 { 0x0202, "FDDI controller"},
1135 { 0x0203, "ATM controller"},
1136 { 0x0280, "Network controller"},
1137 { 0x0300, "VGA controller"},
1138 { 0x0301, "XGA controller"},
1139 { 0x0302, "3D controller"},
1140 { 0x0380, "Display controller"},
1141 { 0x0400, "Video controller"},
1142 { 0x0401, "Audio controller"},
1143 { 0x0402, "Phone"},
1144 { 0x0480, "Multimedia controller"},
1145 { 0x0500, "RAM controller"},
1146 { 0x0501, "Flash controller"},
1147 { 0x0580, "Memory controller"},
1148 { 0x0600, "Host bridge"},
1149 { 0x0601, "ISA bridge"},
1150 { 0x0602, "EISA bridge"},
1151 { 0x0603, "MC bridge"},
1152 { 0x0604, "PCI bridge"},
1153 { 0x0605, "PCMCIA bridge"},
1154 { 0x0606, "NUBUS bridge"},
1155 { 0x0607, "CARDBUS bridge"},
1156 { 0x0608, "RACEWAY bridge"},
1157 { 0x0680, "Bridge"},
1158 { 0x0c03, "USB controller"},
1159 { 0, NULL}
1160 };
1161
1162 static void pci_for_each_device_under_bus(PCIBus *bus,
1163 void (*fn)(PCIBus *b, PCIDevice *d))
1164 {
1165 PCIDevice *d;
1166 int devfn;
1167
1168 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1169 d = bus->devices[devfn];
1170 if (d) {
1171 fn(bus, d);
1172 }
1173 }
1174 }
1175
1176 void pci_for_each_device(PCIBus *bus, int bus_num,
1177 void (*fn)(PCIBus *b, PCIDevice *d))
1178 {
1179 bus = pci_find_bus(bus, bus_num);
1180
1181 if (bus) {
1182 pci_for_each_device_under_bus(bus, fn);
1183 }
1184 }
1185
1186 static void pci_device_print(Monitor *mon, QDict *device)
1187 {
1188 QDict *qdict;
1189 QListEntry *entry;
1190 uint64_t addr, size;
1191
1192 monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1193 monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1194 qdict_get_int(device, "slot"),
1195 qdict_get_int(device, "function"));
1196 monitor_printf(mon, " ");
1197
1198 qdict = qdict_get_qdict(device, "class_info");
1199 if (qdict_haskey(qdict, "desc")) {
1200 monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1201 } else {
1202 monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1203 }
1204
1205 qdict = qdict_get_qdict(device, "id");
1206 monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1207 qdict_get_int(qdict, "device"),
1208 qdict_get_int(qdict, "vendor"));
1209
1210 if (qdict_haskey(device, "irq")) {
1211 monitor_printf(mon, " IRQ %" PRId64 ".\n",
1212 qdict_get_int(device, "irq"));
1213 }
1214
1215 if (qdict_haskey(device, "pci_bridge")) {
1216 QDict *info;
1217
1218 qdict = qdict_get_qdict(device, "pci_bridge");
1219
1220 info = qdict_get_qdict(qdict, "bus");
1221 monitor_printf(mon, " BUS %" PRId64 ".\n",
1222 qdict_get_int(info, "number"));
1223 monitor_printf(mon, " secondary bus %" PRId64 ".\n",
1224 qdict_get_int(info, "secondary"));
1225 monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
1226 qdict_get_int(info, "subordinate"));
1227
1228 info = qdict_get_qdict(qdict, "io_range");
1229 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1230 qdict_get_int(info, "base"),
1231 qdict_get_int(info, "limit"));
1232
1233 info = qdict_get_qdict(qdict, "memory_range");
1234 monitor_printf(mon,
1235 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1236 qdict_get_int(info, "base"),
1237 qdict_get_int(info, "limit"));
1238
1239 info = qdict_get_qdict(qdict, "prefetchable_range");
1240 monitor_printf(mon, " prefetchable memory range "
1241 "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1242 qdict_get_int(info, "base"),
1243 qdict_get_int(info, "limit"));
1244 }
1245
1246 QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1247 qdict = qobject_to_qdict(qlist_entry_obj(entry));
1248 monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1249
1250 addr = qdict_get_int(qdict, "address");
1251 size = qdict_get_int(qdict, "size");
1252
1253 if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1254 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1255 " [0x%04"FMT_PCIBUS"].\n",
1256 addr, addr + size - 1);
1257 } else {
1258 monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1259 " [0x%08"FMT_PCIBUS"].\n",
1260 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1261 qdict_get_bool(qdict, "prefetch") ?
1262 " prefetchable" : "", addr, addr + size - 1);
1263 }
1264 }
1265
1266 monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1267
1268 if (qdict_haskey(device, "pci_bridge")) {
1269 qdict = qdict_get_qdict(device, "pci_bridge");
1270 if (qdict_haskey(qdict, "devices")) {
1271 QListEntry *dev;
1272 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1273 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1274 }
1275 }
1276 }
1277 }
1278
1279 void do_pci_info_print(Monitor *mon, const QObject *data)
1280 {
1281 QListEntry *bus, *dev;
1282
1283 QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1284 QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1285 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1286 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1287 }
1288 }
1289 }
1290
1291 static QObject *pci_get_dev_class(const PCIDevice *dev)
1292 {
1293 int class;
1294 const pci_class_desc *desc;
1295
1296 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1297 desc = pci_class_descriptions;
1298 while (desc->desc && class != desc->class)
1299 desc++;
1300
1301 if (desc->desc) {
1302 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1303 desc->desc, class);
1304 } else {
1305 return qobject_from_jsonf("{ 'class': %d }", class);
1306 }
1307 }
1308
1309 static QObject *pci_get_dev_id(const PCIDevice *dev)
1310 {
1311 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1312 pci_get_word(dev->config + PCI_VENDOR_ID),
1313 pci_get_word(dev->config + PCI_DEVICE_ID));
1314 }
1315
1316 static QObject *pci_get_regions_list(const PCIDevice *dev)
1317 {
1318 int i;
1319 QList *regions_list;
1320
1321 regions_list = qlist_new();
1322
1323 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1324 QObject *obj;
1325 const PCIIORegion *r = &dev->io_regions[i];
1326
1327 if (!r->size) {
1328 continue;
1329 }
1330
1331 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1332 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1333 "'address': %" PRId64 ", "
1334 "'size': %" PRId64 " }",
1335 i, r->addr, r->size);
1336 } else {
1337 int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1338
1339 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1340 "'mem_type_64': %i, 'prefetch': %i, "
1341 "'address': %" PRId64 ", "
1342 "'size': %" PRId64 " }",
1343 i, mem_type_64,
1344 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1345 r->addr, r->size);
1346 }
1347
1348 qlist_append_obj(regions_list, obj);
1349 }
1350
1351 return QOBJECT(regions_list);
1352 }
1353
1354 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1355
1356 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1357 {
1358 uint8_t type;
1359 QObject *obj;
1360
1361 obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1362 " 'qdev_id': %s }",
1363 bus_num,
1364 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1365 pci_get_dev_class(dev), pci_get_dev_id(dev),
1366 pci_get_regions_list(dev),
1367 dev->qdev.id ? dev->qdev.id : "");
1368
1369 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1370 QDict *qdict = qobject_to_qdict(obj);
1371 qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1372 }
1373
1374 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1375 if (type == PCI_HEADER_TYPE_BRIDGE) {
1376 QDict *qdict;
1377 QObject *pci_bridge;
1378
1379 pci_bridge = qobject_from_jsonf("{ 'bus': "
1380 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1381 "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1382 "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1383 "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1384 dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1385 dev->config[PCI_SUBORDINATE_BUS],
1386 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1387 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1388 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1389 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1390 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1391 PCI_BASE_ADDRESS_MEM_PREFETCH),
1392 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1393 PCI_BASE_ADDRESS_MEM_PREFETCH));
1394
1395 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1396 PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1397
1398 if (child_bus) {
1399 qdict = qobject_to_qdict(pci_bridge);
1400 qdict_put_obj(qdict, "devices",
1401 pci_get_devices_list(child_bus,
1402 dev->config[PCI_SECONDARY_BUS]));
1403 }
1404 }
1405 qdict = qobject_to_qdict(obj);
1406 qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1407 }
1408
1409 return obj;
1410 }
1411
1412 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1413 {
1414 int devfn;
1415 PCIDevice *dev;
1416 QList *dev_list;
1417
1418 dev_list = qlist_new();
1419
1420 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1421 dev = bus->devices[devfn];
1422 if (dev) {
1423 qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1424 }
1425 }
1426
1427 return QOBJECT(dev_list);
1428 }
1429
1430 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1431 {
1432 bus = pci_find_bus(bus, bus_num);
1433 if (bus) {
1434 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1435 bus_num, pci_get_devices_list(bus, bus_num));
1436 }
1437
1438 return NULL;
1439 }
1440
1441 void do_pci_info(Monitor *mon, QObject **ret_data)
1442 {
1443 QList *bus_list;
1444 struct PCIHostBus *host;
1445
1446 bus_list = qlist_new();
1447
1448 QLIST_FOREACH(host, &host_buses, next) {
1449 QObject *obj = pci_get_bus_dict(host->bus, 0);
1450 if (obj) {
1451 qlist_append_obj(bus_list, obj);
1452 }
1453 }
1454
1455 *ret_data = QOBJECT(bus_list);
1456 }
1457
1458 static const char * const pci_nic_models[] = {
1459 "ne2k_pci",
1460 "i82551",
1461 "i82557b",
1462 "i82559er",
1463 "rtl8139",
1464 "e1000",
1465 "pcnet",
1466 "virtio",
1467 NULL
1468 };
1469
1470 static const char * const pci_nic_names[] = {
1471 "ne2k_pci",
1472 "i82551",
1473 "i82557b",
1474 "i82559er",
1475 "rtl8139",
1476 "e1000",
1477 "pcnet",
1478 "virtio-net-pci",
1479 NULL
1480 };
1481
1482 /* Initialize a PCI NIC. */
1483 /* FIXME callers should check for failure, but don't */
1484 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1485 const char *default_devaddr)
1486 {
1487 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1488 PCIBus *bus;
1489 int devfn;
1490 PCIDevice *pci_dev;
1491 DeviceState *dev;
1492 int i;
1493
1494 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1495 if (i < 0)
1496 return NULL;
1497
1498 bus = pci_get_bus_devfn(&devfn, devaddr);
1499 if (!bus) {
1500 error_report("Invalid PCI device address %s for device %s",
1501 devaddr, pci_nic_names[i]);
1502 return NULL;
1503 }
1504
1505 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1506 dev = &pci_dev->qdev;
1507 qdev_set_nic_properties(dev, nd);
1508 if (qdev_init(dev) < 0)
1509 return NULL;
1510 return pci_dev;
1511 }
1512
1513 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1514 const char *default_devaddr)
1515 {
1516 PCIDevice *res;
1517
1518 if (qemu_show_nic_models(nd->model, pci_nic_models))
1519 exit(0);
1520
1521 res = pci_nic_init(nd, default_model, default_devaddr);
1522 if (!res)
1523 exit(1);
1524 return res;
1525 }
1526
1527 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1528 {
1529 pci_update_mappings(d);
1530 }
1531
1532 void pci_bridge_update_mappings(PCIBus *b)
1533 {
1534 PCIBus *child;
1535
1536 pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1537
1538 QLIST_FOREACH(child, &b->child, sibling) {
1539 pci_bridge_update_mappings(child);
1540 }
1541 }
1542
1543 /* Whether a given bus number is in range of the secondary
1544 * bus of the given bridge device. */
1545 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1546 {
1547 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1548 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1549 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1550 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1551 }
1552
1553 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1554 {
1555 PCIBus *sec;
1556
1557 if (!bus) {
1558 return NULL;
1559 }
1560
1561 if (pci_bus_num(bus) == bus_num) {
1562 return bus;
1563 }
1564
1565 /* Consider all bus numbers in range for the host pci bridge. */
1566 if (bus->parent_dev &&
1567 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1568 return NULL;
1569 }
1570
1571 /* try child bus */
1572 for (; bus; bus = sec) {
1573 QLIST_FOREACH(sec, &bus->child, sibling) {
1574 assert(sec->parent_dev);
1575 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1576 return sec;
1577 }
1578 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1579 break;
1580 }
1581 }
1582 }
1583
1584 return NULL;
1585 }
1586
1587 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1588 {
1589 bus = pci_find_bus(bus, bus_num);
1590
1591 if (!bus)
1592 return NULL;
1593
1594 return bus->devices[PCI_DEVFN(slot, function)];
1595 }
1596
1597 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1598 {
1599 PCIDevice *pci_dev = (PCIDevice *)qdev;
1600 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1601 PCIBus *bus;
1602 int devfn, rc;
1603 bool is_default_rom;
1604
1605 /* initialize cap_present for pci_is_express() and pci_config_size() */
1606 if (info->is_express) {
1607 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1608 }
1609
1610 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1611 devfn = pci_dev->devfn;
1612 pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1613 info->config_read, info->config_write,
1614 info->is_bridge);
1615 if (pci_dev == NULL)
1616 return -1;
1617 rc = info->init(pci_dev);
1618 if (rc != 0) {
1619 do_pci_unregister_device(pci_dev);
1620 return rc;
1621 }
1622
1623 /* rom loading */
1624 is_default_rom = false;
1625 if (pci_dev->romfile == NULL && info->romfile != NULL) {
1626 pci_dev->romfile = qemu_strdup(info->romfile);
1627 is_default_rom = true;
1628 }
1629 pci_add_option_rom(pci_dev, is_default_rom);
1630
1631 if (bus->hotplug) {
1632 /* Let buses differentiate between hotplug and when device is
1633 * enabled during qemu machine creation. */
1634 rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1635 qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1636 PCI_COLDPLUG_ENABLED);
1637 if (rc != 0) {
1638 int r = pci_unregister_device(&pci_dev->qdev);
1639 assert(!r);
1640 return rc;
1641 }
1642 }
1643 return 0;
1644 }
1645
1646 static int pci_unplug_device(DeviceState *qdev)
1647 {
1648 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1649
1650 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1651 PCI_HOTPLUG_DISABLED);
1652 }
1653
1654 void pci_qdev_register(PCIDeviceInfo *info)
1655 {
1656 info->qdev.init = pci_qdev_init;
1657 info->qdev.unplug = pci_unplug_device;
1658 info->qdev.exit = pci_unregister_device;
1659 info->qdev.bus_info = &pci_bus_info;
1660 qdev_register(&info->qdev);
1661 }
1662
1663 void pci_qdev_register_many(PCIDeviceInfo *info)
1664 {
1665 while (info->qdev.name) {
1666 pci_qdev_register(info);
1667 info++;
1668 }
1669 }
1670
1671 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1672 const char *name)
1673 {
1674 DeviceState *dev;
1675
1676 dev = qdev_create(&bus->qbus, name);
1677 qdev_prop_set_uint32(dev, "addr", devfn);
1678 qdev_prop_set_bit(dev, "multifunction", multifunction);
1679 return DO_UPCAST(PCIDevice, qdev, dev);
1680 }
1681
1682 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1683 bool multifunction,
1684 const char *name)
1685 {
1686 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1687 qdev_init_nofail(&dev->qdev);
1688 return dev;
1689 }
1690
1691 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1692 {
1693 return pci_create_multifunction(bus, devfn, false, name);
1694 }
1695
1696 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1697 {
1698 return pci_create_simple_multifunction(bus, devfn, false, name);
1699 }
1700
1701 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1702 {
1703 int config_size = pci_config_size(pdev);
1704 int offset = PCI_CONFIG_HEADER_SIZE;
1705 int i;
1706 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1707 if (pdev->used[i])
1708 offset = i + 1;
1709 else if (i - offset + 1 == size)
1710 return offset;
1711 return 0;
1712 }
1713
1714 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1715 uint8_t *prev_p)
1716 {
1717 uint8_t next, prev;
1718
1719 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1720 return 0;
1721
1722 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1723 prev = next + PCI_CAP_LIST_NEXT)
1724 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1725 break;
1726
1727 if (prev_p)
1728 *prev_p = prev;
1729 return next;
1730 }
1731
1732 static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1733 {
1734 cpu_register_physical_memory(addr, size, pdev->rom_offset);
1735 }
1736
1737 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1738 This is needed for an option rom which is used for more than one device. */
1739 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1740 {
1741 uint16_t vendor_id;
1742 uint16_t device_id;
1743 uint16_t rom_vendor_id;
1744 uint16_t rom_device_id;
1745 uint16_t rom_magic;
1746 uint16_t pcir_offset;
1747 uint8_t checksum;
1748
1749 /* Words in rom data are little endian (like in PCI configuration),
1750 so they can be read / written with pci_get_word / pci_set_word. */
1751
1752 /* Only a valid rom will be patched. */
1753 rom_magic = pci_get_word(ptr);
1754 if (rom_magic != 0xaa55) {
1755 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1756 return;
1757 }
1758 pcir_offset = pci_get_word(ptr + 0x18);
1759 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1760 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1761 return;
1762 }
1763
1764 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1765 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1766 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1767 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1768
1769 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1770 vendor_id, device_id, rom_vendor_id, rom_device_id);
1771
1772 checksum = ptr[6];
1773
1774 if (vendor_id != rom_vendor_id) {
1775 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1776 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1777 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1778 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1779 ptr[6] = checksum;
1780 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1781 }
1782
1783 if (device_id != rom_device_id) {
1784 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1785 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1786 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1787 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1788 ptr[6] = checksum;
1789 pci_set_word(ptr + pcir_offset + 6, device_id);
1790 }
1791 }
1792
1793 /* Add an option rom for the device */
1794 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1795 {
1796 int size;
1797 char *path;
1798 void *ptr;
1799 char name[32];
1800
1801 if (!pdev->romfile)
1802 return 0;
1803 if (strlen(pdev->romfile) == 0)
1804 return 0;
1805
1806 if (!pdev->rom_bar) {
1807 /*
1808 * Load rom via fw_cfg instead of creating a rom bar,
1809 * for 0.11 compatibility.
1810 */
1811 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1812 if (class == 0x0300) {
1813 rom_add_vga(pdev->romfile);
1814 } else {
1815 rom_add_option(pdev->romfile);
1816 }
1817 return 0;
1818 }
1819
1820 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1821 if (path == NULL) {
1822 path = qemu_strdup(pdev->romfile);
1823 }
1824
1825 size = get_image_size(path);
1826 if (size < 0) {
1827 error_report("%s: failed to find romfile \"%s\"",
1828 __FUNCTION__, pdev->romfile);
1829 return -1;
1830 }
1831 if (size & (size - 1)) {
1832 size = 1 << qemu_fls(size);
1833 }
1834
1835 if (pdev->qdev.info->vmsd)
1836 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1837 else
1838 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1839 pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size);
1840
1841 ptr = qemu_get_ram_ptr(pdev->rom_offset);
1842 load_image(path, ptr);
1843 qemu_free(path);
1844
1845 if (is_default_rom) {
1846 /* Only the default rom images will be patched (if needed). */
1847 pci_patch_ids(pdev, ptr, size);
1848 }
1849
1850 pci_register_bar(pdev, PCI_ROM_SLOT, size,
1851 0, pci_map_option_rom);
1852
1853 return 0;
1854 }
1855
1856 static void pci_del_option_rom(PCIDevice *pdev)
1857 {
1858 if (!pdev->rom_offset)
1859 return;
1860
1861 qemu_ram_free(pdev->rom_offset);
1862 pdev->rom_offset = 0;
1863 }
1864
1865 /*
1866 * if !offset
1867 * Reserve space and add capability to the linked list in pci config space
1868 *
1869 * if offset = 0,
1870 * Find and reserve space and add capability to the linked list
1871 * in pci config space */
1872 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1873 uint8_t offset, uint8_t size)
1874 {
1875 uint8_t *config;
1876 if (!offset) {
1877 offset = pci_find_space(pdev, size);
1878 if (!offset) {
1879 return -ENOSPC;
1880 }
1881 }
1882
1883 config = pdev->config + offset;
1884 config[PCI_CAP_LIST_ID] = cap_id;
1885 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1886 pdev->config[PCI_CAPABILITY_LIST] = offset;
1887 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1888 memset(pdev->used + offset, 0xFF, size);
1889 /* Make capability read-only by default */
1890 memset(pdev->wmask + offset, 0, size);
1891 /* Check capability by default */
1892 memset(pdev->cmask + offset, 0xFF, size);
1893 return offset;
1894 }
1895
1896 /* Unlink capability from the pci config space. */
1897 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1898 {
1899 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1900 if (!offset)
1901 return;
1902 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1903 /* Make capability writeable again */
1904 memset(pdev->wmask + offset, 0xff, size);
1905 memset(pdev->w1cmask + offset, 0, size);
1906 /* Clear cmask as device-specific registers can't be checked */
1907 memset(pdev->cmask + offset, 0, size);
1908 memset(pdev->used + offset, 0, size);
1909
1910 if (!pdev->config[PCI_CAPABILITY_LIST])
1911 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1912 }
1913
1914 /* Reserve space for capability at a known offset (to call after load). */
1915 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1916 {
1917 memset(pdev->used + offset, 0xff, size);
1918 }
1919
1920 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1921 {
1922 return pci_find_capability_list(pdev, cap_id, NULL);
1923 }
1924
1925 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1926 {
1927 PCIDevice *d = (PCIDevice *)dev;
1928 const pci_class_desc *desc;
1929 char ctxt[64];
1930 PCIIORegion *r;
1931 int i, class;
1932
1933 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1934 desc = pci_class_descriptions;
1935 while (desc->desc && class != desc->class)
1936 desc++;
1937 if (desc->desc) {
1938 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1939 } else {
1940 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1941 }
1942
1943 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1944 "pci id %04x:%04x (sub %04x:%04x)\n",
1945 indent, "", ctxt, pci_bus_num(d->bus),
1946 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1947 pci_get_word(d->config + PCI_VENDOR_ID),
1948 pci_get_word(d->config + PCI_DEVICE_ID),
1949 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1950 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1951 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1952 r = &d->io_regions[i];
1953 if (!r->size)
1954 continue;
1955 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1956 " [0x%"FMT_PCIBUS"]\n",
1957 indent, "",
1958 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1959 r->addr, r->addr + r->size - 1);
1960 }
1961 }
1962
1963 static char *pcibus_get_dev_path(DeviceState *dev)
1964 {
1965 PCIDevice *d = (PCIDevice *)dev;
1966 char path[16];
1967
1968 snprintf(path, sizeof(path), "%04x:%02x:%02x.%x",
1969 pci_find_domain(d->bus), d->config[PCI_SECONDARY_BUS],
1970 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
1971
1972 return strdup(path);
1973 }
1974
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