pcie_host: expose address format
[qemu.git] / include / hw / pci / pcie_host.h
blobda0f2759f7d610895ca3f7890eee9951af895bf1
1 /*
2 * pcie_host.h
4 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #ifndef PCIE_HOST_H
22 #define PCIE_HOST_H
24 #include "hw/pci/pci_host.h"
25 #include "exec/memory.h"
27 #define TYPE_PCIE_HOST_BRIDGE "pcie-host-bridge"
28 #define PCIE_HOST_BRIDGE(obj) \
29 OBJECT_CHECK(PCIExpressHost, (obj), TYPE_PCIE_HOST_BRIDGE)
31 /* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
32 #define PCIE_BASE_ADDR_UNMAPPED ((hwaddr)-1ULL)
34 struct PCIExpressHost {
35 PCIHostState pci;
37 /* express part */
39 /* base address where MMCONFIG area is mapped. */
40 hwaddr base_addr;
42 /* the size of MMCONFIG area. It's host bridge dependent */
43 hwaddr size;
45 /* MMCONFIG mmio area */
46 MemoryRegion mmio;
49 int pcie_host_init(PCIExpressHost *e);
50 void pcie_host_mmcfg_unmap(PCIExpressHost *e);
51 void pcie_host_mmcfg_map(PCIExpressHost *e, hwaddr addr, uint32_t size);
52 void pcie_host_mmcfg_update(PCIExpressHost *e,
53 int enable,
54 hwaddr addr,
55 uint32_t size);
58 * PCI express ECAM (Enhanced Configuration Address Mapping) format.
59 * AKA mmcfg address
60 * bit 20 - 28: bus number
61 * bit 15 - 19: device number
62 * bit 12 - 14: function number
63 * bit 0 - 11: offset in configuration space of a given device
65 #define PCIE_MMCFG_SIZE_MAX (1ULL << 28)
66 #define PCIE_MMCFG_SIZE_MIN (1ULL << 20)
67 #define PCIE_MMCFG_BUS_BIT 20
68 #define PCIE_MMCFG_BUS_MASK 0x1ff
69 #define PCIE_MMCFG_DEVFN_BIT 12
70 #define PCIE_MMCFG_DEVFN_MASK 0xff
71 #define PCIE_MMCFG_CONFOFFSET_MASK 0xfff
72 #define PCIE_MMCFG_BUS(addr) (((addr) >> PCIE_MMCFG_BUS_BIT) & \
73 PCIE_MMCFG_BUS_MASK)
74 #define PCIE_MMCFG_DEVFN(addr) (((addr) >> PCIE_MMCFG_DEVFN_BIT) & \
75 PCIE_MMCFG_DEVFN_MASK)
76 #define PCIE_MMCFG_CONFOFFSET(addr) ((addr) & PCIE_MMCFG_CONFOFFSET_MASK)
78 #endif /* PCIE_HOST_H */