target/riscv/cpu.c

   1 /*
   2  * QEMU RISC-V CPU
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/qemu-print.h"
  22 #include "qemu/ctype.h"
  23 #include "qemu/log.h"
  24 #include "cpu.h"
  25 #include "internals.h"
  26 #include "exec/exec-all.h"
  27 #include "qapi/error.h"
  28 #include "qemu/error-report.h"
  29 #include "hw/qdev-properties.h"
  30 #include "migration/vmstate.h"
  31 #include "fpu/softfloat-helpers.h"
  32
  33 /* RISC-V CPU definitions */
  34
  35 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
  36
  37 const char * const riscv_int_regnames[] = {
  38   "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
  39   "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
  40   "x14/a4",  "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3",  "x20/s4",
  41   "x21/s5",  "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
  42   "x28/t3",  "x29/t4", "x30/t5", "x31/t6"
  43 };
  44
  45 const char * const riscv_int_regnamesh[] = {
  46   "x0h/zeroh", "x1h/rah",  "x2h/sph",   "x3h/gph",   "x4h/tph",  "x5h/t0h",
  47   "x6h/t1h",   "x7h/t2h",  "x8h/s0h",   "x9h/s1h",   "x10h/a0h", "x11h/a1h",
  48   "x12h/a2h",  "x13h/a3h", "x14h/a4h",  "x15h/a5h",  "x16h/a6h", "x17h/a7h",
  49   "x18h/s2h",  "x19h/s3h", "x20h/s4h",  "x21h/s5h",  "x22h/s6h", "x23h/s7h",
  50   "x24h/s8h",  "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h",
  51   "x30h/t5h",  "x31h/t6h"
  52 };
  53
  54 const char * const riscv_fpr_regnames[] = {
  55   "f0/ft0",   "f1/ft1",  "f2/ft2",   "f3/ft3",   "f4/ft4",  "f5/ft5",
  56   "f6/ft6",   "f7/ft7",  "f8/fs0",   "f9/fs1",   "f10/fa0", "f11/fa1",
  57   "f12/fa2",  "f13/fa3", "f14/fa4",  "f15/fa5",  "f16/fa6", "f17/fa7",
  58   "f18/fs2",  "f19/fs3", "f20/fs4",  "f21/fs5",  "f22/fs6", "f23/fs7",
  59   "f24/fs8",  "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
  60   "f30/ft10", "f31/ft11"
  61 };
  62
  63 static const char * const riscv_excp_names[] = {
  64     "misaligned_fetch",
  65     "fault_fetch",
  66     "illegal_instruction",
  67     "breakpoint",
  68     "misaligned_load",
  69     "fault_load",
  70     "misaligned_store",
  71     "fault_store",
  72     "user_ecall",
  73     "supervisor_ecall",
  74     "hypervisor_ecall",
  75     "machine_ecall",
  76     "exec_page_fault",
  77     "load_page_fault",
  78     "reserved",
  79     "store_page_fault",
  80     "reserved",
  81     "reserved",
  82     "reserved",
  83     "reserved",
  84     "guest_exec_page_fault",
  85     "guest_load_page_fault",
  86     "reserved",
  87     "guest_store_page_fault",
  88 };
  89
  90 static const char * const riscv_intr_names[] = {
  91     "u_software",
  92     "s_software",
  93     "vs_software",
  94     "m_software",
  95     "u_timer",
  96     "s_timer",
  97     "vs_timer",
  98     "m_timer",
  99     "u_external",
 100     "s_external",
 101     "vs_external",
 102     "m_external",
 103     "reserved",
 104     "reserved",
 105     "reserved",
 106     "reserved"
 107 };
 108
 109 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
 110 {
 111     if (async) {
 112         return (cause < ARRAY_SIZE(riscv_intr_names)) ?
 113                riscv_intr_names[cause] : "(unknown)";
 114     } else {
 115         return (cause < ARRAY_SIZE(riscv_excp_names)) ?
 116                riscv_excp_names[cause] : "(unknown)";
 117     }
 118 }
 119
 120 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
 121 {
 122     env->misa_mxl_max = env->misa_mxl = mxl;
 123     env->misa_ext_mask = env->misa_ext = ext;
 124 }
 125
 126 static void set_priv_version(CPURISCVState *env, int priv_ver)
 127 {
 128     env->priv_ver = priv_ver;
 129 }
 130
 131 static void set_vext_version(CPURISCVState *env, int vext_ver)
 132 {
 133     env->vext_ver = vext_ver;
 134 }
 135
 136 static void set_feature(CPURISCVState *env, int feature)
 137 {
 138     env->features |= (1ULL << feature);
 139 }
 140
 141 static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
 142 {
 143 #ifndef CONFIG_USER_ONLY
 144     env->resetvec = resetvec;
 145 #endif
 146 }
 147
 148 static void riscv_any_cpu_init(Object *obj)
 149 {
 150     CPURISCVState *env = &RISCV_CPU(obj)->env;
 151 #if defined(TARGET_RISCV32)
 152     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 153 #elif defined(TARGET_RISCV64)
 154     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 155 #endif
 156     set_priv_version(env, PRIV_VERSION_1_11_0);
 157 }
 158
 159 #if defined(TARGET_RISCV64)
 160 static void rv64_base_cpu_init(Object *obj)
 161 {
 162     CPURISCVState *env = &RISCV_CPU(obj)->env;
 163     /* We set this in the realise function */
 164     set_misa(env, MXL_RV64, 0);
 165 }
 166
 167 static void rv64_sifive_u_cpu_init(Object *obj)
 168 {
 169     CPURISCVState *env = &RISCV_CPU(obj)->env;
 170     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 171     set_priv_version(env, PRIV_VERSION_1_10_0);
 172 }
 173
 174 static void rv64_sifive_e_cpu_init(Object *obj)
 175 {
 176     CPURISCVState *env = &RISCV_CPU(obj)->env;
 177     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
 178     set_priv_version(env, PRIV_VERSION_1_10_0);
 179     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 180 }
 181
 182 static void rv128_base_cpu_init(Object *obj)
 183 {
 184     if (qemu_tcg_mttcg_enabled()) {
 185         /* Missing 128-bit aligned atomics */
 186         error_report("128-bit RISC-V currently does not work with Multi "
 187                      "Threaded TCG. Please use: -accel tcg,thread=single");
 188         exit(EXIT_FAILURE);
 189     }
 190     CPURISCVState *env = &RISCV_CPU(obj)->env;
 191     /* We set this in the realise function */
 192     set_misa(env, MXL_RV128, 0);
 193 }
 194 #else
 195 static void rv32_base_cpu_init(Object *obj)
 196 {
 197     CPURISCVState *env = &RISCV_CPU(obj)->env;
 198     /* We set this in the realise function */
 199     set_misa(env, MXL_RV32, 0);
 200 }
 201
 202 static void rv32_sifive_u_cpu_init(Object *obj)
 203 {
 204     CPURISCVState *env = &RISCV_CPU(obj)->env;
 205     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 206     set_priv_version(env, PRIV_VERSION_1_10_0);
 207 }
 208
 209 static void rv32_sifive_e_cpu_init(Object *obj)
 210 {
 211     CPURISCVState *env = &RISCV_CPU(obj)->env;
 212     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
 213     set_priv_version(env, PRIV_VERSION_1_10_0);
 214     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 215 }
 216
 217 static void rv32_ibex_cpu_init(Object *obj)
 218 {
 219     CPURISCVState *env = &RISCV_CPU(obj)->env;
 220     set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
 221     set_priv_version(env, PRIV_VERSION_1_10_0);
 222     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 223     qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
 224 }
 225
 226 static void rv32_imafcu_nommu_cpu_init(Object *obj)
 227 {
 228     CPURISCVState *env = &RISCV_CPU(obj)->env;
 229     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
 230     set_priv_version(env, PRIV_VERSION_1_10_0);
 231     set_resetvec(env, DEFAULT_RSTVEC);
 232     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 233 }
 234 #endif
 235
 236 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
 237 {
 238     ObjectClass *oc;
 239     char *typename;
 240     char **cpuname;
 241
 242     cpuname = g_strsplit(cpu_model, ",", 1);
 243     typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
 244     oc = object_class_by_name(typename);
 245     g_strfreev(cpuname);
 246     g_free(typename);
 247     if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
 248         object_class_is_abstract(oc)) {
 249         return NULL;
 250     }
 251     return oc;
 252 }
 253
 254 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 255 {
 256     RISCVCPU *cpu = RISCV_CPU(cs);
 257     CPURISCVState *env = &cpu->env;
 258     int i;
 259
 260 #if !defined(CONFIG_USER_ONLY)
 261     if (riscv_has_ext(env, RVH)) {
 262         qemu_fprintf(f, " %s %d\n", "V      =  ", riscv_cpu_virt_enabled(env));
 263     }
 264 #endif
 265     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
 266 #ifndef CONFIG_USER_ONLY
 267     {
 268         static const int dump_csrs[] = {
 269             CSR_MHARTID,
 270             CSR_MSTATUS,
 271             CSR_MSTATUSH,
 272             CSR_HSTATUS,
 273             CSR_VSSTATUS,
 274             CSR_MIP,
 275             CSR_MIE,
 276             CSR_MIDELEG,
 277             CSR_HIDELEG,
 278             CSR_MEDELEG,
 279             CSR_HEDELEG,
 280             CSR_MTVEC,
 281             CSR_STVEC,
 282             CSR_VSTVEC,
 283             CSR_MEPC,
 284             CSR_SEPC,
 285             CSR_VSEPC,
 286             CSR_MCAUSE,
 287             CSR_SCAUSE,
 288             CSR_VSCAUSE,
 289             CSR_MTVAL,
 290             CSR_STVAL,
 291             CSR_HTVAL,
 292             CSR_MTVAL2,
 293             CSR_MSCRATCH,
 294             CSR_SSCRATCH,
 295             CSR_SATP,
 296             CSR_MMTE,
 297             CSR_UPMBASE,
 298             CSR_UPMMASK,
 299             CSR_SPMBASE,
 300             CSR_SPMMASK,
 301             CSR_MPMBASE,
 302             CSR_MPMMASK,
 303         };
 304
 305         for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
 306             int csrno = dump_csrs[i];
 307             target_ulong val = 0;
 308             RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
 309
 310             /*
 311              * Rely on the smode, hmode, etc, predicates within csr.c
 312              * to do the filtering of the registers that are present.
 313              */
 314             if (res == RISCV_EXCP_NONE) {
 315                 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
 316                              csr_ops[csrno].name, val);
 317             }
 318         }
 319     }
 320 #endif
 321
 322     for (i = 0; i < 32; i++) {
 323         qemu_fprintf(f, " %-8s " TARGET_FMT_lx,
 324                      riscv_int_regnames[i], env->gpr[i]);
 325         if ((i & 3) == 3) {
 326             qemu_fprintf(f, "\n");
 327         }
 328     }
 329     if (flags & CPU_DUMP_FPU) {
 330         for (i = 0; i < 32; i++) {
 331             qemu_fprintf(f, " %-8s %016" PRIx64,
 332                          riscv_fpr_regnames[i], env->fpr[i]);
 333             if ((i & 3) == 3) {
 334                 qemu_fprintf(f, "\n");
 335             }
 336         }
 337     }
 338 }
 339
 340 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
 341 {
 342     RISCVCPU *cpu = RISCV_CPU(cs);
 343     CPURISCVState *env = &cpu->env;
 344     env->pc = value;
 345 }
 346
 347 static void riscv_cpu_synchronize_from_tb(CPUState *cs,
 348                                           const TranslationBlock *tb)
 349 {
 350     RISCVCPU *cpu = RISCV_CPU(cs);
 351     CPURISCVState *env = &cpu->env;
 352     env->pc = tb->pc;
 353 }
 354
 355 static bool riscv_cpu_has_work(CPUState *cs)
 356 {
 357 #ifndef CONFIG_USER_ONLY
 358     RISCVCPU *cpu = RISCV_CPU(cs);
 359     CPURISCVState *env = &cpu->env;
 360     /*
 361      * Definition of the WFI instruction requires it to ignore the privilege
 362      * mode and delegation registers, but respect individual enables
 363      */
 364     return (env->mip & env->mie) != 0;
 365 #else
 366     return true;
 367 #endif
 368 }
 369
 370 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
 371                           target_ulong *data)
 372 {
 373     env->pc = data[0];
 374 }
 375
 376 static void riscv_cpu_reset(DeviceState *dev)
 377 {
 378     CPUState *cs = CPU(dev);
 379     RISCVCPU *cpu = RISCV_CPU(cs);
 380     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
 381     CPURISCVState *env = &cpu->env;
 382
 383     mcc->parent_reset(dev);
 384 #ifndef CONFIG_USER_ONLY
 385     env->misa_mxl = env->misa_mxl_max;
 386     env->priv = PRV_M;
 387     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
 388     if (env->misa_mxl > MXL_RV32) {
 389         /*
 390          * The reset status of SXL/UXL is undefined, but mstatus is WARL
 391          * and we must ensure that the value after init is valid for read.
 392          */
 393         env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
 394         env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
 395     }
 396     env->mcause = 0;
 397     env->pc = env->resetvec;
 398     env->two_stage_lookup = false;
 399     /* mmte is supposed to have pm.current hardwired to 1 */
 400     env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT);
 401 #endif
 402     cs->exception_index = RISCV_EXCP_NONE;
 403     env->load_res = -1;
 404     set_default_nan_mode(1, &env->fp_status);
 405 }
 406
 407 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 408 {
 409     RISCVCPU *cpu = RISCV_CPU(s);
 410
 411     switch (riscv_cpu_mxl(&cpu->env)) {
 412     case MXL_RV32:
 413         info->print_insn = print_insn_riscv32;
 414         break;
 415     case MXL_RV64:
 416         info->print_insn = print_insn_riscv64;
 417         break;
 418     case MXL_RV128:
 419         info->print_insn = print_insn_riscv128;
 420         break;
 421     default:
 422         g_assert_not_reached();
 423     }
 424 }
 425
 426 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 427 {
 428     CPUState *cs = CPU(dev);
 429     RISCVCPU *cpu = RISCV_CPU(dev);
 430     CPURISCVState *env = &cpu->env;
 431     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
 432     int priv_version = 0;
 433     Error *local_err = NULL;
 434
 435     cpu_exec_realizefn(cs, &local_err);
 436     if (local_err != NULL) {
 437         error_propagate(errp, local_err);
 438         return;
 439     }
 440
 441     if (cpu->cfg.priv_spec) {
 442         if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
 443             priv_version = PRIV_VERSION_1_11_0;
 444         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
 445             priv_version = PRIV_VERSION_1_10_0;
 446         } else {
 447             error_setg(errp,
 448                        "Unsupported privilege spec version '%s'",
 449                        cpu->cfg.priv_spec);
 450             return;
 451         }
 452     }
 453
 454     if (priv_version) {
 455         set_priv_version(env, priv_version);
 456     } else if (!env->priv_ver) {
 457         set_priv_version(env, PRIV_VERSION_1_11_0);
 458     }
 459
 460     if (cpu->cfg.mmu) {
 461         set_feature(env, RISCV_FEATURE_MMU);
 462     }
 463
 464     if (cpu->cfg.pmp) {
 465         set_feature(env, RISCV_FEATURE_PMP);
 466
 467         /*
 468          * Enhanced PMP should only be available
 469          * on harts with PMP support
 470          */
 471         if (cpu->cfg.epmp) {
 472             set_feature(env, RISCV_FEATURE_EPMP);
 473         }
 474     }
 475
 476     set_resetvec(env, cpu->cfg.resetvec);
 477
 478     /* Validate that MISA_MXL is set properly. */
 479     switch (env->misa_mxl_max) {
 480 #ifdef TARGET_RISCV64
 481     case MXL_RV64:
 482         break;
 483     case MXL_RV128:
 484         break;
 485 #endif
 486     case MXL_RV32:
 487         break;
 488     default:
 489         g_assert_not_reached();
 490     }
 491     assert(env->misa_mxl_max == env->misa_mxl);
 492
 493     /* If only MISA_EXT is unset for misa, then set it from properties */
 494     if (env->misa_ext == 0) {
 495         uint32_t ext = 0;
 496
 497         /* Do some ISA extension error checking */
 498         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
 499             error_setg(errp,
 500                        "I and E extensions are incompatible");
 501                        return;
 502        }
 503
 504         if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
 505             error_setg(errp,
 506                        "Either I or E extension must be set");
 507                        return;
 508        }
 509
 510        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
 511                                cpu->cfg.ext_a & cpu->cfg.ext_f &
 512                                cpu->cfg.ext_d)) {
 513             warn_report("Setting G will also set IMAFD");
 514             cpu->cfg.ext_i = true;
 515             cpu->cfg.ext_m = true;
 516             cpu->cfg.ext_a = true;
 517             cpu->cfg.ext_f = true;
 518             cpu->cfg.ext_d = true;
 519         }
 520
 521         /* Set the ISA extensions, checks should have happened above */
 522         if (cpu->cfg.ext_i) {
 523             ext |= RVI;
 524         }
 525         if (cpu->cfg.ext_e) {
 526             ext |= RVE;
 527         }
 528         if (cpu->cfg.ext_m) {
 529             ext |= RVM;
 530         }
 531         if (cpu->cfg.ext_a) {
 532             ext |= RVA;
 533         }
 534         if (cpu->cfg.ext_f) {
 535             ext |= RVF;
 536         }
 537         if (cpu->cfg.ext_d) {
 538             ext |= RVD;
 539         }
 540         if (cpu->cfg.ext_c) {
 541             ext |= RVC;
 542         }
 543         if (cpu->cfg.ext_s) {
 544             ext |= RVS;
 545         }
 546         if (cpu->cfg.ext_u) {
 547             ext |= RVU;
 548         }
 549         if (cpu->cfg.ext_h) {
 550             ext |= RVH;
 551         }
 552         if (cpu->cfg.ext_v) {
 553             int vext_version = VEXT_VERSION_1_00_0;
 554             ext |= RVV;
 555             if (!is_power_of_2(cpu->cfg.vlen)) {
 556                 error_setg(errp,
 557                         "Vector extension VLEN must be power of 2");
 558                 return;
 559             }
 560             if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
 561                 error_setg(errp,
 562                         "Vector extension implementation only supports VLEN "
 563                         "in the range [128, %d]", RV_VLEN_MAX);
 564                 return;
 565             }
 566             if (!is_power_of_2(cpu->cfg.elen)) {
 567                 error_setg(errp,
 568                         "Vector extension ELEN must be power of 2");
 569                 return;
 570             }
 571             if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
 572                 error_setg(errp,
 573                         "Vector extension implementation only supports ELEN "
 574                         "in the range [8, 64]");
 575                 return;
 576             }
 577             if (cpu->cfg.vext_spec) {
 578                 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
 579                     vext_version = VEXT_VERSION_1_00_0;
 580                 } else {
 581                     error_setg(errp,
 582                            "Unsupported vector spec version '%s'",
 583                            cpu->cfg.vext_spec);
 584                     return;
 585                 }
 586             } else {
 587                 qemu_log("vector version is not specified, "
 588                          "use the default value v1.0\n");
 589             }
 590             set_vext_version(env, vext_version);
 591         }
 592         if (cpu->cfg.ext_j) {
 593             ext |= RVJ;
 594         }
 595
 596         set_misa(env, env->misa_mxl, ext);
 597     }
 598
 599     riscv_cpu_register_gdb_regs_for_features(cs);
 600
 601     qemu_init_vcpu(cs);
 602     cpu_reset(cs);
 603
 604     mcc->parent_realize(dev, errp);
 605 }
 606
 607 #ifndef CONFIG_USER_ONLY
 608 static void riscv_cpu_set_irq(void *opaque, int irq, int level)
 609 {
 610     RISCVCPU *cpu = RISCV_CPU(opaque);
 611
 612     switch (irq) {
 613     case IRQ_U_SOFT:
 614     case IRQ_S_SOFT:
 615     case IRQ_VS_SOFT:
 616     case IRQ_M_SOFT:
 617     case IRQ_U_TIMER:
 618     case IRQ_S_TIMER:
 619     case IRQ_VS_TIMER:
 620     case IRQ_M_TIMER:
 621     case IRQ_U_EXT:
 622     case IRQ_S_EXT:
 623     case IRQ_VS_EXT:
 624     case IRQ_M_EXT:
 625         riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
 626         break;
 627     default:
 628         g_assert_not_reached();
 629     }
 630 }
 631 #endif /* CONFIG_USER_ONLY */
 632
 633 static void riscv_cpu_init(Object *obj)
 634 {
 635     RISCVCPU *cpu = RISCV_CPU(obj);
 636
 637     cpu_set_cpustate_pointers(cpu);
 638
 639 #ifndef CONFIG_USER_ONLY
 640     qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12);
 641 #endif /* CONFIG_USER_ONLY */
 642 }
 643
 644 static Property riscv_cpu_properties[] = {
 645     /* Defaults for standard extensions */
 646     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
 647     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
 648     DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
 649     DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
 650     DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
 651     DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
 652     DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
 653     DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
 654     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
 655     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
 656     DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
 657     DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
 658     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
 659     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
 660     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
 661     DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
 662     DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
 663     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
 664     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
 665
 666     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
 667     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
 668     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
 669     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 670
 671     DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
 672     DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
 673     DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
 674     DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
 675
 676     /* These are experimental so mark with 'x-' */
 677     DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
 678     /* ePMP 0.9.3 */
 679     DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
 680
 681     DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
 682     DEFINE_PROP_END_OF_LIST(),
 683 };
 684
 685 static gchar *riscv_gdb_arch_name(CPUState *cs)
 686 {
 687     RISCVCPU *cpu = RISCV_CPU(cs);
 688     CPURISCVState *env = &cpu->env;
 689
 690     switch (riscv_cpu_mxl(env)) {
 691     case MXL_RV32:
 692         return g_strdup("riscv:rv32");
 693     case MXL_RV64:
 694     case MXL_RV128:
 695         return g_strdup("riscv:rv64");
 696     default:
 697         g_assert_not_reached();
 698     }
 699 }
 700
 701 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
 702 {
 703     RISCVCPU *cpu = RISCV_CPU(cs);
 704
 705     if (strcmp(xmlname, "riscv-csr.xml") == 0) {
 706         return cpu->dyn_csr_xml;
 707     } else if (strcmp(xmlname, "riscv-vector.xml") == 0) {
 708         return cpu->dyn_vreg_xml;
 709     }
 710
 711     return NULL;
 712 }
 713
 714 #ifndef CONFIG_USER_ONLY
 715 #include "hw/core/sysemu-cpu-ops.h"
 716
 717 static const struct SysemuCPUOps riscv_sysemu_ops = {
 718     .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
 719     .write_elf64_note = riscv_cpu_write_elf64_note,
 720     .write_elf32_note = riscv_cpu_write_elf32_note,
 721     .legacy_vmsd = &vmstate_riscv_cpu,
 722 };
 723 #endif
 724
 725 #include "hw/core/tcg-cpu-ops.h"
 726
 727 static const struct TCGCPUOps riscv_tcg_ops = {
 728     .initialize = riscv_translate_init,
 729     .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
 730
 731 #ifndef CONFIG_USER_ONLY
 732     .tlb_fill = riscv_cpu_tlb_fill,
 733     .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
 734     .do_interrupt = riscv_cpu_do_interrupt,
 735     .do_transaction_failed = riscv_cpu_do_transaction_failed,
 736     .do_unaligned_access = riscv_cpu_do_unaligned_access,
 737 #endif /* !CONFIG_USER_ONLY */
 738 };
 739
 740 static void riscv_cpu_class_init(ObjectClass *c, void *data)
 741 {
 742     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
 743     CPUClass *cc = CPU_CLASS(c);
 744     DeviceClass *dc = DEVICE_CLASS(c);
 745
 746     device_class_set_parent_realize(dc, riscv_cpu_realize,
 747                                     &mcc->parent_realize);
 748
 749     device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
 750
 751     cc->class_by_name = riscv_cpu_class_by_name;
 752     cc->has_work = riscv_cpu_has_work;
 753     cc->dump_state = riscv_cpu_dump_state;
 754     cc->set_pc = riscv_cpu_set_pc;
 755     cc->gdb_read_register = riscv_cpu_gdb_read_register;
 756     cc->gdb_write_register = riscv_cpu_gdb_write_register;
 757     cc->gdb_num_core_regs = 33;
 758 #if defined(TARGET_RISCV32)
 759     cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
 760 #elif defined(TARGET_RISCV64)
 761     cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
 762 #endif
 763     cc->gdb_stop_before_watchpoint = true;
 764     cc->disas_set_info = riscv_cpu_disas_set_info;
 765 #ifndef CONFIG_USER_ONLY
 766     cc->sysemu_ops = &riscv_sysemu_ops;
 767 #endif
 768     cc->gdb_arch_name = riscv_gdb_arch_name;
 769     cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
 770     cc->tcg_ops = &riscv_tcg_ops;
 771
 772     device_class_set_props(dc, riscv_cpu_properties);
 773 }
 774
 775 char *riscv_isa_string(RISCVCPU *cpu)
 776 {
 777     int i;
 778     const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
 779     char *isa_str = g_new(char, maxlen);
 780     char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
 781     for (i = 0; i < sizeof(riscv_exts); i++) {
 782         if (cpu->env.misa_ext & RV(riscv_exts[i])) {
 783             *p++ = qemu_tolower(riscv_exts[i]);
 784         }
 785     }
 786     *p = '\0';
 787     return isa_str;
 788 }
 789
 790 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
 791 {
 792     ObjectClass *class_a = (ObjectClass *)a;
 793     ObjectClass *class_b = (ObjectClass *)b;
 794     const char *name_a, *name_b;
 795
 796     name_a = object_class_get_name(class_a);
 797     name_b = object_class_get_name(class_b);
 798     return strcmp(name_a, name_b);
 799 }
 800
 801 static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
 802 {
 803     const char *typename = object_class_get_name(OBJECT_CLASS(data));
 804     int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
 805
 806     qemu_printf("%.*s\n", len, typename);
 807 }
 808
 809 void riscv_cpu_list(void)
 810 {
 811     GSList *list;
 812
 813     list = object_class_get_list(TYPE_RISCV_CPU, false);
 814     list = g_slist_sort(list, riscv_cpu_list_compare);
 815     g_slist_foreach(list, riscv_cpu_list_entry, NULL);
 816     g_slist_free(list);
 817 }
 818
 819 #define DEFINE_CPU(type_name, initfn)      \
 820     {                                      \
 821         .name = type_name,                 \
 822         .parent = TYPE_RISCV_CPU,          \
 823         .instance_init = initfn            \
 824     }
 825
 826 static const TypeInfo riscv_cpu_type_infos[] = {
 827     {
 828         .name = TYPE_RISCV_CPU,
 829         .parent = TYPE_CPU,
 830         .instance_size = sizeof(RISCVCPU),
 831         .instance_align = __alignof__(RISCVCPU),
 832         .instance_init = riscv_cpu_init,
 833         .abstract = true,
 834         .class_size = sizeof(RISCVCPUClass),
 835         .class_init = riscv_cpu_class_init,
 836     },
 837     DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
 838 #if defined(TARGET_RISCV32)
 839     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           rv32_base_cpu_init),
 840     DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
 841     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32_sifive_e_cpu_init),
 842     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32_imafcu_nommu_cpu_init),
 843     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32_sifive_u_cpu_init),
 844 #elif defined(TARGET_RISCV64)
 845     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           rv64_base_cpu_init),
 846     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
 847     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),
 848     DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C,         rv64_sifive_u_cpu_init),
 849     DEFINE_CPU(TYPE_RISCV_CPU_BASE128,          rv128_base_cpu_init),
 850 #endif
 851 };
 852
 853 DEFINE_TYPES(riscv_cpu_type_infos)