hw/vga.c

   1 /*
   2  * QEMU VGA Emulator.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "console.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "vga_int.h"
  29 #include "pixel_ops.h"
  30 #include "qemu-timer.h"
  31
  32 //#define DEBUG_VGA
  33 //#define DEBUG_VGA_MEM
  34 //#define DEBUG_VGA_REG
  35
  36 //#define DEBUG_BOCHS_VBE
  37
  38 /* force some bits to zero */
  39 const uint8_t sr_mask[8] = {
  40     0x03,
  41     0x3d,
  42     0x0f,
  43     0x3f,
  44     0x0e,
  45     0x00,
  46     0x00,
  47     0xff,
  48 };
  49
  50 const uint8_t gr_mask[16] = {
  51     0x0f, /* 0x00 */
  52     0x0f, /* 0x01 */
  53     0x0f, /* 0x02 */
  54     0x1f, /* 0x03 */
  55     0x03, /* 0x04 */
  56     0x7b, /* 0x05 */
  57     0x0f, /* 0x06 */
  58     0x0f, /* 0x07 */
  59     0xff, /* 0x08 */
  60     0x00, /* 0x09 */
  61     0x00, /* 0x0a */
  62     0x00, /* 0x0b */
  63     0x00, /* 0x0c */
  64     0x00, /* 0x0d */
  65     0x00, /* 0x0e */
  66     0x00, /* 0x0f */
  67 };
  68
  69 #define cbswap_32(__x) \
  70 ((uint32_t)( \
  71                 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
  72                 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) <<  8) | \
  73                 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >>  8) | \
  74                 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
  75
  76 #ifdef HOST_WORDS_BIGENDIAN
  77 #define PAT(x) cbswap_32(x)
  78 #else
  79 #define PAT(x) (x)
  80 #endif
  81
  82 #ifdef HOST_WORDS_BIGENDIAN
  83 #define BIG 1
  84 #else
  85 #define BIG 0
  86 #endif
  87
  88 #ifdef HOST_WORDS_BIGENDIAN
  89 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
  90 #else
  91 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
  92 #endif
  93
  94 static const uint32_t mask16[16] = {
  95     PAT(0x00000000),
  96     PAT(0x000000ff),
  97     PAT(0x0000ff00),
  98     PAT(0x0000ffff),
  99     PAT(0x00ff0000),
 100     PAT(0x00ff00ff),
 101     PAT(0x00ffff00),
 102     PAT(0x00ffffff),
 103     PAT(0xff000000),
 104     PAT(0xff0000ff),
 105     PAT(0xff00ff00),
 106     PAT(0xff00ffff),
 107     PAT(0xffff0000),
 108     PAT(0xffff00ff),
 109     PAT(0xffffff00),
 110     PAT(0xffffffff),
 111 };
 112
 113 #undef PAT
 114
 115 #ifdef HOST_WORDS_BIGENDIAN
 116 #define PAT(x) (x)
 117 #else
 118 #define PAT(x) cbswap_32(x)
 119 #endif
 120
 121 static const uint32_t dmask16[16] = {
 122     PAT(0x00000000),
 123     PAT(0x000000ff),
 124     PAT(0x0000ff00),
 125     PAT(0x0000ffff),
 126     PAT(0x00ff0000),
 127     PAT(0x00ff00ff),
 128     PAT(0x00ffff00),
 129     PAT(0x00ffffff),
 130     PAT(0xff000000),
 131     PAT(0xff0000ff),
 132     PAT(0xff00ff00),
 133     PAT(0xff00ffff),
 134     PAT(0xffff0000),
 135     PAT(0xffff00ff),
 136     PAT(0xffffff00),
 137     PAT(0xffffffff),
 138 };
 139
 140 static const uint32_t dmask4[4] = {
 141     PAT(0x00000000),
 142     PAT(0x0000ffff),
 143     PAT(0xffff0000),
 144     PAT(0xffffffff),
 145 };
 146
 147 static uint32_t expand4[256];
 148 static uint16_t expand2[256];
 149 static uint8_t expand4to8[16];
 150
 151 static void vga_screen_dump(void *opaque, const char *filename);
 152 static char *screen_dump_filename;
 153 static DisplayChangeListener *screen_dump_dcl;
 154
 155 static void vga_dumb_update_retrace_info(VGACommonState *s)
 156 {
 157     (void) s;
 158 }
 159
 160 static void vga_precise_update_retrace_info(VGACommonState *s)
 161 {
 162     int htotal_chars;
 163     int hretr_start_char;
 164     int hretr_skew_chars;
 165     int hretr_end_char;
 166
 167     int vtotal_lines;
 168     int vretr_start_line;
 169     int vretr_end_line;
 170
 171     int dots;
 172 #if 0
 173     int div2, sldiv2;
 174 #endif
 175     int clocking_mode;
 176     int clock_sel;
 177     const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
 178     int64_t chars_per_sec;
 179     struct vga_precise_retrace *r = &s->retrace_info.precise;
 180
 181     htotal_chars = s->cr[0x00] + 5;
 182     hretr_start_char = s->cr[0x04];
 183     hretr_skew_chars = (s->cr[0x05] >> 5) & 3;
 184     hretr_end_char = s->cr[0x05] & 0x1f;
 185
 186     vtotal_lines = (s->cr[0x06]
 187                     | (((s->cr[0x07] & 1) | ((s->cr[0x07] >> 4) & 2)) << 8)) + 2
 188         ;
 189     vretr_start_line = s->cr[0x10]
 190         | ((((s->cr[0x07] >> 2) & 1) | ((s->cr[0x07] >> 6) & 2)) << 8)
 191         ;
 192     vretr_end_line = s->cr[0x11] & 0xf;
 193
 194
 195
 196     clocking_mode = (s->sr[0x01] >> 3) & 1;
 197     clock_sel = (s->msr >> 2) & 3;
 198     dots = (s->msr & 1) ? 8 : 9;
 199
 200     chars_per_sec = clk_hz[clock_sel] / dots;
 201
 202     htotal_chars <<= clocking_mode;
 203
 204     r->total_chars = vtotal_lines * htotal_chars;
 205     if (r->freq) {
 206         r->ticks_per_char = get_ticks_per_sec() / (r->total_chars * r->freq);
 207     } else {
 208         r->ticks_per_char = get_ticks_per_sec() / chars_per_sec;
 209     }
 210
 211     r->vstart = vretr_start_line;
 212     r->vend = r->vstart + vretr_end_line + 1;
 213
 214     r->hstart = hretr_start_char + hretr_skew_chars;
 215     r->hend = r->hstart + hretr_end_char + 1;
 216     r->htotal = htotal_chars;
 217
 218 #if 0
 219     div2 = (s->cr[0x17] >> 2) & 1;
 220     sldiv2 = (s->cr[0x17] >> 3) & 1;
 221     printf (
 222         "hz=%f\n"
 223         "htotal = %d\n"
 224         "hretr_start = %d\n"
 225         "hretr_skew = %d\n"
 226         "hretr_end = %d\n"
 227         "vtotal = %d\n"
 228         "vretr_start = %d\n"
 229         "vretr_end = %d\n"
 230         "div2 = %d sldiv2 = %d\n"
 231         "clocking_mode = %d\n"
 232         "clock_sel = %d %d\n"
 233         "dots = %d\n"
 234         "ticks/char = %" PRId64 "\n"
 235         "\n",
 236         (double) get_ticks_per_sec() / (r->ticks_per_char * r->total_chars),
 237         htotal_chars,
 238         hretr_start_char,
 239         hretr_skew_chars,
 240         hretr_end_char,
 241         vtotal_lines,
 242         vretr_start_line,
 243         vretr_end_line,
 244         div2, sldiv2,
 245         clocking_mode,
 246         clock_sel,
 247         clk_hz[clock_sel],
 248         dots,
 249         r->ticks_per_char
 250         );
 251 #endif
 252 }
 253
 254 static uint8_t vga_precise_retrace(VGACommonState *s)
 255 {
 256     struct vga_precise_retrace *r = &s->retrace_info.precise;
 257     uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
 258
 259     if (r->total_chars) {
 260         int cur_line, cur_line_char, cur_char;
 261         int64_t cur_tick;
 262
 263         cur_tick = qemu_get_clock_ns(vm_clock);
 264
 265         cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
 266         cur_line = cur_char / r->htotal;
 267
 268         if (cur_line >= r->vstart && cur_line <= r->vend) {
 269             val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
 270         } else {
 271             cur_line_char = cur_char % r->htotal;
 272             if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
 273                 val |= ST01_DISP_ENABLE;
 274             }
 275         }
 276
 277         return val;
 278     } else {
 279         return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
 280     }
 281 }
 282
 283 static uint8_t vga_dumb_retrace(VGACommonState *s)
 284 {
 285     return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
 286 }
 287
 288 int vga_ioport_invalid(VGACommonState *s, uint32_t addr)
 289 {
 290     if (s->msr & MSR_COLOR_EMULATION) {
 291         /* Color */
 292         return (addr >= 0x3b0 && addr <= 0x3bf);
 293     } else {
 294         /* Monochrome */
 295         return (addr >= 0x3d0 && addr <= 0x3df);
 296     }
 297 }
 298
 299 uint32_t vga_ioport_read(void *opaque, uint32_t addr)
 300 {
 301     VGACommonState *s = opaque;
 302     int val, index;
 303
 304     if (vga_ioport_invalid(s, addr)) {
 305         val = 0xff;
 306     } else {
 307         switch(addr) {
 308         case 0x3c0:
 309             if (s->ar_flip_flop == 0) {
 310                 val = s->ar_index;
 311             } else {
 312                 val = 0;
 313             }
 314             break;
 315         case 0x3c1:
 316             index = s->ar_index & 0x1f;
 317             if (index < 21)
 318                 val = s->ar[index];
 319             else
 320                 val = 0;
 321             break;
 322         case 0x3c2:
 323             val = s->st00;
 324             break;
 325         case 0x3c4:
 326             val = s->sr_index;
 327             break;
 328         case 0x3c5:
 329             val = s->sr[s->sr_index];
 330 #ifdef DEBUG_VGA_REG
 331             printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
 332 #endif
 333             break;
 334         case 0x3c7:
 335             val = s->dac_state;
 336             break;
 337         case 0x3c8:
 338             val = s->dac_write_index;
 339             break;
 340         case 0x3c9:
 341             val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
 342             if (++s->dac_sub_index == 3) {
 343                 s->dac_sub_index = 0;
 344                 s->dac_read_index++;
 345             }
 346             break;
 347         case 0x3ca:
 348             val = s->fcr;
 349             break;
 350         case 0x3cc:
 351             val = s->msr;
 352             break;
 353         case 0x3ce:
 354             val = s->gr_index;
 355             break;
 356         case 0x3cf:
 357             val = s->gr[s->gr_index];
 358 #ifdef DEBUG_VGA_REG
 359             printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
 360 #endif
 361             break;
 362         case 0x3b4:
 363         case 0x3d4:
 364             val = s->cr_index;
 365             break;
 366         case 0x3b5:
 367         case 0x3d5:
 368             val = s->cr[s->cr_index];
 369 #ifdef DEBUG_VGA_REG
 370             printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
 371 #endif
 372             break;
 373         case 0x3ba:
 374         case 0x3da:
 375             /* just toggle to fool polling */
 376             val = s->st01 = s->retrace(s);
 377             s->ar_flip_flop = 0;
 378             break;
 379         default:
 380             val = 0x00;
 381             break;
 382         }
 383     }
 384 #if defined(DEBUG_VGA)
 385     printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
 386 #endif
 387     return val;
 388 }
 389
 390 void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 391 {
 392     VGACommonState *s = opaque;
 393     int index;
 394
 395     /* check port range access depending on color/monochrome mode */
 396     if (vga_ioport_invalid(s, addr)) {
 397         return;
 398     }
 399 #ifdef DEBUG_VGA
 400     printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
 401 #endif
 402
 403     switch(addr) {
 404     case 0x3c0:
 405         if (s->ar_flip_flop == 0) {
 406             val &= 0x3f;
 407             s->ar_index = val;
 408         } else {
 409             index = s->ar_index & 0x1f;
 410             switch(index) {
 411             case 0x00 ... 0x0f:
 412                 s->ar[index] = val & 0x3f;
 413                 break;
 414             case 0x10:
 415                 s->ar[index] = val & ~0x10;
 416                 break;
 417             case 0x11:
 418                 s->ar[index] = val;
 419                 break;
 420             case 0x12:
 421                 s->ar[index] = val & ~0xc0;
 422                 break;
 423             case 0x13:
 424                 s->ar[index] = val & ~0xf0;
 425                 break;
 426             case 0x14:
 427                 s->ar[index] = val & ~0xf0;
 428                 break;
 429             default:
 430                 break;
 431             }
 432         }
 433         s->ar_flip_flop ^= 1;
 434         break;
 435     case 0x3c2:
 436         s->msr = val & ~0x10;
 437         s->update_retrace_info(s);
 438         break;
 439     case 0x3c4:
 440         s->sr_index = val & 7;
 441         break;
 442     case 0x3c5:
 443 #ifdef DEBUG_VGA_REG
 444         printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
 445 #endif
 446         s->sr[s->sr_index] = val & sr_mask[s->sr_index];
 447         if (s->sr_index == 1) s->update_retrace_info(s);
 448         break;
 449     case 0x3c7:
 450         s->dac_read_index = val;
 451         s->dac_sub_index = 0;
 452         s->dac_state = 3;
 453         break;
 454     case 0x3c8:
 455         s->dac_write_index = val;
 456         s->dac_sub_index = 0;
 457         s->dac_state = 0;
 458         break;
 459     case 0x3c9:
 460         s->dac_cache[s->dac_sub_index] = val;
 461         if (++s->dac_sub_index == 3) {
 462             memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
 463             s->dac_sub_index = 0;
 464             s->dac_write_index++;
 465         }
 466         break;
 467     case 0x3ce:
 468         s->gr_index = val & 0x0f;
 469         break;
 470     case 0x3cf:
 471 #ifdef DEBUG_VGA_REG
 472         printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
 473 #endif
 474         s->gr[s->gr_index] = val & gr_mask[s->gr_index];
 475         break;
 476     case 0x3b4:
 477     case 0x3d4:
 478         s->cr_index = val;
 479         break;
 480     case 0x3b5:
 481     case 0x3d5:
 482 #ifdef DEBUG_VGA_REG
 483         printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
 484 #endif
 485         /* handle CR0-7 protection */
 486         if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
 487             /* can always write bit 4 of CR7 */
 488             if (s->cr_index == 7)
 489                 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
 490             return;
 491         }
 492         s->cr[s->cr_index] = val;
 493
 494         switch(s->cr_index) {
 495         case 0x00:
 496         case 0x04:
 497         case 0x05:
 498         case 0x06:
 499         case 0x07:
 500         case 0x11:
 501         case 0x17:
 502             s->update_retrace_info(s);
 503             break;
 504         }
 505         break;
 506     case 0x3ba:
 507     case 0x3da:
 508         s->fcr = val & 0x10;
 509         break;
 510     }
 511 }
 512
 513 #ifdef CONFIG_BOCHS_VBE
 514 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
 515 {
 516     VGACommonState *s = opaque;
 517     uint32_t val;
 518     val = s->vbe_index;
 519     return val;
 520 }
 521
 522 static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
 523 {
 524     VGACommonState *s = opaque;
 525     uint32_t val;
 526
 527     if (s->vbe_index < VBE_DISPI_INDEX_NB) {
 528         if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
 529             switch(s->vbe_index) {
 530                 /* XXX: do not hardcode ? */
 531             case VBE_DISPI_INDEX_XRES:
 532                 val = VBE_DISPI_MAX_XRES;
 533                 break;
 534             case VBE_DISPI_INDEX_YRES:
 535                 val = VBE_DISPI_MAX_YRES;
 536                 break;
 537             case VBE_DISPI_INDEX_BPP:
 538                 val = VBE_DISPI_MAX_BPP;
 539                 break;
 540             default:
 541                 val = s->vbe_regs[s->vbe_index];
 542                 break;
 543             }
 544         } else {
 545             val = s->vbe_regs[s->vbe_index];
 546         }
 547     } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
 548         val = s->vram_size / (64 * 1024);
 549     } else {
 550         val = 0;
 551     }
 552 #ifdef DEBUG_BOCHS_VBE
 553     printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
 554 #endif
 555     return val;
 556 }
 557
 558 static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
 559 {
 560     VGACommonState *s = opaque;
 561     s->vbe_index = val;
 562 }
 563
 564 static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
 565 {
 566     VGACommonState *s = opaque;
 567
 568     if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
 569 #ifdef DEBUG_BOCHS_VBE
 570         printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
 571 #endif
 572         switch(s->vbe_index) {
 573         case VBE_DISPI_INDEX_ID:
 574             if (val == VBE_DISPI_ID0 ||
 575                 val == VBE_DISPI_ID1 ||
 576                 val == VBE_DISPI_ID2 ||
 577                 val == VBE_DISPI_ID3 ||
 578                 val == VBE_DISPI_ID4) {
 579                 s->vbe_regs[s->vbe_index] = val;
 580             }
 581             break;
 582         case VBE_DISPI_INDEX_XRES:
 583             if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
 584                 s->vbe_regs[s->vbe_index] = val;
 585             }
 586             break;
 587         case VBE_DISPI_INDEX_YRES:
 588             if (val <= VBE_DISPI_MAX_YRES) {
 589                 s->vbe_regs[s->vbe_index] = val;
 590             }
 591             break;
 592         case VBE_DISPI_INDEX_BPP:
 593             if (val == 0)
 594                 val = 8;
 595             if (val == 4 || val == 8 || val == 15 ||
 596                 val == 16 || val == 24 || val == 32) {
 597                 s->vbe_regs[s->vbe_index] = val;
 598             }
 599             break;
 600         case VBE_DISPI_INDEX_BANK:
 601             if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
 602               val &= (s->vbe_bank_mask >> 2);
 603             } else {
 604               val &= s->vbe_bank_mask;
 605             }
 606             s->vbe_regs[s->vbe_index] = val;
 607             s->bank_offset = (val << 16);
 608             break;
 609         case VBE_DISPI_INDEX_ENABLE:
 610             if ((val & VBE_DISPI_ENABLED) &&
 611                 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
 612                 int h, shift_control;
 613
 614                 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
 615                     s->vbe_regs[VBE_DISPI_INDEX_XRES];
 616                 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
 617                     s->vbe_regs[VBE_DISPI_INDEX_YRES];
 618                 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
 619                 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
 620
 621                 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
 622                     s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
 623                 else
 624                     s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
 625                         ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
 626                 s->vbe_start_addr = 0;
 627
 628                 /* clear the screen (should be done in BIOS) */
 629                 if (!(val & VBE_DISPI_NOCLEARMEM)) {
 630                     memset(s->vram_ptr, 0,
 631                            s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
 632                 }
 633
 634                 /* we initialize the VGA graphic mode (should be done
 635                    in BIOS) */
 636                 s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */
 637                 s->cr[0x17] |= 3; /* no CGA modes */
 638                 s->cr[0x13] = s->vbe_line_offset >> 3;
 639                 /* width */
 640                 s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
 641                 /* height (only meaningful if < 1024) */
 642                 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
 643                 s->cr[0x12] = h;
 644                 s->cr[0x07] = (s->cr[0x07] & ~0x42) |
 645                     ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
 646                 /* line compare to 1023 */
 647                 s->cr[0x18] = 0xff;
 648                 s->cr[0x07] |= 0x10;
 649                 s->cr[0x09] |= 0x40;
 650
 651                 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
 652                     shift_control = 0;
 653                     s->sr[0x01] &= ~8; /* no double line */
 654                 } else {
 655                     shift_control = 2;
 656                     s->sr[4] |= 0x08; /* set chain 4 mode */
 657                     s->sr[2] |= 0x0f; /* activate all planes */
 658                 }
 659                 s->gr[0x05] = (s->gr[0x05] & ~0x60) | (shift_control << 5);
 660                 s->cr[0x09] &= ~0x9f; /* no double scan */
 661             } else {
 662                 /* XXX: the bios should do that */
 663                 s->bank_offset = 0;
 664             }
 665             s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
 666             s->vbe_regs[s->vbe_index] = val;
 667             break;
 668         case VBE_DISPI_INDEX_VIRT_WIDTH:
 669             {
 670                 int w, h, line_offset;
 671
 672                 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
 673                     return;
 674                 w = val;
 675                 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
 676                     line_offset = w >> 1;
 677                 else
 678                     line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
 679                 h = s->vram_size / line_offset;
 680                 /* XXX: support weird bochs semantics ? */
 681                 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
 682                     return;
 683                 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
 684                 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
 685                 s->vbe_line_offset = line_offset;
 686             }
 687             break;
 688         case VBE_DISPI_INDEX_X_OFFSET:
 689         case VBE_DISPI_INDEX_Y_OFFSET:
 690             {
 691                 int x;
 692                 s->vbe_regs[s->vbe_index] = val;
 693                 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
 694                 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
 695                 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
 696                     s->vbe_start_addr += x >> 1;
 697                 else
 698                     s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
 699                 s->vbe_start_addr >>= 2;
 700             }
 701             break;
 702         default:
 703             break;
 704         }
 705     }
 706 }
 707 #endif
 708
 709 /* called for accesses between 0xa0000 and 0xc0000 */
 710 uint32_t vga_mem_readb(VGACommonState *s, target_phys_addr_t addr)
 711 {
 712     int memory_map_mode, plane;
 713     uint32_t ret;
 714
 715     /* convert to VGA memory offset */
 716     memory_map_mode = (s->gr[6] >> 2) & 3;
 717     addr &= 0x1ffff;
 718     switch(memory_map_mode) {
 719     case 0:
 720         break;
 721     case 1:
 722         if (addr >= 0x10000)
 723             return 0xff;
 724         addr += s->bank_offset;
 725         break;
 726     case 2:
 727         addr -= 0x10000;
 728         if (addr >= 0x8000)
 729             return 0xff;
 730         break;
 731     default:
 732     case 3:
 733         addr -= 0x18000;
 734         if (addr >= 0x8000)
 735             return 0xff;
 736         break;
 737     }
 738
 739     if (s->sr[4] & 0x08) {
 740         /* chain 4 mode : simplest access */
 741         ret = s->vram_ptr[addr];
 742     } else if (s->gr[5] & 0x10) {
 743         /* odd/even mode (aka text mode mapping) */
 744         plane = (s->gr[4] & 2) | (addr & 1);
 745         ret = s->vram_ptr[((addr & ~1) << 1) | plane];
 746     } else {
 747         /* standard VGA latched access */
 748         s->latch = ((uint32_t *)s->vram_ptr)[addr];
 749
 750         if (!(s->gr[5] & 0x08)) {
 751             /* read mode 0 */
 752             plane = s->gr[4];
 753             ret = GET_PLANE(s->latch, plane);
 754         } else {
 755             /* read mode 1 */
 756             ret = (s->latch ^ mask16[s->gr[2]]) & mask16[s->gr[7]];
 757             ret |= ret >> 16;
 758             ret |= ret >> 8;
 759             ret = (~ret) & 0xff;
 760         }
 761     }
 762     return ret;
 763 }
 764
 765 /* called for accesses between 0xa0000 and 0xc0000 */
 766 void vga_mem_writeb(VGACommonState *s, target_phys_addr_t addr, uint32_t val)
 767 {
 768     int memory_map_mode, plane, write_mode, b, func_select, mask;
 769     uint32_t write_mask, bit_mask, set_mask;
 770
 771 #ifdef DEBUG_VGA_MEM
 772     printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);
 773 #endif
 774     /* convert to VGA memory offset */
 775     memory_map_mode = (s->gr[6] >> 2) & 3;
 776     addr &= 0x1ffff;
 777     switch(memory_map_mode) {
 778     case 0:
 779         break;
 780     case 1:
 781         if (addr >= 0x10000)
 782             return;
 783         addr += s->bank_offset;
 784         break;
 785     case 2:
 786         addr -= 0x10000;
 787         if (addr >= 0x8000)
 788             return;
 789         break;
 790     default:
 791     case 3:
 792         addr -= 0x18000;
 793         if (addr >= 0x8000)
 794             return;
 795         break;
 796     }
 797
 798     if (s->sr[4] & 0x08) {
 799         /* chain 4 mode : simplest access */
 800         plane = addr & 3;
 801         mask = (1 << plane);
 802         if (s->sr[2] & mask) {
 803             s->vram_ptr[addr] = val;
 804 #ifdef DEBUG_VGA_MEM
 805             printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);
 806 #endif
 807             s->plane_updated |= mask; /* only used to detect font change */
 808             memory_region_set_dirty(&s->vram, addr);
 809         }
 810     } else if (s->gr[5] & 0x10) {
 811         /* odd/even mode (aka text mode mapping) */
 812         plane = (s->gr[4] & 2) | (addr & 1);
 813         mask = (1 << plane);
 814         if (s->sr[2] & mask) {
 815             addr = ((addr & ~1) << 1) | plane;
 816             s->vram_ptr[addr] = val;
 817 #ifdef DEBUG_VGA_MEM
 818             printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);
 819 #endif
 820             s->plane_updated |= mask; /* only used to detect font change */
 821             memory_region_set_dirty(&s->vram, addr);
 822         }
 823     } else {
 824         /* standard VGA latched access */
 825         write_mode = s->gr[5] & 3;
 826         switch(write_mode) {
 827         default:
 828         case 0:
 829             /* rotate */
 830             b = s->gr[3] & 7;
 831             val = ((val >> b) | (val << (8 - b))) & 0xff;
 832             val |= val << 8;
 833             val |= val << 16;
 834
 835             /* apply set/reset mask */
 836             set_mask = mask16[s->gr[1]];
 837             val = (val & ~set_mask) | (mask16[s->gr[0]] & set_mask);
 838             bit_mask = s->gr[8];
 839             break;
 840         case 1:
 841             val = s->latch;
 842             goto do_write;
 843         case 2:
 844             val = mask16[val & 0x0f];
 845             bit_mask = s->gr[8];
 846             break;
 847         case 3:
 848             /* rotate */
 849             b = s->gr[3] & 7;
 850             val = (val >> b) | (val << (8 - b));
 851
 852             bit_mask = s->gr[8] & val;
 853             val = mask16[s->gr[0]];
 854             break;
 855         }
 856
 857         /* apply logical operation */
 858         func_select = s->gr[3] >> 3;
 859         switch(func_select) {
 860         case 0:
 861         default:
 862             /* nothing to do */
 863             break;
 864         case 1:
 865             /* and */
 866             val &= s->latch;
 867             break;
 868         case 2:
 869             /* or */
 870             val |= s->latch;
 871             break;
 872         case 3:
 873             /* xor */
 874             val ^= s->latch;
 875             break;
 876         }
 877
 878         /* apply bit mask */
 879         bit_mask |= bit_mask << 8;
 880         bit_mask |= bit_mask << 16;
 881         val = (val & bit_mask) | (s->latch & ~bit_mask);
 882
 883     do_write:
 884         /* mask data according to sr[2] */
 885         mask = s->sr[2];
 886         s->plane_updated |= mask; /* only used to detect font change */
 887         write_mask = mask16[mask];
 888         ((uint32_t *)s->vram_ptr)[addr] =
 889             (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
 890             (val & write_mask);
 891 #ifdef DEBUG_VGA_MEM
 892         printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",
 893                addr * 4, write_mask, val);
 894 #endif
 895         memory_region_set_dirty(&s->vram, addr << 2);
 896     }
 897 }
 898
 899 typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
 900                              const uint8_t *font_ptr, int h,
 901                              uint32_t fgcol, uint32_t bgcol);
 902 typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
 903                                   const uint8_t *font_ptr, int h,
 904                                   uint32_t fgcol, uint32_t bgcol, int dup9);
 905 typedef void vga_draw_line_func(VGACommonState *s1, uint8_t *d,
 906                                 const uint8_t *s, int width);
 907
 908 #define DEPTH 8
 909 #include "vga_template.h"
 910
 911 #define DEPTH 15
 912 #include "vga_template.h"
 913
 914 #define BGR_FORMAT
 915 #define DEPTH 15
 916 #include "vga_template.h"
 917
 918 #define DEPTH 16
 919 #include "vga_template.h"
 920
 921 #define BGR_FORMAT
 922 #define DEPTH 16
 923 #include "vga_template.h"
 924
 925 #define DEPTH 32
 926 #include "vga_template.h"
 927
 928 #define BGR_FORMAT
 929 #define DEPTH 32
 930 #include "vga_template.h"
 931
 932 static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
 933 {
 934     unsigned int col;
 935     col = rgb_to_pixel8(r, g, b);
 936     col |= col << 8;
 937     col |= col << 16;
 938     return col;
 939 }
 940
 941 static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
 942 {
 943     unsigned int col;
 944     col = rgb_to_pixel15(r, g, b);
 945     col |= col << 16;
 946     return col;
 947 }
 948
 949 static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g,
 950                                           unsigned int b)
 951 {
 952     unsigned int col;
 953     col = rgb_to_pixel15bgr(r, g, b);
 954     col |= col << 16;
 955     return col;
 956 }
 957
 958 static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
 959 {
 960     unsigned int col;
 961     col = rgb_to_pixel16(r, g, b);
 962     col |= col << 16;
 963     return col;
 964 }
 965
 966 static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g,
 967                                           unsigned int b)
 968 {
 969     unsigned int col;
 970     col = rgb_to_pixel16bgr(r, g, b);
 971     col |= col << 16;
 972     return col;
 973 }
 974
 975 static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
 976 {
 977     unsigned int col;
 978     col = rgb_to_pixel32(r, g, b);
 979     return col;
 980 }
 981
 982 static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
 983 {
 984     unsigned int col;
 985     col = rgb_to_pixel32bgr(r, g, b);
 986     return col;
 987 }
 988
 989 /* return true if the palette was modified */
 990 static int update_palette16(VGACommonState *s)
 991 {
 992     int full_update, i;
 993     uint32_t v, col, *palette;
 994
 995     full_update = 0;
 996     palette = s->last_palette;
 997     for(i = 0; i < 16; i++) {
 998         v = s->ar[i];
 999         if (s->ar[0x10] & 0x80)
1000             v = ((s->ar[0x14] & 0xf) << 4) | (v & 0xf);
1001         else
1002             v = ((s->ar[0x14] & 0xc) << 4) | (v & 0x3f);
1003         v = v * 3;
1004         col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1005                               c6_to_8(s->palette[v + 1]),
1006                               c6_to_8(s->palette[v + 2]));
1007         if (col != palette[i]) {
1008             full_update = 1;
1009             palette[i] = col;
1010         }
1011     }
1012     return full_update;
1013 }
1014
1015 /* return true if the palette was modified */
1016 static int update_palette256(VGACommonState *s)
1017 {
1018     int full_update, i;
1019     uint32_t v, col, *palette;
1020
1021     full_update = 0;
1022     palette = s->last_palette;
1023     v = 0;
1024     for(i = 0; i < 256; i++) {
1025         if (s->dac_8bit) {
1026           col = s->rgb_to_pixel(s->palette[v],
1027                                 s->palette[v + 1],
1028                                 s->palette[v + 2]);
1029         } else {
1030           col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1031                                 c6_to_8(s->palette[v + 1]),
1032                                 c6_to_8(s->palette[v + 2]));
1033         }
1034         if (col != palette[i]) {
1035             full_update = 1;
1036             palette[i] = col;
1037         }
1038         v += 3;
1039     }
1040     return full_update;
1041 }
1042
1043 static void vga_get_offsets(VGACommonState *s,
1044                             uint32_t *pline_offset,
1045                             uint32_t *pstart_addr,
1046                             uint32_t *pline_compare)
1047 {
1048     uint32_t start_addr, line_offset, line_compare;
1049 #ifdef CONFIG_BOCHS_VBE
1050     if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1051         line_offset = s->vbe_line_offset;
1052         start_addr = s->vbe_start_addr;
1053         line_compare = 65535;
1054     } else
1055 #endif
1056     {
1057         /* compute line_offset in bytes */
1058         line_offset = s->cr[0x13];
1059         line_offset <<= 3;
1060
1061         /* starting address */
1062         start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
1063
1064         /* line compare */
1065         line_compare = s->cr[0x18] |
1066             ((s->cr[0x07] & 0x10) << 4) |
1067             ((s->cr[0x09] & 0x40) << 3);
1068     }
1069     *pline_offset = line_offset;
1070     *pstart_addr = start_addr;
1071     *pline_compare = line_compare;
1072 }
1073
1074 /* update start_addr and line_offset. Return TRUE if modified */
1075 static int update_basic_params(VGACommonState *s)
1076 {
1077     int full_update;
1078     uint32_t start_addr, line_offset, line_compare;
1079
1080     full_update = 0;
1081
1082     s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1083
1084     if (line_offset != s->line_offset ||
1085         start_addr != s->start_addr ||
1086         line_compare != s->line_compare) {
1087         s->line_offset = line_offset;
1088         s->start_addr = start_addr;
1089         s->line_compare = line_compare;
1090         full_update = 1;
1091     }
1092     return full_update;
1093 }
1094
1095 #define NB_DEPTHS 7
1096
1097 static inline int get_depth_index(DisplayState *s)
1098 {
1099     switch(ds_get_bits_per_pixel(s)) {
1100     default:
1101     case 8:
1102         return 0;
1103     case 15:
1104         return 1;
1105     case 16:
1106         return 2;
1107     case 32:
1108         if (is_surface_bgr(s->surface))
1109             return 4;
1110         else
1111             return 3;
1112     }
1113 }
1114
1115 static vga_draw_glyph8_func * const vga_draw_glyph8_table[NB_DEPTHS] = {
1116     vga_draw_glyph8_8,
1117     vga_draw_glyph8_16,
1118     vga_draw_glyph8_16,
1119     vga_draw_glyph8_32,
1120     vga_draw_glyph8_32,
1121     vga_draw_glyph8_16,
1122     vga_draw_glyph8_16,
1123 };
1124
1125 static vga_draw_glyph8_func * const vga_draw_glyph16_table[NB_DEPTHS] = {
1126     vga_draw_glyph16_8,
1127     vga_draw_glyph16_16,
1128     vga_draw_glyph16_16,
1129     vga_draw_glyph16_32,
1130     vga_draw_glyph16_32,
1131     vga_draw_glyph16_16,
1132     vga_draw_glyph16_16,
1133 };
1134
1135 static vga_draw_glyph9_func * const vga_draw_glyph9_table[NB_DEPTHS] = {
1136     vga_draw_glyph9_8,
1137     vga_draw_glyph9_16,
1138     vga_draw_glyph9_16,
1139     vga_draw_glyph9_32,
1140     vga_draw_glyph9_32,
1141     vga_draw_glyph9_16,
1142     vga_draw_glyph9_16,
1143 };
1144
1145 static const uint8_t cursor_glyph[32 * 4] = {
1146     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1147     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1148     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1149     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1150     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1151     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1152     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1153     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1154     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1155     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1156     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1157     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1158     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1159     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1160     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1161     0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1162 };
1163
1164 static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight,
1165                                     int *pcwidth, int *pcheight)
1166 {
1167     int width, cwidth, height, cheight;
1168
1169     /* total width & height */
1170     cheight = (s->cr[9] & 0x1f) + 1;
1171     cwidth = 8;
1172     if (!(s->sr[1] & 0x01))
1173         cwidth = 9;
1174     if (s->sr[1] & 0x08)
1175         cwidth = 16; /* NOTE: no 18 pixel wide */
1176     width = (s->cr[0x01] + 1);
1177     if (s->cr[0x06] == 100) {
1178         /* ugly hack for CGA 160x100x16 - explain me the logic */
1179         height = 100;
1180     } else {
1181         height = s->cr[0x12] |
1182             ((s->cr[0x07] & 0x02) << 7) |
1183             ((s->cr[0x07] & 0x40) << 3);
1184         height = (height + 1) / cheight;
1185     }
1186
1187     *pwidth = width;
1188     *pheight = height;
1189     *pcwidth = cwidth;
1190     *pcheight = cheight;
1191 }
1192
1193 typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1194
1195 static rgb_to_pixel_dup_func * const rgb_to_pixel_dup_table[NB_DEPTHS] = {
1196     rgb_to_pixel8_dup,
1197     rgb_to_pixel15_dup,
1198     rgb_to_pixel16_dup,
1199     rgb_to_pixel32_dup,
1200     rgb_to_pixel32bgr_dup,
1201     rgb_to_pixel15bgr_dup,
1202     rgb_to_pixel16bgr_dup,
1203 };
1204
1205 /*
1206  * Text mode update
1207  * Missing:
1208  * - double scan
1209  * - double width
1210  * - underline
1211  * - flashing
1212  */
1213 static void vga_draw_text(VGACommonState *s, int full_update)
1214 {
1215     int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1216     int cx_min, cx_max, linesize, x_incr, line, line1;
1217     uint32_t offset, fgcol, bgcol, v, cursor_offset;
1218     uint8_t *d1, *d, *src, *dest, *cursor_ptr;
1219     const uint8_t *font_ptr, *font_base[2];
1220     int dup9, line_offset, depth_index;
1221     uint32_t *palette;
1222     uint32_t *ch_attr_ptr;
1223     vga_draw_glyph8_func *vga_draw_glyph8;
1224     vga_draw_glyph9_func *vga_draw_glyph9;
1225
1226     /* compute font data address (in plane 2) */
1227     v = s->sr[3];
1228     offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1229     if (offset != s->font_offsets[0]) {
1230         s->font_offsets[0] = offset;
1231         full_update = 1;
1232     }
1233     font_base[0] = s->vram_ptr + offset;
1234
1235     offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1236     font_base[1] = s->vram_ptr + offset;
1237     if (offset != s->font_offsets[1]) {
1238         s->font_offsets[1] = offset;
1239         full_update = 1;
1240     }
1241     if (s->plane_updated & (1 << 2)) {
1242         /* if the plane 2 was modified since the last display, it
1243            indicates the font may have been modified */
1244         s->plane_updated = 0;
1245         full_update = 1;
1246     }
1247     full_update |= update_basic_params(s);
1248
1249     line_offset = s->line_offset;
1250
1251     vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1252     if ((height * width) > CH_ATTR_SIZE) {
1253         /* better than nothing: exit if transient size is too big */
1254         return;
1255     }
1256
1257     if (width != s->last_width || height != s->last_height ||
1258         cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
1259         s->last_scr_width = width * cw;
1260         s->last_scr_height = height * cheight;
1261         qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height);
1262         s->last_depth = 0;
1263         s->last_width = width;
1264         s->last_height = height;
1265         s->last_ch = cheight;
1266         s->last_cw = cw;
1267         full_update = 1;
1268     }
1269     s->rgb_to_pixel =
1270         rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1271     full_update |= update_palette16(s);
1272     palette = s->last_palette;
1273     x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1274
1275     cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
1276     if (cursor_offset != s->cursor_offset ||
1277         s->cr[0xa] != s->cursor_start ||
1278         s->cr[0xb] != s->cursor_end) {
1279       /* if the cursor position changed, we update the old and new
1280          chars */
1281         if (s->cursor_offset < CH_ATTR_SIZE)
1282             s->last_ch_attr[s->cursor_offset] = -1;
1283         if (cursor_offset < CH_ATTR_SIZE)
1284             s->last_ch_attr[cursor_offset] = -1;
1285         s->cursor_offset = cursor_offset;
1286         s->cursor_start = s->cr[0xa];
1287         s->cursor_end = s->cr[0xb];
1288     }
1289     cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1290
1291     depth_index = get_depth_index(s->ds);
1292     if (cw == 16)
1293         vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1294     else
1295         vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1296     vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1297
1298     dest = ds_get_data(s->ds);
1299     linesize = ds_get_linesize(s->ds);
1300     ch_attr_ptr = s->last_ch_attr;
1301     line = 0;
1302     offset = s->start_addr * 4;
1303     for(cy = 0; cy < height; cy++) {
1304         d1 = dest;
1305         src = s->vram_ptr + offset;
1306         cx_min = width;
1307         cx_max = -1;
1308         for(cx = 0; cx < width; cx++) {
1309             ch_attr = *(uint16_t *)src;
1310             if (full_update || ch_attr != *ch_attr_ptr) {
1311                 if (cx < cx_min)
1312                     cx_min = cx;
1313                 if (cx > cx_max)
1314                     cx_max = cx;
1315                 *ch_attr_ptr = ch_attr;
1316 #ifdef HOST_WORDS_BIGENDIAN
1317                 ch = ch_attr >> 8;
1318                 cattr = ch_attr & 0xff;
1319 #else
1320                 ch = ch_attr & 0xff;
1321                 cattr = ch_attr >> 8;
1322 #endif
1323                 font_ptr = font_base[(cattr >> 3) & 1];
1324                 font_ptr += 32 * 4 * ch;
1325                 bgcol = palette[cattr >> 4];
1326                 fgcol = palette[cattr & 0x0f];
1327                 if (cw != 9) {
1328                     vga_draw_glyph8(d1, linesize,
1329                                     font_ptr, cheight, fgcol, bgcol);
1330                 } else {
1331                     dup9 = 0;
1332                     if (ch >= 0xb0 && ch <= 0xdf && (s->ar[0x10] & 0x04))
1333                         dup9 = 1;
1334                     vga_draw_glyph9(d1, linesize,
1335                                     font_ptr, cheight, fgcol, bgcol, dup9);
1336                 }
1337                 if (src == cursor_ptr &&
1338                     !(s->cr[0x0a] & 0x20)) {
1339                     int line_start, line_last, h;
1340                     /* draw the cursor */
1341                     line_start = s->cr[0x0a] & 0x1f;
1342                     line_last = s->cr[0x0b] & 0x1f;
1343                     /* XXX: check that */
1344                     if (line_last > cheight - 1)
1345                         line_last = cheight - 1;
1346                     if (line_last >= line_start && line_start < cheight) {
1347                         h = line_last - line_start + 1;
1348                         d = d1 + linesize * line_start;
1349                         if (cw != 9) {
1350                             vga_draw_glyph8(d, linesize,
1351                                             cursor_glyph, h, fgcol, bgcol);
1352                         } else {
1353                             vga_draw_glyph9(d, linesize,
1354                                             cursor_glyph, h, fgcol, bgcol, 1);
1355                         }
1356                     }
1357                 }
1358             }
1359             d1 += x_incr;
1360             src += 4;
1361             ch_attr_ptr++;
1362         }
1363         if (cx_max != -1) {
1364             dpy_update(s->ds, cx_min * cw, cy * cheight,
1365                        (cx_max - cx_min + 1) * cw, cheight);
1366         }
1367         dest += linesize * cheight;
1368         line1 = line + cheight;
1369         offset += line_offset;
1370         if (line < s->line_compare && line1 >= s->line_compare) {
1371             offset = 0;
1372         }
1373         line = line1;
1374     }
1375 }
1376
1377 enum {
1378     VGA_DRAW_LINE2,
1379     VGA_DRAW_LINE2D2,
1380     VGA_DRAW_LINE4,
1381     VGA_DRAW_LINE4D2,
1382     VGA_DRAW_LINE8D2,
1383     VGA_DRAW_LINE8,
1384     VGA_DRAW_LINE15,
1385     VGA_DRAW_LINE16,
1386     VGA_DRAW_LINE24,
1387     VGA_DRAW_LINE32,
1388     VGA_DRAW_LINE_NB,
1389 };
1390
1391 static vga_draw_line_func * const vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
1392     vga_draw_line2_8,
1393     vga_draw_line2_16,
1394     vga_draw_line2_16,
1395     vga_draw_line2_32,
1396     vga_draw_line2_32,
1397     vga_draw_line2_16,
1398     vga_draw_line2_16,
1399
1400     vga_draw_line2d2_8,
1401     vga_draw_line2d2_16,
1402     vga_draw_line2d2_16,
1403     vga_draw_line2d2_32,
1404     vga_draw_line2d2_32,
1405     vga_draw_line2d2_16,
1406     vga_draw_line2d2_16,
1407
1408     vga_draw_line4_8,
1409     vga_draw_line4_16,
1410     vga_draw_line4_16,
1411     vga_draw_line4_32,
1412     vga_draw_line4_32,
1413     vga_draw_line4_16,
1414     vga_draw_line4_16,
1415
1416     vga_draw_line4d2_8,
1417     vga_draw_line4d2_16,
1418     vga_draw_line4d2_16,
1419     vga_draw_line4d2_32,
1420     vga_draw_line4d2_32,
1421     vga_draw_line4d2_16,
1422     vga_draw_line4d2_16,
1423
1424     vga_draw_line8d2_8,
1425     vga_draw_line8d2_16,
1426     vga_draw_line8d2_16,
1427     vga_draw_line8d2_32,
1428     vga_draw_line8d2_32,
1429     vga_draw_line8d2_16,
1430     vga_draw_line8d2_16,
1431
1432     vga_draw_line8_8,
1433     vga_draw_line8_16,
1434     vga_draw_line8_16,
1435     vga_draw_line8_32,
1436     vga_draw_line8_32,
1437     vga_draw_line8_16,
1438     vga_draw_line8_16,
1439
1440     vga_draw_line15_8,
1441     vga_draw_line15_15,
1442     vga_draw_line15_16,
1443     vga_draw_line15_32,
1444     vga_draw_line15_32bgr,
1445     vga_draw_line15_15bgr,
1446     vga_draw_line15_16bgr,
1447
1448     vga_draw_line16_8,
1449     vga_draw_line16_15,
1450     vga_draw_line16_16,
1451     vga_draw_line16_32,
1452     vga_draw_line16_32bgr,
1453     vga_draw_line16_15bgr,
1454     vga_draw_line16_16bgr,
1455
1456     vga_draw_line24_8,
1457     vga_draw_line24_15,
1458     vga_draw_line24_16,
1459     vga_draw_line24_32,
1460     vga_draw_line24_32bgr,
1461     vga_draw_line24_15bgr,
1462     vga_draw_line24_16bgr,
1463
1464     vga_draw_line32_8,
1465     vga_draw_line32_15,
1466     vga_draw_line32_16,
1467     vga_draw_line32_32,
1468     vga_draw_line32_32bgr,
1469     vga_draw_line32_15bgr,
1470     vga_draw_line32_16bgr,
1471 };
1472
1473 static int vga_get_bpp(VGACommonState *s)
1474 {
1475     int ret;
1476 #ifdef CONFIG_BOCHS_VBE
1477     if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1478         ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1479     } else
1480 #endif
1481     {
1482         ret = 0;
1483     }
1484     return ret;
1485 }
1486
1487 static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1488 {
1489     int width, height;
1490
1491 #ifdef CONFIG_BOCHS_VBE
1492     if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1493         width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1494         height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1495     } else
1496 #endif
1497     {
1498         width = (s->cr[0x01] + 1) * 8;
1499         height = s->cr[0x12] |
1500             ((s->cr[0x07] & 0x02) << 7) |
1501             ((s->cr[0x07] & 0x40) << 3);
1502         height = (height + 1);
1503     }
1504     *pwidth = width;
1505     *pheight = height;
1506 }
1507
1508 void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2)
1509 {
1510     int y;
1511     if (y1 >= VGA_MAX_HEIGHT)
1512         return;
1513     if (y2 >= VGA_MAX_HEIGHT)
1514         y2 = VGA_MAX_HEIGHT;
1515     for(y = y1; y < y2; y++) {
1516         s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1517     }
1518 }
1519
1520 static void vga_sync_dirty_bitmap(VGACommonState *s)
1521 {
1522     memory_region_sync_dirty_bitmap(&s->vram);
1523 }
1524
1525 void vga_dirty_log_start(VGACommonState *s)
1526 {
1527     memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
1528 }
1529
1530 void vga_dirty_log_stop(VGACommonState *s)
1531 {
1532     memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA);
1533 }
1534
1535 void vga_dirty_log_restart(VGACommonState *s)
1536 {
1537     vga_dirty_log_stop(s);
1538     vga_dirty_log_start(s);
1539 }
1540
1541 /*
1542  * graphic modes
1543  */
1544 static void vga_draw_graphic(VGACommonState *s, int full_update)
1545 {
1546     int y1, y, update, linesize, y_start, double_scan, mask, depth;
1547     int width, height, shift_control, line_offset, bwidth, bits;
1548     ram_addr_t page0, page1, page_min, page_max;
1549     int disp_width, multi_scan, multi_run;
1550     uint8_t *d;
1551     uint32_t v, addr1, addr;
1552     vga_draw_line_func *vga_draw_line;
1553
1554     full_update |= update_basic_params(s);
1555
1556     if (!full_update)
1557         vga_sync_dirty_bitmap(s);
1558
1559     s->get_resolution(s, &width, &height);
1560     disp_width = width;
1561
1562     shift_control = (s->gr[0x05] >> 5) & 3;
1563     double_scan = (s->cr[0x09] >> 7);
1564     if (shift_control != 1) {
1565         multi_scan = (((s->cr[0x09] & 0x1f) + 1) << double_scan) - 1;
1566     } else {
1567         /* in CGA modes, multi_scan is ignored */
1568         /* XXX: is it correct ? */
1569         multi_scan = double_scan;
1570     }
1571     multi_run = multi_scan;
1572     if (shift_control != s->shift_control ||
1573         double_scan != s->double_scan) {
1574         full_update = 1;
1575         s->shift_control = shift_control;
1576         s->double_scan = double_scan;
1577     }
1578
1579     if (shift_control == 0) {
1580         if (s->sr[0x01] & 8) {
1581             disp_width <<= 1;
1582         }
1583     } else if (shift_control == 1) {
1584         if (s->sr[0x01] & 8) {
1585             disp_width <<= 1;
1586         }
1587     }
1588
1589     depth = s->get_bpp(s);
1590     if (s->line_offset != s->last_line_offset ||
1591         disp_width != s->last_width ||
1592         height != s->last_height ||
1593         s->last_depth != depth) {
1594 #if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
1595         if (depth == 16 || depth == 32) {
1596 #else
1597         if (depth == 32) {
1598 #endif
1599             qemu_free_displaysurface(s->ds);
1600             s->ds->surface = qemu_create_displaysurface_from(disp_width, height, depth,
1601                     s->line_offset,
1602                     s->vram_ptr + (s->start_addr * 4));
1603 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
1604             s->ds->surface->pf = qemu_different_endianness_pixelformat(depth);
1605 #endif
1606             dpy_resize(s->ds);
1607         } else {
1608             qemu_console_resize(s->ds, disp_width, height);
1609         }
1610         s->last_scr_width = disp_width;
1611         s->last_scr_height = height;
1612         s->last_width = disp_width;
1613         s->last_height = height;
1614         s->last_line_offset = s->line_offset;
1615         s->last_depth = depth;
1616         full_update = 1;
1617     } else if (is_buffer_shared(s->ds->surface) &&
1618                (full_update || s->ds->surface->data != s->vram_ptr + (s->start_addr * 4))) {
1619         s->ds->surface->data = s->vram_ptr + (s->start_addr * 4);
1620         dpy_setdata(s->ds);
1621     }
1622
1623     s->rgb_to_pixel =
1624         rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1625
1626     if (shift_control == 0) {
1627         full_update |= update_palette16(s);
1628         if (s->sr[0x01] & 8) {
1629             v = VGA_DRAW_LINE4D2;
1630         } else {
1631             v = VGA_DRAW_LINE4;
1632         }
1633         bits = 4;
1634     } else if (shift_control == 1) {
1635         full_update |= update_palette16(s);
1636         if (s->sr[0x01] & 8) {
1637             v = VGA_DRAW_LINE2D2;
1638         } else {
1639             v = VGA_DRAW_LINE2;
1640         }
1641         bits = 4;
1642     } else {
1643         switch(s->get_bpp(s)) {
1644         default:
1645         case 0:
1646             full_update |= update_palette256(s);
1647             v = VGA_DRAW_LINE8D2;
1648             bits = 4;
1649             break;
1650         case 8:
1651             full_update |= update_palette256(s);
1652             v = VGA_DRAW_LINE8;
1653             bits = 8;
1654             break;
1655         case 15:
1656             v = VGA_DRAW_LINE15;
1657             bits = 16;
1658             break;
1659         case 16:
1660             v = VGA_DRAW_LINE16;
1661             bits = 16;
1662             break;
1663         case 24:
1664             v = VGA_DRAW_LINE24;
1665             bits = 24;
1666             break;
1667         case 32:
1668             v = VGA_DRAW_LINE32;
1669             bits = 32;
1670             break;
1671         }
1672     }
1673     vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)];
1674
1675     if (!is_buffer_shared(s->ds->surface) && s->cursor_invalidate)
1676         s->cursor_invalidate(s);
1677
1678     line_offset = s->line_offset;
1679 #if 0
1680     printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1681            width, height, v, line_offset, s->cr[9], s->cr[0x17], s->line_compare, s->sr[0x01]);
1682 #endif
1683     addr1 = (s->start_addr * 4);
1684     bwidth = (width * bits + 7) / 8;
1685     y_start = -1;
1686     page_min = -1;
1687     page_max = 0;
1688     d = ds_get_data(s->ds);
1689     linesize = ds_get_linesize(s->ds);
1690     y1 = 0;
1691     for(y = 0; y < height; y++) {
1692         addr = addr1;
1693         if (!(s->cr[0x17] & 1)) {
1694             int shift;
1695             /* CGA compatibility handling */
1696             shift = 14 + ((s->cr[0x17] >> 6) & 1);
1697             addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1698         }
1699         if (!(s->cr[0x17] & 2)) {
1700             addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1701         }
1702         page0 = addr & TARGET_PAGE_MASK;
1703         page1 = (addr + bwidth - 1) & TARGET_PAGE_MASK;
1704         update = full_update |
1705             memory_region_get_dirty(&s->vram, page0, DIRTY_MEMORY_VGA) |
1706             memory_region_get_dirty(&s->vram, page1, DIRTY_MEMORY_VGA);
1707         if ((page1 - page0) > TARGET_PAGE_SIZE) {
1708             /* if wide line, can use another page */
1709             update |= memory_region_get_dirty(&s->vram,
1710                                               page0 + TARGET_PAGE_SIZE,
1711                                               DIRTY_MEMORY_VGA);
1712         }
1713         /* explicit invalidation for the hardware cursor */
1714         update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
1715         if (update) {
1716             if (y_start < 0)
1717                 y_start = y;
1718             if (page0 < page_min)
1719                 page_min = page0;
1720             if (page1 > page_max)
1721                 page_max = page1;
1722             if (!(is_buffer_shared(s->ds->surface))) {
1723                 vga_draw_line(s, d, s->vram_ptr + addr, width);
1724                 if (s->cursor_draw_line)
1725                     s->cursor_draw_line(s, d, y);
1726             }
1727         } else {
1728             if (y_start >= 0) {
1729                 /* flush to display */
1730                 dpy_update(s->ds, 0, y_start,
1731                            disp_width, y - y_start);
1732                 y_start = -1;
1733             }
1734         }
1735         if (!multi_run) {
1736             mask = (s->cr[0x17] & 3) ^ 3;
1737             if ((y1 & mask) == mask)
1738                 addr1 += line_offset;
1739             y1++;
1740             multi_run = multi_scan;
1741         } else {
1742             multi_run--;
1743         }
1744         /* line compare acts on the displayed lines */
1745         if (y == s->line_compare)
1746             addr1 = 0;
1747         d += linesize;
1748     }
1749     if (y_start >= 0) {
1750         /* flush to display */
1751         dpy_update(s->ds, 0, y_start,
1752                    disp_width, y - y_start);
1753     }
1754     /* reset modified pages */
1755     if (page_max >= page_min) {
1756         memory_region_reset_dirty(&s->vram,
1757                                   page_min,
1758                                   page_max + TARGET_PAGE_SIZE - page_min,
1759                                   DIRTY_MEMORY_VGA);
1760     }
1761     memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
1762 }
1763
1764 static void vga_draw_blank(VGACommonState *s, int full_update)
1765 {
1766     int i, w, val;
1767     uint8_t *d;
1768
1769     if (!full_update)
1770         return;
1771     if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1772         return;
1773
1774     s->rgb_to_pixel =
1775         rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1776     if (ds_get_bits_per_pixel(s->ds) == 8)
1777         val = s->rgb_to_pixel(0, 0, 0);
1778     else
1779         val = 0;
1780     w = s->last_scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1781     d = ds_get_data(s->ds);
1782     for(i = 0; i < s->last_scr_height; i++) {
1783         memset(d, val, w);
1784         d += ds_get_linesize(s->ds);
1785     }
1786     dpy_update(s->ds, 0, 0,
1787                s->last_scr_width, s->last_scr_height);
1788 }
1789
1790 #define GMODE_TEXT     0
1791 #define GMODE_GRAPH    1
1792 #define GMODE_BLANK 2
1793
1794 static void vga_update_display(void *opaque)
1795 {
1796     VGACommonState *s = opaque;
1797     int full_update, graphic_mode;
1798
1799     if (ds_get_bits_per_pixel(s->ds) == 0) {
1800         /* nothing to do */
1801     } else {
1802         full_update = 0;
1803         if (!(s->ar_index & 0x20)) {
1804             graphic_mode = GMODE_BLANK;
1805         } else {
1806             graphic_mode = s->gr[6] & 1;
1807         }
1808         if (graphic_mode != s->graphic_mode) {
1809             s->graphic_mode = graphic_mode;
1810             full_update = 1;
1811         }
1812         switch(graphic_mode) {
1813         case GMODE_TEXT:
1814             vga_draw_text(s, full_update);
1815             break;
1816         case GMODE_GRAPH:
1817             vga_draw_graphic(s, full_update);
1818             break;
1819         case GMODE_BLANK:
1820         default:
1821             vga_draw_blank(s, full_update);
1822             break;
1823         }
1824     }
1825 }
1826
1827 /* force a full display refresh */
1828 static void vga_invalidate_display(void *opaque)
1829 {
1830     VGACommonState *s = opaque;
1831
1832     s->last_width = -1;
1833     s->last_height = -1;
1834 }
1835
1836 void vga_common_reset(VGACommonState *s)
1837 {
1838     s->sr_index = 0;
1839     memset(s->sr, '\0', sizeof(s->sr));
1840     s->gr_index = 0;
1841     memset(s->gr, '\0', sizeof(s->gr));
1842     s->ar_index = 0;
1843     memset(s->ar, '\0', sizeof(s->ar));
1844     s->ar_flip_flop = 0;
1845     s->cr_index = 0;
1846     memset(s->cr, '\0', sizeof(s->cr));
1847     s->msr = 0;
1848     s->fcr = 0;
1849     s->st00 = 0;
1850     s->st01 = 0;
1851     s->dac_state = 0;
1852     s->dac_sub_index = 0;
1853     s->dac_read_index = 0;
1854     s->dac_write_index = 0;
1855     memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1856     s->dac_8bit = 0;
1857     memset(s->palette, '\0', sizeof(s->palette));
1858     s->bank_offset = 0;
1859 #ifdef CONFIG_BOCHS_VBE
1860     s->vbe_index = 0;
1861     memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
1862     s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5;
1863     s->vbe_start_addr = 0;
1864     s->vbe_line_offset = 0;
1865     s->vbe_bank_mask = (s->vram_size >> 16) - 1;
1866 #endif
1867     memset(s->font_offsets, '\0', sizeof(s->font_offsets));
1868     s->graphic_mode = -1; /* force full update */
1869     s->shift_control = 0;
1870     s->double_scan = 0;
1871     s->line_offset = 0;
1872     s->line_compare = 0;
1873     s->start_addr = 0;
1874     s->plane_updated = 0;
1875     s->last_cw = 0;
1876     s->last_ch = 0;
1877     s->last_width = 0;
1878     s->last_height = 0;
1879     s->last_scr_width = 0;
1880     s->last_scr_height = 0;
1881     s->cursor_start = 0;
1882     s->cursor_end = 0;
1883     s->cursor_offset = 0;
1884     memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1885     memset(s->last_palette, '\0', sizeof(s->last_palette));
1886     memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1887     switch (vga_retrace_method) {
1888     case VGA_RETRACE_DUMB:
1889         break;
1890     case VGA_RETRACE_PRECISE:
1891         memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1892         break;
1893     }
1894 }
1895
1896 static void vga_reset(void *opaque)
1897 {
1898     VGACommonState *s =  opaque;
1899     vga_common_reset(s);
1900 }
1901
1902 #define TEXTMODE_X(x)   ((x) % width)
1903 #define TEXTMODE_Y(x)   ((x) / width)
1904 #define VMEM2CHTYPE(v)  ((v & 0xff0007ff) | \
1905         ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1906 /* relay text rendering to the display driver
1907  * instead of doing a full vga_update_display() */
1908 static void vga_update_text(void *opaque, console_ch_t *chardata)
1909 {
1910     VGACommonState *s =  opaque;
1911     int graphic_mode, i, cursor_offset, cursor_visible;
1912     int cw, cheight, width, height, size, c_min, c_max;
1913     uint32_t *src;
1914     console_ch_t *dst, val;
1915     char msg_buffer[80];
1916     int full_update = 0;
1917
1918     if (!(s->ar_index & 0x20)) {
1919         graphic_mode = GMODE_BLANK;
1920     } else {
1921         graphic_mode = s->gr[6] & 1;
1922     }
1923     if (graphic_mode != s->graphic_mode) {
1924         s->graphic_mode = graphic_mode;
1925         full_update = 1;
1926     }
1927     if (s->last_width == -1) {
1928         s->last_width = 0;
1929         full_update = 1;
1930     }
1931
1932     switch (graphic_mode) {
1933     case GMODE_TEXT:
1934         /* TODO: update palette */
1935         full_update |= update_basic_params(s);
1936
1937         /* total width & height */
1938         cheight = (s->cr[9] & 0x1f) + 1;
1939         cw = 8;
1940         if (!(s->sr[1] & 0x01))
1941             cw = 9;
1942         if (s->sr[1] & 0x08)
1943             cw = 16; /* NOTE: no 18 pixel wide */
1944         width = (s->cr[0x01] + 1);
1945         if (s->cr[0x06] == 100) {
1946             /* ugly hack for CGA 160x100x16 - explain me the logic */
1947             height = 100;
1948         } else {
1949             height = s->cr[0x12] |
1950                 ((s->cr[0x07] & 0x02) << 7) |
1951                 ((s->cr[0x07] & 0x40) << 3);
1952             height = (height + 1) / cheight;
1953         }
1954
1955         size = (height * width);
1956         if (size > CH_ATTR_SIZE) {
1957             if (!full_update)
1958                 return;
1959
1960             snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
1961                      width, height);
1962             break;
1963         }
1964
1965         if (width != s->last_width || height != s->last_height ||
1966             cw != s->last_cw || cheight != s->last_ch) {
1967             s->last_scr_width = width * cw;
1968             s->last_scr_height = height * cheight;
1969             s->ds->surface->width = width;
1970             s->ds->surface->height = height;
1971             dpy_resize(s->ds);
1972             s->last_width = width;
1973             s->last_height = height;
1974             s->last_ch = cheight;
1975             s->last_cw = cw;
1976             full_update = 1;
1977         }
1978
1979         /* Update "hardware" cursor */
1980         cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
1981         if (cursor_offset != s->cursor_offset ||
1982             s->cr[0xa] != s->cursor_start ||
1983             s->cr[0xb] != s->cursor_end || full_update) {
1984             cursor_visible = !(s->cr[0xa] & 0x20);
1985             if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
1986                 dpy_cursor(s->ds,
1987                            TEXTMODE_X(cursor_offset),
1988                            TEXTMODE_Y(cursor_offset));
1989             else
1990                 dpy_cursor(s->ds, -1, -1);
1991             s->cursor_offset = cursor_offset;
1992             s->cursor_start = s->cr[0xa];
1993             s->cursor_end = s->cr[0xb];
1994         }
1995
1996         src = (uint32_t *) s->vram_ptr + s->start_addr;
1997         dst = chardata;
1998
1999         if (full_update) {
2000             for (i = 0; i < size; src ++, dst ++, i ++)
2001                 console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src)));
2002
2003             dpy_update(s->ds, 0, 0, width, height);
2004         } else {
2005             c_max = 0;
2006
2007             for (i = 0; i < size; src ++, dst ++, i ++) {
2008                 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
2009                 if (*dst != val) {
2010                     *dst = val;
2011                     c_max = i;
2012                     break;
2013                 }
2014             }
2015             c_min = i;
2016             for (; i < size; src ++, dst ++, i ++) {
2017                 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
2018                 if (*dst != val) {
2019                     *dst = val;
2020                     c_max = i;
2021                 }
2022             }
2023
2024             if (c_min <= c_max) {
2025                 i = TEXTMODE_Y(c_min);
2026                 dpy_update(s->ds, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
2027             }
2028         }
2029
2030         return;
2031     case GMODE_GRAPH:
2032         if (!full_update)
2033             return;
2034
2035         s->get_resolution(s, &width, &height);
2036         snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
2037                  width, height);
2038         break;
2039     case GMODE_BLANK:
2040     default:
2041         if (!full_update)
2042             return;
2043
2044         snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
2045         break;
2046     }
2047
2048     /* Display a message */
2049     s->last_width = 60;
2050     s->last_height = height = 3;
2051     dpy_cursor(s->ds, -1, -1);
2052     s->ds->surface->width = s->last_width;
2053     s->ds->surface->height = height;
2054     dpy_resize(s->ds);
2055
2056     for (dst = chardata, i = 0; i < s->last_width * height; i ++)
2057         console_write_ch(dst ++, ' ');
2058
2059     size = strlen(msg_buffer);
2060     width = (s->last_width - size) / 2;
2061     dst = chardata + s->last_width + width;
2062     for (i = 0; i < size; i ++)
2063         console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
2064
2065     dpy_update(s->ds, 0, 0, s->last_width, height);
2066 }
2067
2068 static uint64_t vga_mem_read(void *opaque, target_phys_addr_t addr,
2069                              unsigned size)
2070 {
2071     VGACommonState *s = opaque;
2072
2073     return vga_mem_readb(s, addr);
2074 }
2075
2076 static void vga_mem_write(void *opaque, target_phys_addr_t addr,
2077                           uint64_t data, unsigned size)
2078 {
2079     VGACommonState *s = opaque;
2080
2081     return vga_mem_writeb(s, addr, data);
2082 }
2083
2084 const MemoryRegionOps vga_mem_ops = {
2085     .read = vga_mem_read,
2086     .write = vga_mem_write,
2087     .endianness = DEVICE_LITTLE_ENDIAN,
2088     .impl = {
2089         .min_access_size = 1,
2090         .max_access_size = 1,
2091     },
2092 };
2093
2094 static int vga_common_post_load(void *opaque, int version_id)
2095 {
2096     VGACommonState *s = opaque;
2097
2098     /* force refresh */
2099     s->graphic_mode = -1;
2100     return 0;
2101 }
2102
2103 const VMStateDescription vmstate_vga_common = {
2104     .name = "vga",
2105     .version_id = 2,
2106     .minimum_version_id = 2,
2107     .minimum_version_id_old = 2,
2108     .post_load = vga_common_post_load,
2109     .fields      = (VMStateField []) {
2110         VMSTATE_UINT32(latch, VGACommonState),
2111         VMSTATE_UINT8(sr_index, VGACommonState),
2112         VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8),
2113         VMSTATE_UINT8(gr_index, VGACommonState),
2114         VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16),
2115         VMSTATE_UINT8(ar_index, VGACommonState),
2116         VMSTATE_BUFFER(ar, VGACommonState),
2117         VMSTATE_INT32(ar_flip_flop, VGACommonState),
2118         VMSTATE_UINT8(cr_index, VGACommonState),
2119         VMSTATE_BUFFER(cr, VGACommonState),
2120         VMSTATE_UINT8(msr, VGACommonState),
2121         VMSTATE_UINT8(fcr, VGACommonState),
2122         VMSTATE_UINT8(st00, VGACommonState),
2123         VMSTATE_UINT8(st01, VGACommonState),
2124
2125         VMSTATE_UINT8(dac_state, VGACommonState),
2126         VMSTATE_UINT8(dac_sub_index, VGACommonState),
2127         VMSTATE_UINT8(dac_read_index, VGACommonState),
2128         VMSTATE_UINT8(dac_write_index, VGACommonState),
2129         VMSTATE_BUFFER(dac_cache, VGACommonState),
2130         VMSTATE_BUFFER(palette, VGACommonState),
2131
2132         VMSTATE_INT32(bank_offset, VGACommonState),
2133         VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState),
2134 #ifdef CONFIG_BOCHS_VBE
2135         VMSTATE_UINT16(vbe_index, VGACommonState),
2136         VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB),
2137         VMSTATE_UINT32(vbe_start_addr, VGACommonState),
2138         VMSTATE_UINT32(vbe_line_offset, VGACommonState),
2139         VMSTATE_UINT32(vbe_bank_mask, VGACommonState),
2140 #endif
2141         VMSTATE_END_OF_LIST()
2142     }
2143 };
2144
2145 void vga_common_init(VGACommonState *s, int vga_ram_size)
2146 {
2147     int i, j, v, b;
2148
2149     for(i = 0;i < 256; i++) {
2150         v = 0;
2151         for(j = 0; j < 8; j++) {
2152             v |= ((i >> j) & 1) << (j * 4);
2153         }
2154         expand4[i] = v;
2155
2156         v = 0;
2157         for(j = 0; j < 4; j++) {
2158             v |= ((i >> (2 * j)) & 3) << (j * 4);
2159         }
2160         expand2[i] = v;
2161     }
2162     for(i = 0; i < 16; i++) {
2163         v = 0;
2164         for(j = 0; j < 4; j++) {
2165             b = ((i >> j) & 1);
2166             v |= b << (2 * j);
2167             v |= b << (2 * j + 1);
2168         }
2169         expand4to8[i] = v;
2170     }
2171
2172 #ifdef CONFIG_BOCHS_VBE
2173     s->is_vbe_vmstate = 1;
2174 #else
2175     s->is_vbe_vmstate = 0;
2176 #endif
2177     memory_region_init_ram(&s->vram, NULL, "vga.vram", vga_ram_size);
2178     s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
2179     s->vram_size = vga_ram_size;
2180     s->get_bpp = vga_get_bpp;
2181     s->get_offsets = vga_get_offsets;
2182     s->get_resolution = vga_get_resolution;
2183     s->update = vga_update_display;
2184     s->invalidate = vga_invalidate_display;
2185     s->screen_dump = vga_screen_dump;
2186     s->text_update = vga_update_text;
2187     switch (vga_retrace_method) {
2188     case VGA_RETRACE_DUMB:
2189         s->retrace = vga_dumb_retrace;
2190         s->update_retrace_info = vga_dumb_update_retrace_info;
2191         break;
2192
2193     case VGA_RETRACE_PRECISE:
2194         s->retrace = vga_precise_retrace;
2195         s->update_retrace_info = vga_precise_update_retrace_info;
2196         break;
2197     }
2198     vga_dirty_log_start(s);
2199 }
2200
2201 /* used by both ISA and PCI */
2202 MemoryRegion *vga_init_io(VGACommonState *s)
2203 {
2204     MemoryRegion *vga_mem;
2205
2206     register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
2207
2208     register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
2209     register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
2210     register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
2211     register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
2212
2213     register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
2214
2215     register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
2216     register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
2217     register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
2218     register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
2219
2220 #ifdef CONFIG_BOCHS_VBE
2221 #if defined (TARGET_I386)
2222     register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2223     register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);
2224
2225     register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2226     register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);
2227 #else
2228     register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2229     register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
2230
2231     register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2232     register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data, s);
2233 #endif
2234 #endif /* CONFIG_BOCHS_VBE */
2235
2236     vga_mem = g_malloc(sizeof(*vga_mem));
2237     memory_region_init_io(vga_mem, &vga_mem_ops, s,
2238                           "vga-lowmem", 0x20000);
2239
2240     return vga_mem;
2241 }
2242
2243 void vga_init(VGACommonState *s, MemoryRegion *address_space)
2244 {
2245     MemoryRegion *vga_io_memory;
2246
2247     qemu_register_reset(vga_reset, s);
2248
2249     s->bank_offset = 0;
2250
2251     vga_io_memory = vga_init_io(s);
2252     memory_region_add_subregion_overlap(address_space,
2253                                         isa_mem_base + 0x000a0000,
2254                                         vga_io_memory,
2255                                         1);
2256     memory_region_set_coalescing(vga_io_memory);
2257 }
2258
2259 void vga_init_vbe(VGACommonState *s, MemoryRegion *system_memory)
2260 {
2261 #ifdef CONFIG_BOCHS_VBE
2262     /* XXX: use optimized standard vga accesses */
2263     memory_region_add_subregion(system_memory,
2264                                 VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2265                                 &s->vram);
2266     s->vbe_mapped = 1;
2267 #endif
2268 }
2269 /********************************************************/
2270 /* vga screen dump */
2271
2272 static void vga_save_dpy_update(DisplayState *ds,
2273                                 int x, int y, int w, int h)
2274 {
2275     if (screen_dump_filename) {
2276         ppm_save(screen_dump_filename, ds->surface);
2277         screen_dump_filename = NULL;
2278     }
2279 }
2280
2281 static void vga_save_dpy_resize(DisplayState *s)
2282 {
2283 }
2284
2285 static void vga_save_dpy_refresh(DisplayState *s)
2286 {
2287 }
2288
2289 int ppm_save(const char *filename, struct DisplaySurface *ds)
2290 {
2291     FILE *f;
2292     uint8_t *d, *d1;
2293     uint32_t v;
2294     int y, x;
2295     uint8_t r, g, b;
2296     int ret;
2297     char *linebuf, *pbuf;
2298
2299     f = fopen(filename, "wb");
2300     if (!f)
2301         return -1;
2302     fprintf(f, "P6\n%d %d\n%d\n",
2303             ds->width, ds->height, 255);
2304     linebuf = g_malloc(ds->width * 3);
2305     d1 = ds->data;
2306     for(y = 0; y < ds->height; y++) {
2307         d = d1;
2308         pbuf = linebuf;
2309         for(x = 0; x < ds->width; x++) {
2310             if (ds->pf.bits_per_pixel == 32)
2311                 v = *(uint32_t *)d;
2312             else
2313                 v = (uint32_t) (*(uint16_t *)d);
2314             r = ((v >> ds->pf.rshift) & ds->pf.rmax) * 256 /
2315                 (ds->pf.rmax + 1);
2316             g = ((v >> ds->pf.gshift) & ds->pf.gmax) * 256 /
2317                 (ds->pf.gmax + 1);
2318             b = ((v >> ds->pf.bshift) & ds->pf.bmax) * 256 /
2319                 (ds->pf.bmax + 1);
2320             *pbuf++ = r;
2321             *pbuf++ = g;
2322             *pbuf++ = b;
2323             d += ds->pf.bytes_per_pixel;
2324         }
2325         d1 += ds->linesize;
2326         ret = fwrite(linebuf, 1, pbuf - linebuf, f);
2327         (void)ret;
2328     }
2329     g_free(linebuf);
2330     fclose(f);
2331     return 0;
2332 }
2333
2334 static DisplayChangeListener* vga_screen_dump_init(DisplayState *ds)
2335 {
2336     DisplayChangeListener *dcl;
2337
2338     dcl = g_malloc0(sizeof(DisplayChangeListener));
2339     dcl->dpy_update = vga_save_dpy_update;
2340     dcl->dpy_resize = vga_save_dpy_resize;
2341     dcl->dpy_refresh = vga_save_dpy_refresh;
2342     register_displaychangelistener(ds, dcl);
2343     return dcl;
2344 }
2345
2346 /* save the vga display in a PPM image even if no display is
2347    available */
2348 static void vga_screen_dump(void *opaque, const char *filename)
2349 {
2350     VGACommonState *s = opaque;
2351
2352     if (!screen_dump_dcl)
2353         screen_dump_dcl = vga_screen_dump_init(s->ds);
2354
2355     screen_dump_filename = (char *)filename;
2356     vga_invalidate_display(s);
2357     vga_hw_update();
2358 }
2359