include/exec/exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef _EXEC_ALL_H_
  21 #define _EXEC_ALL_H_
  22
  23 #include "qemu-common.h"
  24
  25 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  26 #define DEBUG_DISAS
  27
  28 /* Page tracking code uses ram addresses in system mode, and virtual
  29    addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
  30    type.  */
  31 #if defined(CONFIG_USER_ONLY)
  32 typedef abi_ulong tb_page_addr_t;
  33 #else
  34 typedef ram_addr_t tb_page_addr_t;
  35 #endif
  36
  37 /* is_jmp field values */
  38 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  39 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  40 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  41 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  42
  43 struct TranslationBlock;
  44 typedef struct TranslationBlock TranslationBlock;
  45
  46 /* XXX: make safe guess about sizes */
  47 #define MAX_OP_PER_INSTR 266
  48
  49 #if HOST_LONG_BITS == 32
  50 #define MAX_OPC_PARAM_PER_ARG 2
  51 #else
  52 #define MAX_OPC_PARAM_PER_ARG 1
  53 #endif
  54 #define MAX_OPC_PARAM_IARGS 5
  55 #define MAX_OPC_PARAM_OARGS 1
  56 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  57
  58 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  59  * and up to 4 + N parameters on 64-bit archs
  60  * (N = number of input arguments + output arguments).  */
  61 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  62 #define OPC_BUF_SIZE 640
  63 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  64
  65 /* Maximum size a TCG op can expand to.  This is complicated because a
  66    single op may require several host instructions and register reloads.
  67    For now take a wild guess at 192 bytes, which should allow at least
  68    a couple of fixup instructions per argument.  */
  69 #define TCG_MAX_OP_SIZE 192
  70
  71 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  72
  73 #include "qemu/log.h"
  74
  75 void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
  76 void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb);
  77 void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
  78                           int pc_pos);
  79
  80 void cpu_gen_init(void);
  81 int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb,
  82                  int *gen_code_size_ptr);
  83 bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
  84 void page_size_init(void);
  85
  86 void QEMU_NORETURN cpu_resume_from_signal(CPUState *cpu, void *puc);
  87 void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
  88 TranslationBlock *tb_gen_code(CPUState *cpu,
  89                               target_ulong pc, target_ulong cs_base, int flags,
  90                               int cflags);
  91 void cpu_exec_init(CPUArchState *env);
  92 void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
  93 int page_unprotect(target_ulong address, uintptr_t pc, void *puc);
  94 void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
  95                                    int is_cpu_write_access);
  96 void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
  97                               int is_cpu_write_access);
  98 #if !defined(CONFIG_USER_ONLY)
  99 bool qemu_in_vcpu_thread(void);
 100 void cpu_reload_memory_map(CPUState *cpu);
 101 void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as);
 102 /* cputlb.c */
 103 void tlb_flush_page(CPUState *cpu, target_ulong addr);
 104 void tlb_flush(CPUState *cpu, int flush_global);
 105 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
 106                   hwaddr paddr, int prot,
 107                   int mmu_idx, target_ulong size);
 108 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
 109 #else
 110 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
 111 {
 112 }
 113
 114 static inline void tlb_flush(CPUState *cpu, int flush_global)
 115 {
 116 }
 117 #endif
 118
 119 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 120
 121 #define CODE_GEN_PHYS_HASH_BITS     15
 122 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 123
 124 /* estimated block size for TB allocation */
 125 /* XXX: use a per code average code fragment size and modulate it
 126    according to the host CPU */
 127 #if defined(CONFIG_SOFTMMU)
 128 #define CODE_GEN_AVG_BLOCK_SIZE 128
 129 #else
 130 #define CODE_GEN_AVG_BLOCK_SIZE 64
 131 #endif
 132
 133 #if defined(__arm__) || defined(_ARCH_PPC) \
 134     || defined(__x86_64__) || defined(__i386__) \
 135     || defined(__sparc__) || defined(__aarch64__) \
 136     || defined(__s390x__) || defined(__mips__) \
 137     || defined(CONFIG_TCG_INTERPRETER)
 138 #define USE_DIRECT_JUMP
 139 #endif
 140
 141 struct TranslationBlock {
 142     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 143     target_ulong cs_base; /* CS base for this block */
 144     uint64_t flags; /* flags defining in which context the code was generated */
 145     uint16_t size;      /* size of target code for this block (1 <=
 146                            size <= TARGET_PAGE_SIZE) */
 147     uint16_t icount;
 148     uint32_t cflags;    /* compile flags */
 149 #define CF_COUNT_MASK  0x7fff
 150 #define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */
 151 #define CF_NOCACHE     0x10000 /* To be freed after execution */
 152 #define CF_USE_ICOUNT  0x20000
 153
 154     void *tc_ptr;    /* pointer to the translated code */
 155     /* next matching tb for physical address. */
 156     struct TranslationBlock *phys_hash_next;
 157     /* first and second physical page containing code. The lower bit
 158        of the pointer tells the index in page_next[] */
 159     struct TranslationBlock *page_next[2];
 160     tb_page_addr_t page_addr[2];
 161
 162     /* the following data are used to directly call another TB from
 163        the code of this one. */
 164     uint16_t tb_next_offset[2]; /* offset of original jump target */
 165 #ifdef USE_DIRECT_JUMP
 166     uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
 167 #else
 168     uintptr_t tb_next[2]; /* address of jump generated code */
 169 #endif
 170     /* list of TBs jumping to this one. This is a circular list using
 171        the two least significant bits of the pointers to tell what is
 172        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 173        jmp_first */
 174     struct TranslationBlock *jmp_next[2];
 175     struct TranslationBlock *jmp_first;
 176 };
 177
 178 #include "exec/spinlock.h"
 179
 180 typedef struct TBContext TBContext;
 181
 182 struct TBContext {
 183
 184     TranslationBlock *tbs;
 185     TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 186     int nb_tbs;
 187     /* any access to the tbs or the page table must use this lock */
 188     spinlock_t tb_lock;
 189
 190     /* statistics */
 191     int tb_flush_count;
 192     int tb_phys_invalidate_count;
 193
 194     int tb_invalidated_flag;
 195 };
 196
 197 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
 198 {
 199     target_ulong tmp;
 200     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 201     return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
 202 }
 203
 204 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
 205 {
 206     target_ulong tmp;
 207     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 208     return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
 209             | (tmp & TB_JMP_ADDR_MASK));
 210 }
 211
 212 static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
 213 {
 214     return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
 215 }
 216
 217 void tb_free(TranslationBlock *tb);
 218 void tb_flush(CPUArchState *env);
 219 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
 220
 221 #if defined(USE_DIRECT_JUMP)
 222
 223 #if defined(CONFIG_TCG_INTERPRETER)
 224 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 225 {
 226     /* patch the branch destination */
 227     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 228     /* no need to flush icache explicitly */
 229 }
 230 #elif defined(_ARCH_PPC)
 231 void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
 232 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
 233 #elif defined(__i386__) || defined(__x86_64__)
 234 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 235 {
 236     /* patch the branch destination */
 237     stl_le_p((void*)jmp_addr, addr - (jmp_addr + 4));
 238     /* no need to flush icache explicitly */
 239 }
 240 #elif defined(__s390x__)
 241 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 242 {
 243     /* patch the branch destination */
 244     intptr_t disp = addr - (jmp_addr - 2);
 245     stl_be_p((void*)jmp_addr, disp / 2);
 246     /* no need to flush icache explicitly */
 247 }
 248 #elif defined(__aarch64__)
 249 void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
 250 #define tb_set_jmp_target1 aarch64_tb_set_jmp_target
 251 #elif defined(__arm__)
 252 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 253 {
 254 #if !QEMU_GNUC_PREREQ(4, 1)
 255     register unsigned long _beg __asm ("a1");
 256     register unsigned long _end __asm ("a2");
 257     register unsigned long _flg __asm ("a3");
 258 #endif
 259
 260     /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
 261     *(uint32_t *)jmp_addr =
 262         (*(uint32_t *)jmp_addr & ~0xffffff)
 263         | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
 264
 265 #if QEMU_GNUC_PREREQ(4, 1)
 266     __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
 267 #else
 268     /* flush icache */
 269     _beg = jmp_addr;
 270     _end = jmp_addr + 4;
 271     _flg = 0;
 272     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 273 #endif
 274 }
 275 #elif defined(__sparc__) || defined(__mips__)
 276 void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr);
 277 #else
 278 #error tb_set_jmp_target1 is missing
 279 #endif
 280
 281 static inline void tb_set_jmp_target(TranslationBlock *tb,
 282                                      int n, uintptr_t addr)
 283 {
 284     uint16_t offset = tb->tb_jmp_offset[n];
 285     tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);
 286 }
 287
 288 #else
 289
 290 /* set the jump target */
 291 static inline void tb_set_jmp_target(TranslationBlock *tb,
 292                                      int n, uintptr_t addr)
 293 {
 294     tb->tb_next[n] = addr;
 295 }
 296
 297 #endif
 298
 299 static inline void tb_add_jump(TranslationBlock *tb, int n,
 300                                TranslationBlock *tb_next)
 301 {
 302     /* NOTE: this test is only needed for thread safety */
 303     if (!tb->jmp_next[n]) {
 304         /* patch the native jump address */
 305         tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);
 306
 307         /* add in TB jmp circular list */
 308         tb->jmp_next[n] = tb_next->jmp_first;
 309         tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) | (n));
 310     }
 311 }
 312
 313 /* GETRA is the true target of the return instruction that we'll execute,
 314    defined here for simplicity of defining the follow-up macros.  */
 315 #if defined(CONFIG_TCG_INTERPRETER)
 316 extern uintptr_t tci_tb_ptr;
 317 # define GETRA() tci_tb_ptr
 318 #else
 319 # define GETRA() \
 320     ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
 321 #endif
 322
 323 /* The true return address will often point to a host insn that is part of
 324    the next translated guest insn.  Adjust the address backward to point to
 325    the middle of the call insn.  Subtracting one would do the job except for
 326    several compressed mode architectures (arm, mips) which set the low bit
 327    to indicate the compressed mode; subtracting two works around that.  It
 328    is also the case that there are no host isas that contain a call insn
 329    smaller than 4 bytes, so we don't worry about special-casing this.  */
 330 #if defined(CONFIG_TCG_INTERPRETER)
 331 # define GETPC_ADJ   0
 332 #else
 333 # define GETPC_ADJ   2
 334 #endif
 335
 336 #define GETPC()  (GETRA() - GETPC_ADJ)
 337
 338 #if !defined(CONFIG_USER_ONLY)
 339
 340 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align));
 341
 342 struct MemoryRegion *iotlb_to_region(CPUState *cpu,
 343                                      hwaddr index);
 344 bool io_mem_read(struct MemoryRegion *mr, hwaddr addr,
 345                  uint64_t *pvalue, unsigned size);
 346 bool io_mem_write(struct MemoryRegion *mr, hwaddr addr,
 347                   uint64_t value, unsigned size);
 348
 349 void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx,
 350               uintptr_t retaddr);
 351
 352 #endif
 353
 354 #if defined(CONFIG_USER_ONLY)
 355 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
 356 {
 357     return addr;
 358 }
 359 #else
 360 /* cputlb.c */
 361 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr);
 362 #endif
 363
 364 /* vl.c */
 365 extern int singlestep;
 366
 367 /* cpu-exec.c */
 368 extern volatile sig_atomic_t exit_request;
 369
 370 /**
 371  * cpu_can_do_io:
 372  * @cpu: The CPU for which to check IO.
 373  *
 374  * Deterministic execution requires that IO only be performed on the last
 375  * instruction of a TB so that interrupts take effect immediately.
 376  *
 377  * Returns: %true if memory-mapped IO is safe, %false otherwise.
 378  */
 379 static inline bool cpu_can_do_io(CPUState *cpu)
 380 {
 381     if (!use_icount) {
 382         return true;
 383     }
 384     /* If not executing code then assume we are ok.  */
 385     if (cpu->current_tb == NULL) {
 386         return true;
 387     }
 388     return cpu->can_do_io != 0;
 389 }
 390
 391 #endif