hw/pci-bridge/gen_pcie_root_port.c

   1 /*
   2  * Generic PCI Express Root Port emulation
   3  *
   4  * Copyright (C) 2017 Red Hat Inc
   5  *
   6  * Authors:
   7  *   Marcel Apfelbaum <marcel@redhat.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10  * See the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qapi/error.h"
  15 #include "qemu/module.h"
  16 #include "hw/pci/msix.h"
  17 #include "hw/pci/pcie_port.h"
  18 #include "hw/qdev-properties.h"
  19 #include "hw/qdev-properties-system.h"
  20 #include "migration/vmstate.h"
  21 #include "qom/object.h"
  22
  23 #define TYPE_GEN_PCIE_ROOT_PORT                "pcie-root-port"
  24 OBJECT_DECLARE_SIMPLE_TYPE(GenPCIERootPort, GEN_PCIE_ROOT_PORT)
  25
  26 #define GEN_PCIE_ROOT_PORT_AER_OFFSET           0x100
  27 #define GEN_PCIE_ROOT_PORT_ACS_OFFSET \
  28         (GEN_PCIE_ROOT_PORT_AER_OFFSET + PCI_ERR_SIZEOF)
  29
  30 #define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR       1
  31
  32 struct GenPCIERootPort {
  33     /*< private >*/
  34     PCIESlot parent_obj;
  35     /*< public >*/
  36
  37     bool migrate_msix;
  38
  39     /* additional resources to reserve */
  40     PCIResReserve res_reserve;
  41 };
  42
  43 static uint8_t gen_rp_aer_vector(const PCIDevice *d)
  44 {
  45     return 0;
  46 }
  47
  48 static int gen_rp_interrupts_init(PCIDevice *d, Error **errp)
  49 {
  50     int rc;
  51
  52     rc = msix_init_exclusive_bar(d, GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR, 0, errp);
  53
  54     if (rc < 0) {
  55         assert(rc == -ENOTSUP);
  56     } else {
  57         msix_vector_use(d, 0);
  58     }
  59
  60     return rc;
  61 }
  62
  63 static void gen_rp_interrupts_uninit(PCIDevice *d)
  64 {
  65     msix_uninit_exclusive_bar(d);
  66 }
  67
  68 static bool gen_rp_test_migrate_msix(void *opaque, int version_id)
  69 {
  70     GenPCIERootPort *rp = opaque;
  71
  72     return rp->migrate_msix;
  73 }
  74
  75 static void gen_rp_realize(DeviceState *dev, Error **errp)
  76 {
  77     PCIDevice *d = PCI_DEVICE(dev);
  78     GenPCIERootPort *grp = GEN_PCIE_ROOT_PORT(d);
  79     PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
  80     Error *local_err = NULL;
  81
  82     rpc->parent_realize(dev, &local_err);
  83     if (local_err) {
  84         error_propagate(errp, local_err);
  85         return;
  86     }
  87
  88     int rc = pci_bridge_qemu_reserve_cap_init(d, 0,
  89                                               grp->res_reserve, errp);
  90
  91     if (rc < 0) {
  92         rpc->parent_class.exit(d);
  93         return;
  94     }
  95
  96     if (!grp->res_reserve.io) {
  97         pci_word_test_and_clear_mask(d->wmask + PCI_COMMAND,
  98                                      PCI_COMMAND_IO);
  99         d->wmask[PCI_IO_BASE] = 0;
 100         d->wmask[PCI_IO_LIMIT] = 0;
 101     }
 102 }
 103
 104 static const VMStateDescription vmstate_rp_dev = {
 105     .name = "pcie-root-port",
 106     .priority = MIG_PRI_PCI_BUS,
 107     .version_id = 1,
 108     .minimum_version_id = 1,
 109     .post_load = pcie_cap_slot_post_load,
 110     .fields = (VMStateField[]) {
 111         VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
 112         VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
 113                        PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
 114         VMSTATE_MSIX_TEST(parent_obj.parent_obj.parent_obj.parent_obj,
 115                           GenPCIERootPort,
 116                           gen_rp_test_migrate_msix),
 117         VMSTATE_END_OF_LIST()
 118     }
 119 };
 120
 121 static Property gen_rp_props[] = {
 122     DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort,
 123                      migrate_msix, true),
 124     DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort,
 125                        res_reserve.bus, -1),
 126     DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort,
 127                      res_reserve.io, -1),
 128     DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort,
 129                      res_reserve.mem_non_pref, -1),
 130     DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort,
 131                      res_reserve.mem_pref_32, -1),
 132     DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort,
 133                      res_reserve.mem_pref_64, -1),
 134     DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
 135                                 speed, PCIE_LINK_SPEED_16),
 136     DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
 137                                 width, PCIE_LINK_WIDTH_32),
 138     DEFINE_PROP_END_OF_LIST()
 139 };
 140
 141 static void gen_rp_dev_class_init(ObjectClass *klass, void *data)
 142 {
 143     DeviceClass *dc = DEVICE_CLASS(klass);
 144     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 145     PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
 146
 147     k->vendor_id = PCI_VENDOR_ID_REDHAT;
 148     k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_RP;
 149     dc->desc = "PCI Express Root Port";
 150     dc->vmsd = &vmstate_rp_dev;
 151     device_class_set_props(dc, gen_rp_props);
 152
 153     device_class_set_parent_realize(dc, gen_rp_realize, &rpc->parent_realize);
 154
 155     rpc->aer_vector = gen_rp_aer_vector;
 156     rpc->interrupts_init = gen_rp_interrupts_init;
 157     rpc->interrupts_uninit = gen_rp_interrupts_uninit;
 158     rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
 159     rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET;
 160 }
 161
 162 static const TypeInfo gen_rp_dev_info = {
 163     .name          = TYPE_GEN_PCIE_ROOT_PORT,
 164     .parent        = TYPE_PCIE_ROOT_PORT,
 165     .instance_size = sizeof(GenPCIERootPort),
 166     .class_init    = gen_rp_dev_class_init,
 167 };
 168
 169  static void gen_rp_register_types(void)
 170  {
 171     type_register_static(&gen_rp_dev_info);
 172  }
 173  type_init(gen_rp_register_types)