target/arm/translate.h

   1 #ifndef TARGET_ARM_TRANSLATE_H
   2 #define TARGET_ARM_TRANSLATE_H
   3
   4 #include "exec/translator.h"
   5
   6
   7 /* internal defines */
   8 typedef struct DisasContext {
   9     DisasContextBase base;
  10     const ARMISARegisters *isar;
  11
  12     target_ulong pc;
  13     target_ulong page_start;
  14     uint32_t insn;
  15     /* Nonzero if this instruction has been conditionally skipped.  */
  16     int condjmp;
  17     /* The label that will be jumped to when the instruction is skipped.  */
  18     TCGLabel *condlabel;
  19     /* Thumb-2 conditional execution bits.  */
  20     int condexec_mask;
  21     int condexec_cond;
  22     int thumb;
  23     int sctlr_b;
  24     TCGMemOp be_data;
  25 #if !defined(CONFIG_USER_ONLY)
  26     int user;
  27 #endif
  28     ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
  29     uint8_t tbii;      /* TBI1|TBI0 for insns */
  30     uint8_t tbid;      /* TBI1|TBI0 for data */
  31     bool ns;        /* Use non-secure CPREG bank on access */
  32     int fp_excp_el; /* FP exception EL or 0 if enabled */
  33     int sve_excp_el; /* SVE exception EL or 0 if enabled */
  34     int sve_len;     /* SVE vector length in bytes */
  35     /* Flag indicating that exceptions from secure mode are routed to EL3. */
  36     bool secure_routed_to_el3;
  37     bool vfp_enabled; /* FP enabled via FPSCR.EN */
  38     int vec_len;
  39     int vec_stride;
  40     bool v7m_handler_mode;
  41     bool v8m_secure; /* true if v8M and we're in Secure mode */
  42     bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */
  43     bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */
  44     /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
  45      * so that top level loop can generate correct syndrome information.
  46      */
  47     uint32_t svc_imm;
  48     int aarch64;
  49     int current_el;
  50     GHashTable *cp_regs;
  51     uint64_t features; /* CPU features bits */
  52     /* Because unallocated encodings generate different exception syndrome
  53      * information from traps due to FP being disabled, we can't do a single
  54      * "is fp access disabled" check at a high level in the decode tree.
  55      * To help in catching bugs where the access check was forgotten in some
  56      * code path, we set this flag when the access check is done, and assert
  57      * that it is set at the point where we actually touch the FP regs.
  58      */
  59     bool fp_access_checked;
  60     /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
  61      * single-step support).
  62      */
  63     bool ss_active;
  64     bool pstate_ss;
  65     /* True if the insn just emitted was a load-exclusive instruction
  66      * (necessary for syndrome information for single step exceptions),
  67      * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
  68      */
  69     bool is_ldex;
  70     /* True if a single-step exception will be taken to the current EL */
  71     bool ss_same_el;
  72     /* True if v8.3-PAuth is active.  */
  73     bool pauth_active;
  74     /* True with v8.5-BTI and SCTLR_ELx.BT* set.  */
  75     bool bt;
  76     /*
  77      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
  78      *  < 0, set by the current instruction.
  79      */
  80     int8_t btype;
  81     /* True if this page is guarded.  */
  82     bool guarded_page;
  83     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
  84     int c15_cpar;
  85     /* TCG op of the current insn_start.  */
  86     TCGOp *insn_start;
  87 #define TMP_A64_MAX 16
  88     int tmp_a64_count;
  89     TCGv_i64 tmp_a64[TMP_A64_MAX];
  90 } DisasContext;
  91
  92 typedef struct DisasCompare {
  93     TCGCond cond;
  94     TCGv_i32 value;
  95     bool value_global;
  96 } DisasCompare;
  97
  98 /* Share the TCG temporaries common between 32 and 64 bit modes.  */
  99 extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
 100 extern TCGv_i64 cpu_exclusive_addr;
 101 extern TCGv_i64 cpu_exclusive_val;
 102
 103 static inline int arm_dc_feature(DisasContext *dc, int feature)
 104 {
 105     return (dc->features & (1ULL << feature)) != 0;
 106 }
 107
 108 static inline int get_mem_index(DisasContext *s)
 109 {
 110     return arm_to_core_mmu_idx(s->mmu_idx);
 111 }
 112
 113 /* Function used to determine the target exception EL when otherwise not known
 114  * or default.
 115  */
 116 static inline int default_exception_el(DisasContext *s)
 117 {
 118     /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
 119      * there is no secure EL1, so we route exceptions to EL3.  Otherwise,
 120      * exceptions can only be routed to ELs above 1, so we target the higher of
 121      * 1 or the current EL.
 122      */
 123     return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3)
 124             ? 3 : MAX(1, s->current_el);
 125 }
 126
 127 static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
 128 {
 129     /* We don't need to save all of the syndrome so we mask and shift
 130      * out unneeded bits to help the sleb128 encoder do a better job.
 131      */
 132     syn &= ARM_INSN_START_WORD2_MASK;
 133     syn >>= ARM_INSN_START_WORD2_SHIFT;
 134
 135     /* We check and clear insn_start_idx to catch multiple updates.  */
 136     assert(s->insn_start != NULL);
 137     tcg_set_insn_start_param(s->insn_start, 2, syn);
 138     s->insn_start = NULL;
 139 }
 140
 141 /* is_jmp field values */
 142 #define DISAS_JUMP      DISAS_TARGET_0 /* only pc was modified dynamically */
 143 #define DISAS_UPDATE    DISAS_TARGET_1 /* cpu state was modified dynamically */
 144 /* These instructions trap after executing, so the A32/T32 decoder must
 145  * defer them until after the conditional execution state has been updated.
 146  * WFI also needs special handling when single-stepping.
 147  */
 148 #define DISAS_WFI       DISAS_TARGET_2
 149 #define DISAS_SWI       DISAS_TARGET_3
 150 /* WFE */
 151 #define DISAS_WFE       DISAS_TARGET_4
 152 #define DISAS_HVC       DISAS_TARGET_5
 153 #define DISAS_SMC       DISAS_TARGET_6
 154 #define DISAS_YIELD     DISAS_TARGET_7
 155 /* M profile branch which might be an exception return (and so needs
 156  * custom end-of-TB code)
 157  */
 158 #define DISAS_BX_EXCRET DISAS_TARGET_8
 159 /* For instructions which want an immediate exit to the main loop,
 160  * as opposed to attempting to use lookup_and_goto_ptr. Unlike
 161  * DISAS_UPDATE this doesn't write the PC on exiting the translation
 162  * loop so you need to ensure something (gen_a64_set_pc_im or runtime
 163  * helper) has done so before we reach return from cpu_tb_exec.
 164  */
 165 #define DISAS_EXIT      DISAS_TARGET_9
 166
 167 #ifdef TARGET_AARCH64
 168 void a64_translate_init(void);
 169 void gen_a64_set_pc_im(uint64_t val);
 170 void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags);
 171 extern const TranslatorOps aarch64_translator_ops;
 172 #else
 173 static inline void a64_translate_init(void)
 174 {
 175 }
 176
 177 static inline void gen_a64_set_pc_im(uint64_t val)
 178 {
 179 }
 180
 181 static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 182 {
 183 }
 184 #endif
 185
 186 void arm_test_cc(DisasCompare *cmp, int cc);
 187 void arm_free_cc(DisasCompare *cmp);
 188 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
 189 void arm_gen_test_cc(int cc, TCGLabel *label);
 190
 191 /* Return state of Alternate Half-precision flag, caller frees result */
 192 static inline TCGv_i32 get_ahp_flag(void)
 193 {
 194     TCGv_i32 ret = tcg_temp_new_i32();
 195
 196     tcg_gen_ld_i32(ret, cpu_env,
 197                    offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
 198     tcg_gen_extract_i32(ret, ret, 26, 1);
 199
 200     return ret;
 201 }
 202
 203 /* Set bits within PSTATE.  */
 204 static inline void set_pstate_bits(uint32_t bits)
 205 {
 206     TCGv_i32 p = tcg_temp_new_i32();
 207
 208     tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
 209
 210     tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 211     tcg_gen_ori_i32(p, p, bits);
 212     tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 213     tcg_temp_free_i32(p);
 214 }
 215
 216 /* Clear bits within PSTATE.  */
 217 static inline void clear_pstate_bits(uint32_t bits)
 218 {
 219     TCGv_i32 p = tcg_temp_new_i32();
 220
 221     tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
 222
 223     tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 224     tcg_gen_andi_i32(p, p, ~bits);
 225     tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 226     tcg_temp_free_i32(p);
 227 }
 228
 229 /* If the singlestep state is Active-not-pending, advance to Active-pending. */
 230 static inline void gen_ss_advance(DisasContext *s)
 231 {
 232     if (s->ss_active) {
 233         s->pstate_ss = 0;
 234         clear_pstate_bits(PSTATE_SS);
 235     }
 236 }
 237
 238 /* Vector operations shared between ARM and AArch64.  */
 239 extern const GVecGen3 bsl_op;
 240 extern const GVecGen3 bit_op;
 241 extern const GVecGen3 bif_op;
 242 extern const GVecGen3 mla_op[4];
 243 extern const GVecGen3 mls_op[4];
 244 extern const GVecGen3 cmtst_op[4];
 245 extern const GVecGen2i ssra_op[4];
 246 extern const GVecGen2i usra_op[4];
 247 extern const GVecGen2i sri_op[4];
 248 extern const GVecGen2i sli_op[4];
 249 extern const GVecGen4 uqadd_op[4];
 250 extern const GVecGen4 sqadd_op[4];
 251 extern const GVecGen4 uqsub_op[4];
 252 extern const GVecGen4 sqsub_op[4];
 253 void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
 254
 255 /*
 256  * Forward to the isar_feature_* tests given a DisasContext pointer.
 257  */
 258 #define dc_isar_feature(name, ctx) \
 259     ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
 260
 261 #endif /* TARGET_ARM_TRANSLATE_H */