include/qom/cpu.h

   1 /*
   2  * QEMU CPU model
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20 #ifndef QEMU_CPU_H
  21 #define QEMU_CPU_H
  22
  23 #include <signal.h>
  24 #include <setjmp.h>
  25 #include "hw/qdev-core.h"
  26 #include "exec/hwaddr.h"
  27 #include "qemu/queue.h"
  28 #include "qemu/thread.h"
  29 #include "qemu/tls.h"
  30 #include "qemu/typedefs.h"
  31
  32 typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
  33                                      void *opaque);
  34
  35 /**
  36  * vaddr:
  37  * Type wide enough to contain any #target_ulong virtual address.
  38  */
  39 typedef uint64_t vaddr;
  40 #define VADDR_PRId PRId64
  41 #define VADDR_PRIu PRIu64
  42 #define VADDR_PRIo PRIo64
  43 #define VADDR_PRIx PRIx64
  44 #define VADDR_PRIX PRIX64
  45 #define VADDR_MAX UINT64_MAX
  46
  47 /**
  48  * SECTION:cpu
  49  * @section_id: QEMU-cpu
  50  * @title: CPU Class
  51  * @short_description: Base class for all CPUs
  52  */
  53
  54 #define TYPE_CPU "cpu"
  55
  56 /* Since this macro is used a lot in hot code paths and in conjunction with
  57  * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
  58  * an unchecked cast.
  59  */
  60 #define CPU(obj) ((CPUState *)(obj))
  61
  62 #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
  63 #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
  64
  65 typedef struct CPUState CPUState;
  66
  67 typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
  68                                     bool is_write, bool is_exec, int opaque,
  69                                     unsigned size);
  70
  71 struct TranslationBlock;
  72
  73 /**
  74  * CPUClass:
  75  * @class_by_name: Callback to map -cpu command line model name to an
  76  * instantiatable CPU type.
  77  * @parse_features: Callback to parse command line arguments.
  78  * @reset: Callback to reset the #CPUState to its initial state.
  79  * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
  80  * @has_work: Callback for checking if there is work to do.
  81  * @do_interrupt: Callback for interrupt handling.
  82  * @do_unassigned_access: Callback for unassigned access handling.
  83  * @do_unaligned_access: Callback for unaligned access handling, if
  84  * the target defines #ALIGNED_ONLY.
  85  * @memory_rw_debug: Callback for GDB memory access.
  86  * @dump_state: Callback for dumping state.
  87  * @dump_statistics: Callback for dumping statistics.
  88  * @get_arch_id: Callback for getting architecture-dependent CPU ID.
  89  * @get_paging_enabled: Callback for inquiring whether paging is enabled.
  90  * @get_memory_mapping: Callback for obtaining the memory mappings.
  91  * @set_pc: Callback for setting the Program Counter register.
  92  * @synchronize_from_tb: Callback for synchronizing state from a TCG
  93  * #TranslationBlock.
  94  * @handle_mmu_fault: Callback for handling an MMU fault.
  95  * @get_phys_page_debug: Callback for obtaining a physical address.
  96  * @gdb_read_register: Callback for letting GDB read a register.
  97  * @gdb_write_register: Callback for letting GDB write a register.
  98  * @debug_excp_handler: Callback for handling debug exceptions.
  99  * @vmsd: State description for migration.
 100  * @gdb_num_core_regs: Number of core registers accessible to GDB.
 101  * @gdb_core_xml_file: File name for core registers GDB XML description.
 102  * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
 103  *           before the insn which triggers a watchpoint rather than after it.
 104  * @cpu_exec_enter: Callback for cpu_exec preparation.
 105  * @cpu_exec_exit: Callback for cpu_exec cleanup.
 106  * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec.
 107  *
 108  * Represents a CPU family or model.
 109  */
 110 typedef struct CPUClass {
 111     /*< private >*/
 112     DeviceClass parent_class;
 113     /*< public >*/
 114
 115     ObjectClass *(*class_by_name)(const char *cpu_model);
 116     void (*parse_features)(CPUState *cpu, char *str, Error **errp);
 117
 118     void (*reset)(CPUState *cpu);
 119     int reset_dump_flags;
 120     bool (*has_work)(CPUState *cpu);
 121     void (*do_interrupt)(CPUState *cpu);
 122     CPUUnassignedAccess do_unassigned_access;
 123     void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
 124                                 int is_write, int is_user, uintptr_t retaddr);
 125     bool (*virtio_is_big_endian)(CPUState *cpu);
 126     int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
 127                            uint8_t *buf, int len, bool is_write);
 128     void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 129                        int flags);
 130     void (*dump_statistics)(CPUState *cpu, FILE *f,
 131                             fprintf_function cpu_fprintf, int flags);
 132     int64_t (*get_arch_id)(CPUState *cpu);
 133     bool (*get_paging_enabled)(const CPUState *cpu);
 134     void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
 135                                Error **errp);
 136     void (*set_pc)(CPUState *cpu, vaddr value);
 137     void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
 138     int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw,
 139                             int mmu_index);
 140     hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
 141     int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
 142     int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
 143     void (*debug_excp_handler)(CPUState *cpu);
 144
 145     int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
 146                             int cpuid, void *opaque);
 147     int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
 148                                 void *opaque);
 149     int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
 150                             int cpuid, void *opaque);
 151     int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
 152                                 void *opaque);
 153
 154     const struct VMStateDescription *vmsd;
 155     int gdb_num_core_regs;
 156     const char *gdb_core_xml_file;
 157     bool gdb_stop_before_watchpoint;
 158
 159     void (*cpu_exec_enter)(CPUState *cpu);
 160     void (*cpu_exec_exit)(CPUState *cpu);
 161     bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
 162 } CPUClass;
 163
 164 #ifdef HOST_WORDS_BIGENDIAN
 165 typedef struct icount_decr_u16 {
 166     uint16_t high;
 167     uint16_t low;
 168 } icount_decr_u16;
 169 #else
 170 typedef struct icount_decr_u16 {
 171     uint16_t low;
 172     uint16_t high;
 173 } icount_decr_u16;
 174 #endif
 175
 176 typedef struct CPUBreakpoint {
 177     vaddr pc;
 178     int flags; /* BP_* */
 179     QTAILQ_ENTRY(CPUBreakpoint) entry;
 180 } CPUBreakpoint;
 181
 182 typedef struct CPUWatchpoint {
 183     vaddr vaddr;
 184     vaddr len;
 185     vaddr hitaddr;
 186     int flags; /* BP_* */
 187     QTAILQ_ENTRY(CPUWatchpoint) entry;
 188 } CPUWatchpoint;
 189
 190 struct KVMState;
 191 struct kvm_run;
 192
 193 #define TB_JMP_CACHE_BITS 12
 194 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
 195
 196 /**
 197  * CPUState:
 198  * @cpu_index: CPU index (informative).
 199  * @nr_cores: Number of cores within this CPU package.
 200  * @nr_threads: Number of threads within this CPU.
 201  * @numa_node: NUMA node this CPU is belonging to.
 202  * @host_tid: Host thread ID.
 203  * @running: #true if CPU is currently running (usermode).
 204  * @created: Indicates whether the CPU thread has been successfully created.
 205  * @interrupt_request: Indicates a pending interrupt request.
 206  * @halted: Nonzero if the CPU is in suspended state.
 207  * @stop: Indicates a pending stop request.
 208  * @stopped: Indicates the CPU has been artificially stopped.
 209  * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
 210  *           CPU and return to its top level loop.
 211  * @singlestep_enabled: Flags for single-stepping.
 212  * @icount_extra: Instructions until next timer event.
 213  * @icount_decr: Number of cycles left, with interrupt flag in high bit.
 214  * This allows a single read-compare-cbranch-write sequence to test
 215  * for both decrementer underflow and exceptions.
 216  * @can_do_io: Nonzero if memory-mapped IO is safe.
 217  * @env_ptr: Pointer to subclass-specific CPUArchState field.
 218  * @current_tb: Currently executing TB.
 219  * @gdb_regs: Additional GDB registers.
 220  * @gdb_num_regs: Number of total registers accessible to GDB.
 221  * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
 222  * @next_cpu: Next CPU sharing TB cache.
 223  * @opaque: User data.
 224  * @mem_io_pc: Host Program Counter at which the memory was accessed.
 225  * @mem_io_vaddr: Target virtual address at which the memory was accessed.
 226  * @kvm_fd: vCPU file descriptor for KVM.
 227  *
 228  * State of one CPU core or thread.
 229  */
 230 struct CPUState {
 231     /*< private >*/
 232     DeviceState parent_obj;
 233     /*< public >*/
 234
 235     int nr_cores;
 236     int nr_threads;
 237     int numa_node;
 238
 239     struct QemuThread *thread;
 240 #ifdef _WIN32
 241     HANDLE hThread;
 242 #endif
 243     int thread_id;
 244     uint32_t host_tid;
 245     bool running;
 246     struct QemuCond *halt_cond;
 247     struct qemu_work_item *queued_work_first, *queued_work_last;
 248     bool thread_kicked;
 249     bool created;
 250     bool stop;
 251     bool stopped;
 252     volatile sig_atomic_t exit_request;
 253     uint32_t interrupt_request;
 254     int singlestep_enabled;
 255     int64_t icount_extra;
 256     sigjmp_buf jmp_env;
 257
 258     AddressSpace *as;
 259     MemoryListener *tcg_as_listener;
 260
 261     void *env_ptr; /* CPUArchState */
 262     struct TranslationBlock *current_tb;
 263     struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
 264     struct GDBRegisterState *gdb_regs;
 265     int gdb_num_regs;
 266     int gdb_num_g_regs;
 267     QTAILQ_ENTRY(CPUState) node;
 268
 269     /* ice debug support */
 270     QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;
 271
 272     QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;
 273     CPUWatchpoint *watchpoint_hit;
 274
 275     void *opaque;
 276
 277     /* In order to avoid passing too many arguments to the MMIO helpers,
 278      * we store some rarely used information in the CPU context.
 279      */
 280     uintptr_t mem_io_pc;
 281     vaddr mem_io_vaddr;
 282
 283     int kvm_fd;
 284     bool kvm_vcpu_dirty;
 285     struct KVMState *kvm_state;
 286     struct kvm_run *kvm_run;
 287
 288     /* TODO Move common fields from CPUArchState here. */
 289     int cpu_index; /* used by alpha TCG */
 290     uint32_t halted; /* used by alpha, cris, ppc TCG */
 291     union {
 292         uint32_t u32;
 293         icount_decr_u16 u16;
 294     } icount_decr;
 295     uint32_t can_do_io;
 296     int32_t exception_index; /* used by m68k TCG */
 297
 298     /* Note that this is accessed at the start of every TB via a negative
 299        offset from AREG0.  Leave this field at the end so as to make the
 300        (absolute value) offset as small as possible.  This reduces code
 301        size, especially for hosts without large memory offsets.  */
 302     volatile sig_atomic_t tcg_exit_req;
 303 };
 304
 305 QTAILQ_HEAD(CPUTailQ, CPUState);
 306 extern struct CPUTailQ cpus;
 307 #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node)
 308 #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node)
 309 #define CPU_FOREACH_SAFE(cpu, next_cpu) \
 310     QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu)
 311 #define first_cpu QTAILQ_FIRST(&cpus)
 312
 313 DECLARE_TLS(CPUState *, current_cpu);
 314 #define current_cpu tls_var(current_cpu)
 315
 316 /**
 317  * cpu_paging_enabled:
 318  * @cpu: The CPU whose state is to be inspected.
 319  *
 320  * Returns: %true if paging is enabled, %false otherwise.
 321  */
 322 bool cpu_paging_enabled(const CPUState *cpu);
 323
 324 /**
 325  * cpu_get_memory_mapping:
 326  * @cpu: The CPU whose memory mappings are to be obtained.
 327  * @list: Where to write the memory mappings to.
 328  * @errp: Pointer for reporting an #Error.
 329  */
 330 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
 331                             Error **errp);
 332
 333 /**
 334  * cpu_write_elf64_note:
 335  * @f: pointer to a function that writes memory to a file
 336  * @cpu: The CPU whose memory is to be dumped
 337  * @cpuid: ID number of the CPU
 338  * @opaque: pointer to the CPUState struct
 339  */
 340 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
 341                          int cpuid, void *opaque);
 342
 343 /**
 344  * cpu_write_elf64_qemunote:
 345  * @f: pointer to a function that writes memory to a file
 346  * @cpu: The CPU whose memory is to be dumped
 347  * @cpuid: ID number of the CPU
 348  * @opaque: pointer to the CPUState struct
 349  */
 350 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 351                              void *opaque);
 352
 353 /**
 354  * cpu_write_elf32_note:
 355  * @f: pointer to a function that writes memory to a file
 356  * @cpu: The CPU whose memory is to be dumped
 357  * @cpuid: ID number of the CPU
 358  * @opaque: pointer to the CPUState struct
 359  */
 360 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
 361                          int cpuid, void *opaque);
 362
 363 /**
 364  * cpu_write_elf32_qemunote:
 365  * @f: pointer to a function that writes memory to a file
 366  * @cpu: The CPU whose memory is to be dumped
 367  * @cpuid: ID number of the CPU
 368  * @opaque: pointer to the CPUState struct
 369  */
 370 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
 371                              void *opaque);
 372
 373 /**
 374  * CPUDumpFlags:
 375  * @CPU_DUMP_CODE:
 376  * @CPU_DUMP_FPU: dump FPU register state, not just integer
 377  * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
 378  */
 379 enum CPUDumpFlags {
 380     CPU_DUMP_CODE = 0x00010000,
 381     CPU_DUMP_FPU  = 0x00020000,
 382     CPU_DUMP_CCOP = 0x00040000,
 383 };
 384
 385 /**
 386  * cpu_dump_state:
 387  * @cpu: The CPU whose state is to be dumped.
 388  * @f: File to dump to.
 389  * @cpu_fprintf: Function to dump with.
 390  * @flags: Flags what to dump.
 391  *
 392  * Dumps CPU state.
 393  */
 394 void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 395                     int flags);
 396
 397 /**
 398  * cpu_dump_statistics:
 399  * @cpu: The CPU whose state is to be dumped.
 400  * @f: File to dump to.
 401  * @cpu_fprintf: Function to dump with.
 402  * @flags: Flags what to dump.
 403  *
 404  * Dumps CPU statistics.
 405  */
 406 void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 407                          int flags);
 408
 409 #ifndef CONFIG_USER_ONLY
 410 /**
 411  * cpu_get_phys_page_debug:
 412  * @cpu: The CPU to obtain the physical page address for.
 413  * @addr: The virtual address.
 414  *
 415  * Obtains the physical page corresponding to a virtual one.
 416  * Use it only for debugging because no protection checks are done.
 417  *
 418  * Returns: Corresponding physical page address or -1 if no page found.
 419  */
 420 static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
 421 {
 422     CPUClass *cc = CPU_GET_CLASS(cpu);
 423
 424     return cc->get_phys_page_debug(cpu, addr);
 425 }
 426 #endif
 427
 428 /**
 429  * cpu_reset:
 430  * @cpu: The CPU whose state is to be reset.
 431  */
 432 void cpu_reset(CPUState *cpu);
 433
 434 /**
 435  * cpu_class_by_name:
 436  * @typename: The CPU base type.
 437  * @cpu_model: The model string without any parameters.
 438  *
 439  * Looks up a CPU #ObjectClass matching name @cpu_model.
 440  *
 441  * Returns: A #CPUClass or %NULL if not matching class is found.
 442  */
 443 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
 444
 445 /**
 446  * cpu_generic_init:
 447  * @typename: The CPU base type.
 448  * @cpu_model: The model string including optional parameters.
 449  *
 450  * Instantiates a CPU, processes optional parameters and realizes the CPU.
 451  *
 452  * Returns: A #CPUState or %NULL if an error occurred.
 453  */
 454 CPUState *cpu_generic_init(const char *typename, const char *cpu_model);
 455
 456 /**
 457  * cpu_has_work:
 458  * @cpu: The vCPU to check.
 459  *
 460  * Checks whether the CPU has work to do.
 461  *
 462  * Returns: %true if the CPU has work, %false otherwise.
 463  */
 464 static inline bool cpu_has_work(CPUState *cpu)
 465 {
 466     CPUClass *cc = CPU_GET_CLASS(cpu);
 467
 468     g_assert(cc->has_work);
 469     return cc->has_work(cpu);
 470 }
 471
 472 /**
 473  * qemu_cpu_is_self:
 474  * @cpu: The vCPU to check against.
 475  *
 476  * Checks whether the caller is executing on the vCPU thread.
 477  *
 478  * Returns: %true if called from @cpu's thread, %false otherwise.
 479  */
 480 bool qemu_cpu_is_self(CPUState *cpu);
 481
 482 /**
 483  * qemu_cpu_kick:
 484  * @cpu: The vCPU to kick.
 485  *
 486  * Kicks @cpu's thread.
 487  */
 488 void qemu_cpu_kick(CPUState *cpu);
 489
 490 /**
 491  * cpu_is_stopped:
 492  * @cpu: The CPU to check.
 493  *
 494  * Checks whether the CPU is stopped.
 495  *
 496  * Returns: %true if run state is not running or if artificially stopped;
 497  * %false otherwise.
 498  */
 499 bool cpu_is_stopped(CPUState *cpu);
 500
 501 /**
 502  * run_on_cpu:
 503  * @cpu: The vCPU to run on.
 504  * @func: The function to be executed.
 505  * @data: Data to pass to the function.
 506  *
 507  * Schedules the function @func for execution on the vCPU @cpu.
 508  */
 509 void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
 510
 511 /**
 512  * async_run_on_cpu:
 513  * @cpu: The vCPU to run on.
 514  * @func: The function to be executed.
 515  * @data: Data to pass to the function.
 516  *
 517  * Schedules the function @func for execution on the vCPU @cpu asynchronously.
 518  */
 519 void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
 520
 521 /**
 522  * qemu_get_cpu:
 523  * @index: The CPUState@cpu_index value of the CPU to obtain.
 524  *
 525  * Gets a CPU matching @index.
 526  *
 527  * Returns: The CPU or %NULL if there is no matching CPU.
 528  */
 529 CPUState *qemu_get_cpu(int index);
 530
 531 /**
 532  * cpu_exists:
 533  * @id: Guest-exposed CPU ID to lookup.
 534  *
 535  * Search for CPU with specified ID.
 536  *
 537  * Returns: %true - CPU is found, %false - CPU isn't found.
 538  */
 539 bool cpu_exists(int64_t id);
 540
 541 #ifndef CONFIG_USER_ONLY
 542
 543 typedef void (*CPUInterruptHandler)(CPUState *, int);
 544
 545 extern CPUInterruptHandler cpu_interrupt_handler;
 546
 547 /**
 548  * cpu_interrupt:
 549  * @cpu: The CPU to set an interrupt on.
 550  * @mask: The interupts to set.
 551  *
 552  * Invokes the interrupt handler.
 553  */
 554 static inline void cpu_interrupt(CPUState *cpu, int mask)
 555 {
 556     cpu_interrupt_handler(cpu, mask);
 557 }
 558
 559 #else /* USER_ONLY */
 560
 561 void cpu_interrupt(CPUState *cpu, int mask);
 562
 563 #endif /* USER_ONLY */
 564
 565 #ifdef CONFIG_SOFTMMU
 566 static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 567                                          bool is_write, bool is_exec,
 568                                          int opaque, unsigned size)
 569 {
 570     CPUClass *cc = CPU_GET_CLASS(cpu);
 571
 572     if (cc->do_unassigned_access) {
 573         cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
 574     }
 575 }
 576
 577 static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
 578                                         int is_write, int is_user,
 579                                         uintptr_t retaddr)
 580 {
 581     CPUClass *cc = CPU_GET_CLASS(cpu);
 582
 583     return cc->do_unaligned_access(cpu, addr, is_write, is_user, retaddr);
 584 }
 585 #endif
 586
 587 /**
 588  * cpu_reset_interrupt:
 589  * @cpu: The CPU to clear the interrupt on.
 590  * @mask: The interrupt mask to clear.
 591  *
 592  * Resets interrupts on the vCPU @cpu.
 593  */
 594 void cpu_reset_interrupt(CPUState *cpu, int mask);
 595
 596 /**
 597  * cpu_exit:
 598  * @cpu: The CPU to exit.
 599  *
 600  * Requests the CPU @cpu to exit execution.
 601  */
 602 void cpu_exit(CPUState *cpu);
 603
 604 /**
 605  * cpu_resume:
 606  * @cpu: The CPU to resume.
 607  *
 608  * Resumes CPU, i.e. puts CPU into runnable state.
 609  */
 610 void cpu_resume(CPUState *cpu);
 611
 612 /**
 613  * qemu_init_vcpu:
 614  * @cpu: The vCPU to initialize.
 615  *
 616  * Initializes a vCPU.
 617  */
 618 void qemu_init_vcpu(CPUState *cpu);
 619
 620 #define SSTEP_ENABLE  0x1  /* Enable simulated HW single stepping */
 621 #define SSTEP_NOIRQ   0x2  /* Do not use IRQ while single stepping */
 622 #define SSTEP_NOTIMER 0x4  /* Do not Timers while single stepping */
 623
 624 /**
 625  * cpu_single_step:
 626  * @cpu: CPU to the flags for.
 627  * @enabled: Flags to enable.
 628  *
 629  * Enables or disables single-stepping for @cpu.
 630  */
 631 void cpu_single_step(CPUState *cpu, int enabled);
 632
 633 /* Breakpoint/watchpoint flags */
 634 #define BP_MEM_READ           0x01
 635 #define BP_MEM_WRITE          0x02
 636 #define BP_MEM_ACCESS         (BP_MEM_READ | BP_MEM_WRITE)
 637 #define BP_STOP_BEFORE_ACCESS 0x04
 638 /* 0x08 currently unused */
 639 #define BP_GDB                0x10
 640 #define BP_CPU                0x20
 641 #define BP_WATCHPOINT_HIT_READ 0x40
 642 #define BP_WATCHPOINT_HIT_WRITE 0x80
 643 #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE)
 644
 645 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
 646                           CPUBreakpoint **breakpoint);
 647 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
 648 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
 649 void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
 650
 651 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
 652                           int flags, CPUWatchpoint **watchpoint);
 653 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
 654                           vaddr len, int flags);
 655 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
 656 void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
 657
 658 void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
 659     GCC_FMT_ATTR(2, 3);
 660
 661 #ifdef CONFIG_SOFTMMU
 662 extern const struct VMStateDescription vmstate_cpu_common;
 663 #else
 664 #define vmstate_cpu_common vmstate_dummy
 665 #endif
 666
 667 #define VMSTATE_CPU() {                                                     \
 668     .name = "parent_obj",                                                   \
 669     .size = sizeof(CPUState),                                               \
 670     .vmsd = &vmstate_cpu_common,                                            \
 671     .flags = VMS_STRUCT,                                                    \
 672     .offset = 0,                                                            \
 673 }
 674
 675 #endif