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eepro100: Fix PXE boot
[qemu.git] / hw / eepro100.c
blobf6764cc7fa1b2ca9b0e014f7b3821fe847d797de
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (c) 2006-2007 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386) ok
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * non-i386 platforms
28 * Windows networking
29 *
30 * References:
31 *
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
34 */
35
36 #include <stddef.h> /* offsetof */
37 #include <stdbool.h>
38 #include "hw.h"
39 #include "pci.h"
40 #include "net.h"
41 #include "eeprom93xx.h"
42
43 /* Common declarations for all PCI devices. */
44
45 #define PCI_CONFIG_8(offset, value) \
46 (pci_conf[offset] = (value))
47 #define PCI_CONFIG_16(offset, value) \
48 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
49 #define PCI_CONFIG_32(offset, value) \
50 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
51
52 #define KiB 1024
53
54 /* Debug EEPRO100 card. */
55 #if 0
56 # define DEBUG_EEPRO100
57 #endif
58
59 #ifdef DEBUG_EEPRO100
60 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
61 #else
62 #define logout(fmt, ...) ((void)0)
63 #endif
64
65 /* Set flags to 0 to disable debug output. */
66 #define INT 1 /* interrupt related actions */
67 #define MDI 1 /* mdi related actions */
68 #define OTHER 1
69 #define RXTX 1
70 #define EEPROM 1 /* eeprom related actions */
71
72 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
73
74 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
75
76 #define MAX_ETH_FRAME_SIZE 1514
77
78 /* This driver supports several different devices which are declared here. */
79 #define i82550 0x82550
80 #define i82551 0x82551
81 #define i82557A 0x82557a
82 #define i82557B 0x82557b
83 #define i82557C 0x82557c
84 #define i82558A 0x82558a
85 #define i82558B 0x82558b
86 #define i82559A 0x82559a
87 #define i82559B 0x82559b
88 #define i82559C 0x82559c
89 #define i82559ER 0x82559e
90 #define i82562 0x82562
91
92 /* Use 64 word EEPROM. TODO: could be a runtime option. */
93 #define EEPROM_SIZE 64
94
95 #define PCI_MEM_SIZE (4 * KiB)
96 #define PCI_IO_SIZE 64
97 #define PCI_FLASH_SIZE (128 * KiB)
98
99 #define BIT(n) (1 << (n))
100 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
101
102 /* The SCB accepts the following controls for the Tx and Rx units: */
103 #define CU_NOP 0x0000 /* No operation. */
104 #define CU_START 0x0010 /* CU start. */
105 #define CU_RESUME 0x0020 /* CU resume. */
106 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
107 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
108 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
109 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
110 #define CU_SRESUME 0x00a0 /* CU static resume. */
111
112 #define RU_NOP 0x0000
113 #define RX_START 0x0001
114 #define RX_RESUME 0x0002
115 #define RX_ABORT 0x0004
116 #define RX_ADDR_LOAD 0x0006
117 #define RX_RESUMENR 0x0007
118 #define INT_MASK 0x0100
119 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
120
121 /* Offsets to the various registers.
122 All accesses need not be longword aligned. */
123 enum speedo_offsets {
124 SCBStatus = 0, /* Status Word. */
125 SCBAck = 1,
126 SCBCmd = 2, /* Rx/Command Unit command and status. */
127 SCBIntmask = 3,
128 SCBPointer = 4, /* General purpose pointer. */
129 SCBPort = 8, /* Misc. commands and operands. */
130 SCBflash = 12, /* Flash memory control. */
131 SCBeeprom = 14, /* EEPROM control. */
132 SCBCtrlMDI = 16, /* MDI interface control. */
133 SCBEarlyRx = 20, /* Early receive byte count. */
134 SCBFlow = 24, /* Flow Control. */
135 SCBpmdr = 27, /* Power Management Driver. */
136 SCBgctrl = 28, /* General Control. */
137 SCBgstat = 29, /* General Status. */
138 };
139
140 /* A speedo3 transmit buffer descriptor with two buffers... */
141 typedef struct {
142 uint16_t status;
143 uint16_t command;
144 uint32_t link; /* void * */
145 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
146 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
147 uint8_t tx_threshold; /* transmit threshold */
148 uint8_t tbd_count; /* TBD number */
149 //~ /* This constitutes two "TBD" entries: hdr and data */
150 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
151 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
152 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
153 //~ int32_t tx_buf_size1; /* Length of Tx data. */
154 } eepro100_tx_t;
155
156 /* Receive frame descriptor. */
157 typedef struct {
158 int16_t status;
159 uint16_t command;
160 uint32_t link; /* struct RxFD * */
161 uint32_t rx_buf_addr; /* void * */
162 uint16_t count;
163 uint16_t size;
164 char packet[MAX_ETH_FRAME_SIZE + 4];
165 } eepro100_rx_t;
166
167 typedef struct {
168 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
169 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
170 tx_multiple_collisions, tx_total_collisions;
171 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
172 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
173 rx_short_frame_errors;
174 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
175 uint16_t xmt_tco_frames, rcv_tco_frames;
176 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
177 uint32_t reserved[4];
178 } eepro100_stats_t;
179
180 typedef enum {
181 cu_idle = 0,
182 cu_suspended = 1,
183 cu_active = 2,
184 cu_lpq_active = 2,
185 cu_hqp_active = 3
186 } cu_state_t;
187
188 typedef enum {
189 ru_idle = 0,
190 ru_suspended = 1,
191 ru_no_resources = 2,
192 ru_ready = 4
193 } ru_state_t;
194
195 typedef struct {
196 PCIDevice dev;
197 uint8_t mult[8]; /* multicast mask array */
198 int mmio_index;
199 NICState *nic;
200 NICConf conf;
201 uint8_t scb_stat; /* SCB stat/ack byte */
202 uint8_t int_stat; /* PCI interrupt status */
203 /* region must not be saved by nic_save. */
204 uint32_t region[3]; /* PCI region addresses */
205 uint16_t mdimem[32];
206 eeprom_t *eeprom;
207 uint32_t device; /* device variant */
208 uint32_t pointer;
209 /* (cu_base + cu_offset) address the next command block in the command block list. */
210 uint32_t cu_base; /* CU base address */
211 uint32_t cu_offset; /* CU address offset */
212 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
213 uint32_t ru_base; /* RU base address */
214 uint32_t ru_offset; /* RU address offset */
215 uint32_t statsaddr; /* pointer to eepro100_stats_t */
216
217 /* Temporary status information (no need to save these values),
218 * used while processing CU commands. */
219 eepro100_tx_t tx; /* transmit buffer descriptor */
220 uint32_t cb_address; /* = cu_base + cu_offset */
221
222 /* Statistical counters. Also used for wake-up packet (i82559). */
223 eepro100_stats_t statistics;
224
225 #if 0
226 uint16_t status;
227 #endif
228
229 /* Configuration bytes. */
230 uint8_t configuration[22];
231
232 /* Data in mem is always in the byte order of the controller (le). */
233 uint8_t mem[PCI_MEM_SIZE];
234 /* vmstate for each particular nic */
235 VMStateDescription *vmstate;
236
237 /* Quasi static device properties (no need to save them). */
238 uint16_t stats_size;
239 bool has_extended_tcb_support;
240 } EEPRO100State;
241
242 /* Word indices in EEPROM. */
243 typedef enum {
244 EEPROM_CNFG_MDIX = 0x03,
245 EEPROM_ID = 0x05,
246 EEPROM_PHY_ID = 0x06,
247 EEPROM_VENDOR_ID = 0x0c,
248 EEPROM_CONFIG_ASF = 0x0d,
249 EEPROM_DEVICE_ID = 0x23,
250 EEPROM_SMBUS_ADDR = 0x90,
251 } EEPROMOffset;
252
253 /* Default values for MDI (PHY) registers */
254 static const uint16_t eepro100_mdi_default[] = {
255 /* MDI Registers 0 - 6, 7 */
256 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
257 /* MDI Registers 8 - 15 */
258 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
259 /* MDI Registers 16 - 31 */
260 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
261 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
262 };
263
264 /* Readonly mask for MDI (PHY) registers */
265 static const uint16_t eepro100_mdi_mask[] = {
266 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
267 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
268 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
269 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
270 };
271
272 /* XXX: optimize */
273 static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
274 {
275 val = cpu_to_le32(val);
276 cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val));
277 }
278
279 #define POLYNOMIAL 0x04c11db6
280
281 /* From FreeBSD */
282 /* XXX: optimize */
283 static unsigned compute_mcast_idx(const uint8_t * ep)
284 {
285 uint32_t crc;
286 int carry, i, j;
287 uint8_t b;
288
289 crc = 0xffffffff;
290 for (i = 0; i < 6; i++) {
291 b = *ep++;
292 for (j = 0; j < 8; j++) {
293 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
294 crc <<= 1;
295 b >>= 1;
296 if (carry) {
297 crc = ((crc ^ POLYNOMIAL) | carry);
298 }
299 }
300 }
301 return (crc & BITS(7, 2)) >> 2;
302 }
303
304 #if defined(DEBUG_EEPRO100)
305 static const char *nic_dump(const uint8_t * buf, unsigned size)
306 {
307 static char dump[3 * 16 + 1];
308 char *p = &dump[0];
309 if (size > 16) {
310 size = 16;
311 }
312 while (size-- > 0) {
313 p += sprintf(p, " %02x", *buf++);
314 }
315 return dump;
316 }
317 #endif /* DEBUG_EEPRO100 */
318
319 enum scb_stat_ack {
320 stat_ack_not_ours = 0x00,
321 stat_ack_sw_gen = 0x04,
322 stat_ack_rnr = 0x10,
323 stat_ack_cu_idle = 0x20,
324 stat_ack_frame_rx = 0x40,
325 stat_ack_cu_cmd_done = 0x80,
326 stat_ack_not_present = 0xFF,
327 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
328 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
329 };
330
331 static void disable_interrupt(EEPRO100State * s)
332 {
333 if (s->int_stat) {
334 TRACE(INT, logout("interrupt disabled\n"));
335 qemu_irq_lower(s->dev.irq[0]);
336 s->int_stat = 0;
337 }
338 }
339
340 static void enable_interrupt(EEPRO100State * s)
341 {
342 if (!s->int_stat) {
343 TRACE(INT, logout("interrupt enabled\n"));
344 qemu_irq_raise(s->dev.irq[0]);
345 s->int_stat = 1;
346 }
347 }
348
349 static void eepro100_acknowledge(EEPRO100State * s)
350 {
351 s->scb_stat &= ~s->mem[SCBAck];
352 s->mem[SCBAck] = s->scb_stat;
353 if (s->scb_stat == 0) {
354 disable_interrupt(s);
355 }
356 }
357
358 static void eepro100_interrupt(EEPRO100State * s, uint8_t stat)
359 {
360 uint8_t mask = ~s->mem[SCBIntmask];
361 s->mem[SCBAck] |= stat;
362 stat = s->scb_stat = s->mem[SCBAck];
363 stat &= (mask | 0x0f);
364 //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
365 if (stat && (mask & 0x01)) {
366 /* SCB mask and SCB Bit M do not disable interrupt. */
367 enable_interrupt(s);
368 } else if (s->int_stat) {
369 disable_interrupt(s);
370 }
371 }
372
373 static void eepro100_cx_interrupt(EEPRO100State * s)
374 {
375 /* CU completed action command. */
376 /* Transmit not ok (82557 only, not in emulation). */
377 eepro100_interrupt(s, 0x80);
378 }
379
380 static void eepro100_cna_interrupt(EEPRO100State * s)
381 {
382 /* CU left the active state. */
383 eepro100_interrupt(s, 0x20);
384 }
385
386 static void eepro100_fr_interrupt(EEPRO100State * s)
387 {
388 /* RU received a complete frame. */
389 eepro100_interrupt(s, 0x40);
390 }
391
392 #if 0
393 static void eepro100_rnr_interrupt(EEPRO100State * s)
394 {
395 /* RU is not ready. */
396 eepro100_interrupt(s, 0x10);
397 }
398 #endif
399
400 static void eepro100_mdi_interrupt(EEPRO100State * s)
401 {
402 /* MDI completed read or write cycle. */
403 eepro100_interrupt(s, 0x08);
404 }
405
406 static void eepro100_swi_interrupt(EEPRO100State * s)
407 {
408 /* Software has requested an interrupt. */
409 eepro100_interrupt(s, 0x04);
410 }
411
412 #if 0
413 static void eepro100_fcp_interrupt(EEPRO100State * s)
414 {
415 /* Flow control pause interrupt (82558 and later). */
416 eepro100_interrupt(s, 0x01);
417 }
418 #endif
419
420 static void pci_reset(EEPRO100State * s)
421 {
422 uint32_t device = s->device;
423 uint8_t *pci_conf = s->dev.config;
424 bool power_management = 1;
425
426 TRACE(OTHER, logout("%p\n", s));
427
428 /* PCI Vendor ID */
429 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
430 /* PCI Device ID depends on device and is set below. */
431 /* PCI Command */
432 /* TODO: this is the default, do not override. */
433 PCI_CONFIG_16(PCI_COMMAND, 0x0000);
434 /* PCI Status */
435 /* TODO: Value at RST# should be 0. */
436 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK);
437 /* PCI Revision ID */
438 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
439 /* TODO: this is the default, do not override. */
440 /* PCI Class Code */
441 PCI_CONFIG_8(PCI_CLASS_PROG, 0x00);
442 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
443 /* PCI Cache Line Size */
444 /* check cache line size!!! */
445 //~ PCI_CONFIG_8(0x0c, 0x00);
446 /* PCI Latency Timer */
447 PCI_CONFIG_8(PCI_LATENCY_TIMER, 0x20); // latency timer = 32 clocks
448 /* PCI Header Type */
449 /* BIST (built-in self test) */
450 #if defined(TARGET_I386)
451 // !!! workaround for buggy bios
452 //~ #define PCI_BASE_ADDRESS_MEM_PREFETCH 0
453 #endif
454 #if 0
455 /* PCI Base Address Registers */
456 /* CSR Memory Mapped Base Address */
457 PCI_CONFIG_32(PCI_BASE_ADDRESS_0,
458 PCI_BASE_ADDRESS_SPACE_MEMORY |
459 PCI_BASE_ADDRESS_MEM_PREFETCH);
460 /* CSR I/O Mapped Base Address */
461 PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_SPACE_IO);
462 #if 0
463 /* Flash Memory Mapped Base Address */
464 PCI_CONFIG_32(PCI_BASE_ADDRESS_2,
465 0xfffe0000 | PCI_BASE_ADDRESS_SPACE_MEMORY);
466 #endif
467 #endif
468 /* Expansion ROM Base Address (depends on boot disable!!!) */
469 /* TODO: not needed, set when BAR is registered */
470 PCI_CONFIG_32(PCI_ROM_ADDRESS, PCI_BASE_ADDRESS_SPACE_MEMORY);
471 /* Capability Pointer */
472 /* TODO: revisions with power_management 1 use this but
473 * do not set new capability list bit in status register. */
474 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0xdc);
475 /* Interrupt Line */
476 /* Interrupt Pin */
477 /* TODO: RST# value should be 0 */
478 PCI_CONFIG_8(PCI_INTERRUPT_PIN, 1); // interrupt pin 0
479 /* Minimum Grant */
480 PCI_CONFIG_8(PCI_MIN_GNT, 0x08);
481 /* Maximum Latency */
482 PCI_CONFIG_8(PCI_MAX_LAT, 0x18);
483
484 switch (device) {
485 case i82550:
486 // TODO: check device id.
487 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
488 /* Revision ID: 0x0c, 0x0d, 0x0e. */
489 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
490 // TODO: check size of statistical counters.
491 s->stats_size = 80;
492 // TODO: check extended tcb support.
493 s->has_extended_tcb_support = 1;
494 break;
495 case i82551:
496 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
497 /* Revision ID: 0x0f, 0x10. */
498 PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
499 // TODO: check size of statistical counters.
500 s->stats_size = 80;
501 s->has_extended_tcb_support = 1;
502 break;
503 case i82557A:
504 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
505 PCI_CONFIG_8(PCI_REVISION_ID, 0x01);
506 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
507 power_management = 0;
508 break;
509 case i82557B:
510 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
511 PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
512 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
513 power_management = 0;
514 break;
515 case i82557C:
516 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
517 PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
518 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
519 power_management = 0;
520 break;
521 case i82558A:
522 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
523 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
524 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
525 PCI_CONFIG_8(PCI_REVISION_ID, 0x04);
526 s->stats_size = 76;
527 s->has_extended_tcb_support = 1;
528 break;
529 case i82558B:
530 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
531 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
532 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
533 PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
534 s->stats_size = 76;
535 s->has_extended_tcb_support = 1;
536 break;
537 case i82559A:
538 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
539 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
540 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
541 PCI_CONFIG_8(PCI_REVISION_ID, 0x06);
542 s->stats_size = 80;
543 s->has_extended_tcb_support = 1;
544 break;
545 case i82559B:
546 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
547 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
548 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
549 PCI_CONFIG_8(PCI_REVISION_ID, 0x07);
550 s->stats_size = 80;
551 s->has_extended_tcb_support = 1;
552 break;
553 case i82559C:
554 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
555 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
556 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
557 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
558 // TODO: Windows wants revision id 0x0c.
559 PCI_CONFIG_8(PCI_REVISION_ID, 0x0c);
560 #if EEPROM_SIZE > 0
561 PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
562 PCI_CONFIG_16(PCI_SUBSYSTEM_ID, 0x0040);
563 #endif
564 s->stats_size = 80;
565 s->has_extended_tcb_support = 1;
566 break;
567 case i82559ER:
568 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
569 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
570 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
571 PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
572 s->stats_size = 80;
573 s->has_extended_tcb_support = 1;
574 break;
575 case i82562:
576 // TODO: check device id.
577 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
578 /* TODO: wrong revision id. */
579 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
580 s->stats_size = 80;
581 s->has_extended_tcb_support = 1;
582 break;
583 default:
584 logout("Device %X is undefined!\n", device);
585 }
586
587 s->configuration[6] |= BIT(5);
588
589 if (s->stats_size == 80) {
590 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
591 if (s->configuration[6] & BIT(2)) {
592 /* TCO statistical counters. */
593 assert(s->configuration[6] & BIT(5));
594 } else {
595 if (s->configuration[6] & BIT(5)) {
596 /* No extended statistical counters, i82557 compatible. */
597 s->stats_size = 64;
598 } else {
599 /* i82558 compatible. */
600 s->stats_size = 76;
601 }
602 }
603 } else {
604 if (s->configuration[6] & BIT(5)) {
605 /* No extended statistical counters. */
606 s->stats_size = 64;
607 }
608 }
609 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
610
611 if (power_management) {
612 /* Power Management Capabilities */
613 PCI_CONFIG_8(0xdc, 0x01);
614 /* Next Item Pointer */
615 /* Capability ID */
616 PCI_CONFIG_16(0xde, 0x7e21);
617 /* TODO: Power Management Control / Status. */
618 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
619 }
620
621 #if EEPROM_SIZE > 0
622 if (device == i82557C || device == i82558B || device == i82559C) {
623 // TODO: get vendor id from EEPROM for i82557C or later.
624 // TODO: get device id from EEPROM for i82557C or later.
625 // TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
626 // TODO: header type is determined by EEPROM for i82559.
627 // TODO: get subsystem id from EEPROM for i82557C or later.
628 // TODO: get subsystem vendor id from EEPROM for i82557C or later.
629 // TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
630 // TODO: capability pointer depends on EEPROM for i82558.
631 logout("Get device id and revision from EEPROM!!!\n");
632 }
633 #endif /* EEPROM_SIZE > 0 */
634 }
635
636 static void nic_selective_reset(EEPRO100State * s)
637 {
638 size_t i;
639 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
640 //~ eeprom93xx_reset(s->eeprom);
641 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
642 eeprom_contents[EEPROM_ID] = 0x4000;
643 if (s->device == i82557B || s->device == i82557C)
644 eeprom_contents[5] = 0x0100;
645 eeprom_contents[EEPROM_PHY_ID] = 1;
646 uint16_t sum = 0;
647 for (i = 0; i < EEPROM_SIZE - 1; i++) {
648 sum += eeprom_contents[i];
649 }
650 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
651 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
652
653 memset(s->mem, 0, sizeof(s->mem));
654 uint32_t val = BIT(21);
655 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
656
657 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
658 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
659 }
660
661 static void nic_reset(void *opaque)
662 {
663 EEPRO100State *s = opaque;
664 TRACE(OTHER, logout("%p\n", s));
665 /* TODO: Clearing of multicast table for selective reset, too? */
666 memset(&s->mult[0], 0, sizeof(s->mult));
667 nic_selective_reset(s);
668 }
669
670 #if defined(DEBUG_EEPRO100)
671 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
672 "Command/Status",
673 "General Pointer",
674 "Port",
675 "EEPROM/Flash Control",
676 "MDI Control",
677 "Receive DMA Byte Count",
678 "Flow Control",
679 "General Status/Control"
680 };
681
682 static char *regname(uint32_t addr)
683 {
684 static char buf[32];
685 if (addr < PCI_IO_SIZE) {
686 const char *r = e100_reg[addr / 4];
687 if (r != 0) {
688 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
689 } else {
690 snprintf(buf, sizeof(buf), "0x%02x", addr);
691 }
692 } else {
693 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
694 }
695 return buf;
696 }
697 #endif /* DEBUG_EEPRO100 */
698
699 #if 0
700 static uint16_t eepro100_read_status(EEPRO100State * s)
701 {
702 uint16_t val = s->status;
703 TRACE(OTHER, logout("val=0x%04x\n", val));
704 return val;
705 }
706
707 static void eepro100_write_status(EEPRO100State * s, uint16_t val)
708 {
709 TRACE(OTHER, logout("val=0x%04x\n", val));
710 s->status = val;
711 }
712 #endif
713
714 /*****************************************************************************
715 *
716 * Command emulation.
717 *
718 ****************************************************************************/
719
720 #if 0
721 static uint16_t eepro100_read_command(EEPRO100State * s)
722 {
723 uint16_t val = 0xffff;
724 //~ TRACE(OTHER, logout("val=0x%04x\n", val));
725 return val;
726 }
727 #endif
728
729 /* Commands that can be put in a command list entry. */
730 enum commands {
731 CmdNOp = 0,
732 CmdIASetup = 1,
733 CmdConfigure = 2,
734 CmdMulticastList = 3,
735 CmdTx = 4,
736 CmdTDR = 5, /* load microcode */
737 CmdDump = 6,
738 CmdDiagnose = 7,
739
740 /* And some extra flags: */
741 CmdSuspend = 0x4000, /* Suspend after completion. */
742 CmdIntr = 0x2000, /* Interrupt after completion. */
743 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
744 };
745
746 static cu_state_t get_cu_state(EEPRO100State * s)
747 {
748 return ((s->mem[SCBStatus] >> 6) & 0x03);
749 }
750
751 static void set_cu_state(EEPRO100State * s, cu_state_t state)
752 {
753 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6);
754 }
755
756 static ru_state_t get_ru_state(EEPRO100State * s)
757 {
758 return ((s->mem[SCBStatus] >> 2) & 0x0f);
759 }
760
761 static void set_ru_state(EEPRO100State * s, ru_state_t state)
762 {
763 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2);
764 }
765
766 static void dump_statistics(EEPRO100State * s)
767 {
768 /* Dump statistical data. Most data is never changed by the emulation
769 * and always 0, so we first just copy the whole block and then those
770 * values which really matter.
771 * Number of data should check configuration!!!
772 */
773 cpu_physical_memory_write(s->statsaddr,
774 (uint8_t *) & s->statistics, s->stats_size);
775 stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
776 stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
777 stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
778 stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
779 //~ stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
780 //~ stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
781 //~ missing("CU dump statistical counters");
782 }
783
784 static void tx_command(EEPRO100State *s)
785 {
786 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
787 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
788 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
789 uint8_t buf[2600];
790 uint16_t size = 0;
791 uint32_t tbd_address = s->cb_address + 0x10;
792 TRACE(RXTX, logout
793 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
794 tbd_array, tcb_bytes, s->tx.tbd_count));
795
796 if (tcb_bytes > 2600) {
797 logout("TCB byte count too large, using 2600\n");
798 tcb_bytes = 2600;
799 }
800 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
801 logout
802 ("illegal values of TBD array address and TCB byte count!\n");
803 }
804 assert(tcb_bytes <= sizeof(buf));
805 while (size < tcb_bytes) {
806 uint32_t tx_buffer_address = ldl_phys(tbd_address);
807 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
808 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
809 tbd_address += 8;
810 TRACE(RXTX, logout
811 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
812 tx_buffer_address, tx_buffer_size));
813 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
814 cpu_physical_memory_read(tx_buffer_address, &buf[size],
815 tx_buffer_size);
816 size += tx_buffer_size;
817 }
818 if (tbd_array == 0xffffffff) {
819 /* Simplified mode. Was already handled by code above. */
820 } else {
821 /* Flexible mode. */
822 uint8_t tbd_count = 0;
823 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
824 /* Extended Flexible TCB. */
825 for (; tbd_count < 2; tbd_count++) {
826 uint32_t tx_buffer_address = ldl_phys(tbd_address);
827 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
828 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
829 tbd_address += 8;
830 TRACE(RXTX, logout
831 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
832 tx_buffer_address, tx_buffer_size));
833 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
834 cpu_physical_memory_read(tx_buffer_address, &buf[size],
835 tx_buffer_size);
836 size += tx_buffer_size;
837 if (tx_buffer_el & 1) {
838 break;
839 }
840 }
841 }
842 tbd_address = tbd_array;
843 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
844 uint32_t tx_buffer_address = ldl_phys(tbd_address);
845 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
846 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
847 tbd_address += 8;
848 TRACE(RXTX, logout
849 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
850 tx_buffer_address, tx_buffer_size));
851 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
852 cpu_physical_memory_read(tx_buffer_address, &buf[size],
853 tx_buffer_size);
854 size += tx_buffer_size;
855 if (tx_buffer_el & 1) {
856 break;
857 }
858 }
859 }
860 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
861 qemu_send_packet(&s->nic->nc, buf, size);
862 s->statistics.tx_good_frames++;
863 /* Transmit with bad status would raise an CX/TNO interrupt.
864 * (82557 only). Emulation never has bad status. */
865 //~ eepro100_cx_interrupt(s);
866 }
867
868 static void set_multicast_list(EEPRO100State *s)
869 {
870 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
871 uint16_t i;
872 memset(&s->mult[0], 0, sizeof(s->mult));
873 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
874 for (i = 0; i < multicast_count; i += 6) {
875 uint8_t multicast_addr[6];
876 cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
877 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
878 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
879 assert(mcast_idx < 64);
880 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
881 }
882 }
883
884 static void action_command(EEPRO100State *s)
885 {
886 for (;;) {
887 s->cb_address = s->cu_base + s->cu_offset;
888 cpu_physical_memory_read(s->cb_address, (uint8_t *)&s->tx, sizeof(s->tx));
889 uint16_t status = le16_to_cpu(s->tx.status);
890 uint16_t command = le16_to_cpu(s->tx.command);
891 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
892 status, command, s->tx.link);
893 bool bit_el = ((command & 0x8000) != 0);
894 bool bit_s = ((command & 0x4000) != 0);
895 bool bit_i = ((command & 0x2000) != 0);
896 bool bit_nc = ((command & 0x0010) != 0);
897 bool success = true;
898 //~ bool bit_sf = ((command & 0x0008) != 0);
899 uint16_t cmd = command & 0x0007;
900 s->cu_offset = le32_to_cpu(s->tx.link);
901 switch (cmd) {
902 case CmdNOp:
903 /* Do nothing. */
904 break;
905 case CmdIASetup:
906 cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
907 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
908 break;
909 case CmdConfigure:
910 cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
911 sizeof(s->configuration));
912 TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)));
913 break;
914 case CmdMulticastList:
915 set_multicast_list(s);
916 break;
917 case CmdTx:
918 if (bit_nc) {
919 missing("CmdTx: NC = 0");
920 success = false;
921 break;
922 }
923 tx_command(s);
924 break;
925 case CmdTDR:
926 TRACE(OTHER, logout("load microcode\n"));
927 /* Starting with offset 8, the command contains
928 * 64 dwords microcode which we just ignore here. */
929 break;
930 default:
931 missing("undefined command");
932 success = false;
933 break;
934 }
935 /* Write new status. */
936 stw_phys(s->cb_address, status | 0x8000 | (success ? 0x2000 : 0));
937 if (bit_i) {
938 /* CU completed action. */
939 eepro100_cx_interrupt(s);
940 }
941 if (bit_el) {
942 /* CU becomes idle. Terminate command loop. */
943 set_cu_state(s, cu_idle);
944 eepro100_cna_interrupt(s);
945 break;
946 } else if (bit_s) {
947 /* CU becomes suspended. Terminate command loop. */
948 set_cu_state(s, cu_suspended);
949 eepro100_cna_interrupt(s);
950 break;
951 } else {
952 /* More entries in list. */
953 TRACE(OTHER, logout("CU list with at least one more entry\n"));
954 }
955 }
956 TRACE(OTHER, logout("CU list empty\n"));
957 /* List is empty. Now CU is idle or suspended. */
958 }
959
960 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
961 {
962 switch (val) {
963 case CU_NOP:
964 /* No operation. */
965 break;
966 case CU_START:
967 if (get_cu_state(s) != cu_idle) {
968 /* Intel documentation says that CU must be idle for the CU
969 * start command. Intel driver for Linux also starts the CU
970 * from suspended state. */
971 logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle);
972 //~ assert(!"wrong CU state");
973 }
974 set_cu_state(s, cu_active);
975 s->cu_offset = s->pointer;
976 action_command(s);
977 break;
978 case CU_RESUME:
979 if (get_cu_state(s) != cu_suspended) {
980 logout("bad CU resume from CU state %u\n", get_cu_state(s));
981 /* Workaround for bad Linux eepro100 driver which resumes
982 * from idle state. */
983 //~ missing("cu resume");
984 set_cu_state(s, cu_suspended);
985 }
986 if (get_cu_state(s) == cu_suspended) {
987 TRACE(OTHER, logout("CU resuming\n"));
988 set_cu_state(s, cu_active);
989 action_command(s);
990 }
991 break;
992 case CU_STATSADDR:
993 /* Load dump counters address. */
994 s->statsaddr = s->pointer;
995 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
996 break;
997 case CU_SHOWSTATS:
998 /* Dump statistical counters. */
999 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
1000 dump_statistics(s);
1001 stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
1002 break;
1003 case CU_CMD_BASE:
1004 /* Load CU base. */
1005 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
1006 s->cu_base = s->pointer;
1007 break;
1008 case CU_DUMPSTATS:
1009 /* Dump and reset statistical counters. */
1010 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
1011 dump_statistics(s);
1012 stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
1013 memset(&s->statistics, 0, sizeof(s->statistics));
1014 break;
1015 case CU_SRESUME:
1016 /* CU static resume. */
1017 missing("CU static resume");
1018 break;
1019 default:
1020 missing("Undefined CU command");
1021 }
1022 }
1023
1024 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1025 {
1026 switch (val) {
1027 case RU_NOP:
1028 /* No operation. */
1029 break;
1030 case RX_START:
1031 /* RU start. */
1032 if (get_ru_state(s) != ru_idle) {
1033 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
1034 //~ assert(!"wrong RU state");
1035 }
1036 set_ru_state(s, ru_ready);
1037 s->ru_offset = s->pointer;
1038 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
1039 break;
1040 case RX_RESUME:
1041 /* Restart RU. */
1042 if (get_ru_state(s) != ru_suspended) {
1043 logout("RU state is %u, should be %u\n", get_ru_state(s),
1044 ru_suspended);
1045 //~ assert(!"wrong RU state");
1046 }
1047 set_ru_state(s, ru_ready);
1048 break;
1049 case RX_ADDR_LOAD:
1050 /* Load RU base. */
1051 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1052 s->ru_base = s->pointer;
1053 break;
1054 default:
1055 logout("val=0x%02x (undefined RU command)\n", val);
1056 missing("Undefined SU command");
1057 }
1058 }
1059
1060 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1061 {
1062 eepro100_ru_command(s, val & 0x0f);
1063 eepro100_cu_command(s, val & 0xf0);
1064 if ((val) == 0) {
1065 TRACE(OTHER, logout("val=0x%02x\n", val));
1066 }
1067 /* Clear command byte after command was accepted. */
1068 s->mem[SCBCmd] = 0;
1069 }
1070
1071 /*****************************************************************************
1072 *
1073 * EEPROM emulation.
1074 *
1075 ****************************************************************************/
1076
1077 #define EEPROM_CS 0x02
1078 #define EEPROM_SK 0x01
1079 #define EEPROM_DI 0x04
1080 #define EEPROM_DO 0x08
1081
1082 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1083 {
1084 uint16_t val;
1085 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
1086 if (eeprom93xx_read(s->eeprom)) {
1087 val |= EEPROM_DO;
1088 } else {
1089 val &= ~EEPROM_DO;
1090 }
1091 TRACE(EEPROM, logout("val=0x%04x\n", val));
1092 return val;
1093 }
1094
1095 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1096 {
1097 TRACE(EEPROM, logout("val=0x%02x\n", val));
1098
1099 /* mask unwriteable bits */
1100 //~ val = SET_MASKED(val, 0x31, eeprom->value);
1101
1102 int eecs = ((val & EEPROM_CS) != 0);
1103 int eesk = ((val & EEPROM_SK) != 0);
1104 int eedi = ((val & EEPROM_DI) != 0);
1105 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1106 }
1107
1108 static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
1109 {
1110 s->pointer = le32_to_cpu(val);
1111 TRACE(OTHER, logout("val=0x%08x\n", val));
1112 }
1113
1114 /*****************************************************************************
1115 *
1116 * MDI emulation.
1117 *
1118 ****************************************************************************/
1119
1120 #if defined(DEBUG_EEPRO100)
1121 static const char * const mdi_op_name[] = {
1122 "opcode 0",
1123 "write",
1124 "read",
1125 "opcode 3"
1126 };
1127
1128 static const char * const mdi_reg_name[] = {
1129 "Control",
1130 "Status",
1131 "PHY Identification (Word 1)",
1132 "PHY Identification (Word 2)",
1133 "Auto-Negotiation Advertisement",
1134 "Auto-Negotiation Link Partner Ability",
1135 "Auto-Negotiation Expansion"
1136 };
1137
1138 static const char *reg2name(uint8_t reg)
1139 {
1140 static char buffer[10];
1141 const char *p = buffer;
1142 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1143 p = mdi_reg_name[reg];
1144 } else {
1145 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1146 }
1147 return p;
1148 }
1149 #endif /* DEBUG_EEPRO100 */
1150
1151 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1152 {
1153 uint32_t val;
1154 memcpy(&val, &s->mem[0x10], sizeof(val));
1155
1156 #ifdef DEBUG_EEPRO100
1157 uint8_t raiseint = (val & BIT(29)) >> 29;
1158 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1159 uint8_t phy = (val & BITS(25, 21)) >> 21;
1160 uint8_t reg = (val & BITS(20, 16)) >> 16;
1161 uint16_t data = (val & BITS(15, 0));
1162 #endif
1163 /* Emulation takes no time to finish MDI transaction. */
1164 val |= BIT(28);
1165 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1166 val, raiseint, mdi_op_name[opcode], phy,
1167 reg2name(reg), data));
1168 return val;
1169 }
1170
1171 static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1172 {
1173 uint8_t raiseint = (val & BIT(29)) >> 29;
1174 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1175 uint8_t phy = (val & BITS(25, 21)) >> 21;
1176 uint8_t reg = (val & BITS(20, 16)) >> 16;
1177 uint16_t data = (val & BITS(15, 0));
1178 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1179 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1180 if (phy != 1) {
1181 /* Unsupported PHY address. */
1182 //~ logout("phy must be 1 but is %u\n", phy);
1183 data = 0;
1184 } else if (opcode != 1 && opcode != 2) {
1185 /* Unsupported opcode. */
1186 logout("opcode must be 1 or 2 but is %u\n", opcode);
1187 data = 0;
1188 } else if (reg > 6) {
1189 /* Unsupported register. */
1190 logout("register must be 0...6 but is %u\n", reg);
1191 data = 0;
1192 } else {
1193 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1194 val, raiseint, mdi_op_name[opcode], phy,
1195 reg2name(reg), data));
1196 if (opcode == 1) {
1197 /* MDI write */
1198 switch (reg) {
1199 case 0: /* Control Register */
1200 if (data & 0x8000) {
1201 /* Reset status and control registers to default. */
1202 s->mdimem[0] = eepro100_mdi_default[0];
1203 s->mdimem[1] = eepro100_mdi_default[1];
1204 data = s->mdimem[reg];
1205 } else {
1206 /* Restart Auto Configuration = Normal Operation */
1207 data &= ~0x0200;
1208 }
1209 break;
1210 case 1: /* Status Register */
1211 missing("not writable");
1212 data = s->mdimem[reg];
1213 break;
1214 case 2: /* PHY Identification Register (Word 1) */
1215 case 3: /* PHY Identification Register (Word 2) */
1216 missing("not implemented");
1217 break;
1218 case 4: /* Auto-Negotiation Advertisement Register */
1219 case 5: /* Auto-Negotiation Link Partner Ability Register */
1220 break;
1221 case 6: /* Auto-Negotiation Expansion Register */
1222 default:
1223 missing("not implemented");
1224 }
1225 s->mdimem[reg] = data;
1226 } else if (opcode == 2) {
1227 /* MDI read */
1228 switch (reg) {
1229 case 0: /* Control Register */
1230 if (data & 0x8000) {
1231 /* Reset status and control registers to default. */
1232 s->mdimem[0] = eepro100_mdi_default[0];
1233 s->mdimem[1] = eepro100_mdi_default[1];
1234 }
1235 break;
1236 case 1: /* Status Register */
1237 s->mdimem[reg] |= 0x0020;
1238 break;
1239 case 2: /* PHY Identification Register (Word 1) */
1240 case 3: /* PHY Identification Register (Word 2) */
1241 case 4: /* Auto-Negotiation Advertisement Register */
1242 break;
1243 case 5: /* Auto-Negotiation Link Partner Ability Register */
1244 s->mdimem[reg] = 0x41fe;
1245 break;
1246 case 6: /* Auto-Negotiation Expansion Register */
1247 s->mdimem[reg] = 0x0001;
1248 break;
1249 }
1250 data = s->mdimem[reg];
1251 }
1252 /* Emulation takes no time to finish MDI transaction.
1253 * Set MDI bit in SCB status register. */
1254 s->mem[SCBAck] |= 0x08;
1255 val |= BIT(28);
1256 if (raiseint) {
1257 eepro100_mdi_interrupt(s);
1258 }
1259 }
1260 val = (val & 0xffff0000) + data;
1261 memcpy(&s->mem[0x10], &val, sizeof(val));
1262 }
1263
1264 /*****************************************************************************
1265 *
1266 * Port emulation.
1267 *
1268 ****************************************************************************/
1269
1270 #define PORT_SOFTWARE_RESET 0
1271 #define PORT_SELFTEST 1
1272 #define PORT_SELECTIVE_RESET 2
1273 #define PORT_DUMP 3
1274 #define PORT_SELECTION_MASK 3
1275
1276 typedef struct {
1277 uint32_t st_sign; /* Self Test Signature */
1278 uint32_t st_result; /* Self Test Results */
1279 } eepro100_selftest_t;
1280
1281 static uint32_t eepro100_read_port(EEPRO100State * s)
1282 {
1283 return 0;
1284 }
1285
1286 static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1287 {
1288 val = le32_to_cpu(val);
1289 uint32_t address = (val & ~PORT_SELECTION_MASK);
1290 uint8_t selection = (val & PORT_SELECTION_MASK);
1291 switch (selection) {
1292 case PORT_SOFTWARE_RESET:
1293 nic_reset(s);
1294 break;
1295 case PORT_SELFTEST:
1296 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1297 eepro100_selftest_t data;
1298 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1299 data.st_sign = 0xffffffff;
1300 data.st_result = 0;
1301 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1302 break;
1303 case PORT_SELECTIVE_RESET:
1304 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1305 nic_selective_reset(s);
1306 break;
1307 default:
1308 logout("val=0x%08x\n", val);
1309 missing("unknown port selection");
1310 }
1311 }
1312
1313 /*****************************************************************************
1314 *
1315 * General hardware emulation.
1316 *
1317 ****************************************************************************/
1318
1319 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1320 {
1321 uint8_t val;
1322 if (addr <= sizeof(s->mem) - sizeof(val)) {
1323 memcpy(&val, &s->mem[addr], sizeof(val));
1324 }
1325
1326 switch (addr) {
1327 case SCBStatus:
1328 //~ val = eepro100_read_status(s);
1329 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1330 break;
1331 case SCBAck:
1332 //~ val = eepro100_read_status(s);
1333 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1334 break;
1335 case SCBCmd:
1336 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1337 //~ val = eepro100_read_command(s);
1338 break;
1339 case SCBIntmask:
1340 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1341 break;
1342 case SCBPort + 3:
1343 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1344 break;
1345 case SCBeeprom:
1346 val = eepro100_read_eeprom(s);
1347 break;
1348 case SCBpmdr: /* Power Management Driver Register */
1349 val = 0;
1350 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1351 break;
1352 case SCBgstat: /* General Status Register */
1353 /* 100 Mbps full duplex, valid link */
1354 val = 0x07;
1355 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1356 break;
1357 default:
1358 logout("addr=%s val=0x%02x\n", regname(addr), val);
1359 missing("unknown byte read");
1360 }
1361 return val;
1362 }
1363
1364 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1365 {
1366 uint16_t val;
1367 if (addr <= sizeof(s->mem) - sizeof(val)) {
1368 memcpy(&val, &s->mem[addr], sizeof(val));
1369 }
1370
1371 switch (addr) {
1372 case SCBStatus:
1373 //~ val = eepro100_read_status(s);
1374 case SCBCmd:
1375 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1376 break;
1377 case SCBeeprom:
1378 val = eepro100_read_eeprom(s);
1379 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1380 break;
1381 default:
1382 logout("addr=%s val=0x%04x\n", regname(addr), val);
1383 missing("unknown word read");
1384 }
1385 return val;
1386 }
1387
1388 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1389 {
1390 uint32_t val;
1391 if (addr <= sizeof(s->mem) - sizeof(val)) {
1392 memcpy(&val, &s->mem[addr], sizeof(val));
1393 }
1394
1395 switch (addr) {
1396 case SCBStatus:
1397 //~ val = eepro100_read_status(s);
1398 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1399 break;
1400 case SCBPointer:
1401 //~ val = eepro100_read_pointer(s);
1402 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1403 break;
1404 case SCBPort:
1405 val = eepro100_read_port(s);
1406 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1407 break;
1408 case SCBCtrlMDI:
1409 val = eepro100_read_mdi(s);
1410 break;
1411 default:
1412 logout("addr=%s val=0x%08x\n", regname(addr), val);
1413 missing("unknown longword read");
1414 }
1415 return val;
1416 }
1417
1418 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1419 {
1420 if (addr <= sizeof(s->mem) - sizeof(val)) {
1421 memcpy(&s->mem[addr], &val, sizeof(val));
1422 }
1423
1424 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1425
1426 switch (addr) {
1427 case SCBStatus:
1428 //~ eepro100_write_status(s, val);
1429 break;
1430 case SCBAck:
1431 eepro100_acknowledge(s);
1432 break;
1433 case SCBCmd:
1434 eepro100_write_command(s, val);
1435 break;
1436 case SCBIntmask:
1437 if (val & BIT(1)) {
1438 eepro100_swi_interrupt(s);
1439 }
1440 eepro100_interrupt(s, 0);
1441 break;
1442 case SCBPort + 3:
1443 case SCBFlow: /* does not exist on 82557 */
1444 case SCBFlow + 1:
1445 case SCBFlow + 2:
1446 case SCBpmdr: /* does not exist on 82557 */
1447 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1448 break;
1449 case SCBeeprom:
1450 eepro100_write_eeprom(s->eeprom, val);
1451 break;
1452 default:
1453 logout("addr=%s val=0x%02x\n", regname(addr), val);
1454 missing("unknown byte write");
1455 }
1456 }
1457
1458 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1459 {
1460 if (addr <= sizeof(s->mem) - sizeof(val)) {
1461 memcpy(&s->mem[addr], &val, sizeof(val));
1462 }
1463
1464 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1465
1466 switch (addr) {
1467 case SCBStatus:
1468 //~ eepro100_write_status(s, val);
1469 eepro100_acknowledge(s);
1470 break;
1471 case SCBCmd:
1472 eepro100_write_command(s, val);
1473 eepro100_write1(s, SCBIntmask, val >> 8);
1474 break;
1475 case SCBeeprom:
1476 eepro100_write_eeprom(s->eeprom, val);
1477 break;
1478 default:
1479 logout("addr=%s val=0x%04x\n", regname(addr), val);
1480 missing("unknown word write");
1481 }
1482 }
1483
1484 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1485 {
1486 if (addr <= sizeof(s->mem) - sizeof(val)) {
1487 memcpy(&s->mem[addr], &val, sizeof(val));
1488 }
1489
1490 switch (addr) {
1491 case SCBPointer:
1492 eepro100_write_pointer(s, val);
1493 break;
1494 case SCBPort:
1495 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1496 eepro100_write_port(s, val);
1497 break;
1498 case SCBCtrlMDI:
1499 eepro100_write_mdi(s, val);
1500 break;
1501 default:
1502 logout("addr=%s val=0x%08x\n", regname(addr), val);
1503 missing("unknown longword write");
1504 }
1505 }
1506
1507 /*****************************************************************************
1508 *
1509 * Port mapped I/O.
1510 *
1511 ****************************************************************************/
1512
1513 static uint32_t ioport_read1(void *opaque, uint32_t addr)
1514 {
1515 EEPRO100State *s = opaque;
1516 //~ logout("addr=%s\n", regname(addr));
1517 return eepro100_read1(s, addr - s->region[1]);
1518 }
1519
1520 static uint32_t ioport_read2(void *opaque, uint32_t addr)
1521 {
1522 EEPRO100State *s = opaque;
1523 return eepro100_read2(s, addr - s->region[1]);
1524 }
1525
1526 static uint32_t ioport_read4(void *opaque, uint32_t addr)
1527 {
1528 EEPRO100State *s = opaque;
1529 return eepro100_read4(s, addr - s->region[1]);
1530 }
1531
1532 static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1533 {
1534 EEPRO100State *s = opaque;
1535 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1536 eepro100_write1(s, addr - s->region[1], val);
1537 }
1538
1539 static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1540 {
1541 EEPRO100State *s = opaque;
1542 eepro100_write2(s, addr - s->region[1], val);
1543 }
1544
1545 static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1546 {
1547 EEPRO100State *s = opaque;
1548 eepro100_write4(s, addr - s->region[1], val);
1549 }
1550
1551 /***********************************************************/
1552 /* PCI EEPRO100 definitions */
1553
1554 static void pci_map(PCIDevice * pci_dev, int region_num,
1555 pcibus_t addr, pcibus_t size, int type)
1556 {
1557 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1558
1559 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1560 "size=0x%08"FMT_PCIBUS", type=%d\n",
1561 region_num, addr, size, type));
1562
1563 assert(region_num == 1);
1564 register_ioport_write(addr, size, 1, ioport_write1, s);
1565 register_ioport_read(addr, size, 1, ioport_read1, s);
1566 register_ioport_write(addr, size, 2, ioport_write2, s);
1567 register_ioport_read(addr, size, 2, ioport_read2, s);
1568 register_ioport_write(addr, size, 4, ioport_write4, s);
1569 register_ioport_read(addr, size, 4, ioport_read4, s);
1570
1571 s->region[region_num] = addr;
1572 }
1573
1574 /*****************************************************************************
1575 *
1576 * Memory mapped I/O.
1577 *
1578 ****************************************************************************/
1579
1580 static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1581 {
1582 EEPRO100State *s = opaque;
1583 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1584 eepro100_write1(s, addr, val);
1585 }
1586
1587 static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1588 {
1589 EEPRO100State *s = opaque;
1590 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1591 eepro100_write2(s, addr, val);
1592 }
1593
1594 static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1595 {
1596 EEPRO100State *s = opaque;
1597 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1598 eepro100_write4(s, addr, val);
1599 }
1600
1601 static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1602 {
1603 EEPRO100State *s = opaque;
1604 //~ logout("addr=%s\n", regname(addr));
1605 return eepro100_read1(s, addr);
1606 }
1607
1608 static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1609 {
1610 EEPRO100State *s = opaque;
1611 //~ logout("addr=%s\n", regname(addr));
1612 return eepro100_read2(s, addr);
1613 }
1614
1615 static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1616 {
1617 EEPRO100State *s = opaque;
1618 //~ logout("addr=%s\n", regname(addr));
1619 return eepro100_read4(s, addr);
1620 }
1621
1622 static CPUWriteMemoryFunc * const pci_mmio_write[] = {
1623 pci_mmio_writeb,
1624 pci_mmio_writew,
1625 pci_mmio_writel
1626 };
1627
1628 static CPUReadMemoryFunc * const pci_mmio_read[] = {
1629 pci_mmio_readb,
1630 pci_mmio_readw,
1631 pci_mmio_readl
1632 };
1633
1634 static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
1635 pcibus_t addr, pcibus_t size, int type)
1636 {
1637 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1638
1639 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1640 "size=0x%08"FMT_PCIBUS", type=%d\n",
1641 region_num, addr, size, type));
1642
1643 if (region_num == 0) {
1644 /* Map control / status registers. */
1645 cpu_register_physical_memory(addr, size, s->mmio_index);
1646 s->region[region_num] = addr;
1647 }
1648 }
1649
1650 static int nic_can_receive(VLANClientState *nc)
1651 {
1652 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1653 TRACE(RXTX, logout("%p\n", s));
1654 return get_ru_state(s) == ru_ready;
1655 //~ return !eepro100_buffer_full(s);
1656 }
1657
1658 static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
1659 {
1660 /* TODO:
1661 * - Magic packets should set bit 30 in power management driver register.
1662 * - Interesting packets should set bit 29 in power management driver register.
1663 */
1664 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1665 uint16_t rfd_status = 0xa000;
1666 static const uint8_t broadcast_macaddr[6] =
1667 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1668
1669 /* TODO: check multiple IA bit. */
1670 if (s->configuration[20] & BIT(6)) {
1671 missing("Multiple IA bit");
1672 return -1;
1673 }
1674
1675 if (s->configuration[8] & 0x80) {
1676 /* CSMA is disabled. */
1677 logout("%p received while CSMA is disabled\n", s);
1678 return -1;
1679 } else if (size < 64 && (s->configuration[7] & 1)) {
1680 /* Short frame and configuration byte 7/0 (discard short receive) set:
1681 * Short frame is discarded */
1682 logout("%p received short frame (%zu byte)\n", s, size);
1683 s->statistics.rx_short_frame_errors++;
1684 //~ return -1;
1685 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) {
1686 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1687 * Long frames are discarded. */
1688 logout("%p received long frame (%zu byte), ignored\n", s, size);
1689 return -1;
1690 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { // !!!
1691 /* Frame matches individual address. */
1692 /* TODO: check configuration byte 15/4 (ignore U/L). */
1693 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1694 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1695 /* Broadcast frame. */
1696 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1697 rfd_status |= 0x0002;
1698 } else if (buf[0] & 0x01) {
1699 /* Multicast frame. */
1700 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1701 if (s->configuration[21] & BIT(3)) {
1702 /* Multicast all bit is set, receive all multicast frames. */
1703 } else {
1704 unsigned mcast_idx = compute_mcast_idx(buf);
1705 assert(mcast_idx < 64);
1706 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1707 /* Multicast frame is allowed in hash table. */
1708 } else if (s->configuration[15] & 1) {
1709 /* Promiscuous: receive all. */
1710 rfd_status |= 0x0004;
1711 } else {
1712 TRACE(RXTX, logout("%p multicast ignored\n", s));
1713 return -1;
1714 }
1715 }
1716 /* TODO: Next not for promiscuous mode? */
1717 rfd_status |= 0x0002;
1718 } else if (s->configuration[15] & 1) {
1719 /* Promiscuous: receive all. */
1720 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1721 rfd_status |= 0x0004;
1722 } else {
1723 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1724 nic_dump(buf, size)));
1725 return size;
1726 }
1727
1728 if (get_ru_state(s) != ru_ready) {
1729 /* No resources available. */
1730 logout("no resources, state=%u\n", get_ru_state(s));
1731 s->statistics.rx_resource_errors++;
1732 //~ assert(!"no resources");
1733 return -1;
1734 }
1735 //~ !!!
1736 //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
1737 eepro100_rx_t rx;
1738 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
1739 offsetof(eepro100_rx_t, packet));
1740 uint16_t rfd_command = le16_to_cpu(rx.command);
1741 uint16_t rfd_size = le16_to_cpu(rx.size);
1742
1743 if (size > rfd_size) {
1744 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1745 "(%zu bytes); data truncated\n", rfd_size, size);
1746 size = rfd_size;
1747 }
1748 if (size < 64) {
1749 rfd_status |= 0x0080;
1750 }
1751 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1752 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1753 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
1754 rfd_status);
1755 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
1756 /* Early receive interrupt not supported. */
1757 //~ eepro100_er_interrupt(s);
1758 /* Receive CRC Transfer not supported. */
1759 if (s->configuration[18] & 4) {
1760 missing("Receive CRC Transfer");
1761 return -1;
1762 }
1763 /* TODO: check stripping enable bit. */
1764 //~ assert(!(s->configuration[17] & 1));
1765 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1766 offsetof(eepro100_rx_t, packet), buf, size);
1767 s->statistics.rx_good_frames++;
1768 eepro100_fr_interrupt(s);
1769 s->ru_offset = le32_to_cpu(rx.link);
1770 if (rfd_command & 0x8000) {
1771 /* EL bit is set, so this was the last frame. */
1772 logout("receive: Running out of frames\n");
1773 set_ru_state(s, ru_suspended);
1774 }
1775 if (rfd_command & 0x4000) {
1776 /* S bit is set. */
1777 set_ru_state(s, ru_suspended);
1778 }
1779 return size;
1780 }
1781
1782 static const VMStateDescription vmstate_eepro100 = {
1783 .version_id = 3,
1784 .minimum_version_id = 2,
1785 .minimum_version_id_old = 2,
1786 .fields = (VMStateField []) {
1787 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1788 VMSTATE_UNUSED(32),
1789 VMSTATE_BUFFER(mult, EEPRO100State),
1790 VMSTATE_BUFFER(mem, EEPRO100State),
1791 /* Save all members of struct between scb_stat and mem. */
1792 VMSTATE_UINT8(scb_stat, EEPRO100State),
1793 VMSTATE_UINT8(int_stat, EEPRO100State),
1794 VMSTATE_UNUSED(3*4),
1795 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1796 VMSTATE_UNUSED(19*4),
1797 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1798 /* The eeprom should be saved and restored by its own routines. */
1799 VMSTATE_UINT32(device, EEPRO100State),
1800 /* TODO check device. */
1801 VMSTATE_UINT32(pointer, EEPRO100State),
1802 VMSTATE_UINT32(cu_base, EEPRO100State),
1803 VMSTATE_UINT32(cu_offset, EEPRO100State),
1804 VMSTATE_UINT32(ru_base, EEPRO100State),
1805 VMSTATE_UINT32(ru_offset, EEPRO100State),
1806 VMSTATE_UINT32(statsaddr, EEPRO100State),
1807 /* Save eepro100_stats_t statistics. */
1808 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1809 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1810 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1811 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1812 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1813 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1814 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1815 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1816 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1817 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1818 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1819 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1820 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1821 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1822 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1823 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1824 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1825 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1826 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1827 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1828 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1829 #if 0
1830 VMSTATE_UINT16(status, EEPRO100State),
1831 #endif
1832 /* Configuration bytes. */
1833 VMSTATE_BUFFER(configuration, EEPRO100State),
1834 VMSTATE_END_OF_LIST()
1835 }
1836 };
1837
1838 static void nic_cleanup(VLANClientState *nc)
1839 {
1840 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1841
1842 s->nic = NULL;
1843 }
1844
1845 static int pci_nic_uninit(PCIDevice *pci_dev)
1846 {
1847 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1848
1849 cpu_unregister_io_memory(s->mmio_index);
1850 vmstate_unregister(s->vmstate, s);
1851 eeprom93xx_free(s->eeprom);
1852 qemu_del_vlan_client(&s->nic->nc);
1853 return 0;
1854 }
1855
1856 static NetClientInfo net_eepro100_info = {
1857 .type = NET_CLIENT_TYPE_NIC,
1858 .size = sizeof(NICState),
1859 .can_receive = nic_can_receive,
1860 .receive = nic_receive,
1861 .cleanup = nic_cleanup,
1862 };
1863
1864 static int nic_init(PCIDevice *pci_dev, uint32_t device)
1865 {
1866 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1867
1868 TRACE(OTHER, logout("\n"));
1869
1870 s->device = device;
1871
1872 pci_reset(s);
1873
1874 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1875 * i82559 and later support 64 or 256 word EEPROM. */
1876 s->eeprom = eeprom93xx_new(EEPROM_SIZE);
1877
1878 /* Handler for memory-mapped I/O */
1879 s->mmio_index =
1880 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
1881
1882 pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
1883 PCI_BASE_ADDRESS_SPACE_MEMORY |
1884 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map);
1885 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
1886 pci_map);
1887 pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
1888 pci_mmio_map);
1889
1890 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1891 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1892 assert(s->region[1] == 0);
1893
1894 nic_reset(s);
1895
1896 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1897 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
1898
1899 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1900 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
1901
1902 qemu_register_reset(nic_reset, s);
1903
1904 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1905 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1906 s->vmstate->name = s->nic->nc.model;
1907 vmstate_register(-1, s->vmstate, s);
1908
1909 return 0;
1910 }
1911
1912 static int pci_i82550_init(PCIDevice *pci_dev)
1913 {
1914 return nic_init(pci_dev, i82550);
1915 }
1916
1917 static int pci_i82551_init(PCIDevice *pci_dev)
1918 {
1919 return nic_init(pci_dev, i82551);
1920 }
1921
1922 static int pci_i82557a_init(PCIDevice *pci_dev)
1923 {
1924 return nic_init(pci_dev, i82557A);
1925 }
1926
1927 static int pci_i82557b_init(PCIDevice *pci_dev)
1928 {
1929 return nic_init(pci_dev, i82557B);
1930 }
1931
1932 static int pci_i82557c_init(PCIDevice *pci_dev)
1933 {
1934 return nic_init(pci_dev, i82557C);
1935 }
1936
1937 static int pci_i82558a_init(PCIDevice *pci_dev)
1938 {
1939 return nic_init(pci_dev, i82558A);
1940 }
1941
1942 static int pci_i82558b_init(PCIDevice *pci_dev)
1943 {
1944 return nic_init(pci_dev, i82558B);
1945 }
1946
1947 static int pci_i82559a_init(PCIDevice *pci_dev)
1948 {
1949 return nic_init(pci_dev, i82559A);
1950 }
1951
1952 static int pci_i82559b_init(PCIDevice *pci_dev)
1953 {
1954 return nic_init(pci_dev, i82559B);
1955 }
1956
1957 static int pci_i82559c_init(PCIDevice *pci_dev)
1958 {
1959 return nic_init(pci_dev, i82559C);
1960 }
1961
1962 static int pci_i82559er_init(PCIDevice *pci_dev)
1963 {
1964 return nic_init(pci_dev, i82559ER);
1965 }
1966
1967 static int pci_i82562_init(PCIDevice *pci_dev)
1968 {
1969 return nic_init(pci_dev, i82562);
1970 }
1971
1972 static PCIDeviceInfo eepro100_info[] = {
1973 {
1974 .qdev.name = "i82550",
1975 .qdev.size = sizeof(EEPRO100State),
1976 .init = pci_i82550_init,
1977 .exit = pci_nic_uninit,
1978 .qdev.props = (Property[]) {
1979 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1980 DEFINE_PROP_END_OF_LIST(),
1981 },
1982 },{
1983 .qdev.name = "i82551",
1984 .qdev.size = sizeof(EEPRO100State),
1985 .init = pci_i82551_init,
1986 .exit = pci_nic_uninit,
1987 .qdev.props = (Property[]) {
1988 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1989 DEFINE_PROP_END_OF_LIST(),
1990 },
1991 },{
1992 .qdev.name = "i82557a",
1993 .qdev.size = sizeof(EEPRO100State),
1994 .init = pci_i82557a_init,
1995 .exit = pci_nic_uninit,
1996 .qdev.props = (Property[]) {
1997 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1998 DEFINE_PROP_END_OF_LIST(),
1999 },
2000 },{
2001 .qdev.name = "i82557b",
2002 .qdev.size = sizeof(EEPRO100State),
2003 .init = pci_i82557b_init,
2004 .exit = pci_nic_uninit,
2005 .qdev.props = (Property[]) {
2006 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2007 DEFINE_PROP_END_OF_LIST(),
2008 },
2009 },{
2010 .qdev.name = "i82557c",
2011 .qdev.size = sizeof(EEPRO100State),
2012 .init = pci_i82557c_init,
2013 .exit = pci_nic_uninit,
2014 .qdev.props = (Property[]) {
2015 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2016 DEFINE_PROP_END_OF_LIST(),
2017 },
2018 },{
2019 .qdev.name = "i82558a",
2020 .qdev.size = sizeof(EEPRO100State),
2021 .init = pci_i82558a_init,
2022 .exit = pci_nic_uninit,
2023 .qdev.props = (Property[]) {
2024 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2025 DEFINE_PROP_END_OF_LIST(),
2026 },
2027 },{
2028 .qdev.name = "i82558b",
2029 .qdev.size = sizeof(EEPRO100State),
2030 .init = pci_i82558b_init,
2031 .exit = pci_nic_uninit,
2032 .qdev.props = (Property[]) {
2033 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2034 DEFINE_PROP_END_OF_LIST(),
2035 },
2036 },{
2037 .qdev.name = "i82559a",
2038 .qdev.size = sizeof(EEPRO100State),
2039 .init = pci_i82559a_init,
2040 .exit = pci_nic_uninit,
2041 .qdev.props = (Property[]) {
2042 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2043 DEFINE_PROP_END_OF_LIST(),
2044 },
2045 },{
2046 .qdev.name = "i82559b",
2047 .qdev.size = sizeof(EEPRO100State),
2048 .init = pci_i82559b_init,
2049 .exit = pci_nic_uninit,
2050 .qdev.props = (Property[]) {
2051 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2052 DEFINE_PROP_END_OF_LIST(),
2053 },
2054 },{
2055 .qdev.name = "i82559c",
2056 .qdev.size = sizeof(EEPRO100State),
2057 .init = pci_i82559c_init,
2058 .exit = pci_nic_uninit,
2059 .qdev.props = (Property[]) {
2060 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2061 DEFINE_PROP_END_OF_LIST(),
2062 },
2063 },{
2064 .qdev.name = "i82559er",
2065 .qdev.size = sizeof(EEPRO100State),
2066 .init = pci_i82559er_init,
2067 .exit = pci_nic_uninit,
2068 .romfile = "pxe-i82559er.bin",
2069 .qdev.props = (Property[]) {
2070 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2071 DEFINE_PROP_END_OF_LIST(),
2072 },
2073 },{
2074 .qdev.name = "i82562",
2075 .qdev.size = sizeof(EEPRO100State),
2076 .init = pci_i82562_init,
2077 .exit = pci_nic_uninit,
2078 .qdev.props = (Property[]) {
2079 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2080 DEFINE_PROP_END_OF_LIST(),
2081 },
2082 },{
2083 /* end of list */
2084 }
2085 };
2086
2087 static void eepro100_register_devices(void)
2088 {
2089 pci_qdev_register_many(eepro100_info);
2090 }
2091
2092 device_init(eepro100_register_devices)
QEmu