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hw/ppc/spapr: Add some missing hcall function set strings
[qemu.git] / hw / ppc / spapr.c
blobd26b4c26ed1022f1e88ff9c5efcd1fc8fb2d03d7
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/numa.h"
31 #include "hw/hw.h"
32 #include "qemu/log.h"
33 #include "hw/fw-path-provider.h"
34 #include "elf.h"
35 #include "net/net.h"
36 #include "sysemu/device_tree.h"
37 #include "sysemu/block-backend.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/kvm.h"
40 #include "sysemu/device_tree.h"
41 #include "kvm_ppc.h"
42 #include "migration/migration.h"
43 #include "mmu-hash64.h"
44 #include "qom/cpu.h"
45
46 #include "hw/boards.h"
47 #include "hw/ppc/ppc.h"
48 #include "hw/loader.h"
49
50 #include "hw/ppc/spapr.h"
51 #include "hw/ppc/spapr_vio.h"
52 #include "hw/pci-host/spapr.h"
53 #include "hw/ppc/xics.h"
54 #include "hw/pci/msi.h"
55
56 #include "hw/pci/pci.h"
57 #include "hw/scsi/scsi.h"
58 #include "hw/virtio/virtio-scsi.h"
59
60 #include "exec/address-spaces.h"
61 #include "hw/usb.h"
62 #include "qemu/config-file.h"
63 #include "qemu/error-report.h"
64 #include "trace.h"
65 #include "hw/nmi.h"
66
67 #include "hw/compat.h"
68 #include "qemu/cutils.h"
69 #include "hw/ppc/spapr_cpu_core.h"
70 #include "qmp-commands.h"
71
72 #include <libfdt.h>
73
74 /* SLOF memory layout:
75 *
76 * SLOF raw image loaded at 0, copies its romfs right below the flat
77 * device-tree, then position SLOF itself 31M below that
78 *
79 * So we set FW_OVERHEAD to 40MB which should account for all of that
80 * and more
81 *
82 * We load our kernel at 4M, leaving space for SLOF initial image
83 */
84 #define FDT_MAX_SIZE 0x100000
85 #define RTAS_MAX_SIZE 0x10000
86 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
87 #define FW_MAX_SIZE 0x400000
88 #define FW_FILE_NAME "slof.bin"
89 #define FW_OVERHEAD 0x2800000
90 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
91
92 #define MIN_RMA_SLOF 128UL
93
94 #define PHANDLE_XICP 0x00001111
95
96 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
97
98 static XICSState *try_create_xics(const char *type, int nr_servers,
99 int nr_irqs, Error **errp)
100 {
101 Error *err = NULL;
102 DeviceState *dev;
103
104 dev = qdev_create(NULL, type);
105 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
106 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
107 object_property_set_bool(OBJECT(dev), true, "realized", &err);
108 if (err) {
109 error_propagate(errp, err);
110 object_unparent(OBJECT(dev));
111 return NULL;
112 }
113 return XICS_COMMON(dev);
114 }
115
116 static XICSState *xics_system_init(MachineState *machine,
117 int nr_servers, int nr_irqs, Error **errp)
118 {
119 XICSState *icp = NULL;
120
121 if (kvm_enabled()) {
122 Error *err = NULL;
123
124 if (machine_kernel_irqchip_allowed(machine)) {
125 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err);
126 }
127 if (machine_kernel_irqchip_required(machine) && !icp) {
128 error_reportf_err(err,
129 "kernel_irqchip requested but unavailable: ");
130 } else {
131 error_free(err);
132 }
133 }
134
135 if (!icp) {
136 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, errp);
137 }
138
139 return icp;
140 }
141
142 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
143 int smt_threads)
144 {
145 int i, ret = 0;
146 uint32_t servers_prop[smt_threads];
147 uint32_t gservers_prop[smt_threads * 2];
148 int index = ppc_get_vcpu_dt_id(cpu);
149
150 if (cpu->cpu_version) {
151 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version);
152 if (ret < 0) {
153 return ret;
154 }
155 }
156
157 /* Build interrupt servers and gservers properties */
158 for (i = 0; i < smt_threads; i++) {
159 servers_prop[i] = cpu_to_be32(index + i);
160 /* Hack, direct the group queues back to cpu 0 */
161 gservers_prop[i*2] = cpu_to_be32(index + i);
162 gservers_prop[i*2 + 1] = 0;
163 }
164 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
165 servers_prop, sizeof(servers_prop));
166 if (ret < 0) {
167 return ret;
168 }
169 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
170 gservers_prop, sizeof(gservers_prop));
171
172 return ret;
173 }
174
175 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
176 {
177 int ret = 0;
178 PowerPCCPU *cpu = POWERPC_CPU(cs);
179 int index = ppc_get_vcpu_dt_id(cpu);
180 uint32_t associativity[] = {cpu_to_be32(0x5),
181 cpu_to_be32(0x0),
182 cpu_to_be32(0x0),
183 cpu_to_be32(0x0),
184 cpu_to_be32(cs->numa_node),
185 cpu_to_be32(index)};
186
187 /* Advertise NUMA via ibm,associativity */
188 if (nb_numa_nodes > 1) {
189 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
190 sizeof(associativity));
191 }
192
193 return ret;
194 }
195
196 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
197 {
198 int ret = 0, offset, cpus_offset;
199 CPUState *cs;
200 char cpu_model[32];
201 int smt = kvmppc_smt_threads();
202 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
203
204 CPU_FOREACH(cs) {
205 PowerPCCPU *cpu = POWERPC_CPU(cs);
206 DeviceClass *dc = DEVICE_GET_CLASS(cs);
207 int index = ppc_get_vcpu_dt_id(cpu);
208
209 if ((index % smt) != 0) {
210 continue;
211 }
212
213 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
214
215 cpus_offset = fdt_path_offset(fdt, "/cpus");
216 if (cpus_offset < 0) {
217 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
218 "cpus");
219 if (cpus_offset < 0) {
220 return cpus_offset;
221 }
222 }
223 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
224 if (offset < 0) {
225 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
226 if (offset < 0) {
227 return offset;
228 }
229 }
230
231 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
232 pft_size_prop, sizeof(pft_size_prop));
233 if (ret < 0) {
234 return ret;
235 }
236
237 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
238 if (ret < 0) {
239 return ret;
240 }
241
242 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
243 ppc_get_compat_smt_threads(cpu));
244 if (ret < 0) {
245 return ret;
246 }
247 }
248 return ret;
249 }
250
251
252 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
253 size_t maxsize)
254 {
255 size_t maxcells = maxsize / sizeof(uint32_t);
256 int i, j, count;
257 uint32_t *p = prop;
258
259 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
260 struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
261
262 if (!sps->page_shift) {
263 break;
264 }
265 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) {
266 if (sps->enc[count].page_shift == 0) {
267 break;
268 }
269 }
270 if ((p - prop) >= (maxcells - 3 - count * 2)) {
271 break;
272 }
273 *(p++) = cpu_to_be32(sps->page_shift);
274 *(p++) = cpu_to_be32(sps->slb_enc);
275 *(p++) = cpu_to_be32(count);
276 for (j = 0; j < count; j++) {
277 *(p++) = cpu_to_be32(sps->enc[j].page_shift);
278 *(p++) = cpu_to_be32(sps->enc[j].pte_enc);
279 }
280 }
281
282 return (p - prop) * sizeof(uint32_t);
283 }
284
285 static hwaddr spapr_node0_size(void)
286 {
287 MachineState *machine = MACHINE(qdev_get_machine());
288
289 if (nb_numa_nodes) {
290 int i;
291 for (i = 0; i < nb_numa_nodes; ++i) {
292 if (numa_info[i].node_mem) {
293 return MIN(pow2floor(numa_info[i].node_mem),
294 machine->ram_size);
295 }
296 }
297 }
298 return machine->ram_size;
299 }
300
301 #define _FDT(exp) \
302 do { \
303 int ret = (exp); \
304 if (ret < 0) { \
305 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
306 #exp, fdt_strerror(ret)); \
307 exit(1); \
308 } \
309 } while (0)
310
311 static void add_str(GString *s, const gchar *s1)
312 {
313 g_string_append_len(s, s1, strlen(s1) + 1);
314 }
315
316 static void *spapr_create_fdt_skel(hwaddr initrd_base,
317 hwaddr initrd_size,
318 hwaddr kernel_size,
319 bool little_endian,
320 const char *kernel_cmdline,
321 uint32_t epow_irq)
322 {
323 void *fdt;
324 uint32_t start_prop = cpu_to_be32(initrd_base);
325 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
326 GString *hypertas = g_string_sized_new(256);
327 GString *qemu_hypertas = g_string_sized_new(256);
328 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
329 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)};
330 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
331 char *buf;
332
333 add_str(hypertas, "hcall-pft");
334 add_str(hypertas, "hcall-term");
335 add_str(hypertas, "hcall-dabr");
336 add_str(hypertas, "hcall-interrupt");
337 add_str(hypertas, "hcall-tce");
338 add_str(hypertas, "hcall-vio");
339 add_str(hypertas, "hcall-splpar");
340 add_str(hypertas, "hcall-bulk");
341 add_str(hypertas, "hcall-set-mode");
342 add_str(hypertas, "hcall-sprg0");
343 add_str(hypertas, "hcall-copy");
344 add_str(hypertas, "hcall-debug");
345 add_str(qemu_hypertas, "hcall-memop1");
346
347 fdt = g_malloc0(FDT_MAX_SIZE);
348 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
349
350 if (kernel_size) {
351 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
352 }
353 if (initrd_size) {
354 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
355 }
356 _FDT((fdt_finish_reservemap(fdt)));
357
358 /* Root node */
359 _FDT((fdt_begin_node(fdt, "")));
360 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
361 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
362 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries")));
363
364 /*
365 * Add info to guest to indentify which host is it being run on
366 * and what is the uuid of the guest
367 */
368 if (kvmppc_get_host_model(&buf)) {
369 _FDT((fdt_property_string(fdt, "host-model", buf)));
370 g_free(buf);
371 }
372 if (kvmppc_get_host_serial(&buf)) {
373 _FDT((fdt_property_string(fdt, "host-serial", buf)));
374 g_free(buf);
375 }
376
377 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1],
378 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4],
379 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7],
380 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10],
381 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13],
382 qemu_uuid[14], qemu_uuid[15]);
383
384 _FDT((fdt_property_string(fdt, "vm,uuid", buf)));
385 if (qemu_uuid_set) {
386 _FDT((fdt_property_string(fdt, "system-id", buf)));
387 }
388 g_free(buf);
389
390 if (qemu_get_vm_name()) {
391 _FDT((fdt_property_string(fdt, "ibm,partition-name",
392 qemu_get_vm_name())));
393 }
394
395 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
396 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
397
398 /* /chosen */
399 _FDT((fdt_begin_node(fdt, "chosen")));
400
401 /* Set Form1_affinity */
402 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
403
404 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
405 _FDT((fdt_property(fdt, "linux,initrd-start",
406 &start_prop, sizeof(start_prop))));
407 _FDT((fdt_property(fdt, "linux,initrd-end",
408 &end_prop, sizeof(end_prop))));
409 if (kernel_size) {
410 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
411 cpu_to_be64(kernel_size) };
412
413 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
414 if (little_endian) {
415 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0)));
416 }
417 }
418 if (boot_menu) {
419 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu)));
420 }
421 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
422 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
423 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
424
425 _FDT((fdt_end_node(fdt)));
426
427 /* RTAS */
428 _FDT((fdt_begin_node(fdt, "rtas")));
429
430 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
431 add_str(hypertas, "hcall-multi-tce");
432 }
433 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str,
434 hypertas->len)));
435 g_string_free(hypertas, TRUE);
436 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str,
437 qemu_hypertas->len)));
438 g_string_free(qemu_hypertas, TRUE);
439
440 _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
441 refpoints, sizeof(refpoints))));
442
443 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
444 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate",
445 RTAS_EVENT_SCAN_RATE)));
446
447 if (msi_nonbroken) {
448 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0)));
449 }
450
451 /*
452 * According to PAPR, rtas ibm,os-term does not guarantee a return
453 * back to the guest cpu.
454 *
455 * While an additional ibm,extended-os-term property indicates that
456 * rtas call return will always occur. Set this property.
457 */
458 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0)));
459
460 _FDT((fdt_end_node(fdt)));
461
462 /* interrupt controller */
463 _FDT((fdt_begin_node(fdt, "interrupt-controller")));
464
465 _FDT((fdt_property_string(fdt, "device_type",
466 "PowerPC-External-Interrupt-Presentation")));
467 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
468 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
469 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
470 interrupt_server_ranges_prop,
471 sizeof(interrupt_server_ranges_prop))));
472 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
473 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
474 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
475
476 _FDT((fdt_end_node(fdt)));
477
478 /* vdevice */
479 _FDT((fdt_begin_node(fdt, "vdevice")));
480
481 _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
482 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
483 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
484 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
485 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
486 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
487
488 _FDT((fdt_end_node(fdt)));
489
490 /* event-sources */
491 spapr_events_fdt_skel(fdt, epow_irq);
492
493 /* /hypervisor node */
494 if (kvm_enabled()) {
495 uint8_t hypercall[16];
496
497 /* indicate KVM hypercall interface */
498 _FDT((fdt_begin_node(fdt, "hypervisor")));
499 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm")));
500 if (kvmppc_has_cap_fixup_hcalls()) {
501 /*
502 * Older KVM versions with older guest kernels were broken with the
503 * magic page, don't allow the guest to map it.
504 */
505 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
506 sizeof(hypercall))) {
507 _FDT((fdt_property(fdt, "hcall-instructions", hypercall,
508 sizeof(hypercall))));
509 }
510 }
511 _FDT((fdt_end_node(fdt)));
512 }
513
514 _FDT((fdt_end_node(fdt))); /* close root node */
515 _FDT((fdt_finish(fdt)));
516
517 return fdt;
518 }
519
520 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
521 hwaddr size)
522 {
523 uint32_t associativity[] = {
524 cpu_to_be32(0x4), /* length */
525 cpu_to_be32(0x0), cpu_to_be32(0x0),
526 cpu_to_be32(0x0), cpu_to_be32(nodeid)
527 };
528 char mem_name[32];
529 uint64_t mem_reg_property[2];
530 int off;
531
532 mem_reg_property[0] = cpu_to_be64(start);
533 mem_reg_property[1] = cpu_to_be64(size);
534
535 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
536 off = fdt_add_subnode(fdt, 0, mem_name);
537 _FDT(off);
538 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
539 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
540 sizeof(mem_reg_property))));
541 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
542 sizeof(associativity))));
543 return off;
544 }
545
546 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
547 {
548 MachineState *machine = MACHINE(spapr);
549 hwaddr mem_start, node_size;
550 int i, nb_nodes = nb_numa_nodes;
551 NodeInfo *nodes = numa_info;
552 NodeInfo ramnode;
553
554 /* No NUMA nodes, assume there is just one node with whole RAM */
555 if (!nb_numa_nodes) {
556 nb_nodes = 1;
557 ramnode.node_mem = machine->ram_size;
558 nodes = &ramnode;
559 }
560
561 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
562 if (!nodes[i].node_mem) {
563 continue;
564 }
565 if (mem_start >= machine->ram_size) {
566 node_size = 0;
567 } else {
568 node_size = nodes[i].node_mem;
569 if (node_size > machine->ram_size - mem_start) {
570 node_size = machine->ram_size - mem_start;
571 }
572 }
573 if (!mem_start) {
574 /* ppc_spapr_init() checks for rma_size <= node0_size already */
575 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
576 mem_start += spapr->rma_size;
577 node_size -= spapr->rma_size;
578 }
579 for ( ; node_size; ) {
580 hwaddr sizetmp = pow2floor(node_size);
581
582 /* mem_start != 0 here */
583 if (ctzl(mem_start) < ctzl(sizetmp)) {
584 sizetmp = 1ULL << ctzl(mem_start);
585 }
586
587 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
588 node_size -= sizetmp;
589 mem_start += sizetmp;
590 }
591 }
592
593 return 0;
594 }
595
596 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
597 sPAPRMachineState *spapr)
598 {
599 PowerPCCPU *cpu = POWERPC_CPU(cs);
600 CPUPPCState *env = &cpu->env;
601 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
602 int index = ppc_get_vcpu_dt_id(cpu);
603 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
604 0xffffffff, 0xffffffff};
605 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
606 : SPAPR_TIMEBASE_FREQ;
607 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
608 uint32_t page_sizes_prop[64];
609 size_t page_sizes_prop_size;
610 uint32_t vcpus_per_socket = smp_threads * smp_cores;
611 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
612 sPAPRDRConnector *drc;
613 sPAPRDRConnectorClass *drck;
614 int drc_index;
615
616 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index);
617 if (drc) {
618 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
619 drc_index = drck->get_index(drc);
620 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
621 }
622
623 /* Note: we keep CI large pages off for now because a 64K capable guest
624 * provisioned with large pages might otherwise try to map a qemu
625 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
626 * even if that qemu runs on a 4k host.
627 *
628 * We can later add this bit back when we are confident this is not
629 * an issue (!HV KVM or 64K host)
630 */
631 uint8_t pa_features_206[] = { 6, 0,
632 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
633 uint8_t pa_features_207[] = { 24, 0,
634 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
635 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
636 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
637 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
638 uint8_t *pa_features;
639 size_t pa_size;
640
641 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
642 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
643
644 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
645 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
646 env->dcache_line_size)));
647 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
648 env->dcache_line_size)));
649 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
650 env->icache_line_size)));
651 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
652 env->icache_line_size)));
653
654 if (pcc->l1_dcache_size) {
655 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
656 pcc->l1_dcache_size)));
657 } else {
658 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n");
659 }
660 if (pcc->l1_icache_size) {
661 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
662 pcc->l1_icache_size)));
663 } else {
664 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n");
665 }
666
667 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
668 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
669 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
670 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
671 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
672 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
673
674 if (env->spr_cb[SPR_PURR].oea_read) {
675 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
676 }
677
678 if (env->mmu_model & POWERPC_MMU_1TSEG) {
679 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
680 segs, sizeof(segs))));
681 }
682
683 /* Advertise VMX/VSX (vector extensions) if available
684 * 0 / no property == no vector extensions
685 * 1 == VMX / Altivec available
686 * 2 == VSX available */
687 if (env->insns_flags & PPC_ALTIVEC) {
688 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
689
690 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
691 }
692
693 /* Advertise DFP (Decimal Floating Point) if available
694 * 0 / no property == no DFP
695 * 1 == DFP available */
696 if (env->insns_flags2 & PPC2_DFP) {
697 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
698 }
699
700 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop,
701 sizeof(page_sizes_prop));
702 if (page_sizes_prop_size) {
703 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
704 page_sizes_prop, page_sizes_prop_size)));
705 }
706
707 /* Do the ibm,pa-features property, adjust it for ci-large-pages */
708 if (env->mmu_model == POWERPC_MMU_2_06) {
709 pa_features = pa_features_206;
710 pa_size = sizeof(pa_features_206);
711 } else /* env->mmu_model == POWERPC_MMU_2_07 */ {
712 pa_features = pa_features_207;
713 pa_size = sizeof(pa_features_207);
714 }
715 if (env->ci_large_pages) {
716 pa_features[3] |= 0x20;
717 }
718 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
719
720 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
721 cs->cpu_index / vcpus_per_socket)));
722
723 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
724 pft_size_prop, sizeof(pft_size_prop))));
725
726 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
727
728 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
729 ppc_get_compat_smt_threads(cpu)));
730 }
731
732 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
733 {
734 CPUState *cs;
735 int cpus_offset;
736 char *nodename;
737 int smt = kvmppc_smt_threads();
738
739 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
740 _FDT(cpus_offset);
741 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
742 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
743
744 /*
745 * We walk the CPUs in reverse order to ensure that CPU DT nodes
746 * created by fdt_add_subnode() end up in the right order in FDT
747 * for the guest kernel the enumerate the CPUs correctly.
748 */
749 CPU_FOREACH_REVERSE(cs) {
750 PowerPCCPU *cpu = POWERPC_CPU(cs);
751 int index = ppc_get_vcpu_dt_id(cpu);
752 DeviceClass *dc = DEVICE_GET_CLASS(cs);
753 int offset;
754
755 if ((index % smt) != 0) {
756 continue;
757 }
758
759 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
760 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
761 g_free(nodename);
762 _FDT(offset);
763 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
764 }
765
766 }
767
768 /*
769 * Adds ibm,dynamic-reconfiguration-memory node.
770 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
771 * of this device tree node.
772 */
773 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
774 {
775 MachineState *machine = MACHINE(spapr);
776 int ret, i, offset;
777 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
778 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
779 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
780 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
781 memory_region_size(&spapr->hotplug_memory.mr)) /
782 lmb_size;
783 uint32_t *int_buf, *cur_index, buf_len;
784 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
785
786 /*
787 * Don't create the node if there is no hotpluggable memory
788 */
789 if (machine->ram_size == machine->maxram_size) {
790 return 0;
791 }
792
793 /*
794 * Allocate enough buffer size to fit in ibm,dynamic-memory
795 * or ibm,associativity-lookup-arrays
796 */
797 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
798 * sizeof(uint32_t);
799 cur_index = int_buf = g_malloc0(buf_len);
800
801 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
802
803 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
804 sizeof(prop_lmb_size));
805 if (ret < 0) {
806 goto out;
807 }
808
809 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
810 if (ret < 0) {
811 goto out;
812 }
813
814 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
815 if (ret < 0) {
816 goto out;
817 }
818
819 /* ibm,dynamic-memory */
820 int_buf[0] = cpu_to_be32(nr_lmbs);
821 cur_index++;
822 for (i = 0; i < nr_lmbs; i++) {
823 uint64_t addr = i * lmb_size;
824 uint32_t *dynamic_memory = cur_index;
825
826 if (i >= hotplug_lmb_start) {
827 sPAPRDRConnector *drc;
828 sPAPRDRConnectorClass *drck;
829
830 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i);
831 g_assert(drc);
832 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
833
834 dynamic_memory[0] = cpu_to_be32(addr >> 32);
835 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
836 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
837 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
838 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
839 if (memory_region_present(get_system_memory(), addr)) {
840 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
841 } else {
842 dynamic_memory[5] = cpu_to_be32(0);
843 }
844 } else {
845 /*
846 * LMB information for RMA, boot time RAM and gap b/n RAM and
847 * hotplug memory region -- all these are marked as reserved
848 * and as having no valid DRC.
849 */
850 dynamic_memory[0] = cpu_to_be32(addr >> 32);
851 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
852 dynamic_memory[2] = cpu_to_be32(0);
853 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
854 dynamic_memory[4] = cpu_to_be32(-1);
855 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
856 SPAPR_LMB_FLAGS_DRC_INVALID);
857 }
858
859 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
860 }
861 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
862 if (ret < 0) {
863 goto out;
864 }
865
866 /* ibm,associativity-lookup-arrays */
867 cur_index = int_buf;
868 int_buf[0] = cpu_to_be32(nr_nodes);
869 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
870 cur_index += 2;
871 for (i = 0; i < nr_nodes; i++) {
872 uint32_t associativity[] = {
873 cpu_to_be32(0x0),
874 cpu_to_be32(0x0),
875 cpu_to_be32(0x0),
876 cpu_to_be32(i)
877 };
878 memcpy(cur_index, associativity, sizeof(associativity));
879 cur_index += 4;
880 }
881 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
882 (cur_index - int_buf) * sizeof(uint32_t));
883 out:
884 g_free(int_buf);
885 return ret;
886 }
887
888 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
889 target_ulong addr, target_ulong size,
890 bool cpu_update, bool memory_update)
891 {
892 void *fdt, *fdt_skel;
893 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
894 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
895
896 size -= sizeof(hdr);
897
898 /* Create sceleton */
899 fdt_skel = g_malloc0(size);
900 _FDT((fdt_create(fdt_skel, size)));
901 _FDT((fdt_begin_node(fdt_skel, "")));
902 _FDT((fdt_end_node(fdt_skel)));
903 _FDT((fdt_finish(fdt_skel)));
904 fdt = g_malloc0(size);
905 _FDT((fdt_open_into(fdt_skel, fdt, size)));
906 g_free(fdt_skel);
907
908 /* Fixup cpu nodes */
909 if (cpu_update) {
910 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
911 }
912
913 /* Generate ibm,dynamic-reconfiguration-memory node if required */
914 if (memory_update && smc->dr_lmb_enabled) {
915 _FDT((spapr_populate_drconf_memory(spapr, fdt)));
916 }
917
918 /* Pack resulting tree */
919 _FDT((fdt_pack(fdt)));
920
921 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
922 trace_spapr_cas_failed(size);
923 return -1;
924 }
925
926 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
927 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
928 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
929 g_free(fdt);
930
931 return 0;
932 }
933
934 static void spapr_finalize_fdt(sPAPRMachineState *spapr,
935 hwaddr fdt_addr,
936 hwaddr rtas_addr,
937 hwaddr rtas_size)
938 {
939 MachineState *machine = MACHINE(qdev_get_machine());
940 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
941 const char *boot_device = machine->boot_order;
942 int ret, i;
943 size_t cb = 0;
944 char *bootlist;
945 void *fdt;
946 sPAPRPHBState *phb;
947
948 fdt = g_malloc(FDT_MAX_SIZE);
949
950 /* open out the base tree into a temp buffer for the final tweaks */
951 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
952
953 ret = spapr_populate_memory(spapr, fdt);
954 if (ret < 0) {
955 fprintf(stderr, "couldn't setup memory nodes in fdt\n");
956 exit(1);
957 }
958
959 ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
960 if (ret < 0) {
961 fprintf(stderr, "couldn't setup vio devices in fdt\n");
962 exit(1);
963 }
964
965 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
966 ret = spapr_rng_populate_dt(fdt);
967 if (ret < 0) {
968 fprintf(stderr, "could not set up rng device in the fdt\n");
969 exit(1);
970 }
971 }
972
973 QLIST_FOREACH(phb, &spapr->phbs, list) {
974 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
975 if (ret < 0) {
976 error_report("couldn't setup PCI devices in fdt");
977 exit(1);
978 }
979 }
980
981 /* RTAS */
982 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
983 if (ret < 0) {
984 fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
985 }
986
987 /* cpus */
988 spapr_populate_cpus_dt_node(fdt, spapr);
989
990 bootlist = get_boot_devices_list(&cb, true);
991 if (cb && bootlist) {
992 int offset = fdt_path_offset(fdt, "/chosen");
993 if (offset < 0) {
994 exit(1);
995 }
996 for (i = 0; i < cb; i++) {
997 if (bootlist[i] == '\n') {
998 bootlist[i] = ' ';
999 }
1000
1001 }
1002 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist);
1003 }
1004
1005 if (boot_device && strlen(boot_device)) {
1006 int offset = fdt_path_offset(fdt, "/chosen");
1007
1008 if (offset < 0) {
1009 exit(1);
1010 }
1011 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device);
1012 }
1013
1014 if (!spapr->has_graphics) {
1015 spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
1016 }
1017
1018 if (smc->dr_lmb_enabled) {
1019 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1020 }
1021
1022 if (smc->dr_cpu_enabled) {
1023 int offset = fdt_path_offset(fdt, "/cpus");
1024 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1025 SPAPR_DR_CONNECTOR_TYPE_CPU);
1026 if (ret < 0) {
1027 error_report("Couldn't set up CPU DR device tree properties");
1028 exit(1);
1029 }
1030 }
1031
1032 _FDT((fdt_pack(fdt)));
1033
1034 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1035 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1036 fdt_totalsize(fdt), FDT_MAX_SIZE);
1037 exit(1);
1038 }
1039
1040 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1041 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1042
1043 g_free(bootlist);
1044 g_free(fdt);
1045 }
1046
1047 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1048 {
1049 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1050 }
1051
1052 static void emulate_spapr_hypercall(PowerPCCPU *cpu)
1053 {
1054 CPUPPCState *env = &cpu->env;
1055
1056 if (msr_pr) {
1057 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1058 env->gpr[3] = H_PRIVILEGE;
1059 } else {
1060 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1061 }
1062 }
1063
1064 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1065 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1066 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1067 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1068 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1069
1070 /*
1071 * Get the fd to access the kernel htab, re-opening it if necessary
1072 */
1073 static int get_htab_fd(sPAPRMachineState *spapr)
1074 {
1075 if (spapr->htab_fd >= 0) {
1076 return spapr->htab_fd;
1077 }
1078
1079 spapr->htab_fd = kvmppc_get_htab_fd(false);
1080 if (spapr->htab_fd < 0) {
1081 error_report("Unable to open fd for reading hash table from KVM: %s",
1082 strerror(errno));
1083 }
1084
1085 return spapr->htab_fd;
1086 }
1087
1088 static void close_htab_fd(sPAPRMachineState *spapr)
1089 {
1090 if (spapr->htab_fd >= 0) {
1091 close(spapr->htab_fd);
1092 }
1093 spapr->htab_fd = -1;
1094 }
1095
1096 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1097 {
1098 int shift;
1099
1100 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1101 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1102 * that's much more than is needed for Linux guests */
1103 shift = ctz64(pow2ceil(ramsize)) - 7;
1104 shift = MAX(shift, 18); /* Minimum architected size */
1105 shift = MIN(shift, 46); /* Maximum architected size */
1106 return shift;
1107 }
1108
1109 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1110 Error **errp)
1111 {
1112 long rc;
1113
1114 /* Clean up any HPT info from a previous boot */
1115 g_free(spapr->htab);
1116 spapr->htab = NULL;
1117 spapr->htab_shift = 0;
1118 close_htab_fd(spapr);
1119
1120 rc = kvmppc_reset_htab(shift);
1121 if (rc < 0) {
1122 /* kernel-side HPT needed, but couldn't allocate one */
1123 error_setg_errno(errp, errno,
1124 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1125 shift);
1126 /* This is almost certainly fatal, but if the caller really
1127 * wants to carry on with shift == 0, it's welcome to try */
1128 } else if (rc > 0) {
1129 /* kernel-side HPT allocated */
1130 if (rc != shift) {
1131 error_setg(errp,
1132 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1133 shift, rc);
1134 }
1135
1136 spapr->htab_shift = shift;
1137 spapr->htab = NULL;
1138 } else {
1139 /* kernel-side HPT not needed, allocate in userspace instead */
1140 size_t size = 1ULL << shift;
1141 int i;
1142
1143 spapr->htab = qemu_memalign(size, size);
1144 if (!spapr->htab) {
1145 error_setg_errno(errp, errno,
1146 "Could not allocate HPT of order %d", shift);
1147 return;
1148 }
1149
1150 memset(spapr->htab, 0, size);
1151 spapr->htab_shift = shift;
1152
1153 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1154 DIRTY_HPTE(HPTE(spapr->htab, i));
1155 }
1156 }
1157 }
1158
1159 static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1160 {
1161 bool matched = false;
1162
1163 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1164 matched = true;
1165 }
1166
1167 if (!matched) {
1168 error_report("Device %s is not supported by this machine yet.",
1169 qdev_fw_name(DEVICE(sbdev)));
1170 exit(1);
1171 }
1172
1173 return 0;
1174 }
1175
1176 static void ppc_spapr_reset(void)
1177 {
1178 MachineState *machine = MACHINE(qdev_get_machine());
1179 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1180 PowerPCCPU *first_ppc_cpu;
1181 uint32_t rtas_limit;
1182
1183 /* Check for unknown sysbus devices */
1184 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1185
1186 /* Allocate and/or reset the hash page table */
1187 spapr_reallocate_hpt(spapr,
1188 spapr_hpt_shift_for_ramsize(machine->maxram_size),
1189 &error_fatal);
1190
1191 /* Update the RMA size if necessary */
1192 if (spapr->vrma_adjust) {
1193 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1194 spapr->htab_shift);
1195 }
1196
1197 qemu_devices_reset();
1198
1199 /*
1200 * We place the device tree and RTAS just below either the top of the RMA,
1201 * or just below 2GB, whichever is lowere, so that it can be
1202 * processed with 32-bit real mode code if necessary
1203 */
1204 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1205 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1206 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
1207
1208 /* Load the fdt */
1209 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
1210 spapr->rtas_size);
1211
1212 /* Copy RTAS over */
1213 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob,
1214 spapr->rtas_size);
1215
1216 /* Set up the entry state */
1217 first_ppc_cpu = POWERPC_CPU(first_cpu);
1218 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr;
1219 first_ppc_cpu->env.gpr[5] = 0;
1220 first_cpu->halted = 0;
1221 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1222
1223 }
1224
1225 static void spapr_create_nvram(sPAPRMachineState *spapr)
1226 {
1227 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1228 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1229
1230 if (dinfo) {
1231 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1232 &error_fatal);
1233 }
1234
1235 qdev_init_nofail(dev);
1236
1237 spapr->nvram = (struct sPAPRNVRAM *)dev;
1238 }
1239
1240 static void spapr_rtc_create(sPAPRMachineState *spapr)
1241 {
1242 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1243
1244 qdev_init_nofail(dev);
1245 spapr->rtc = dev;
1246
1247 object_property_add_alias(qdev_get_machine(), "rtc-time",
1248 OBJECT(spapr->rtc), "date", NULL);
1249 }
1250
1251 /* Returns whether we want to use VGA or not */
1252 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1253 {
1254 switch (vga_interface_type) {
1255 case VGA_NONE:
1256 return false;
1257 case VGA_DEVICE:
1258 return true;
1259 case VGA_STD:
1260 case VGA_VIRTIO:
1261 return pci_vga_init(pci_bus) != NULL;
1262 default:
1263 error_setg(errp,
1264 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1265 return false;
1266 }
1267 }
1268
1269 static int spapr_post_load(void *opaque, int version_id)
1270 {
1271 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1272 int err = 0;
1273
1274 /* In earlier versions, there was no separate qdev for the PAPR
1275 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1276 * So when migrating from those versions, poke the incoming offset
1277 * value into the RTC device */
1278 if (version_id < 3) {
1279 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1280 }
1281
1282 return err;
1283 }
1284
1285 static bool version_before_3(void *opaque, int version_id)
1286 {
1287 return version_id < 3;
1288 }
1289
1290 static const VMStateDescription vmstate_spapr = {
1291 .name = "spapr",
1292 .version_id = 3,
1293 .minimum_version_id = 1,
1294 .post_load = spapr_post_load,
1295 .fields = (VMStateField[]) {
1296 /* used to be @next_irq */
1297 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1298
1299 /* RTC offset */
1300 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1301
1302 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1303 VMSTATE_END_OF_LIST()
1304 },
1305 };
1306
1307 static int htab_save_setup(QEMUFile *f, void *opaque)
1308 {
1309 sPAPRMachineState *spapr = opaque;
1310
1311 /* "Iteration" header */
1312 qemu_put_be32(f, spapr->htab_shift);
1313
1314 if (spapr->htab) {
1315 spapr->htab_save_index = 0;
1316 spapr->htab_first_pass = true;
1317 } else {
1318 assert(kvm_enabled());
1319 }
1320
1321
1322 return 0;
1323 }
1324
1325 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1326 int64_t max_ns)
1327 {
1328 bool has_timeout = max_ns != -1;
1329 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1330 int index = spapr->htab_save_index;
1331 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1332
1333 assert(spapr->htab_first_pass);
1334
1335 do {
1336 int chunkstart;
1337
1338 /* Consume invalid HPTEs */
1339 while ((index < htabslots)
1340 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1341 index++;
1342 CLEAN_HPTE(HPTE(spapr->htab, index));
1343 }
1344
1345 /* Consume valid HPTEs */
1346 chunkstart = index;
1347 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1348 && HPTE_VALID(HPTE(spapr->htab, index))) {
1349 index++;
1350 CLEAN_HPTE(HPTE(spapr->htab, index));
1351 }
1352
1353 if (index > chunkstart) {
1354 int n_valid = index - chunkstart;
1355
1356 qemu_put_be32(f, chunkstart);
1357 qemu_put_be16(f, n_valid);
1358 qemu_put_be16(f, 0);
1359 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1360 HASH_PTE_SIZE_64 * n_valid);
1361
1362 if (has_timeout &&
1363 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1364 break;
1365 }
1366 }
1367 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1368
1369 if (index >= htabslots) {
1370 assert(index == htabslots);
1371 index = 0;
1372 spapr->htab_first_pass = false;
1373 }
1374 spapr->htab_save_index = index;
1375 }
1376
1377 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1378 int64_t max_ns)
1379 {
1380 bool final = max_ns < 0;
1381 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1382 int examined = 0, sent = 0;
1383 int index = spapr->htab_save_index;
1384 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1385
1386 assert(!spapr->htab_first_pass);
1387
1388 do {
1389 int chunkstart, invalidstart;
1390
1391 /* Consume non-dirty HPTEs */
1392 while ((index < htabslots)
1393 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1394 index++;
1395 examined++;
1396 }
1397
1398 chunkstart = index;
1399 /* Consume valid dirty HPTEs */
1400 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1401 && HPTE_DIRTY(HPTE(spapr->htab, index))
1402 && HPTE_VALID(HPTE(spapr->htab, index))) {
1403 CLEAN_HPTE(HPTE(spapr->htab, index));
1404 index++;
1405 examined++;
1406 }
1407
1408 invalidstart = index;
1409 /* Consume invalid dirty HPTEs */
1410 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1411 && HPTE_DIRTY(HPTE(spapr->htab, index))
1412 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1413 CLEAN_HPTE(HPTE(spapr->htab, index));
1414 index++;
1415 examined++;
1416 }
1417
1418 if (index > chunkstart) {
1419 int n_valid = invalidstart - chunkstart;
1420 int n_invalid = index - invalidstart;
1421
1422 qemu_put_be32(f, chunkstart);
1423 qemu_put_be16(f, n_valid);
1424 qemu_put_be16(f, n_invalid);
1425 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1426 HASH_PTE_SIZE_64 * n_valid);
1427 sent += index - chunkstart;
1428
1429 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1430 break;
1431 }
1432 }
1433
1434 if (examined >= htabslots) {
1435 break;
1436 }
1437
1438 if (index >= htabslots) {
1439 assert(index == htabslots);
1440 index = 0;
1441 }
1442 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1443
1444 if (index >= htabslots) {
1445 assert(index == htabslots);
1446 index = 0;
1447 }
1448
1449 spapr->htab_save_index = index;
1450
1451 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1452 }
1453
1454 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1455 #define MAX_KVM_BUF_SIZE 2048
1456
1457 static int htab_save_iterate(QEMUFile *f, void *opaque)
1458 {
1459 sPAPRMachineState *spapr = opaque;
1460 int fd;
1461 int rc = 0;
1462
1463 /* Iteration header */
1464 qemu_put_be32(f, 0);
1465
1466 if (!spapr->htab) {
1467 assert(kvm_enabled());
1468
1469 fd = get_htab_fd(spapr);
1470 if (fd < 0) {
1471 return fd;
1472 }
1473
1474 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1475 if (rc < 0) {
1476 return rc;
1477 }
1478 } else if (spapr->htab_first_pass) {
1479 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1480 } else {
1481 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1482 }
1483
1484 /* End marker */
1485 qemu_put_be32(f, 0);
1486 qemu_put_be16(f, 0);
1487 qemu_put_be16(f, 0);
1488
1489 return rc;
1490 }
1491
1492 static int htab_save_complete(QEMUFile *f, void *opaque)
1493 {
1494 sPAPRMachineState *spapr = opaque;
1495 int fd;
1496
1497 /* Iteration header */
1498 qemu_put_be32(f, 0);
1499
1500 if (!spapr->htab) {
1501 int rc;
1502
1503 assert(kvm_enabled());
1504
1505 fd = get_htab_fd(spapr);
1506 if (fd < 0) {
1507 return fd;
1508 }
1509
1510 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1511 if (rc < 0) {
1512 return rc;
1513 }
1514 close_htab_fd(spapr);
1515 } else {
1516 if (spapr->htab_first_pass) {
1517 htab_save_first_pass(f, spapr, -1);
1518 }
1519 htab_save_later_pass(f, spapr, -1);
1520 }
1521
1522 /* End marker */
1523 qemu_put_be32(f, 0);
1524 qemu_put_be16(f, 0);
1525 qemu_put_be16(f, 0);
1526
1527 return 0;
1528 }
1529
1530 static int htab_load(QEMUFile *f, void *opaque, int version_id)
1531 {
1532 sPAPRMachineState *spapr = opaque;
1533 uint32_t section_hdr;
1534 int fd = -1;
1535
1536 if (version_id < 1 || version_id > 1) {
1537 error_report("htab_load() bad version");
1538 return -EINVAL;
1539 }
1540
1541 section_hdr = qemu_get_be32(f);
1542
1543 if (section_hdr) {
1544 Error *local_err = NULL;
1545
1546 /* First section gives the htab size */
1547 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1548 if (local_err) {
1549 error_report_err(local_err);
1550 return -EINVAL;
1551 }
1552 return 0;
1553 }
1554
1555 if (!spapr->htab) {
1556 assert(kvm_enabled());
1557
1558 fd = kvmppc_get_htab_fd(true);
1559 if (fd < 0) {
1560 error_report("Unable to open fd to restore KVM hash table: %s",
1561 strerror(errno));
1562 }
1563 }
1564
1565 while (true) {
1566 uint32_t index;
1567 uint16_t n_valid, n_invalid;
1568
1569 index = qemu_get_be32(f);
1570 n_valid = qemu_get_be16(f);
1571 n_invalid = qemu_get_be16(f);
1572
1573 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1574 /* End of Stream */
1575 break;
1576 }
1577
1578 if ((index + n_valid + n_invalid) >
1579 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1580 /* Bad index in stream */
1581 error_report(
1582 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1583 index, n_valid, n_invalid, spapr->htab_shift);
1584 return -EINVAL;
1585 }
1586
1587 if (spapr->htab) {
1588 if (n_valid) {
1589 qemu_get_buffer(f, HPTE(spapr->htab, index),
1590 HASH_PTE_SIZE_64 * n_valid);
1591 }
1592 if (n_invalid) {
1593 memset(HPTE(spapr->htab, index + n_valid), 0,
1594 HASH_PTE_SIZE_64 * n_invalid);
1595 }
1596 } else {
1597 int rc;
1598
1599 assert(fd >= 0);
1600
1601 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1602 if (rc < 0) {
1603 return rc;
1604 }
1605 }
1606 }
1607
1608 if (!spapr->htab) {
1609 assert(fd >= 0);
1610 close(fd);
1611 }
1612
1613 return 0;
1614 }
1615
1616 static SaveVMHandlers savevm_htab_handlers = {
1617 .save_live_setup = htab_save_setup,
1618 .save_live_iterate = htab_save_iterate,
1619 .save_live_complete_precopy = htab_save_complete,
1620 .load_state = htab_load,
1621 };
1622
1623 static void spapr_boot_set(void *opaque, const char *boot_device,
1624 Error **errp)
1625 {
1626 MachineState *machine = MACHINE(qdev_get_machine());
1627 machine->boot_order = g_strdup(boot_device);
1628 }
1629
1630 /*
1631 * Reset routine for LMB DR devices.
1632 *
1633 * Unlike PCI DR devices, LMB DR devices explicitly register this reset
1634 * routine. Reset for PCI DR devices will be handled by PHB reset routine
1635 * when it walks all its children devices. LMB devices reset occurs
1636 * as part of spapr_ppc_reset().
1637 */
1638 static void spapr_drc_reset(void *opaque)
1639 {
1640 sPAPRDRConnector *drc = opaque;
1641 DeviceState *d = DEVICE(drc);
1642
1643 if (d) {
1644 device_reset(d);
1645 }
1646 }
1647
1648 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1649 {
1650 MachineState *machine = MACHINE(spapr);
1651 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
1652 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
1653 int i;
1654
1655 for (i = 0; i < nr_lmbs; i++) {
1656 sPAPRDRConnector *drc;
1657 uint64_t addr;
1658
1659 addr = i * lmb_size + spapr->hotplug_memory.base;
1660 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1661 addr/lmb_size);
1662 qemu_register_reset(spapr_drc_reset, drc);
1663 }
1664 }
1665
1666 /*
1667 * If RAM size, maxmem size and individual node mem sizes aren't aligned
1668 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
1669 * since we can't support such unaligned sizes with DRCONF_MEMORY.
1670 */
1671 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
1672 {
1673 int i;
1674
1675 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1676 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1677 " is not aligned to %llu MiB",
1678 machine->ram_size,
1679 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1680 return;
1681 }
1682
1683 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1684 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1685 " is not aligned to %llu MiB",
1686 machine->ram_size,
1687 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1688 return;
1689 }
1690
1691 for (i = 0; i < nb_numa_nodes; i++) {
1692 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
1693 error_setg(errp,
1694 "Node %d memory size 0x%" PRIx64
1695 " is not aligned to %llu MiB",
1696 i, numa_info[i].node_mem,
1697 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1698 return;
1699 }
1700 }
1701 }
1702
1703 /* pSeries LPAR / sPAPR hardware init */
1704 static void ppc_spapr_init(MachineState *machine)
1705 {
1706 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1707 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1708 const char *kernel_filename = machine->kernel_filename;
1709 const char *kernel_cmdline = machine->kernel_cmdline;
1710 const char *initrd_filename = machine->initrd_filename;
1711 PCIHostState *phb;
1712 int i;
1713 MemoryRegion *sysmem = get_system_memory();
1714 MemoryRegion *ram = g_new(MemoryRegion, 1);
1715 MemoryRegion *rma_region;
1716 void *rma = NULL;
1717 hwaddr rma_alloc_size;
1718 hwaddr node0_size = spapr_node0_size();
1719 uint32_t initrd_base = 0;
1720 long kernel_size = 0, initrd_size = 0;
1721 long load_limit, fw_size;
1722 bool kernel_le = false;
1723 char *filename;
1724 int smt = kvmppc_smt_threads();
1725 int spapr_cores = smp_cpus / smp_threads;
1726 int spapr_max_cores = max_cpus / smp_threads;
1727
1728 if (smc->dr_cpu_enabled) {
1729 if (smp_cpus % smp_threads) {
1730 error_report("smp_cpus (%u) must be multiple of threads (%u)",
1731 smp_cpus, smp_threads);
1732 exit(1);
1733 }
1734 if (max_cpus % smp_threads) {
1735 error_report("max_cpus (%u) must be multiple of threads (%u)",
1736 max_cpus, smp_threads);
1737 exit(1);
1738 }
1739 }
1740
1741 msi_nonbroken = true;
1742
1743 QLIST_INIT(&spapr->phbs);
1744
1745 cpu_ppc_hypercall = emulate_spapr_hypercall;
1746
1747 /* Allocate RMA if necessary */
1748 rma_alloc_size = kvmppc_alloc_rma(&rma);
1749
1750 if (rma_alloc_size == -1) {
1751 error_report("Unable to create RMA");
1752 exit(1);
1753 }
1754
1755 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
1756 spapr->rma_size = rma_alloc_size;
1757 } else {
1758 spapr->rma_size = node0_size;
1759
1760 /* With KVM, we don't actually know whether KVM supports an
1761 * unbounded RMA (PR KVM) or is limited by the hash table size
1762 * (HV KVM using VRMA), so we always assume the latter
1763 *
1764 * In that case, we also limit the initial allocations for RTAS
1765 * etc... to 256M since we have no way to know what the VRMA size
1766 * is going to be as it depends on the size of the hash table
1767 * isn't determined yet.
1768 */
1769 if (kvm_enabled()) {
1770 spapr->vrma_adjust = 1;
1771 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1772 }
1773 }
1774
1775 if (spapr->rma_size > node0_size) {
1776 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
1777 spapr->rma_size);
1778 exit(1);
1779 }
1780
1781 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
1782 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
1783
1784 /* Set up Interrupt Controller before we create the VCPUs */
1785 spapr->icp = xics_system_init(machine,
1786 DIV_ROUND_UP(max_cpus * smt, smp_threads),
1787 XICS_IRQS, &error_fatal);
1788
1789 if (smc->dr_lmb_enabled) {
1790 spapr_validate_node_memory(machine, &error_fatal);
1791 }
1792
1793 /* init CPUs */
1794 if (machine->cpu_model == NULL) {
1795 machine->cpu_model = kvm_enabled() ? "host" : "POWER7";
1796 }
1797
1798 if (smc->dr_cpu_enabled) {
1799 char *type = spapr_get_cpu_core_type(machine->cpu_model);
1800
1801 spapr->cores = g_new0(Object *, spapr_max_cores);
1802 for (i = 0; i < spapr_max_cores; i++) {
1803 int core_dt_id = i * smt;
1804 sPAPRDRConnector *drc =
1805 spapr_dr_connector_new(OBJECT(spapr),
1806 SPAPR_DR_CONNECTOR_TYPE_CPU, core_dt_id);
1807
1808 qemu_register_reset(spapr_drc_reset, drc);
1809
1810 if (i < spapr_cores) {
1811 char *type = spapr_get_cpu_core_type(machine->cpu_model);
1812 Object *core;
1813
1814 if (!object_class_by_name(type)) {
1815 error_report("Unable to find sPAPR CPU Core definition");
1816 exit(1);
1817 }
1818
1819 core = object_new(type);
1820 object_property_set_int(core, smp_threads, "nr-threads",
1821 &error_fatal);
1822 object_property_set_int(core, core_dt_id, CPU_CORE_PROP_CORE_ID,
1823 &error_fatal);
1824 object_property_set_bool(core, true, "realized", &error_fatal);
1825 }
1826 }
1827 g_free(type);
1828 } else {
1829 for (i = 0; i < smp_cpus; i++) {
1830 PowerPCCPU *cpu = cpu_ppc_init(machine->cpu_model);
1831 if (cpu == NULL) {
1832 error_report("Unable to find PowerPC CPU definition");
1833 exit(1);
1834 }
1835 spapr_cpu_init(spapr, cpu, &error_fatal);
1836 }
1837 }
1838
1839 if (kvm_enabled()) {
1840 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
1841 kvmppc_enable_logical_ci_hcalls();
1842 kvmppc_enable_set_mode_hcall();
1843 }
1844
1845 /* allocate RAM */
1846 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
1847 machine->ram_size);
1848 memory_region_add_subregion(sysmem, 0, ram);
1849
1850 if (rma_alloc_size && rma) {
1851 rma_region = g_new(MemoryRegion, 1);
1852 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
1853 rma_alloc_size, rma);
1854 vmstate_register_ram_global(rma_region);
1855 memory_region_add_subregion(sysmem, 0, rma_region);
1856 }
1857
1858 /* initialize hotplug memory address space */
1859 if (machine->ram_size < machine->maxram_size) {
1860 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
1861 /*
1862 * Limit the number of hotpluggable memory slots to half the number
1863 * slots that KVM supports, leaving the other half for PCI and other
1864 * devices. However ensure that number of slots doesn't drop below 32.
1865 */
1866 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
1867 SPAPR_MAX_RAM_SLOTS;
1868
1869 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
1870 max_memslots = SPAPR_MAX_RAM_SLOTS;
1871 }
1872 if (machine->ram_slots > max_memslots) {
1873 error_report("Specified number of memory slots %"
1874 PRIu64" exceeds max supported %d",
1875 machine->ram_slots, max_memslots);
1876 exit(1);
1877 }
1878
1879 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
1880 SPAPR_HOTPLUG_MEM_ALIGN);
1881 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
1882 "hotplug-memory", hotplug_mem_size);
1883 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
1884 &spapr->hotplug_memory.mr);
1885 }
1886
1887 if (smc->dr_lmb_enabled) {
1888 spapr_create_lmb_dr_connectors(spapr);
1889 }
1890
1891 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
1892 if (!filename) {
1893 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
1894 exit(1);
1895 }
1896 spapr->rtas_size = get_image_size(filename);
1897 if (spapr->rtas_size < 0) {
1898 error_report("Could not get size of LPAR rtas '%s'", filename);
1899 exit(1);
1900 }
1901 spapr->rtas_blob = g_malloc(spapr->rtas_size);
1902 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
1903 error_report("Could not load LPAR rtas '%s'", filename);
1904 exit(1);
1905 }
1906 if (spapr->rtas_size > RTAS_MAX_SIZE) {
1907 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
1908 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
1909 exit(1);
1910 }
1911 g_free(filename);
1912
1913 /* Set up EPOW events infrastructure */
1914 spapr_events_init(spapr);
1915
1916 /* Set up the RTC RTAS interfaces */
1917 spapr_rtc_create(spapr);
1918
1919 /* Set up VIO bus */
1920 spapr->vio_bus = spapr_vio_bus_init();
1921
1922 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
1923 if (serial_hds[i]) {
1924 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
1925 }
1926 }
1927
1928 /* We always have at least the nvram device on VIO */
1929 spapr_create_nvram(spapr);
1930
1931 /* Set up PCI */
1932 spapr_pci_rtas_init();
1933
1934 phb = spapr_create_phb(spapr, 0);
1935
1936 for (i = 0; i < nb_nics; i++) {
1937 NICInfo *nd = &nd_table[i];
1938
1939 if (!nd->model) {
1940 nd->model = g_strdup("ibmveth");
1941 }
1942
1943 if (strcmp(nd->model, "ibmveth") == 0) {
1944 spapr_vlan_create(spapr->vio_bus, nd);
1945 } else {
1946 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
1947 }
1948 }
1949
1950 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
1951 spapr_vscsi_create(spapr->vio_bus);
1952 }
1953
1954 /* Graphics */
1955 if (spapr_vga_init(phb->bus, &error_fatal)) {
1956 spapr->has_graphics = true;
1957 machine->usb |= defaults_enabled() && !machine->usb_disabled;
1958 }
1959
1960 if (machine->usb) {
1961 if (smc->use_ohci_by_default) {
1962 pci_create_simple(phb->bus, -1, "pci-ohci");
1963 } else {
1964 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
1965 }
1966
1967 if (spapr->has_graphics) {
1968 USBBus *usb_bus = usb_bus_find(-1);
1969
1970 usb_create_simple(usb_bus, "usb-kbd");
1971 usb_create_simple(usb_bus, "usb-mouse");
1972 }
1973 }
1974
1975 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
1976 error_report(
1977 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
1978 MIN_RMA_SLOF);
1979 exit(1);
1980 }
1981
1982 if (kernel_filename) {
1983 uint64_t lowaddr = 0;
1984
1985 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
1986 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
1987 0, 0);
1988 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) {
1989 kernel_size = load_elf(kernel_filename,
1990 translate_kernel_address, NULL,
1991 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE,
1992 0, 0);
1993 kernel_le = kernel_size > 0;
1994 }
1995 if (kernel_size < 0) {
1996 error_report("error loading %s: %s",
1997 kernel_filename, load_elf_strerror(kernel_size));
1998 exit(1);
1999 }
2000
2001 /* load initrd */
2002 if (initrd_filename) {
2003 /* Try to locate the initrd in the gap between the kernel
2004 * and the firmware. Add a bit of space just in case
2005 */
2006 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
2007 initrd_size = load_image_targphys(initrd_filename, initrd_base,
2008 load_limit - initrd_base);
2009 if (initrd_size < 0) {
2010 error_report("could not load initial ram disk '%s'",
2011 initrd_filename);
2012 exit(1);
2013 }
2014 } else {
2015 initrd_base = 0;
2016 initrd_size = 0;
2017 }
2018 }
2019
2020 if (bios_name == NULL) {
2021 bios_name = FW_FILE_NAME;
2022 }
2023 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2024 if (!filename) {
2025 error_report("Could not find LPAR firmware '%s'", bios_name);
2026 exit(1);
2027 }
2028 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2029 if (fw_size <= 0) {
2030 error_report("Could not load LPAR firmware '%s'", filename);
2031 exit(1);
2032 }
2033 g_free(filename);
2034
2035 /* FIXME: Should register things through the MachineState's qdev
2036 * interface, this is a legacy from the sPAPREnvironment structure
2037 * which predated MachineState but had a similar function */
2038 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2039 register_savevm_live(NULL, "spapr/htab", -1, 1,
2040 &savevm_htab_handlers, spapr);
2041
2042 /* Prepare the device tree */
2043 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size,
2044 kernel_size, kernel_le,
2045 kernel_cmdline,
2046 spapr->check_exception_irq);
2047 assert(spapr->fdt_skel != NULL);
2048
2049 /* used by RTAS */
2050 QTAILQ_INIT(&spapr->ccs_list);
2051 qemu_register_reset(spapr_ccs_reset_hook, spapr);
2052
2053 qemu_register_boot_set(spapr_boot_set, spapr);
2054 }
2055
2056 static int spapr_kvm_type(const char *vm_type)
2057 {
2058 if (!vm_type) {
2059 return 0;
2060 }
2061
2062 if (!strcmp(vm_type, "HV")) {
2063 return 1;
2064 }
2065
2066 if (!strcmp(vm_type, "PR")) {
2067 return 2;
2068 }
2069
2070 error_report("Unknown kvm-type specified '%s'", vm_type);
2071 exit(1);
2072 }
2073
2074 /*
2075 * Implementation of an interface to adjust firmware path
2076 * for the bootindex property handling.
2077 */
2078 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2079 DeviceState *dev)
2080 {
2081 #define CAST(type, obj, name) \
2082 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2083 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2084 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2085
2086 if (d) {
2087 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2088 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2089 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2090
2091 if (spapr) {
2092 /*
2093 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2094 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2095 * in the top 16 bits of the 64-bit LUN
2096 */
2097 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2098 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2099 (uint64_t)id << 48);
2100 } else if (virtio) {
2101 /*
2102 * We use SRP luns of the form 01000000 | (target << 8) | lun
2103 * in the top 32 bits of the 64-bit LUN
2104 * Note: the quote above is from SLOF and it is wrong,
2105 * the actual binding is:
2106 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2107 */
2108 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2109 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2110 (uint64_t)id << 32);
2111 } else if (usb) {
2112 /*
2113 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2114 * in the top 32 bits of the 64-bit LUN
2115 */
2116 unsigned usb_port = atoi(usb->port->path);
2117 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2118 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2119 (uint64_t)id << 32);
2120 }
2121 }
2122
2123 if (phb) {
2124 /* Replace "pci" with "pci@800000020000000" */
2125 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2126 }
2127
2128 return NULL;
2129 }
2130
2131 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2132 {
2133 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2134
2135 return g_strdup(spapr->kvm_type);
2136 }
2137
2138 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2139 {
2140 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2141
2142 g_free(spapr->kvm_type);
2143 spapr->kvm_type = g_strdup(value);
2144 }
2145
2146 static void spapr_machine_initfn(Object *obj)
2147 {
2148 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2149
2150 spapr->htab_fd = -1;
2151 object_property_add_str(obj, "kvm-type",
2152 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2153 object_property_set_description(obj, "kvm-type",
2154 "Specifies the KVM virtualization mode (HV, PR)",
2155 NULL);
2156 }
2157
2158 static void spapr_machine_finalizefn(Object *obj)
2159 {
2160 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2161
2162 g_free(spapr->kvm_type);
2163 }
2164
2165 static void ppc_cpu_do_nmi_on_cpu(void *arg)
2166 {
2167 CPUState *cs = arg;
2168
2169 cpu_synchronize_state(cs);
2170 ppc_cpu_do_system_reset(cs);
2171 }
2172
2173 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2174 {
2175 CPUState *cs;
2176
2177 CPU_FOREACH(cs) {
2178 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs);
2179 }
2180 }
2181
2182 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size,
2183 uint32_t node, Error **errp)
2184 {
2185 sPAPRDRConnector *drc;
2186 sPAPRDRConnectorClass *drck;
2187 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2188 int i, fdt_offset, fdt_size;
2189 void *fdt;
2190
2191 for (i = 0; i < nr_lmbs; i++) {
2192 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2193 addr/SPAPR_MEMORY_BLOCK_SIZE);
2194 g_assert(drc);
2195
2196 fdt = create_device_tree(&fdt_size);
2197 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2198 SPAPR_MEMORY_BLOCK_SIZE);
2199
2200 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2201 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
2202 addr += SPAPR_MEMORY_BLOCK_SIZE;
2203 }
2204 /* send hotplug notification to the
2205 * guest only in case of hotplugged memory
2206 */
2207 if (dev->hotplugged) {
2208 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs);
2209 }
2210 }
2211
2212 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2213 uint32_t node, Error **errp)
2214 {
2215 Error *local_err = NULL;
2216 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2217 PCDIMMDevice *dimm = PC_DIMM(dev);
2218 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2219 MemoryRegion *mr = ddc->get_memory_region(dimm);
2220 uint64_t align = memory_region_get_alignment(mr);
2221 uint64_t size = memory_region_size(mr);
2222 uint64_t addr;
2223
2224 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2225 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2226 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2227 goto out;
2228 }
2229
2230 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2231 if (local_err) {
2232 goto out;
2233 }
2234
2235 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2236 if (local_err) {
2237 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2238 goto out;
2239 }
2240
2241 spapr_add_lmbs(dev, addr, size, node, &error_abort);
2242
2243 out:
2244 error_propagate(errp, local_err);
2245 }
2246
2247 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
2248 sPAPRMachineState *spapr)
2249 {
2250 PowerPCCPU *cpu = POWERPC_CPU(cs);
2251 DeviceClass *dc = DEVICE_GET_CLASS(cs);
2252 int id = ppc_get_vcpu_dt_id(cpu);
2253 void *fdt;
2254 int offset, fdt_size;
2255 char *nodename;
2256
2257 fdt = create_device_tree(&fdt_size);
2258 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
2259 offset = fdt_add_subnode(fdt, 0, nodename);
2260
2261 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
2262 g_free(nodename);
2263
2264 *fdt_offset = offset;
2265 return fdt;
2266 }
2267
2268 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2269 DeviceState *dev, Error **errp)
2270 {
2271 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2272
2273 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2274 int node;
2275
2276 if (!smc->dr_lmb_enabled) {
2277 error_setg(errp, "Memory hotplug not supported for this machine");
2278 return;
2279 }
2280 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2281 if (*errp) {
2282 return;
2283 }
2284 if (node < 0 || node >= MAX_NODES) {
2285 error_setg(errp, "Invaild node %d", node);
2286 return;
2287 }
2288
2289 /*
2290 * Currently PowerPC kernel doesn't allow hot-adding memory to
2291 * memory-less node, but instead will silently add the memory
2292 * to the first node that has some memory. This causes two
2293 * unexpected behaviours for the user.
2294 *
2295 * - Memory gets hotplugged to a different node than what the user
2296 * specified.
2297 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
2298 * to memory-less node, a reboot will set things accordingly
2299 * and the previously hotplugged memory now ends in the right node.
2300 * This appears as if some memory moved from one node to another.
2301 *
2302 * So until kernel starts supporting memory hotplug to memory-less
2303 * nodes, just prevent such attempts upfront in QEMU.
2304 */
2305 if (nb_numa_nodes && !numa_info[node].node_mem) {
2306 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2307 node);
2308 return;
2309 }
2310
2311 spapr_memory_plug(hotplug_dev, dev, node, errp);
2312 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2313 spapr_core_plug(hotplug_dev, dev, errp);
2314 }
2315 }
2316
2317 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2318 DeviceState *dev, Error **errp)
2319 {
2320 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2321
2322 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2323 error_setg(errp, "Memory hot unplug not supported by sPAPR");
2324 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2325 if (!smc->dr_cpu_enabled) {
2326 error_setg(errp, "CPU hot unplug not supported on this machine");
2327 return;
2328 }
2329 spapr_core_unplug(hotplug_dev, dev, errp);
2330 }
2331 }
2332
2333 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
2334 DeviceState *dev, Error **errp)
2335 {
2336 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2337 spapr_core_pre_plug(hotplug_dev, dev, errp);
2338 }
2339 }
2340
2341 static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine,
2342 DeviceState *dev)
2343 {
2344 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2345 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
2346 return HOTPLUG_HANDLER(machine);
2347 }
2348 return NULL;
2349 }
2350
2351 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2352 {
2353 /* Allocate to NUMA nodes on a "socket" basis (not that concept of
2354 * socket means much for the paravirtualized PAPR platform) */
2355 return cpu_index / smp_threads / smp_cores;
2356 }
2357
2358 static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine)
2359 {
2360 int i;
2361 HotpluggableCPUList *head = NULL;
2362 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2363 int spapr_max_cores = max_cpus / smp_threads;
2364 int smt = kvmppc_smt_threads();
2365
2366 for (i = 0; i < spapr_max_cores; i++) {
2367 HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1);
2368 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1);
2369 CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1);
2370
2371 cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model);
2372 cpu_item->vcpus_count = smp_threads;
2373 cpu_props->has_core_id = true;
2374 cpu_props->core_id = i * smt;
2375 /* TODO: add 'has_node/node' here to describe
2376 to which node core belongs */
2377
2378 cpu_item->props = cpu_props;
2379 if (spapr->cores[i]) {
2380 cpu_item->has_qom_path = true;
2381 cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]);
2382 }
2383 list_item->value = cpu_item;
2384 list_item->next = head;
2385 head = list_item;
2386 }
2387 return head;
2388 }
2389
2390 static void spapr_machine_class_init(ObjectClass *oc, void *data)
2391 {
2392 MachineClass *mc = MACHINE_CLASS(oc);
2393 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
2394 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
2395 NMIClass *nc = NMI_CLASS(oc);
2396 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2397
2398 mc->desc = "pSeries Logical Partition (PAPR compliant)";
2399
2400 /*
2401 * We set up the default / latest behaviour here. The class_init
2402 * functions for the specific versioned machine types can override
2403 * these details for backwards compatibility
2404 */
2405 mc->init = ppc_spapr_init;
2406 mc->reset = ppc_spapr_reset;
2407 mc->block_default_type = IF_SCSI;
2408 mc->max_cpus = MAX_CPUMASK_BITS;
2409 mc->no_parallel = 1;
2410 mc->default_boot_order = "";
2411 mc->default_ram_size = 512 * M_BYTE;
2412 mc->kvm_type = spapr_kvm_type;
2413 mc->has_dynamic_sysbus = true;
2414 mc->pci_allow_0_address = true;
2415 mc->get_hotplug_handler = spapr_get_hotpug_handler;
2416 hc->pre_plug = spapr_machine_device_pre_plug;
2417 hc->plug = spapr_machine_device_plug;
2418 hc->unplug = spapr_machine_device_unplug;
2419 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
2420 mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus;
2421
2422 smc->dr_lmb_enabled = true;
2423 smc->dr_cpu_enabled = true;
2424 fwc->get_dev_path = spapr_get_fw_dev_path;
2425 nc->nmi_monitor_handler = spapr_nmi;
2426 }
2427
2428 static const TypeInfo spapr_machine_info = {
2429 .name = TYPE_SPAPR_MACHINE,
2430 .parent = TYPE_MACHINE,
2431 .abstract = true,
2432 .instance_size = sizeof(sPAPRMachineState),
2433 .instance_init = spapr_machine_initfn,
2434 .instance_finalize = spapr_machine_finalizefn,
2435 .class_size = sizeof(sPAPRMachineClass),
2436 .class_init = spapr_machine_class_init,
2437 .interfaces = (InterfaceInfo[]) {
2438 { TYPE_FW_PATH_PROVIDER },
2439 { TYPE_NMI },
2440 { TYPE_HOTPLUG_HANDLER },
2441 { }
2442 },
2443 };
2444
2445 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
2446 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
2447 void *data) \
2448 { \
2449 MachineClass *mc = MACHINE_CLASS(oc); \
2450 spapr_machine_##suffix##_class_options(mc); \
2451 if (latest) { \
2452 mc->alias = "pseries"; \
2453 mc->is_default = 1; \
2454 } \
2455 } \
2456 static void spapr_machine_##suffix##_instance_init(Object *obj) \
2457 { \
2458 MachineState *machine = MACHINE(obj); \
2459 spapr_machine_##suffix##_instance_options(machine); \
2460 } \
2461 static const TypeInfo spapr_machine_##suffix##_info = { \
2462 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
2463 .parent = TYPE_SPAPR_MACHINE, \
2464 .class_init = spapr_machine_##suffix##_class_init, \
2465 .instance_init = spapr_machine_##suffix##_instance_init, \
2466 }; \
2467 static void spapr_machine_register_##suffix(void) \
2468 { \
2469 type_register(&spapr_machine_##suffix##_info); \
2470 } \
2471 type_init(spapr_machine_register_##suffix)
2472
2473 /*
2474 * pseries-2.7
2475 */
2476 static void spapr_machine_2_7_instance_options(MachineState *machine)
2477 {
2478 }
2479
2480 static void spapr_machine_2_7_class_options(MachineClass *mc)
2481 {
2482 /* Defaults for the latest behaviour inherited from the base class */
2483 }
2484
2485 DEFINE_SPAPR_MACHINE(2_7, "2.7", true);
2486
2487 /*
2488 * pseries-2.6
2489 */
2490 #define SPAPR_COMPAT_2_6 \
2491 HW_COMPAT_2_6
2492
2493 static void spapr_machine_2_6_instance_options(MachineState *machine)
2494 {
2495 }
2496
2497 static void spapr_machine_2_6_class_options(MachineClass *mc)
2498 {
2499 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2500
2501 spapr_machine_2_7_class_options(mc);
2502 smc->dr_cpu_enabled = false;
2503 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
2504 }
2505
2506 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
2507
2508 /*
2509 * pseries-2.5
2510 */
2511 #define SPAPR_COMPAT_2_5 \
2512 HW_COMPAT_2_5 \
2513 { \
2514 .driver = "spapr-vlan", \
2515 .property = "use-rx-buffer-pools", \
2516 .value = "off", \
2517 },
2518
2519 static void spapr_machine_2_5_instance_options(MachineState *machine)
2520 {
2521 }
2522
2523 static void spapr_machine_2_5_class_options(MachineClass *mc)
2524 {
2525 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2526
2527 spapr_machine_2_6_class_options(mc);
2528 smc->use_ohci_by_default = true;
2529 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
2530 }
2531
2532 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
2533
2534 /*
2535 * pseries-2.4
2536 */
2537 #define SPAPR_COMPAT_2_4 \
2538 HW_COMPAT_2_4
2539
2540 static void spapr_machine_2_4_instance_options(MachineState *machine)
2541 {
2542 spapr_machine_2_5_instance_options(machine);
2543 }
2544
2545 static void spapr_machine_2_4_class_options(MachineClass *mc)
2546 {
2547 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2548
2549 spapr_machine_2_5_class_options(mc);
2550 smc->dr_lmb_enabled = false;
2551 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
2552 }
2553
2554 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
2555
2556 /*
2557 * pseries-2.3
2558 */
2559 #define SPAPR_COMPAT_2_3 \
2560 HW_COMPAT_2_3 \
2561 {\
2562 .driver = "spapr-pci-host-bridge",\
2563 .property = "dynamic-reconfiguration",\
2564 .value = "off",\
2565 },
2566
2567 static void spapr_machine_2_3_instance_options(MachineState *machine)
2568 {
2569 spapr_machine_2_4_instance_options(machine);
2570 savevm_skip_section_footers();
2571 global_state_set_optional();
2572 savevm_skip_configuration();
2573 }
2574
2575 static void spapr_machine_2_3_class_options(MachineClass *mc)
2576 {
2577 spapr_machine_2_4_class_options(mc);
2578 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
2579 }
2580 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
2581
2582 /*
2583 * pseries-2.2
2584 */
2585
2586 #define SPAPR_COMPAT_2_2 \
2587 HW_COMPAT_2_2 \
2588 {\
2589 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2590 .property = "mem_win_size",\
2591 .value = "0x20000000",\
2592 },
2593
2594 static void spapr_machine_2_2_instance_options(MachineState *machine)
2595 {
2596 spapr_machine_2_3_instance_options(machine);
2597 machine->suppress_vmdesc = true;
2598 }
2599
2600 static void spapr_machine_2_2_class_options(MachineClass *mc)
2601 {
2602 spapr_machine_2_3_class_options(mc);
2603 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
2604 }
2605 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
2606
2607 /*
2608 * pseries-2.1
2609 */
2610 #define SPAPR_COMPAT_2_1 \
2611 HW_COMPAT_2_1
2612
2613 static void spapr_machine_2_1_instance_options(MachineState *machine)
2614 {
2615 spapr_machine_2_2_instance_options(machine);
2616 }
2617
2618 static void spapr_machine_2_1_class_options(MachineClass *mc)
2619 {
2620 spapr_machine_2_2_class_options(mc);
2621 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
2622 }
2623 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
2624
2625 static void spapr_machine_register_types(void)
2626 {
2627 type_register_static(&spapr_machine_info);
2628 }
2629
2630 type_init(spapr_machine_register_types)
QEmu