x86: Extend validity of bsp_to_cpu
[qemu.git] / hw / pc.c
blobe50a48848d1b65ec0ea2d2b5aed53a08fef68098
1 /*
2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
24 #include "hw.h"
25 #include "pc.h"
26 #include "fdc.h"
27 #include "pci.h"
28 #include "vmware_vga.h"
29 #include "usb-uhci.h"
30 #include "usb-ohci.h"
31 #include "prep_pci.h"
32 #include "apb_pci.h"
33 #include "block.h"
34 #include "sysemu.h"
35 #include "audio/audio.h"
36 #include "net.h"
37 #include "smbus.h"
38 #include "boards.h"
39 #include "monitor.h"
40 #include "fw_cfg.h"
41 #include "hpet_emul.h"
42 #include "watchdog.h"
43 #include "smbios.h"
44 #include "ide.h"
45 #include "loader.h"
46 #include "elf.h"
47 #include "multiboot.h"
49 /* output Bochs bios info messages */
50 //#define DEBUG_BIOS
52 #define BIOS_FILENAME "bios.bin"
54 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
56 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
57 #define ACPI_DATA_SIZE 0x10000
58 #define BIOS_CFG_IOPORT 0x510
59 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
60 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
61 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
62 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
64 #define MAX_IDE_BUS 2
66 static FDCtrl *floppy_controller;
67 static RTCState *rtc_state;
68 static PITState *pit;
69 static PCII440FXState *i440fx_state;
71 #define E820_NR_ENTRIES 16
73 struct e820_entry {
74 uint64_t address;
75 uint64_t length;
76 uint32_t type;
79 struct e820_table {
80 uint32_t count;
81 struct e820_entry entry[E820_NR_ENTRIES];
84 static struct e820_table e820_table;
86 typedef struct isa_irq_state {
87 qemu_irq *i8259;
88 qemu_irq *ioapic;
89 } IsaIrqState;
91 static void isa_irq_handler(void *opaque, int n, int level)
93 IsaIrqState *isa = (IsaIrqState *)opaque;
95 if (n < 16) {
96 qemu_set_irq(isa->i8259[n], level);
98 if (isa->ioapic)
99 qemu_set_irq(isa->ioapic[n], level);
102 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
106 /* MSDOS compatibility mode FPU exception support */
107 static qemu_irq ferr_irq;
108 /* XXX: add IGNNE support */
109 void cpu_set_ferr(CPUX86State *s)
111 qemu_irq_raise(ferr_irq);
114 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
116 qemu_irq_lower(ferr_irq);
119 /* TSC handling */
120 uint64_t cpu_get_tsc(CPUX86State *env)
122 return cpu_get_ticks();
125 /* SMM support */
126 void cpu_smm_update(CPUState *env)
128 if (i440fx_state && env == first_cpu)
129 i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
133 /* IRQ handling */
134 int cpu_get_pic_interrupt(CPUState *env)
136 int intno;
138 intno = apic_get_interrupt(env);
139 if (intno >= 0) {
140 /* set irq request if a PIC irq is still pending */
141 /* XXX: improve that */
142 pic_update_irq(isa_pic);
143 return intno;
145 /* read the irq from the PIC */
146 if (!apic_accept_pic_intr(env))
147 return -1;
149 intno = pic_read_irq(isa_pic);
150 return intno;
153 static void pic_irq_request(void *opaque, int irq, int level)
155 CPUState *env = first_cpu;
157 if (env->apic_state) {
158 while (env) {
159 if (apic_accept_pic_intr(env))
160 apic_deliver_pic_intr(env, level);
161 env = env->next_cpu;
163 } else {
164 if (level)
165 cpu_interrupt(env, CPU_INTERRUPT_HARD);
166 else
167 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
171 /* PC cmos mappings */
173 #define REG_EQUIPMENT_BYTE 0x14
175 static int cmos_get_fd_drive_type(int fd0)
177 int val;
179 switch (fd0) {
180 case 0:
181 /* 1.44 Mb 3"5 drive */
182 val = 4;
183 break;
184 case 1:
185 /* 2.88 Mb 3"5 drive */
186 val = 5;
187 break;
188 case 2:
189 /* 1.2 Mb 5"5 drive */
190 val = 2;
191 break;
192 default:
193 val = 0;
194 break;
196 return val;
199 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
201 RTCState *s = rtc_state;
202 int cylinders, heads, sectors;
203 bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
204 rtc_set_memory(s, type_ofs, 47);
205 rtc_set_memory(s, info_ofs, cylinders);
206 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
207 rtc_set_memory(s, info_ofs + 2, heads);
208 rtc_set_memory(s, info_ofs + 3, 0xff);
209 rtc_set_memory(s, info_ofs + 4, 0xff);
210 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
211 rtc_set_memory(s, info_ofs + 6, cylinders);
212 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
213 rtc_set_memory(s, info_ofs + 8, sectors);
216 /* convert boot_device letter to something recognizable by the bios */
217 static int boot_device2nibble(char boot_device)
219 switch(boot_device) {
220 case 'a':
221 case 'b':
222 return 0x01; /* floppy boot */
223 case 'c':
224 return 0x02; /* hard drive boot */
225 case 'd':
226 return 0x03; /* CD-ROM boot */
227 case 'n':
228 return 0x04; /* Network boot */
230 return 0;
233 /* copy/pasted from cmos_init, should be made a general function
234 and used there as well */
235 static int pc_boot_set(void *opaque, const char *boot_device)
237 Monitor *mon = cur_mon;
238 #define PC_MAX_BOOT_DEVICES 3
239 RTCState *s = (RTCState *)opaque;
240 int nbds, bds[3] = { 0, };
241 int i;
243 nbds = strlen(boot_device);
244 if (nbds > PC_MAX_BOOT_DEVICES) {
245 monitor_printf(mon, "Too many boot devices for PC\n");
246 return(1);
248 for (i = 0; i < nbds; i++) {
249 bds[i] = boot_device2nibble(boot_device[i]);
250 if (bds[i] == 0) {
251 monitor_printf(mon, "Invalid boot device for PC: '%c'\n",
252 boot_device[i]);
253 return(1);
256 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
257 rtc_set_memory(s, 0x38, (bds[2] << 4));
258 return(0);
261 /* hd_table must contain 4 block drivers */
262 static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
263 const char *boot_device, DriveInfo **hd_table)
265 RTCState *s = rtc_state;
266 int nbds, bds[3] = { 0, };
267 int val;
268 int fd0, fd1, nb;
269 int i;
271 /* various important CMOS locations needed by PC/Bochs bios */
273 /* memory size */
274 val = 640; /* base memory in K */
275 rtc_set_memory(s, 0x15, val);
276 rtc_set_memory(s, 0x16, val >> 8);
278 val = (ram_size / 1024) - 1024;
279 if (val > 65535)
280 val = 65535;
281 rtc_set_memory(s, 0x17, val);
282 rtc_set_memory(s, 0x18, val >> 8);
283 rtc_set_memory(s, 0x30, val);
284 rtc_set_memory(s, 0x31, val >> 8);
286 if (above_4g_mem_size) {
287 rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
288 rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
289 rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
292 if (ram_size > (16 * 1024 * 1024))
293 val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
294 else
295 val = 0;
296 if (val > 65535)
297 val = 65535;
298 rtc_set_memory(s, 0x34, val);
299 rtc_set_memory(s, 0x35, val >> 8);
301 /* set the number of CPU */
302 rtc_set_memory(s, 0x5f, smp_cpus - 1);
304 /* set boot devices, and disable floppy signature check if requested */
305 #define PC_MAX_BOOT_DEVICES 3
306 nbds = strlen(boot_device);
307 if (nbds > PC_MAX_BOOT_DEVICES) {
308 fprintf(stderr, "Too many boot devices for PC\n");
309 exit(1);
311 for (i = 0; i < nbds; i++) {
312 bds[i] = boot_device2nibble(boot_device[i]);
313 if (bds[i] == 0) {
314 fprintf(stderr, "Invalid boot device for PC: '%c'\n",
315 boot_device[i]);
316 exit(1);
319 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
320 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
322 /* floppy type */
324 fd0 = fdctrl_get_drive_type(floppy_controller, 0);
325 fd1 = fdctrl_get_drive_type(floppy_controller, 1);
327 val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
328 rtc_set_memory(s, 0x10, val);
330 val = 0;
331 nb = 0;
332 if (fd0 < 3)
333 nb++;
334 if (fd1 < 3)
335 nb++;
336 switch (nb) {
337 case 0:
338 break;
339 case 1:
340 val |= 0x01; /* 1 drive, ready for boot */
341 break;
342 case 2:
343 val |= 0x41; /* 2 drives, ready for boot */
344 break;
346 val |= 0x02; /* FPU is there */
347 val |= 0x04; /* PS/2 mouse installed */
348 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
350 /* hard drives */
352 rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
353 if (hd_table[0])
354 cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv);
355 if (hd_table[1])
356 cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv);
358 val = 0;
359 for (i = 0; i < 4; i++) {
360 if (hd_table[i]) {
361 int cylinders, heads, sectors, translation;
362 /* NOTE: bdrv_get_geometry_hint() returns the physical
363 geometry. It is always such that: 1 <= sects <= 63, 1
364 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
365 geometry can be different if a translation is done. */
366 translation = bdrv_get_translation_hint(hd_table[i]->bdrv);
367 if (translation == BIOS_ATA_TRANSLATION_AUTO) {
368 bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, &sectors);
369 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
370 /* No translation. */
371 translation = 0;
372 } else {
373 /* LBA translation. */
374 translation = 1;
376 } else {
377 translation--;
379 val |= translation << (i * 2);
382 rtc_set_memory(s, 0x39, val);
385 void ioport_set_a20(int enable)
387 /* XXX: send to all CPUs ? */
388 cpu_x86_set_a20(first_cpu, enable);
391 int ioport_get_a20(void)
393 return ((first_cpu->a20_mask >> 20) & 1);
396 static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
398 ioport_set_a20((val >> 1) & 1);
399 /* XXX: bit 0 is fast reset */
402 static uint32_t ioport92_read(void *opaque, uint32_t addr)
404 return ioport_get_a20() << 1;
407 /***********************************************************/
408 /* Bochs BIOS debug ports */
410 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
412 static const char shutdown_str[8] = "Shutdown";
413 static int shutdown_index = 0;
415 switch(addr) {
416 /* Bochs BIOS messages */
417 case 0x400:
418 case 0x401:
419 fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
420 exit(1);
421 case 0x402:
422 case 0x403:
423 #ifdef DEBUG_BIOS
424 fprintf(stderr, "%c", val);
425 #endif
426 break;
427 case 0x8900:
428 /* same as Bochs power off */
429 if (val == shutdown_str[shutdown_index]) {
430 shutdown_index++;
431 if (shutdown_index == 8) {
432 shutdown_index = 0;
433 qemu_system_shutdown_request();
435 } else {
436 shutdown_index = 0;
438 break;
440 /* LGPL'ed VGA BIOS messages */
441 case 0x501:
442 case 0x502:
443 fprintf(stderr, "VGA BIOS panic, line %d\n", val);
444 exit(1);
445 case 0x500:
446 case 0x503:
447 #ifdef DEBUG_BIOS
448 fprintf(stderr, "%c", val);
449 #endif
450 break;
454 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
456 int index = e820_table.count;
457 struct e820_entry *entry;
459 if (index >= E820_NR_ENTRIES)
460 return -EBUSY;
461 entry = &e820_table.entry[index];
463 entry->address = address;
464 entry->length = length;
465 entry->type = type;
467 e820_table.count++;
468 return e820_table.count;
471 static void *bochs_bios_init(void)
473 void *fw_cfg;
474 uint8_t *smbios_table;
475 size_t smbios_len;
476 uint64_t *numa_fw_cfg;
477 int i, j;
479 register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
480 register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
481 register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
482 register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
483 register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
485 register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
486 register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
487 register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
488 register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
490 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
492 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
493 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
494 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
495 acpi_tables_len);
496 fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
498 smbios_table = smbios_get_table(&smbios_len);
499 if (smbios_table)
500 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
501 smbios_table, smbios_len);
502 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
503 sizeof(struct e820_table));
505 /* allocate memory for the NUMA channel: one (64bit) word for the number
506 * of nodes, one word for each VCPU->node and one word for each node to
507 * hold the amount of memory.
509 numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
510 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
511 for (i = 0; i < smp_cpus; i++) {
512 for (j = 0; j < nb_numa_nodes; j++) {
513 if (node_cpumask[j] & (1 << i)) {
514 numa_fw_cfg[i + 1] = cpu_to_le64(j);
515 break;
519 for (i = 0; i < nb_numa_nodes; i++) {
520 numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
522 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
523 (1 + smp_cpus + nb_numa_nodes) * 8);
525 return fw_cfg;
528 static long get_file_size(FILE *f)
530 long where, size;
532 /* XXX: on Unix systems, using fstat() probably makes more sense */
534 where = ftell(f);
535 fseek(f, 0, SEEK_END);
536 size = ftell(f);
537 fseek(f, where, SEEK_SET);
539 return size;
542 static void load_linux(void *fw_cfg,
543 const char *kernel_filename,
544 const char *initrd_filename,
545 const char *kernel_cmdline,
546 target_phys_addr_t max_ram_size)
548 uint16_t protocol;
549 int setup_size, kernel_size, initrd_size = 0, cmdline_size;
550 uint32_t initrd_max;
551 uint8_t header[8192], *setup, *kernel, *initrd_data;
552 target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
553 FILE *f;
554 char *vmode;
556 /* Align to 16 bytes as a paranoia measure */
557 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
559 /* load the kernel header */
560 f = fopen(kernel_filename, "rb");
561 if (!f || !(kernel_size = get_file_size(f)) ||
562 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
563 MIN(ARRAY_SIZE(header), kernel_size)) {
564 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
565 kernel_filename, strerror(errno));
566 exit(1);
569 /* kernel protocol version */
570 #if 0
571 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
572 #endif
573 if (ldl_p(header+0x202) == 0x53726448)
574 protocol = lduw_p(header+0x206);
575 else {
576 /* This looks like a multiboot kernel. If it is, let's stop
577 treating it like a Linux kernel. */
578 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
579 kernel_cmdline, kernel_size, header))
580 return;
581 protocol = 0;
584 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
585 /* Low kernel */
586 real_addr = 0x90000;
587 cmdline_addr = 0x9a000 - cmdline_size;
588 prot_addr = 0x10000;
589 } else if (protocol < 0x202) {
590 /* High but ancient kernel */
591 real_addr = 0x90000;
592 cmdline_addr = 0x9a000 - cmdline_size;
593 prot_addr = 0x100000;
594 } else {
595 /* High and recent kernel */
596 real_addr = 0x10000;
597 cmdline_addr = 0x20000;
598 prot_addr = 0x100000;
601 #if 0
602 fprintf(stderr,
603 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
604 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
605 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
606 real_addr,
607 cmdline_addr,
608 prot_addr);
609 #endif
611 /* highest address for loading the initrd */
612 if (protocol >= 0x203)
613 initrd_max = ldl_p(header+0x22c);
614 else
615 initrd_max = 0x37ffffff;
617 if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
618 initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
620 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
621 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
622 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
623 (uint8_t*)strdup(kernel_cmdline),
624 strlen(kernel_cmdline)+1);
626 if (protocol >= 0x202) {
627 stl_p(header+0x228, cmdline_addr);
628 } else {
629 stw_p(header+0x20, 0xA33F);
630 stw_p(header+0x22, cmdline_addr-real_addr);
633 /* handle vga= parameter */
634 vmode = strstr(kernel_cmdline, "vga=");
635 if (vmode) {
636 unsigned int video_mode;
637 /* skip "vga=" */
638 vmode += 4;
639 if (!strncmp(vmode, "normal", 6)) {
640 video_mode = 0xffff;
641 } else if (!strncmp(vmode, "ext", 3)) {
642 video_mode = 0xfffe;
643 } else if (!strncmp(vmode, "ask", 3)) {
644 video_mode = 0xfffd;
645 } else {
646 video_mode = strtol(vmode, NULL, 0);
648 stw_p(header+0x1fa, video_mode);
651 /* loader type */
652 /* High nybble = B reserved for Qemu; low nybble is revision number.
653 If this code is substantially changed, you may want to consider
654 incrementing the revision. */
655 if (protocol >= 0x200)
656 header[0x210] = 0xB0;
658 /* heap */
659 if (protocol >= 0x201) {
660 header[0x211] |= 0x80; /* CAN_USE_HEAP */
661 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
664 /* load initrd */
665 if (initrd_filename) {
666 if (protocol < 0x200) {
667 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
668 exit(1);
671 initrd_size = get_image_size(initrd_filename);
672 initrd_addr = (initrd_max-initrd_size) & ~4095;
674 initrd_data = qemu_malloc(initrd_size);
675 load_image(initrd_filename, initrd_data);
677 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
678 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
679 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
681 stl_p(header+0x218, initrd_addr);
682 stl_p(header+0x21c, initrd_size);
685 /* load kernel and setup */
686 setup_size = header[0x1f1];
687 if (setup_size == 0)
688 setup_size = 4;
689 setup_size = (setup_size+1)*512;
690 kernel_size -= setup_size;
692 setup = qemu_malloc(setup_size);
693 kernel = qemu_malloc(kernel_size);
694 fseek(f, 0, SEEK_SET);
695 if (fread(setup, 1, setup_size, f) != setup_size) {
696 fprintf(stderr, "fread() failed\n");
697 exit(1);
699 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
700 fprintf(stderr, "fread() failed\n");
701 exit(1);
703 fclose(f);
704 memcpy(setup, header, MIN(sizeof(header), setup_size));
706 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
707 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
708 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
710 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
711 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
712 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
714 option_rom[nb_option_roms] = "linuxboot.bin";
715 nb_option_roms++;
718 static const int ide_iobase[2] = { 0x1f0, 0x170 };
719 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
720 static const int ide_irq[2] = { 14, 15 };
722 #define NE2000_NB_MAX 6
724 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
725 0x280, 0x380 };
726 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
728 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
729 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
731 #ifdef HAS_AUDIO
732 static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
734 struct soundhw *c;
736 for (c = soundhw; c->name; ++c) {
737 if (c->enabled) {
738 if (c->isa) {
739 c->init.init_isa(pic);
740 } else {
741 if (pci_bus) {
742 c->init.init_pci(pci_bus);
748 #endif
750 static void pc_init_ne2k_isa(NICInfo *nd)
752 static int nb_ne2k = 0;
754 if (nb_ne2k == NE2000_NB_MAX)
755 return;
756 isa_ne2000_init(ne2000_io[nb_ne2k],
757 ne2000_irq[nb_ne2k], nd);
758 nb_ne2k++;
761 int cpu_is_bsp(CPUState *env)
763 /* We hard-wire the BSP to the first CPU. */
764 return env->cpu_index == 0;
767 static CPUState *pc_new_cpu(const char *cpu_model)
769 CPUState *env;
771 env = cpu_init(cpu_model);
772 if (!env) {
773 fprintf(stderr, "Unable to find x86 CPU definition\n");
774 exit(1);
776 if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
777 env->cpuid_apic_id = env->cpu_index;
778 /* APIC reset callback resets cpu */
779 apic_init(env);
780 } else {
781 qemu_register_reset((QEMUResetHandler*)cpu_reset, env);
783 return env;
786 /* PC hardware initialisation */
787 static void pc_init1(ram_addr_t ram_size,
788 const char *boot_device,
789 const char *kernel_filename,
790 const char *kernel_cmdline,
791 const char *initrd_filename,
792 const char *cpu_model,
793 int pci_enabled)
795 char *filename;
796 int ret, linux_boot, i;
797 ram_addr_t ram_addr, bios_offset, option_rom_offset;
798 ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
799 int bios_size, isa_bios_size;
800 PCIBus *pci_bus;
801 ISADevice *isa_dev;
802 int piix3_devfn = -1;
803 CPUState *env;
804 qemu_irq *cpu_irq;
805 qemu_irq *isa_irq;
806 qemu_irq *i8259;
807 IsaIrqState *isa_irq_state;
808 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
809 DriveInfo *fd[MAX_FD];
810 void *fw_cfg;
812 if (ram_size >= 0xe0000000 ) {
813 above_4g_mem_size = ram_size - 0xe0000000;
814 below_4g_mem_size = 0xe0000000;
815 } else {
816 below_4g_mem_size = ram_size;
819 linux_boot = (kernel_filename != NULL);
821 /* init CPUs */
822 if (cpu_model == NULL) {
823 #ifdef TARGET_X86_64
824 cpu_model = "qemu64";
825 #else
826 cpu_model = "qemu32";
827 #endif
830 for (i = 0; i < smp_cpus; i++) {
831 env = pc_new_cpu(cpu_model);
834 vmport_init();
836 /* allocate RAM */
837 ram_addr = qemu_ram_alloc(below_4g_mem_size);
838 cpu_register_physical_memory(0, 0xa0000, ram_addr);
839 cpu_register_physical_memory(0x100000,
840 below_4g_mem_size - 0x100000,
841 ram_addr + 0x100000);
843 /* above 4giga memory allocation */
844 if (above_4g_mem_size > 0) {
845 #if TARGET_PHYS_ADDR_BITS == 32
846 hw_error("To much RAM for 32-bit physical address");
847 #else
848 ram_addr = qemu_ram_alloc(above_4g_mem_size);
849 cpu_register_physical_memory(0x100000000ULL,
850 above_4g_mem_size,
851 ram_addr);
852 #endif
856 /* BIOS load */
857 if (bios_name == NULL)
858 bios_name = BIOS_FILENAME;
859 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
860 if (filename) {
861 bios_size = get_image_size(filename);
862 } else {
863 bios_size = -1;
865 if (bios_size <= 0 ||
866 (bios_size % 65536) != 0) {
867 goto bios_error;
869 bios_offset = qemu_ram_alloc(bios_size);
870 ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size));
871 if (ret != 0) {
872 bios_error:
873 fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
874 exit(1);
876 if (filename) {
877 qemu_free(filename);
879 /* map the last 128KB of the BIOS in ISA space */
880 isa_bios_size = bios_size;
881 if (isa_bios_size > (128 * 1024))
882 isa_bios_size = 128 * 1024;
883 cpu_register_physical_memory(0x100000 - isa_bios_size,
884 isa_bios_size,
885 (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
887 option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE);
888 cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset);
890 /* map all the bios at the top of memory */
891 cpu_register_physical_memory((uint32_t)(-bios_size),
892 bios_size, bios_offset | IO_MEM_ROM);
894 fw_cfg = bochs_bios_init();
895 rom_set_fw(fw_cfg);
897 if (linux_boot) {
898 load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
901 for (i = 0; i < nb_option_roms; i++) {
902 rom_add_option(option_rom[i]);
905 cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
906 i8259 = i8259_init(cpu_irq[0]);
907 isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
908 isa_irq_state->i8259 = i8259;
909 isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
911 if (pci_enabled) {
912 pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq);
913 } else {
914 pci_bus = NULL;
915 isa_bus_new(NULL);
917 isa_bus_irqs(isa_irq);
919 ferr_irq = isa_reserve_irq(13);
921 /* init basic PC hardware */
922 register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
924 register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
926 if (cirrus_vga_enabled) {
927 if (pci_enabled) {
928 pci_cirrus_vga_init(pci_bus);
929 } else {
930 isa_cirrus_vga_init();
932 } else if (vmsvga_enabled) {
933 if (pci_enabled)
934 pci_vmsvga_init(pci_bus);
935 else
936 fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
937 } else if (std_vga_enabled) {
938 if (pci_enabled) {
939 pci_vga_init(pci_bus, 0, 0);
940 } else {
941 isa_vga_init();
945 rtc_state = rtc_init(2000);
947 qemu_register_boot_set(pc_boot_set, rtc_state);
949 register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
950 register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
952 if (pci_enabled) {
953 isa_irq_state->ioapic = ioapic_init();
955 pit = pit_init(0x40, isa_reserve_irq(0));
956 pcspk_init(pit);
957 if (!no_hpet) {
958 hpet_init(isa_irq);
961 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
962 if (serial_hds[i]) {
963 serial_isa_init(i, serial_hds[i]);
967 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
968 if (parallel_hds[i]) {
969 parallel_init(i, parallel_hds[i]);
973 for(i = 0; i < nb_nics; i++) {
974 NICInfo *nd = &nd_table[i];
976 if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
977 pc_init_ne2k_isa(nd);
978 else
979 pci_nic_init_nofail(nd, "e1000", NULL);
982 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
983 fprintf(stderr, "qemu: too many IDE bus\n");
984 exit(1);
987 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
988 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
991 if (pci_enabled) {
992 pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
993 } else {
994 for(i = 0; i < MAX_IDE_BUS; i++) {
995 isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
996 hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
1000 isa_dev = isa_create_simple("i8042");
1001 DMA_init(0);
1002 #ifdef HAS_AUDIO
1003 audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
1004 #endif
1006 for(i = 0; i < MAX_FD; i++) {
1007 fd[i] = drive_get(IF_FLOPPY, 0, i);
1009 floppy_controller = fdctrl_init_isa(fd);
1011 cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1013 if (pci_enabled && usb_enabled) {
1014 usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1017 if (pci_enabled && acpi_enabled) {
1018 uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1019 i2c_bus *smbus;
1021 /* TODO: Populate SPD eeprom data. */
1022 smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
1023 isa_reserve_irq(9));
1024 for (i = 0; i < 8; i++) {
1025 DeviceState *eeprom;
1026 eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
1027 qdev_prop_set_uint8(eeprom, "address", 0x50 + i);
1028 qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
1029 qdev_init_nofail(eeprom);
1031 piix4_acpi_system_hot_add_init(pci_bus);
1034 if (i440fx_state) {
1035 i440fx_init_memory_mappings(i440fx_state);
1038 if (pci_enabled) {
1039 int max_bus;
1040 int bus;
1042 max_bus = drive_get_max_bus(IF_SCSI);
1043 for (bus = 0; bus <= max_bus; bus++) {
1044 pci_create_simple(pci_bus, -1, "lsi53c895a");
1049 static void pc_init_pci(ram_addr_t ram_size,
1050 const char *boot_device,
1051 const char *kernel_filename,
1052 const char *kernel_cmdline,
1053 const char *initrd_filename,
1054 const char *cpu_model)
1056 pc_init1(ram_size, boot_device,
1057 kernel_filename, kernel_cmdline,
1058 initrd_filename, cpu_model, 1);
1061 static void pc_init_isa(ram_addr_t ram_size,
1062 const char *boot_device,
1063 const char *kernel_filename,
1064 const char *kernel_cmdline,
1065 const char *initrd_filename,
1066 const char *cpu_model)
1068 if (cpu_model == NULL)
1069 cpu_model = "486";
1070 pc_init1(ram_size, boot_device,
1071 kernel_filename, kernel_cmdline,
1072 initrd_filename, cpu_model, 0);
1075 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
1076 BIOS will read it and start S3 resume at POST Entry */
1077 void cmos_set_s3_resume(void)
1079 if (rtc_state)
1080 rtc_set_memory(rtc_state, 0xF, 0xFE);
1083 static QEMUMachine pc_machine = {
1084 .name = "pc-0.13",
1085 .alias = "pc",
1086 .desc = "Standard PC",
1087 .init = pc_init_pci,
1088 .max_cpus = 255,
1089 .is_default = 1,
1092 static QEMUMachine pc_machine_v0_12 = {
1093 .name = "pc-0.12",
1094 .desc = "Standard PC",
1095 .init = pc_init_pci,
1096 .max_cpus = 255,
1097 .compat_props = (GlobalProperty[]) {
1099 .driver = "virtio-serial-pci",
1100 .property = "max_nr_ports",
1101 .value = stringify(1),
1103 .driver = "virtio-serial-pci",
1104 .property = "vectors",
1105 .value = stringify(0),
1107 { /* end of list */ }
1111 static QEMUMachine pc_machine_v0_11 = {
1112 .name = "pc-0.11",
1113 .desc = "Standard PC, qemu 0.11",
1114 .init = pc_init_pci,
1115 .max_cpus = 255,
1116 .compat_props = (GlobalProperty[]) {
1118 .driver = "virtio-blk-pci",
1119 .property = "vectors",
1120 .value = stringify(0),
1122 .driver = "virtio-serial-pci",
1123 .property = "max_nr_ports",
1124 .value = stringify(1),
1126 .driver = "virtio-serial-pci",
1127 .property = "vectors",
1128 .value = stringify(0),
1130 .driver = "ide-drive",
1131 .property = "ver",
1132 .value = "0.11",
1134 .driver = "scsi-disk",
1135 .property = "ver",
1136 .value = "0.11",
1138 .driver = "PCI",
1139 .property = "rombar",
1140 .value = stringify(0),
1142 { /* end of list */ }
1146 static QEMUMachine pc_machine_v0_10 = {
1147 .name = "pc-0.10",
1148 .desc = "Standard PC, qemu 0.10",
1149 .init = pc_init_pci,
1150 .max_cpus = 255,
1151 .compat_props = (GlobalProperty[]) {
1153 .driver = "virtio-blk-pci",
1154 .property = "class",
1155 .value = stringify(PCI_CLASS_STORAGE_OTHER),
1157 .driver = "virtio-serial-pci",
1158 .property = "class",
1159 .value = stringify(PCI_CLASS_DISPLAY_OTHER),
1161 .driver = "virtio-serial-pci",
1162 .property = "max_nr_ports",
1163 .value = stringify(1),
1165 .driver = "virtio-serial-pci",
1166 .property = "vectors",
1167 .value = stringify(0),
1169 .driver = "virtio-net-pci",
1170 .property = "vectors",
1171 .value = stringify(0),
1173 .driver = "virtio-blk-pci",
1174 .property = "vectors",
1175 .value = stringify(0),
1177 .driver = "ide-drive",
1178 .property = "ver",
1179 .value = "0.10",
1181 .driver = "scsi-disk",
1182 .property = "ver",
1183 .value = "0.10",
1185 .driver = "PCI",
1186 .property = "rombar",
1187 .value = stringify(0),
1189 { /* end of list */ }
1193 static QEMUMachine isapc_machine = {
1194 .name = "isapc",
1195 .desc = "ISA-only PC",
1196 .init = pc_init_isa,
1197 .max_cpus = 1,
1200 static void pc_machine_init(void)
1202 qemu_register_machine(&pc_machine);
1203 qemu_register_machine(&pc_machine_v0_12);
1204 qemu_register_machine(&pc_machine_v0_11);
1205 qemu_register_machine(&pc_machine_v0_10);
1206 qemu_register_machine(&isapc_machine);
1209 machine_init(pc_machine_init);