2 * RISC-V GDB Server Stub
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "exec/gdbstub.h"
30 static const struct TypeSize vec_lanes
[] = {
32 { "uint128", "quads", 128, 'q' },
34 { "uint64", "longs", 64, 'l' },
36 { "uint32", "words", 32, 'w' },
38 { "uint16", "shorts", 16, 's' },
40 * TODO: currently there is no reliable way of telling
41 * if the remote gdb actually understands ieee_half so
42 * we don't expose it in the target description for now.
43 * { "ieee_half", 16, 'h', 'f' },
46 { "uint8", "bytes", 8, 'b' },
49 int riscv_cpu_gdb_read_register(CPUState
*cs
, GByteArray
*mem_buf
, int n
)
51 RISCVCPU
*cpu
= RISCV_CPU(cs
);
52 CPURISCVState
*env
= &cpu
->env
;
63 switch (env
->misa_mxl_max
) {
65 return gdb_get_reg32(mem_buf
, tmp
);
68 return gdb_get_reg64(mem_buf
, tmp
);
70 g_assert_not_reached();
75 int riscv_cpu_gdb_write_register(CPUState
*cs
, uint8_t *mem_buf
, int n
)
77 RISCVCPU
*cpu
= RISCV_CPU(cs
);
78 CPURISCVState
*env
= &cpu
->env
;
82 switch (env
->misa_mxl_max
) {
84 tmp
= (int32_t)ldl_p(mem_buf
);
89 if (env
->xl
< MXL_RV64
) {
90 tmp
= (int32_t)ldq_p(mem_buf
);
97 g_assert_not_reached();
99 if (n
> 0 && n
< 32) {
101 } else if (n
== 32) {
108 static int riscv_gdb_get_fpu(CPURISCVState
*env
, GByteArray
*buf
, int n
)
111 if (env
->misa_ext
& RVD
) {
112 return gdb_get_reg64(buf
, env
->fpr
[n
]);
114 if (env
->misa_ext
& RVF
) {
115 return gdb_get_reg32(buf
, env
->fpr
[n
]);
117 /* there is hole between ft11 and fflags in fpu.xml */
118 } else if (n
< 36 && n
> 32) {
119 target_ulong val
= 0;
122 * CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP
123 * register 33, so we recalculate the map index.
124 * This also works for CSR_FRM and CSR_FCSR.
126 result
= riscv_csrrw_debug(env
, n
- 32, &val
,
128 if (result
== RISCV_EXCP_NONE
) {
129 return gdb_get_regl(buf
, val
);
135 static int riscv_gdb_set_fpu(CPURISCVState
*env
, uint8_t *mem_buf
, int n
)
138 env
->fpr
[n
] = ldq_p(mem_buf
); /* always 64-bit */
139 return sizeof(uint64_t);
140 /* there is hole between ft11 and fflags in fpu.xml */
141 } else if (n
< 36 && n
> 32) {
142 target_ulong val
= ldtul_p(mem_buf
);
145 * CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP
146 * register 33, so we recalculate the map index.
147 * This also works for CSR_FRM and CSR_FCSR.
149 result
= riscv_csrrw_debug(env
, n
- 32, NULL
,
151 if (result
== RISCV_EXCP_NONE
) {
152 return sizeof(target_ulong
);
159 * Convert register index number passed by GDB to the correspond
160 * vector CSR number. Vector CSRs are defined after vector registers
161 * in dynamic generated riscv-vector.xml, thus the starting register index
162 * of vector CSRs is 32.
163 * Return 0 if register index number is out of range.
165 static int riscv_gdb_vector_csrno(int num_regs
)
168 * The order of vector CSRs in the switch case
169 * should match with the order defined in csr_ops[].
187 /* Unknown register. */
192 static int riscv_gdb_get_vector(CPURISCVState
*env
, GByteArray
*buf
, int n
)
194 uint16_t vlenb
= env_archcpu(env
)->cfg
.vlen
>> 3;
198 for (i
= 0; i
< vlenb
; i
+= 8) {
199 cnt
+= gdb_get_reg64(buf
,
200 env
->vreg
[(n
* vlenb
+ i
) / 8]);
205 int csrno
= riscv_gdb_vector_csrno(n
);
211 target_ulong val
= 0;
212 int result
= riscv_csrrw_debug(env
, csrno
, &val
, 0, 0);
215 return gdb_get_regl(buf
, val
);
221 static int riscv_gdb_set_vector(CPURISCVState
*env
, uint8_t *mem_buf
, int n
)
223 uint16_t vlenb
= env_archcpu(env
)->cfg
.vlen
>> 3;
226 for (i
= 0; i
< vlenb
; i
+= 8) {
227 env
->vreg
[(n
* vlenb
+ i
) / 8] = ldq_p(mem_buf
+ i
);
232 int csrno
= riscv_gdb_vector_csrno(n
);
238 target_ulong val
= ldtul_p(mem_buf
);
239 int result
= riscv_csrrw_debug(env
, csrno
, NULL
, val
, -1);
242 return sizeof(target_ulong
);
248 static int riscv_gdb_get_csr(CPURISCVState
*env
, GByteArray
*buf
, int n
)
250 if (n
< CSR_TABLE_SIZE
) {
251 target_ulong val
= 0;
254 result
= riscv_csrrw_debug(env
, n
, &val
, 0, 0);
255 if (result
== RISCV_EXCP_NONE
) {
256 return gdb_get_regl(buf
, val
);
262 static int riscv_gdb_set_csr(CPURISCVState
*env
, uint8_t *mem_buf
, int n
)
264 if (n
< CSR_TABLE_SIZE
) {
265 target_ulong val
= ldtul_p(mem_buf
);
268 result
= riscv_csrrw_debug(env
, n
, NULL
, val
, -1);
269 if (result
== RISCV_EXCP_NONE
) {
270 return sizeof(target_ulong
);
276 static int riscv_gdb_get_virtual(CPURISCVState
*cs
, GByteArray
*buf
, int n
)
279 #ifdef CONFIG_USER_ONLY
280 return gdb_get_regl(buf
, 0);
282 return gdb_get_regl(buf
, cs
->priv
);
288 static int riscv_gdb_set_virtual(CPURISCVState
*cs
, uint8_t *mem_buf
, int n
)
291 #ifndef CONFIG_USER_ONLY
292 cs
->priv
= ldtul_p(mem_buf
) & 0x3;
293 if (cs
->priv
== PRV_H
) {
297 return sizeof(target_ulong
);
302 static int riscv_gen_dynamic_csr_xml(CPUState
*cs
, int base_reg
)
304 RISCVCPU
*cpu
= RISCV_CPU(cs
);
305 CPURISCVState
*env
= &cpu
->env
;
306 GString
*s
= g_string_new(NULL
);
307 riscv_csr_predicate_fn predicate
;
308 int bitsize
= 16 << env
->misa_mxl_max
;
311 /* Until gdb knows about 128-bit registers */
316 g_string_printf(s
, "<?xml version=\"1.0\"?>");
317 g_string_append_printf(s
, "<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">");
318 g_string_append_printf(s
, "<feature name=\"org.gnu.gdb.riscv.csr\">");
320 for (i
= 0; i
< CSR_TABLE_SIZE
; i
++) {
321 predicate
= csr_ops
[i
].predicate
;
322 if (predicate
&& (predicate(env
, i
) == RISCV_EXCP_NONE
)) {
323 if (csr_ops
[i
].name
) {
324 g_string_append_printf(s
, "<reg name=\"%s\"", csr_ops
[i
].name
);
326 g_string_append_printf(s
, "<reg name=\"csr%03x\"", i
);
328 g_string_append_printf(s
, " bitsize=\"%d\"", bitsize
);
329 g_string_append_printf(s
, " regnum=\"%d\"/>", base_reg
+ i
);
333 g_string_append_printf(s
, "</feature>");
335 cpu
->dyn_csr_xml
= g_string_free(s
, false);
336 return CSR_TABLE_SIZE
;
339 static int ricsv_gen_dynamic_vector_xml(CPUState
*cs
, int base_reg
)
341 RISCVCPU
*cpu
= RISCV_CPU(cs
);
342 GString
*s
= g_string_new(NULL
);
343 g_autoptr(GString
) ts
= g_string_new("");
344 int reg_width
= cpu
->cfg
.vlen
;
348 g_string_printf(s
, "<?xml version=\"1.0\"?>");
349 g_string_append_printf(s
, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
350 g_string_append_printf(s
, "<feature name=\"org.gnu.gdb.riscv.vector\">");
352 /* First define types and totals in a whole VL */
353 for (i
= 0; i
< ARRAY_SIZE(vec_lanes
); i
++) {
354 int count
= reg_width
/ vec_lanes
[i
].size
;
355 g_string_printf(ts
, "%s", vec_lanes
[i
].id
);
356 g_string_append_printf(s
,
357 "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
358 ts
->str
, vec_lanes
[i
].gdb_type
, count
);
362 g_string_append_printf(s
, "<union id=\"riscv_vector\">");
363 for (i
= 0; i
< ARRAY_SIZE(vec_lanes
); i
++) {
364 g_string_append_printf(s
, "<field name=\"%c\" type=\"%s\"/>",
368 g_string_append(s
, "</union>");
370 /* Define vector registers */
371 for (i
= 0; i
< 32; i
++) {
372 g_string_append_printf(s
,
373 "<reg name=\"v%d\" bitsize=\"%d\""
374 " regnum=\"%d\" group=\"vector\""
375 " type=\"riscv_vector\"/>",
376 i
, reg_width
, base_reg
++);
380 /* Define vector CSRs */
381 const char *vector_csrs
[7] = {
382 "vstart", "vxsat", "vxrm", "vcsr",
383 "vl", "vtype", "vlenb"
386 for (i
= 0; i
< 7; i
++) {
387 g_string_append_printf(s
,
388 "<reg name=\"%s\" bitsize=\"%d\""
389 " regnum=\"%d\" group=\"vector\""
391 vector_csrs
[i
], TARGET_LONG_BITS
, base_reg
++);
395 g_string_append_printf(s
, "</feature>");
397 cpu
->dyn_vreg_xml
= g_string_free(s
, false);
401 void riscv_cpu_register_gdb_regs_for_features(CPUState
*cs
)
403 RISCVCPU
*cpu
= RISCV_CPU(cs
);
404 CPURISCVState
*env
= &cpu
->env
;
405 if (env
->misa_ext
& RVD
) {
406 gdb_register_coprocessor(cs
, riscv_gdb_get_fpu
, riscv_gdb_set_fpu
,
407 36, "riscv-64bit-fpu.xml", 0);
408 } else if (env
->misa_ext
& RVF
) {
409 gdb_register_coprocessor(cs
, riscv_gdb_get_fpu
, riscv_gdb_set_fpu
,
410 36, "riscv-32bit-fpu.xml", 0);
412 if (env
->misa_ext
& RVV
) {
413 gdb_register_coprocessor(cs
, riscv_gdb_get_vector
, riscv_gdb_set_vector
,
414 ricsv_gen_dynamic_vector_xml(cs
,
416 "riscv-vector.xml", 0);
418 switch (env
->misa_mxl_max
) {
420 gdb_register_coprocessor(cs
, riscv_gdb_get_virtual
,
421 riscv_gdb_set_virtual
,
422 1, "riscv-32bit-virtual.xml", 0);
426 gdb_register_coprocessor(cs
, riscv_gdb_get_virtual
,
427 riscv_gdb_set_virtual
,
428 1, "riscv-64bit-virtual.xml", 0);
431 g_assert_not_reached();
434 gdb_register_coprocessor(cs
, riscv_gdb_get_csr
, riscv_gdb_set_csr
,
435 riscv_gen_dynamic_csr_xml(cs
, cs
->gdb_num_regs
),