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tcg/aarch64: add ext argument to tcg_out_insn_3310
[qemu.git] / hw / net / vmxnet3.c
blob59b06b84126b68f8cc62323d61ca32a2475224e6
1 /*
2 * QEMU VMWARE VMXNET3 paravirtual NIC
3 *
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
5 *
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
7 *
8 * Authors:
9 * Dmitry Fleytman <dmitry@daynix.com>
10 * Tamir Shomer <tamirs@daynix.com>
11 * Yan Vugenfirer <yan@daynix.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2.
14 * See the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "hw/hw.h"
19 #include "hw/pci/pci.h"
20 #include "net/net.h"
21 #include "net/tap.h"
22 #include "net/checksum.h"
23 #include "sysemu/sysemu.h"
24 #include "qemu-common.h"
25 #include "qemu/bswap.h"
26 #include "hw/pci/msix.h"
27 #include "hw/pci/msi.h"
28
29 #include "vmxnet3.h"
30 #include "vmxnet_debug.h"
31 #include "vmware_utils.h"
32 #include "vmxnet_tx_pkt.h"
33 #include "vmxnet_rx_pkt.h"
34
35 #define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
36 #define VMXNET3_MSIX_BAR_SIZE 0x2000
37 #define MIN_BUF_SIZE 60
38
39 #define VMXNET3_BAR0_IDX (0)
40 #define VMXNET3_BAR1_IDX (1)
41 #define VMXNET3_MSIX_BAR_IDX (2)
42
43 #define VMXNET3_OFF_MSIX_TABLE (0x000)
44 #define VMXNET3_OFF_MSIX_PBA (0x800)
45
46 /* Link speed in Mbps should be shifted by 16 */
47 #define VMXNET3_LINK_SPEED (1000 << 16)
48
49 /* Link status: 1 - up, 0 - down. */
50 #define VMXNET3_LINK_STATUS_UP 0x1
51
52 /* Least significant bit should be set for revision and version */
53 #define VMXNET3_DEVICE_VERSION 0x1
54 #define VMXNET3_DEVICE_REVISION 0x1
55
56 /* Number of interrupt vectors for non-MSIx modes */
57 #define VMXNET3_MAX_NMSIX_INTRS (1)
58
59 /* Macros for rings descriptors access */
60 #define VMXNET3_READ_TX_QUEUE_DESCR8(dpa, field) \
61 (vmw_shmem_ld8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
62
63 #define VMXNET3_WRITE_TX_QUEUE_DESCR8(dpa, field, value) \
64 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field, value)))
65
66 #define VMXNET3_READ_TX_QUEUE_DESCR32(dpa, field) \
67 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
68
69 #define VMXNET3_WRITE_TX_QUEUE_DESCR32(dpa, field, value) \
70 (vmw_shmem_st32(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
71
72 #define VMXNET3_READ_TX_QUEUE_DESCR64(dpa, field) \
73 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field)))
74
75 #define VMXNET3_WRITE_TX_QUEUE_DESCR64(dpa, field, value) \
76 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_TxQueueDesc, field), value))
77
78 #define VMXNET3_READ_RX_QUEUE_DESCR64(dpa, field) \
79 (vmw_shmem_ld64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
80
81 #define VMXNET3_READ_RX_QUEUE_DESCR32(dpa, field) \
82 (vmw_shmem_ld32(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field)))
83
84 #define VMXNET3_WRITE_RX_QUEUE_DESCR64(dpa, field, value) \
85 (vmw_shmem_st64(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
86
87 #define VMXNET3_WRITE_RX_QUEUE_DESCR8(dpa, field, value) \
88 (vmw_shmem_st8(dpa + offsetof(struct Vmxnet3_RxQueueDesc, field), value))
89
90 /* Macros for guest driver shared area access */
91 #define VMXNET3_READ_DRV_SHARED64(shpa, field) \
92 (vmw_shmem_ld64(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
93
94 #define VMXNET3_READ_DRV_SHARED32(shpa, field) \
95 (vmw_shmem_ld32(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
96
97 #define VMXNET3_WRITE_DRV_SHARED32(shpa, field, val) \
98 (vmw_shmem_st32(shpa + offsetof(struct Vmxnet3_DriverShared, field), val))
99
100 #define VMXNET3_READ_DRV_SHARED16(shpa, field) \
101 (vmw_shmem_ld16(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
102
103 #define VMXNET3_READ_DRV_SHARED8(shpa, field) \
104 (vmw_shmem_ld8(shpa + offsetof(struct Vmxnet3_DriverShared, field)))
105
106 #define VMXNET3_READ_DRV_SHARED(shpa, field, b, l) \
107 (vmw_shmem_read(shpa + offsetof(struct Vmxnet3_DriverShared, field), b, l))
108
109 #define VMXNET_FLAG_IS_SET(field, flag) (((field) & (flag)) == (flag))
110
111 #define TYPE_VMXNET3 "vmxnet3"
112 #define VMXNET3(obj) OBJECT_CHECK(VMXNET3State, (obj), TYPE_VMXNET3)
113
114 /* Cyclic ring abstraction */
115 typedef struct {
116 hwaddr pa;
117 size_t size;
118 size_t cell_size;
119 size_t next;
120 uint8_t gen;
121 } Vmxnet3Ring;
122
123 static inline void vmxnet3_ring_init(Vmxnet3Ring *ring,
124 hwaddr pa,
125 size_t size,
126 size_t cell_size,
127 bool zero_region)
128 {
129 ring->pa = pa;
130 ring->size = size;
131 ring->cell_size = cell_size;
132 ring->gen = VMXNET3_INIT_GEN;
133 ring->next = 0;
134
135 if (zero_region) {
136 vmw_shmem_set(pa, 0, size * cell_size);
137 }
138 }
139
140 #define VMXNET3_RING_DUMP(macro, ring_name, ridx, r) \
141 macro("%s#%d: base %" PRIx64 " size %lu cell_size %lu gen %d next %lu", \
142 (ring_name), (ridx), \
143 (r)->pa, (r)->size, (r)->cell_size, (r)->gen, (r)->next)
144
145 static inline void vmxnet3_ring_inc(Vmxnet3Ring *ring)
146 {
147 if (++ring->next >= ring->size) {
148 ring->next = 0;
149 ring->gen ^= 1;
150 }
151 }
152
153 static inline void vmxnet3_ring_dec(Vmxnet3Ring *ring)
154 {
155 if (ring->next-- == 0) {
156 ring->next = ring->size - 1;
157 ring->gen ^= 1;
158 }
159 }
160
161 static inline hwaddr vmxnet3_ring_curr_cell_pa(Vmxnet3Ring *ring)
162 {
163 return ring->pa + ring->next * ring->cell_size;
164 }
165
166 static inline void vmxnet3_ring_read_curr_cell(Vmxnet3Ring *ring, void *buff)
167 {
168 vmw_shmem_read(vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
169 }
170
171 static inline void vmxnet3_ring_write_curr_cell(Vmxnet3Ring *ring, void *buff)
172 {
173 vmw_shmem_write(vmxnet3_ring_curr_cell_pa(ring), buff, ring->cell_size);
174 }
175
176 static inline size_t vmxnet3_ring_curr_cell_idx(Vmxnet3Ring *ring)
177 {
178 return ring->next;
179 }
180
181 static inline uint8_t vmxnet3_ring_curr_gen(Vmxnet3Ring *ring)
182 {
183 return ring->gen;
184 }
185
186 /* Debug trace-related functions */
187 static inline void
188 vmxnet3_dump_tx_descr(struct Vmxnet3_TxDesc *descr)
189 {
190 VMW_PKPRN("TX DESCR: "
191 "addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
192 "dtype: %d, ext1: %d, msscof: %d, hlen: %d, om: %d, "
193 "eop: %d, cq: %d, ext2: %d, ti: %d, tci: %d",
194 le64_to_cpu(descr->addr), descr->len, descr->gen, descr->rsvd,
195 descr->dtype, descr->ext1, descr->msscof, descr->hlen, descr->om,
196 descr->eop, descr->cq, descr->ext2, descr->ti, descr->tci);
197 }
198
199 static inline void
200 vmxnet3_dump_virt_hdr(struct virtio_net_hdr *vhdr)
201 {
202 VMW_PKPRN("VHDR: flags 0x%x, gso_type: 0x%x, hdr_len: %d, gso_size: %d, "
203 "csum_start: %d, csum_offset: %d",
204 vhdr->flags, vhdr->gso_type, vhdr->hdr_len, vhdr->gso_size,
205 vhdr->csum_start, vhdr->csum_offset);
206 }
207
208 static inline void
209 vmxnet3_dump_rx_descr(struct Vmxnet3_RxDesc *descr)
210 {
211 VMW_PKPRN("RX DESCR: addr %" PRIx64 ", len: %d, gen: %d, rsvd: %d, "
212 "dtype: %d, ext1: %d, btype: %d",
213 le64_to_cpu(descr->addr), descr->len, descr->gen,
214 descr->rsvd, descr->dtype, descr->ext1, descr->btype);
215 }
216
217 /* Device state and helper functions */
218 #define VMXNET3_RX_RINGS_PER_QUEUE (2)
219
220 typedef struct {
221 Vmxnet3Ring tx_ring;
222 Vmxnet3Ring comp_ring;
223
224 uint8_t intr_idx;
225 hwaddr tx_stats_pa;
226 struct UPT1_TxStats txq_stats;
227 } Vmxnet3TxqDescr;
228
229 typedef struct {
230 Vmxnet3Ring rx_ring[VMXNET3_RX_RINGS_PER_QUEUE];
231 Vmxnet3Ring comp_ring;
232 uint8_t intr_idx;
233 hwaddr rx_stats_pa;
234 struct UPT1_RxStats rxq_stats;
235 } Vmxnet3RxqDescr;
236
237 typedef struct {
238 bool is_masked;
239 bool is_pending;
240 bool is_asserted;
241 } Vmxnet3IntState;
242
243 typedef struct {
244 PCIDevice parent_obj;
245 NICState *nic;
246 NICConf conf;
247 MemoryRegion bar0;
248 MemoryRegion bar1;
249 MemoryRegion msix_bar;
250
251 Vmxnet3RxqDescr rxq_descr[VMXNET3_DEVICE_MAX_RX_QUEUES];
252 Vmxnet3TxqDescr txq_descr[VMXNET3_DEVICE_MAX_TX_QUEUES];
253
254 /* Whether MSI-X support was installed successfully */
255 bool msix_used;
256 /* Whether MSI support was installed successfully */
257 bool msi_used;
258 hwaddr drv_shmem;
259 hwaddr temp_shared_guest_driver_memory;
260
261 uint8_t txq_num;
262
263 /* This boolean tells whether RX packet being indicated has to */
264 /* be split into head and body chunks from different RX rings */
265 bool rx_packets_compound;
266
267 bool rx_vlan_stripping;
268 bool lro_supported;
269
270 uint8_t rxq_num;
271
272 /* Network MTU */
273 uint32_t mtu;
274
275 /* Maximum number of fragments for indicated TX packets */
276 uint32_t max_tx_frags;
277
278 /* Maximum number of fragments for indicated RX packets */
279 uint16_t max_rx_frags;
280
281 /* Index for events interrupt */
282 uint8_t event_int_idx;
283
284 /* Whether automatic interrupts masking enabled */
285 bool auto_int_masking;
286
287 bool peer_has_vhdr;
288
289 /* TX packets to QEMU interface */
290 struct VmxnetTxPkt *tx_pkt;
291 uint32_t offload_mode;
292 uint32_t cso_or_gso_size;
293 uint16_t tci;
294 bool needs_vlan;
295
296 struct VmxnetRxPkt *rx_pkt;
297
298 bool tx_sop;
299 bool skip_current_tx_pkt;
300
301 uint32_t device_active;
302 uint32_t last_command;
303
304 uint32_t link_status_and_speed;
305
306 Vmxnet3IntState interrupt_states[VMXNET3_MAX_INTRS];
307
308 uint32_t temp_mac; /* To store the low part first */
309
310 MACAddr perm_mac;
311 uint32_t vlan_table[VMXNET3_VFT_SIZE];
312 uint32_t rx_mode;
313 MACAddr *mcast_list;
314 uint32_t mcast_list_len;
315 uint32_t mcast_list_buff_size; /* needed for live migration. */
316 } VMXNET3State;
317
318 /* Interrupt management */
319
320 /*
321 *This function returns sign whether interrupt line is in asserted state
322 * This depends on the type of interrupt used. For INTX interrupt line will
323 * be asserted until explicit deassertion, for MSI(X) interrupt line will
324 * be deasserted automatically due to notification semantics of the MSI(X)
325 * interrupts
326 */
327 static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx)
328 {
329 PCIDevice *d = PCI_DEVICE(s);
330
331 if (s->msix_used && msix_enabled(d)) {
332 VMW_IRPRN("Sending MSI-X notification for vector %u", int_idx);
333 msix_notify(d, int_idx);
334 return false;
335 }
336 if (s->msi_used && msi_enabled(d)) {
337 VMW_IRPRN("Sending MSI notification for vector %u", int_idx);
338 msi_notify(d, int_idx);
339 return false;
340 }
341
342 VMW_IRPRN("Asserting line for interrupt %u", int_idx);
343 pci_irq_assert(d);
344 return true;
345 }
346
347 static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx)
348 {
349 PCIDevice *d = PCI_DEVICE(s);
350
351 /*
352 * This function should never be called for MSI(X) interrupts
353 * because deassertion never required for message interrupts
354 */
355 assert(!s->msix_used || !msix_enabled(d));
356 /*
357 * This function should never be called for MSI(X) interrupts
358 * because deassertion never required for message interrupts
359 */
360 assert(!s->msi_used || !msi_enabled(d));
361
362 VMW_IRPRN("Deasserting line for interrupt %u", lidx);
363 pci_irq_deassert(d);
364 }
365
366 static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx)
367 {
368 if (!s->interrupt_states[lidx].is_pending &&
369 s->interrupt_states[lidx].is_asserted) {
370 VMW_IRPRN("New interrupt line state for index %d is DOWN", lidx);
371 _vmxnet3_deassert_interrupt_line(s, lidx);
372 s->interrupt_states[lidx].is_asserted = false;
373 return;
374 }
375
376 if (s->interrupt_states[lidx].is_pending &&
377 !s->interrupt_states[lidx].is_masked &&
378 !s->interrupt_states[lidx].is_asserted) {
379 VMW_IRPRN("New interrupt line state for index %d is UP", lidx);
380 s->interrupt_states[lidx].is_asserted =
381 _vmxnet3_assert_interrupt_line(s, lidx);
382 s->interrupt_states[lidx].is_pending = false;
383 return;
384 }
385 }
386
387 static void vmxnet3_trigger_interrupt(VMXNET3State *s, int lidx)
388 {
389 PCIDevice *d = PCI_DEVICE(s);
390 s->interrupt_states[lidx].is_pending = true;
391 vmxnet3_update_interrupt_line_state(s, lidx);
392
393 if (s->msix_used && msix_enabled(d) && s->auto_int_masking) {
394 goto do_automask;
395 }
396
397 if (s->msi_used && msi_enabled(d) && s->auto_int_masking) {
398 goto do_automask;
399 }
400
401 return;
402
403 do_automask:
404 s->interrupt_states[lidx].is_masked = true;
405 vmxnet3_update_interrupt_line_state(s, lidx);
406 }
407
408 static bool vmxnet3_interrupt_asserted(VMXNET3State *s, int lidx)
409 {
410 return s->interrupt_states[lidx].is_asserted;
411 }
412
413 static void vmxnet3_clear_interrupt(VMXNET3State *s, int int_idx)
414 {
415 s->interrupt_states[int_idx].is_pending = false;
416 if (s->auto_int_masking) {
417 s->interrupt_states[int_idx].is_masked = true;
418 }
419 vmxnet3_update_interrupt_line_state(s, int_idx);
420 }
421
422 static void
423 vmxnet3_on_interrupt_mask_changed(VMXNET3State *s, int lidx, bool is_masked)
424 {
425 s->interrupt_states[lidx].is_masked = is_masked;
426 vmxnet3_update_interrupt_line_state(s, lidx);
427 }
428
429 static bool vmxnet3_verify_driver_magic(hwaddr dshmem)
430 {
431 return (VMXNET3_READ_DRV_SHARED32(dshmem, magic) == VMXNET3_REV1_MAGIC);
432 }
433
434 #define VMXNET3_GET_BYTE(x, byte_num) (((x) >> (byte_num)*8) & 0xFF)
435 #define VMXNET3_MAKE_BYTE(byte_num, val) \
436 (((uint32_t)((val) & 0xFF)) << (byte_num)*8)
437
438 static void vmxnet3_set_variable_mac(VMXNET3State *s, uint32_t h, uint32_t l)
439 {
440 s->conf.macaddr.a[0] = VMXNET3_GET_BYTE(l, 0);
441 s->conf.macaddr.a[1] = VMXNET3_GET_BYTE(l, 1);
442 s->conf.macaddr.a[2] = VMXNET3_GET_BYTE(l, 2);
443 s->conf.macaddr.a[3] = VMXNET3_GET_BYTE(l, 3);
444 s->conf.macaddr.a[4] = VMXNET3_GET_BYTE(h, 0);
445 s->conf.macaddr.a[5] = VMXNET3_GET_BYTE(h, 1);
446
447 VMW_CFPRN("Variable MAC: " VMXNET_MF, VMXNET_MA(s->conf.macaddr.a));
448
449 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
450 }
451
452 static uint64_t vmxnet3_get_mac_low(MACAddr *addr)
453 {
454 return VMXNET3_MAKE_BYTE(0, addr->a[0]) |
455 VMXNET3_MAKE_BYTE(1, addr->a[1]) |
456 VMXNET3_MAKE_BYTE(2, addr->a[2]) |
457 VMXNET3_MAKE_BYTE(3, addr->a[3]);
458 }
459
460 static uint64_t vmxnet3_get_mac_high(MACAddr *addr)
461 {
462 return VMXNET3_MAKE_BYTE(0, addr->a[4]) |
463 VMXNET3_MAKE_BYTE(1, addr->a[5]);
464 }
465
466 static void
467 vmxnet3_inc_tx_consumption_counter(VMXNET3State *s, int qidx)
468 {
469 vmxnet3_ring_inc(&s->txq_descr[qidx].tx_ring);
470 }
471
472 static inline void
473 vmxnet3_inc_rx_consumption_counter(VMXNET3State *s, int qidx, int ridx)
474 {
475 vmxnet3_ring_inc(&s->rxq_descr[qidx].rx_ring[ridx]);
476 }
477
478 static inline void
479 vmxnet3_inc_tx_completion_counter(VMXNET3State *s, int qidx)
480 {
481 vmxnet3_ring_inc(&s->txq_descr[qidx].comp_ring);
482 }
483
484 static void
485 vmxnet3_inc_rx_completion_counter(VMXNET3State *s, int qidx)
486 {
487 vmxnet3_ring_inc(&s->rxq_descr[qidx].comp_ring);
488 }
489
490 static void
491 vmxnet3_dec_rx_completion_counter(VMXNET3State *s, int qidx)
492 {
493 vmxnet3_ring_dec(&s->rxq_descr[qidx].comp_ring);
494 }
495
496 static void vmxnet3_complete_packet(VMXNET3State *s, int qidx, uint32 tx_ridx)
497 {
498 struct Vmxnet3_TxCompDesc txcq_descr;
499
500 VMXNET3_RING_DUMP(VMW_RIPRN, "TXC", qidx, &s->txq_descr[qidx].comp_ring);
501
502 txcq_descr.txdIdx = tx_ridx;
503 txcq_descr.gen = vmxnet3_ring_curr_gen(&s->txq_descr[qidx].comp_ring);
504
505 vmxnet3_ring_write_curr_cell(&s->txq_descr[qidx].comp_ring, &txcq_descr);
506
507 /* Flush changes in TX descriptor before changing the counter value */
508 smp_wmb();
509
510 vmxnet3_inc_tx_completion_counter(s, qidx);
511 vmxnet3_trigger_interrupt(s, s->txq_descr[qidx].intr_idx);
512 }
513
514 static bool
515 vmxnet3_setup_tx_offloads(VMXNET3State *s)
516 {
517 switch (s->offload_mode) {
518 case VMXNET3_OM_NONE:
519 vmxnet_tx_pkt_build_vheader(s->tx_pkt, false, false, 0);
520 break;
521
522 case VMXNET3_OM_CSUM:
523 vmxnet_tx_pkt_build_vheader(s->tx_pkt, false, true, 0);
524 VMW_PKPRN("L4 CSO requested\n");
525 break;
526
527 case VMXNET3_OM_TSO:
528 vmxnet_tx_pkt_build_vheader(s->tx_pkt, true, true,
529 s->cso_or_gso_size);
530 vmxnet_tx_pkt_update_ip_checksums(s->tx_pkt);
531 VMW_PKPRN("GSO offload requested.");
532 break;
533
534 default:
535 g_assert_not_reached();
536 return false;
537 }
538
539 return true;
540 }
541
542 static void
543 vmxnet3_tx_retrieve_metadata(VMXNET3State *s,
544 const struct Vmxnet3_TxDesc *txd)
545 {
546 s->offload_mode = txd->om;
547 s->cso_or_gso_size = txd->msscof;
548 s->tci = txd->tci;
549 s->needs_vlan = txd->ti;
550 }
551
552 typedef enum {
553 VMXNET3_PKT_STATUS_OK,
554 VMXNET3_PKT_STATUS_ERROR,
555 VMXNET3_PKT_STATUS_DISCARD,/* only for tx */
556 VMXNET3_PKT_STATUS_OUT_OF_BUF /* only for rx */
557 } Vmxnet3PktStatus;
558
559 static void
560 vmxnet3_on_tx_done_update_stats(VMXNET3State *s, int qidx,
561 Vmxnet3PktStatus status)
562 {
563 size_t tot_len = vmxnet_tx_pkt_get_total_len(s->tx_pkt);
564 struct UPT1_TxStats *stats = &s->txq_descr[qidx].txq_stats;
565
566 switch (status) {
567 case VMXNET3_PKT_STATUS_OK:
568 switch (vmxnet_tx_pkt_get_packet_type(s->tx_pkt)) {
569 case ETH_PKT_BCAST:
570 stats->bcastPktsTxOK++;
571 stats->bcastBytesTxOK += tot_len;
572 break;
573 case ETH_PKT_MCAST:
574 stats->mcastPktsTxOK++;
575 stats->mcastBytesTxOK += tot_len;
576 break;
577 case ETH_PKT_UCAST:
578 stats->ucastPktsTxOK++;
579 stats->ucastBytesTxOK += tot_len;
580 break;
581 default:
582 g_assert_not_reached();
583 }
584
585 if (s->offload_mode == VMXNET3_OM_TSO) {
586 /*
587 * According to VMWARE headers this statistic is a number
588 * of packets after segmentation but since we don't have
589 * this information in QEMU model, the best we can do is to
590 * provide number of non-segmented packets
591 */
592 stats->TSOPktsTxOK++;
593 stats->TSOBytesTxOK += tot_len;
594 }
595 break;
596
597 case VMXNET3_PKT_STATUS_DISCARD:
598 stats->pktsTxDiscard++;
599 break;
600
601 case VMXNET3_PKT_STATUS_ERROR:
602 stats->pktsTxError++;
603 break;
604
605 default:
606 g_assert_not_reached();
607 }
608 }
609
610 static void
611 vmxnet3_on_rx_done_update_stats(VMXNET3State *s,
612 int qidx,
613 Vmxnet3PktStatus status)
614 {
615 struct UPT1_RxStats *stats = &s->rxq_descr[qidx].rxq_stats;
616 size_t tot_len = vmxnet_rx_pkt_get_total_len(s->rx_pkt);
617
618 switch (status) {
619 case VMXNET3_PKT_STATUS_OUT_OF_BUF:
620 stats->pktsRxOutOfBuf++;
621 break;
622
623 case VMXNET3_PKT_STATUS_ERROR:
624 stats->pktsRxError++;
625 break;
626 case VMXNET3_PKT_STATUS_OK:
627 switch (vmxnet_rx_pkt_get_packet_type(s->rx_pkt)) {
628 case ETH_PKT_BCAST:
629 stats->bcastPktsRxOK++;
630 stats->bcastBytesRxOK += tot_len;
631 break;
632 case ETH_PKT_MCAST:
633 stats->mcastPktsRxOK++;
634 stats->mcastBytesRxOK += tot_len;
635 break;
636 case ETH_PKT_UCAST:
637 stats->ucastPktsRxOK++;
638 stats->ucastBytesRxOK += tot_len;
639 break;
640 default:
641 g_assert_not_reached();
642 }
643
644 if (tot_len > s->mtu) {
645 stats->LROPktsRxOK++;
646 stats->LROBytesRxOK += tot_len;
647 }
648 break;
649 default:
650 g_assert_not_reached();
651 }
652 }
653
654 static inline bool
655 vmxnet3_pop_next_tx_descr(VMXNET3State *s,
656 int qidx,
657 struct Vmxnet3_TxDesc *txd,
658 uint32_t *descr_idx)
659 {
660 Vmxnet3Ring *ring = &s->txq_descr[qidx].tx_ring;
661
662 vmxnet3_ring_read_curr_cell(ring, txd);
663 if (txd->gen == vmxnet3_ring_curr_gen(ring)) {
664 /* Only read after generation field verification */
665 smp_rmb();
666 /* Re-read to be sure we got the latest version */
667 vmxnet3_ring_read_curr_cell(ring, txd);
668 VMXNET3_RING_DUMP(VMW_RIPRN, "TX", qidx, ring);
669 *descr_idx = vmxnet3_ring_curr_cell_idx(ring);
670 vmxnet3_inc_tx_consumption_counter(s, qidx);
671 return true;
672 }
673
674 return false;
675 }
676
677 static bool
678 vmxnet3_send_packet(VMXNET3State *s, uint32_t qidx)
679 {
680 Vmxnet3PktStatus status = VMXNET3_PKT_STATUS_OK;
681
682 if (!vmxnet3_setup_tx_offloads(s)) {
683 status = VMXNET3_PKT_STATUS_ERROR;
684 goto func_exit;
685 }
686
687 /* debug prints */
688 vmxnet3_dump_virt_hdr(vmxnet_tx_pkt_get_vhdr(s->tx_pkt));
689 vmxnet_tx_pkt_dump(s->tx_pkt);
690
691 if (!vmxnet_tx_pkt_send(s->tx_pkt, qemu_get_queue(s->nic))) {
692 status = VMXNET3_PKT_STATUS_DISCARD;
693 goto func_exit;
694 }
695
696 func_exit:
697 vmxnet3_on_tx_done_update_stats(s, qidx, status);
698 return (status == VMXNET3_PKT_STATUS_OK);
699 }
700
701 static void vmxnet3_process_tx_queue(VMXNET3State *s, int qidx)
702 {
703 struct Vmxnet3_TxDesc txd;
704 uint32_t txd_idx;
705 uint32_t data_len;
706 hwaddr data_pa;
707
708 for (;;) {
709 if (!vmxnet3_pop_next_tx_descr(s, qidx, &txd, &txd_idx)) {
710 break;
711 }
712
713 vmxnet3_dump_tx_descr(&txd);
714
715 if (!s->skip_current_tx_pkt) {
716 data_len = (txd.len > 0) ? txd.len : VMXNET3_MAX_TX_BUF_SIZE;
717 data_pa = le64_to_cpu(txd.addr);
718
719 if (!vmxnet_tx_pkt_add_raw_fragment(s->tx_pkt,
720 data_pa,
721 data_len)) {
722 s->skip_current_tx_pkt = true;
723 }
724 }
725
726 if (s->tx_sop) {
727 vmxnet3_tx_retrieve_metadata(s, &txd);
728 s->tx_sop = false;
729 }
730
731 if (txd.eop) {
732 if (!s->skip_current_tx_pkt) {
733 vmxnet_tx_pkt_parse(s->tx_pkt);
734
735 if (s->needs_vlan) {
736 vmxnet_tx_pkt_setup_vlan_header(s->tx_pkt, s->tci);
737 }
738
739 vmxnet3_send_packet(s, qidx);
740 } else {
741 vmxnet3_on_tx_done_update_stats(s, qidx,
742 VMXNET3_PKT_STATUS_ERROR);
743 }
744
745 vmxnet3_complete_packet(s, qidx, txd_idx);
746 s->tx_sop = true;
747 s->skip_current_tx_pkt = false;
748 vmxnet_tx_pkt_reset(s->tx_pkt);
749 }
750 }
751 }
752
753 static inline void
754 vmxnet3_read_next_rx_descr(VMXNET3State *s, int qidx, int ridx,
755 struct Vmxnet3_RxDesc *dbuf, uint32_t *didx)
756 {
757 Vmxnet3Ring *ring = &s->rxq_descr[qidx].rx_ring[ridx];
758 *didx = vmxnet3_ring_curr_cell_idx(ring);
759 vmxnet3_ring_read_curr_cell(ring, dbuf);
760 }
761
762 static inline uint8_t
763 vmxnet3_get_rx_ring_gen(VMXNET3State *s, int qidx, int ridx)
764 {
765 return s->rxq_descr[qidx].rx_ring[ridx].gen;
766 }
767
768 static inline hwaddr
769 vmxnet3_pop_rxc_descr(VMXNET3State *s, int qidx, uint32_t *descr_gen)
770 {
771 uint8_t ring_gen;
772 struct Vmxnet3_RxCompDesc rxcd;
773
774 hwaddr daddr =
775 vmxnet3_ring_curr_cell_pa(&s->rxq_descr[qidx].comp_ring);
776
777 cpu_physical_memory_read(daddr, &rxcd, sizeof(struct Vmxnet3_RxCompDesc));
778 ring_gen = vmxnet3_ring_curr_gen(&s->rxq_descr[qidx].comp_ring);
779
780 if (rxcd.gen != ring_gen) {
781 *descr_gen = ring_gen;
782 vmxnet3_inc_rx_completion_counter(s, qidx);
783 return daddr;
784 }
785
786 return 0;
787 }
788
789 static inline void
790 vmxnet3_revert_rxc_descr(VMXNET3State *s, int qidx)
791 {
792 vmxnet3_dec_rx_completion_counter(s, qidx);
793 }
794
795 #define RXQ_IDX (0)
796 #define RX_HEAD_BODY_RING (0)
797 #define RX_BODY_ONLY_RING (1)
798
799 static bool
800 vmxnet3_get_next_head_rx_descr(VMXNET3State *s,
801 struct Vmxnet3_RxDesc *descr_buf,
802 uint32_t *descr_idx,
803 uint32_t *ridx)
804 {
805 for (;;) {
806 uint32_t ring_gen;
807 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
808 descr_buf, descr_idx);
809
810 /* If no more free descriptors - return */
811 ring_gen = vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING);
812 if (descr_buf->gen != ring_gen) {
813 return false;
814 }
815
816 /* Only read after generation field verification */
817 smp_rmb();
818 /* Re-read to be sure we got the latest version */
819 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING,
820 descr_buf, descr_idx);
821
822 /* Mark current descriptor as used/skipped */
823 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
824
825 /* If this is what we are looking for - return */
826 if (descr_buf->btype == VMXNET3_RXD_BTYPE_HEAD) {
827 *ridx = RX_HEAD_BODY_RING;
828 return true;
829 }
830 }
831 }
832
833 static bool
834 vmxnet3_get_next_body_rx_descr(VMXNET3State *s,
835 struct Vmxnet3_RxDesc *d,
836 uint32_t *didx,
837 uint32_t *ridx)
838 {
839 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
840
841 /* Try to find corresponding descriptor in head/body ring */
842 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_HEAD_BODY_RING)) {
843 /* Only read after generation field verification */
844 smp_rmb();
845 /* Re-read to be sure we got the latest version */
846 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_HEAD_BODY_RING, d, didx);
847 if (d->btype == VMXNET3_RXD_BTYPE_BODY) {
848 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_HEAD_BODY_RING);
849 *ridx = RX_HEAD_BODY_RING;
850 return true;
851 }
852 }
853
854 /*
855 * If there is no free descriptors on head/body ring or next free
856 * descriptor is a head descriptor switch to body only ring
857 */
858 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
859
860 /* If no more free descriptors - return */
861 if (d->gen == vmxnet3_get_rx_ring_gen(s, RXQ_IDX, RX_BODY_ONLY_RING)) {
862 /* Only read after generation field verification */
863 smp_rmb();
864 /* Re-read to be sure we got the latest version */
865 vmxnet3_read_next_rx_descr(s, RXQ_IDX, RX_BODY_ONLY_RING, d, didx);
866 assert(d->btype == VMXNET3_RXD_BTYPE_BODY);
867 *ridx = RX_BODY_ONLY_RING;
868 vmxnet3_inc_rx_consumption_counter(s, RXQ_IDX, RX_BODY_ONLY_RING);
869 return true;
870 }
871
872 return false;
873 }
874
875 static inline bool
876 vmxnet3_get_next_rx_descr(VMXNET3State *s, bool is_head,
877 struct Vmxnet3_RxDesc *descr_buf,
878 uint32_t *descr_idx,
879 uint32_t *ridx)
880 {
881 if (is_head || !s->rx_packets_compound) {
882 return vmxnet3_get_next_head_rx_descr(s, descr_buf, descr_idx, ridx);
883 } else {
884 return vmxnet3_get_next_body_rx_descr(s, descr_buf, descr_idx, ridx);
885 }
886 }
887
888 /* In case packet was csum offloaded (either NEEDS_CSUM or DATA_VALID),
889 * the implementation always passes an RxCompDesc with a "Checksum
890 * calculated and found correct" to the OS (cnc=0 and tuc=1, see
891 * vmxnet3_rx_update_descr). This emulates the observed ESXi behavior.
892 *
893 * Therefore, if packet has the NEEDS_CSUM set, we must calculate
894 * and place a fully computed checksum into the tcp/udp header.
895 * Otherwise, the OS driver will receive a checksum-correct indication
896 * (CHECKSUM_UNNECESSARY), but with the actual tcp/udp checksum field
897 * having just the pseudo header csum value.
898 *
899 * While this is not a problem if packet is destined for local delivery,
900 * in the case the host OS performs forwarding, it will forward an
901 * incorrectly checksummed packet.
902 */
903 static void vmxnet3_rx_need_csum_calculate(struct VmxnetRxPkt *pkt,
904 const void *pkt_data,
905 size_t pkt_len)
906 {
907 struct virtio_net_hdr *vhdr;
908 bool isip4, isip6, istcp, isudp;
909 uint8_t *data;
910 int len;
911
912 if (!vmxnet_rx_pkt_has_virt_hdr(pkt)) {
913 return;
914 }
915
916 vhdr = vmxnet_rx_pkt_get_vhdr(pkt);
917 if (!VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM)) {
918 return;
919 }
920
921 vmxnet_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
922 if (!(isip4 || isip6) || !(istcp || isudp)) {
923 return;
924 }
925
926 vmxnet3_dump_virt_hdr(vhdr);
927
928 /* Validate packet len: csum_start + scum_offset + length of csum field */
929 if (pkt_len < (vhdr->csum_start + vhdr->csum_offset + 2)) {
930 VMW_PKPRN("packet len:%d < csum_start(%d) + csum_offset(%d) + 2, "
931 "cannot calculate checksum",
932 len, vhdr->csum_start, vhdr->csum_offset);
933 return;
934 }
935
936 data = (uint8_t *)pkt_data + vhdr->csum_start;
937 len = pkt_len - vhdr->csum_start;
938 /* Put the checksum obtained into the packet */
939 stw_be_p(data + vhdr->csum_offset, net_raw_checksum(data, len));
940
941 vhdr->flags &= ~VIRTIO_NET_HDR_F_NEEDS_CSUM;
942 vhdr->flags |= VIRTIO_NET_HDR_F_DATA_VALID;
943 }
944
945 static void vmxnet3_rx_update_descr(struct VmxnetRxPkt *pkt,
946 struct Vmxnet3_RxCompDesc *rxcd)
947 {
948 int csum_ok, is_gso;
949 bool isip4, isip6, istcp, isudp;
950 struct virtio_net_hdr *vhdr;
951 uint8_t offload_type;
952
953 if (vmxnet_rx_pkt_is_vlan_stripped(pkt)) {
954 rxcd->ts = 1;
955 rxcd->tci = vmxnet_rx_pkt_get_vlan_tag(pkt);
956 }
957
958 if (!vmxnet_rx_pkt_has_virt_hdr(pkt)) {
959 goto nocsum;
960 }
961
962 vhdr = vmxnet_rx_pkt_get_vhdr(pkt);
963 /*
964 * Checksum is valid when lower level tell so or when lower level
965 * requires checksum offload telling that packet produced/bridged
966 * locally and did travel over network after last checksum calculation
967 * or production
968 */
969 csum_ok = VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_DATA_VALID) ||
970 VMXNET_FLAG_IS_SET(vhdr->flags, VIRTIO_NET_HDR_F_NEEDS_CSUM);
971
972 offload_type = vhdr->gso_type & ~VIRTIO_NET_HDR_GSO_ECN;
973 is_gso = (offload_type != VIRTIO_NET_HDR_GSO_NONE) ? 1 : 0;
974
975 if (!csum_ok && !is_gso) {
976 goto nocsum;
977 }
978
979 vmxnet_rx_pkt_get_protocols(pkt, &isip4, &isip6, &isudp, &istcp);
980 if ((!istcp && !isudp) || (!isip4 && !isip6)) {
981 goto nocsum;
982 }
983
984 rxcd->cnc = 0;
985 rxcd->v4 = isip4 ? 1 : 0;
986 rxcd->v6 = isip6 ? 1 : 0;
987 rxcd->tcp = istcp ? 1 : 0;
988 rxcd->udp = isudp ? 1 : 0;
989 rxcd->fcs = rxcd->tuc = rxcd->ipc = 1;
990 return;
991
992 nocsum:
993 rxcd->cnc = 1;
994 return;
995 }
996
997 static void
998 vmxnet3_physical_memory_writev(const struct iovec *iov,
999 size_t start_iov_off,
1000 hwaddr target_addr,
1001 size_t bytes_to_copy)
1002 {
1003 size_t curr_off = 0;
1004 size_t copied = 0;
1005
1006 while (bytes_to_copy) {
1007 if (start_iov_off < (curr_off + iov->iov_len)) {
1008 size_t chunk_len =
1009 MIN((curr_off + iov->iov_len) - start_iov_off, bytes_to_copy);
1010
1011 cpu_physical_memory_write(target_addr + copied,
1012 iov->iov_base + start_iov_off - curr_off,
1013 chunk_len);
1014
1015 copied += chunk_len;
1016 start_iov_off += chunk_len;
1017 curr_off = start_iov_off;
1018 bytes_to_copy -= chunk_len;
1019 } else {
1020 curr_off += iov->iov_len;
1021 }
1022 iov++;
1023 }
1024 }
1025
1026 static bool
1027 vmxnet3_indicate_packet(VMXNET3State *s)
1028 {
1029 struct Vmxnet3_RxDesc rxd;
1030 bool is_head = true;
1031 uint32_t rxd_idx;
1032 uint32_t rx_ridx = 0;
1033
1034 struct Vmxnet3_RxCompDesc rxcd;
1035 uint32_t new_rxcd_gen = VMXNET3_INIT_GEN;
1036 hwaddr new_rxcd_pa = 0;
1037 hwaddr ready_rxcd_pa = 0;
1038 struct iovec *data = vmxnet_rx_pkt_get_iovec(s->rx_pkt);
1039 size_t bytes_copied = 0;
1040 size_t bytes_left = vmxnet_rx_pkt_get_total_len(s->rx_pkt);
1041 uint16_t num_frags = 0;
1042 size_t chunk_size;
1043
1044 vmxnet_rx_pkt_dump(s->rx_pkt);
1045
1046 while (bytes_left > 0) {
1047
1048 /* cannot add more frags to packet */
1049 if (num_frags == s->max_rx_frags) {
1050 break;
1051 }
1052
1053 new_rxcd_pa = vmxnet3_pop_rxc_descr(s, RXQ_IDX, &new_rxcd_gen);
1054 if (!new_rxcd_pa) {
1055 break;
1056 }
1057
1058 if (!vmxnet3_get_next_rx_descr(s, is_head, &rxd, &rxd_idx, &rx_ridx)) {
1059 break;
1060 }
1061
1062 chunk_size = MIN(bytes_left, rxd.len);
1063 vmxnet3_physical_memory_writev(data, bytes_copied,
1064 le64_to_cpu(rxd.addr), chunk_size);
1065 bytes_copied += chunk_size;
1066 bytes_left -= chunk_size;
1067
1068 vmxnet3_dump_rx_descr(&rxd);
1069
1070 if (ready_rxcd_pa != 0) {
1071 cpu_physical_memory_write(ready_rxcd_pa, &rxcd, sizeof(rxcd));
1072 }
1073
1074 memset(&rxcd, 0, sizeof(struct Vmxnet3_RxCompDesc));
1075 rxcd.rxdIdx = rxd_idx;
1076 rxcd.len = chunk_size;
1077 rxcd.sop = is_head;
1078 rxcd.gen = new_rxcd_gen;
1079 rxcd.rqID = RXQ_IDX + rx_ridx * s->rxq_num;
1080
1081 if (bytes_left == 0) {
1082 vmxnet3_rx_update_descr(s->rx_pkt, &rxcd);
1083 }
1084
1085 VMW_RIPRN("RX Completion descriptor: rxRing: %lu rxIdx %lu len %lu "
1086 "sop %d csum_correct %lu",
1087 (unsigned long) rx_ridx,
1088 (unsigned long) rxcd.rxdIdx,
1089 (unsigned long) rxcd.len,
1090 (int) rxcd.sop,
1091 (unsigned long) rxcd.tuc);
1092
1093 is_head = false;
1094 ready_rxcd_pa = new_rxcd_pa;
1095 new_rxcd_pa = 0;
1096 num_frags++;
1097 }
1098
1099 if (ready_rxcd_pa != 0) {
1100 rxcd.eop = 1;
1101 rxcd.err = (bytes_left != 0);
1102 cpu_physical_memory_write(ready_rxcd_pa, &rxcd, sizeof(rxcd));
1103
1104 /* Flush RX descriptor changes */
1105 smp_wmb();
1106 }
1107
1108 if (new_rxcd_pa != 0) {
1109 vmxnet3_revert_rxc_descr(s, RXQ_IDX);
1110 }
1111
1112 vmxnet3_trigger_interrupt(s, s->rxq_descr[RXQ_IDX].intr_idx);
1113
1114 if (bytes_left == 0) {
1115 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_OK);
1116 return true;
1117 } else if (num_frags == s->max_rx_frags) {
1118 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX, VMXNET3_PKT_STATUS_ERROR);
1119 return false;
1120 } else {
1121 vmxnet3_on_rx_done_update_stats(s, RXQ_IDX,
1122 VMXNET3_PKT_STATUS_OUT_OF_BUF);
1123 return false;
1124 }
1125 }
1126
1127 static void
1128 vmxnet3_io_bar0_write(void *opaque, hwaddr addr,
1129 uint64_t val, unsigned size)
1130 {
1131 VMXNET3State *s = opaque;
1132
1133 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_TXPROD,
1134 VMXNET3_DEVICE_MAX_TX_QUEUES, VMXNET3_REG_ALIGN)) {
1135 int tx_queue_idx =
1136 VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_TXPROD,
1137 VMXNET3_REG_ALIGN);
1138 assert(tx_queue_idx <= s->txq_num);
1139 vmxnet3_process_tx_queue(s, tx_queue_idx);
1140 return;
1141 }
1142
1143 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1144 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
1145 int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
1146 VMXNET3_REG_ALIGN);
1147
1148 VMW_CBPRN("Interrupt mask for line %d written: 0x%" PRIx64, l, val);
1149
1150 vmxnet3_on_interrupt_mask_changed(s, l, val);
1151 return;
1152 }
1153
1154 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD,
1155 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN) ||
1156 VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_RXPROD2,
1157 VMXNET3_DEVICE_MAX_RX_QUEUES, VMXNET3_REG_ALIGN)) {
1158 return;
1159 }
1160
1161 VMW_WRPRN("BAR0 unknown write [%" PRIx64 "] = %" PRIx64 ", size %d",
1162 (uint64_t) addr, val, size);
1163 }
1164
1165 static uint64_t
1166 vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size)
1167 {
1168 if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
1169 VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
1170 g_assert_not_reached();
1171 }
1172
1173 VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);
1174 return 0;
1175 }
1176
1177 static void vmxnet3_reset_interrupt_states(VMXNET3State *s)
1178 {
1179 int i;
1180 for (i = 0; i < ARRAY_SIZE(s->interrupt_states); i++) {
1181 s->interrupt_states[i].is_asserted = false;
1182 s->interrupt_states[i].is_pending = false;
1183 s->interrupt_states[i].is_masked = true;
1184 }
1185 }
1186
1187 static void vmxnet3_reset_mac(VMXNET3State *s)
1188 {
1189 memcpy(&s->conf.macaddr.a, &s->perm_mac.a, sizeof(s->perm_mac.a));
1190 VMW_CFPRN("MAC address set to: " VMXNET_MF, VMXNET_MA(s->conf.macaddr.a));
1191 }
1192
1193 static void vmxnet3_deactivate_device(VMXNET3State *s)
1194 {
1195 VMW_CBPRN("Deactivating vmxnet3...");
1196 s->device_active = false;
1197 }
1198
1199 static void vmxnet3_reset(VMXNET3State *s)
1200 {
1201 VMW_CBPRN("Resetting vmxnet3...");
1202
1203 vmxnet3_deactivate_device(s);
1204 vmxnet3_reset_interrupt_states(s);
1205 vmxnet_tx_pkt_reset(s->tx_pkt);
1206 s->drv_shmem = 0;
1207 s->tx_sop = true;
1208 s->skip_current_tx_pkt = false;
1209 }
1210
1211 static void vmxnet3_update_rx_mode(VMXNET3State *s)
1212 {
1213 s->rx_mode = VMXNET3_READ_DRV_SHARED32(s->drv_shmem,
1214 devRead.rxFilterConf.rxMode);
1215 VMW_CFPRN("RX mode: 0x%08X", s->rx_mode);
1216 }
1217
1218 static void vmxnet3_update_vlan_filters(VMXNET3State *s)
1219 {
1220 int i;
1221
1222 /* Copy configuration from shared memory */
1223 VMXNET3_READ_DRV_SHARED(s->drv_shmem,
1224 devRead.rxFilterConf.vfTable,
1225 s->vlan_table,
1226 sizeof(s->vlan_table));
1227
1228 /* Invert byte order when needed */
1229 for (i = 0; i < ARRAY_SIZE(s->vlan_table); i++) {
1230 s->vlan_table[i] = le32_to_cpu(s->vlan_table[i]);
1231 }
1232
1233 /* Dump configuration for debugging purposes */
1234 VMW_CFPRN("Configured VLANs:");
1235 for (i = 0; i < sizeof(s->vlan_table) * 8; i++) {
1236 if (VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, i)) {
1237 VMW_CFPRN("\tVLAN %d is present", i);
1238 }
1239 }
1240 }
1241
1242 static void vmxnet3_update_mcast_filters(VMXNET3State *s)
1243 {
1244 uint16_t list_bytes =
1245 VMXNET3_READ_DRV_SHARED16(s->drv_shmem,
1246 devRead.rxFilterConf.mfTableLen);
1247
1248 s->mcast_list_len = list_bytes / sizeof(s->mcast_list[0]);
1249
1250 s->mcast_list = g_realloc(s->mcast_list, list_bytes);
1251 if (!s->mcast_list) {
1252 if (s->mcast_list_len == 0) {
1253 VMW_CFPRN("Current multicast list is empty");
1254 } else {
1255 VMW_ERPRN("Failed to allocate multicast list of %d elements",
1256 s->mcast_list_len);
1257 }
1258 s->mcast_list_len = 0;
1259 } else {
1260 int i;
1261 hwaddr mcast_list_pa =
1262 VMXNET3_READ_DRV_SHARED64(s->drv_shmem,
1263 devRead.rxFilterConf.mfTablePA);
1264
1265 cpu_physical_memory_read(mcast_list_pa, s->mcast_list, list_bytes);
1266 VMW_CFPRN("Current multicast list len is %d:", s->mcast_list_len);
1267 for (i = 0; i < s->mcast_list_len; i++) {
1268 VMW_CFPRN("\t" VMXNET_MF, VMXNET_MA(s->mcast_list[i].a));
1269 }
1270 }
1271 }
1272
1273 static void vmxnet3_setup_rx_filtering(VMXNET3State *s)
1274 {
1275 vmxnet3_update_rx_mode(s);
1276 vmxnet3_update_vlan_filters(s);
1277 vmxnet3_update_mcast_filters(s);
1278 }
1279
1280 static uint32_t vmxnet3_get_interrupt_config(VMXNET3State *s)
1281 {
1282 uint32_t interrupt_mode = VMXNET3_IT_AUTO | (VMXNET3_IMM_AUTO << 2);
1283 VMW_CFPRN("Interrupt config is 0x%X", interrupt_mode);
1284 return interrupt_mode;
1285 }
1286
1287 static void vmxnet3_fill_stats(VMXNET3State *s)
1288 {
1289 int i;
1290 for (i = 0; i < s->txq_num; i++) {
1291 cpu_physical_memory_write(s->txq_descr[i].tx_stats_pa,
1292 &s->txq_descr[i].txq_stats,
1293 sizeof(s->txq_descr[i].txq_stats));
1294 }
1295
1296 for (i = 0; i < s->rxq_num; i++) {
1297 cpu_physical_memory_write(s->rxq_descr[i].rx_stats_pa,
1298 &s->rxq_descr[i].rxq_stats,
1299 sizeof(s->rxq_descr[i].rxq_stats));
1300 }
1301 }
1302
1303 static void vmxnet3_adjust_by_guest_type(VMXNET3State *s)
1304 {
1305 struct Vmxnet3_GOSInfo gos;
1306
1307 VMXNET3_READ_DRV_SHARED(s->drv_shmem, devRead.misc.driverInfo.gos,
1308 &gos, sizeof(gos));
1309 s->rx_packets_compound =
1310 (gos.gosType == VMXNET3_GOS_TYPE_WIN) ? false : true;
1311
1312 VMW_CFPRN("Guest type specifics: RXCOMPOUND: %d", s->rx_packets_compound);
1313 }
1314
1315 static void
1316 vmxnet3_dump_conf_descr(const char *name,
1317 struct Vmxnet3_VariableLenConfDesc *pm_descr)
1318 {
1319 VMW_CFPRN("%s descriptor dump: Version %u, Length %u",
1320 name, pm_descr->confVer, pm_descr->confLen);
1321
1322 };
1323
1324 static void vmxnet3_update_pm_state(VMXNET3State *s)
1325 {
1326 struct Vmxnet3_VariableLenConfDesc pm_descr;
1327
1328 pm_descr.confLen =
1329 VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confLen);
1330 pm_descr.confVer =
1331 VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.pmConfDesc.confVer);
1332 pm_descr.confPA =
1333 VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.pmConfDesc.confPA);
1334
1335 vmxnet3_dump_conf_descr("PM State", &pm_descr);
1336 }
1337
1338 static void vmxnet3_update_features(VMXNET3State *s)
1339 {
1340 uint32_t guest_features;
1341 int rxcso_supported;
1342
1343 guest_features = VMXNET3_READ_DRV_SHARED32(s->drv_shmem,
1344 devRead.misc.uptFeatures);
1345
1346 rxcso_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXCSUM);
1347 s->rx_vlan_stripping = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_RXVLAN);
1348 s->lro_supported = VMXNET_FLAG_IS_SET(guest_features, UPT1_F_LRO);
1349
1350 VMW_CFPRN("Features configuration: LRO: %d, RXCSUM: %d, VLANSTRIP: %d",
1351 s->lro_supported, rxcso_supported,
1352 s->rx_vlan_stripping);
1353 if (s->peer_has_vhdr) {
1354 qemu_set_offload(qemu_get_queue(s->nic)->peer,
1355 rxcso_supported,
1356 s->lro_supported,
1357 s->lro_supported,
1358 0,
1359 0);
1360 }
1361 }
1362
1363 static bool vmxnet3_verify_intx(VMXNET3State *s, int intx)
1364 {
1365 return s->msix_used || s->msi_used || (intx ==
1366 (pci_get_byte(s->parent_obj.config + PCI_INTERRUPT_PIN) - 1));
1367 }
1368
1369 static void vmxnet3_validate_interrupt_idx(bool is_msix, int idx)
1370 {
1371 int max_ints = is_msix ? VMXNET3_MAX_INTRS : VMXNET3_MAX_NMSIX_INTRS;
1372 if (idx >= max_ints) {
1373 hw_error("Bad interrupt index: %d\n", idx);
1374 }
1375 }
1376
1377 static void vmxnet3_validate_interrupts(VMXNET3State *s)
1378 {
1379 int i;
1380
1381 VMW_CFPRN("Verifying event interrupt index (%d)", s->event_int_idx);
1382 vmxnet3_validate_interrupt_idx(s->msix_used, s->event_int_idx);
1383
1384 for (i = 0; i < s->txq_num; i++) {
1385 int idx = s->txq_descr[i].intr_idx;
1386 VMW_CFPRN("Verifying TX queue %d interrupt index (%d)", i, idx);
1387 vmxnet3_validate_interrupt_idx(s->msix_used, idx);
1388 }
1389
1390 for (i = 0; i < s->rxq_num; i++) {
1391 int idx = s->rxq_descr[i].intr_idx;
1392 VMW_CFPRN("Verifying RX queue %d interrupt index (%d)", i, idx);
1393 vmxnet3_validate_interrupt_idx(s->msix_used, idx);
1394 }
1395 }
1396
1397 static void vmxnet3_validate_queues(VMXNET3State *s)
1398 {
1399 /*
1400 * txq_num and rxq_num are total number of queues
1401 * configured by guest. These numbers must not
1402 * exceed corresponding maximal values.
1403 */
1404
1405 if (s->txq_num > VMXNET3_DEVICE_MAX_TX_QUEUES) {
1406 hw_error("Bad TX queues number: %d\n", s->txq_num);
1407 }
1408
1409 if (s->rxq_num > VMXNET3_DEVICE_MAX_RX_QUEUES) {
1410 hw_error("Bad RX queues number: %d\n", s->rxq_num);
1411 }
1412 }
1413
1414 static void vmxnet3_activate_device(VMXNET3State *s)
1415 {
1416 int i;
1417 static const uint32_t VMXNET3_DEF_TX_THRESHOLD = 1;
1418 hwaddr qdescr_table_pa;
1419 uint64_t pa;
1420 uint32_t size;
1421
1422 /* Verify configuration consistency */
1423 if (!vmxnet3_verify_driver_magic(s->drv_shmem)) {
1424 VMW_ERPRN("Device configuration received from driver is invalid");
1425 return;
1426 }
1427
1428 vmxnet3_adjust_by_guest_type(s);
1429 vmxnet3_update_features(s);
1430 vmxnet3_update_pm_state(s);
1431 vmxnet3_setup_rx_filtering(s);
1432 /* Cache fields from shared memory */
1433 s->mtu = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, devRead.misc.mtu);
1434 VMW_CFPRN("MTU is %u", s->mtu);
1435
1436 s->max_rx_frags =
1437 VMXNET3_READ_DRV_SHARED16(s->drv_shmem, devRead.misc.maxNumRxSG);
1438
1439 if (s->max_rx_frags == 0) {
1440 s->max_rx_frags = 1;
1441 }
1442
1443 VMW_CFPRN("Max RX fragments is %u", s->max_rx_frags);
1444
1445 s->event_int_idx =
1446 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.intrConf.eventIntrIdx);
1447 assert(vmxnet3_verify_intx(s, s->event_int_idx));
1448 VMW_CFPRN("Events interrupt line is %u", s->event_int_idx);
1449
1450 s->auto_int_masking =
1451 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.intrConf.autoMask);
1452 VMW_CFPRN("Automatic interrupt masking is %d", (int)s->auto_int_masking);
1453
1454 s->txq_num =
1455 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.misc.numTxQueues);
1456 s->rxq_num =
1457 VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.misc.numRxQueues);
1458
1459 VMW_CFPRN("Number of TX/RX queues %u/%u", s->txq_num, s->rxq_num);
1460 vmxnet3_validate_queues(s);
1461
1462 qdescr_table_pa =
1463 VMXNET3_READ_DRV_SHARED64(s->drv_shmem, devRead.misc.queueDescPA);
1464 VMW_CFPRN("TX queues descriptors table is at 0x%" PRIx64, qdescr_table_pa);
1465
1466 /*
1467 * Worst-case scenario is a packet that holds all TX rings space so
1468 * we calculate total size of all TX rings for max TX fragments number
1469 */
1470 s->max_tx_frags = 0;
1471
1472 /* TX queues */
1473 for (i = 0; i < s->txq_num; i++) {
1474 hwaddr qdescr_pa =
1475 qdescr_table_pa + i * sizeof(struct Vmxnet3_TxQueueDesc);
1476
1477 /* Read interrupt number for this TX queue */
1478 s->txq_descr[i].intr_idx =
1479 VMXNET3_READ_TX_QUEUE_DESCR8(qdescr_pa, conf.intrIdx);
1480 assert(vmxnet3_verify_intx(s, s->txq_descr[i].intr_idx));
1481
1482 VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx);
1483
1484 /* Read rings memory locations for TX queues */
1485 pa = VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa, conf.txRingBasePA);
1486 size = VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa, conf.txRingSize);
1487
1488 vmxnet3_ring_init(&s->txq_descr[i].tx_ring, pa, size,
1489 sizeof(struct Vmxnet3_TxDesc), false);
1490 VMXNET3_RING_DUMP(VMW_CFPRN, "TX", i, &s->txq_descr[i].tx_ring);
1491
1492 s->max_tx_frags += size;
1493
1494 /* TXC ring */
1495 pa = VMXNET3_READ_TX_QUEUE_DESCR64(qdescr_pa, conf.compRingBasePA);
1496 size = VMXNET3_READ_TX_QUEUE_DESCR32(qdescr_pa, conf.compRingSize);
1497 vmxnet3_ring_init(&s->txq_descr[i].comp_ring, pa, size,
1498 sizeof(struct Vmxnet3_TxCompDesc), true);
1499 VMXNET3_RING_DUMP(VMW_CFPRN, "TXC", i, &s->txq_descr[i].comp_ring);
1500
1501 s->txq_descr[i].tx_stats_pa =
1502 qdescr_pa + offsetof(struct Vmxnet3_TxQueueDesc, stats);
1503
1504 memset(&s->txq_descr[i].txq_stats, 0,
1505 sizeof(s->txq_descr[i].txq_stats));
1506
1507 /* Fill device-managed parameters for queues */
1508 VMXNET3_WRITE_TX_QUEUE_DESCR32(qdescr_pa,
1509 ctrl.txThreshold,
1510 VMXNET3_DEF_TX_THRESHOLD);
1511 }
1512
1513 /* Preallocate TX packet wrapper */
1514 VMW_CFPRN("Max TX fragments is %u", s->max_tx_frags);
1515 vmxnet_tx_pkt_init(&s->tx_pkt, s->max_tx_frags, s->peer_has_vhdr);
1516 vmxnet_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
1517
1518 /* Read rings memory locations for RX queues */
1519 for (i = 0; i < s->rxq_num; i++) {
1520 int j;
1521 hwaddr qd_pa =
1522 qdescr_table_pa + s->txq_num * sizeof(struct Vmxnet3_TxQueueDesc) +
1523 i * sizeof(struct Vmxnet3_RxQueueDesc);
1524
1525 /* Read interrupt number for this RX queue */
1526 s->rxq_descr[i].intr_idx =
1527 VMXNET3_READ_TX_QUEUE_DESCR8(qd_pa, conf.intrIdx);
1528 assert(vmxnet3_verify_intx(s, s->rxq_descr[i].intr_idx));
1529
1530 VMW_CFPRN("RX Queue %d interrupt: %d", i, s->rxq_descr[i].intr_idx);
1531
1532 /* Read rings memory locations */
1533 for (j = 0; j < VMXNET3_RX_RINGS_PER_QUEUE; j++) {
1534 /* RX rings */
1535 pa = VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa, conf.rxRingBasePA[j]);
1536 size = VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa, conf.rxRingSize[j]);
1537 vmxnet3_ring_init(&s->rxq_descr[i].rx_ring[j], pa, size,
1538 sizeof(struct Vmxnet3_RxDesc), false);
1539 VMW_CFPRN("RX queue %d:%d: Base: %" PRIx64 ", Size: %d",
1540 i, j, pa, size);
1541 }
1542
1543 /* RXC ring */
1544 pa = VMXNET3_READ_RX_QUEUE_DESCR64(qd_pa, conf.compRingBasePA);
1545 size = VMXNET3_READ_RX_QUEUE_DESCR32(qd_pa, conf.compRingSize);
1546 vmxnet3_ring_init(&s->rxq_descr[i].comp_ring, pa, size,
1547 sizeof(struct Vmxnet3_RxCompDesc), true);
1548 VMW_CFPRN("RXC queue %d: Base: %" PRIx64 ", Size: %d", i, pa, size);
1549
1550 s->rxq_descr[i].rx_stats_pa =
1551 qd_pa + offsetof(struct Vmxnet3_RxQueueDesc, stats);
1552 memset(&s->rxq_descr[i].rxq_stats, 0,
1553 sizeof(s->rxq_descr[i].rxq_stats));
1554 }
1555
1556 vmxnet3_validate_interrupts(s);
1557
1558 /* Make sure everything is in place before device activation */
1559 smp_wmb();
1560
1561 vmxnet3_reset_mac(s);
1562
1563 s->device_active = true;
1564 }
1565
1566 static void vmxnet3_handle_command(VMXNET3State *s, uint64_t cmd)
1567 {
1568 s->last_command = cmd;
1569
1570 switch (cmd) {
1571 case VMXNET3_CMD_GET_PERM_MAC_HI:
1572 VMW_CBPRN("Set: Get upper part of permanent MAC");
1573 break;
1574
1575 case VMXNET3_CMD_GET_PERM_MAC_LO:
1576 VMW_CBPRN("Set: Get lower part of permanent MAC");
1577 break;
1578
1579 case VMXNET3_CMD_GET_STATS:
1580 VMW_CBPRN("Set: Get device statistics");
1581 vmxnet3_fill_stats(s);
1582 break;
1583
1584 case VMXNET3_CMD_ACTIVATE_DEV:
1585 VMW_CBPRN("Set: Activating vmxnet3 device");
1586 vmxnet3_activate_device(s);
1587 break;
1588
1589 case VMXNET3_CMD_UPDATE_RX_MODE:
1590 VMW_CBPRN("Set: Update rx mode");
1591 vmxnet3_update_rx_mode(s);
1592 break;
1593
1594 case VMXNET3_CMD_UPDATE_VLAN_FILTERS:
1595 VMW_CBPRN("Set: Update VLAN filters");
1596 vmxnet3_update_vlan_filters(s);
1597 break;
1598
1599 case VMXNET3_CMD_UPDATE_MAC_FILTERS:
1600 VMW_CBPRN("Set: Update MAC filters");
1601 vmxnet3_update_mcast_filters(s);
1602 break;
1603
1604 case VMXNET3_CMD_UPDATE_FEATURE:
1605 VMW_CBPRN("Set: Update features");
1606 vmxnet3_update_features(s);
1607 break;
1608
1609 case VMXNET3_CMD_UPDATE_PMCFG:
1610 VMW_CBPRN("Set: Update power management config");
1611 vmxnet3_update_pm_state(s);
1612 break;
1613
1614 case VMXNET3_CMD_GET_LINK:
1615 VMW_CBPRN("Set: Get link");
1616 break;
1617
1618 case VMXNET3_CMD_RESET_DEV:
1619 VMW_CBPRN("Set: Reset device");
1620 vmxnet3_reset(s);
1621 break;
1622
1623 case VMXNET3_CMD_QUIESCE_DEV:
1624 VMW_CBPRN("Set: VMXNET3_CMD_QUIESCE_DEV - pause the device");
1625 vmxnet3_deactivate_device(s);
1626 break;
1627
1628 case VMXNET3_CMD_GET_CONF_INTR:
1629 VMW_CBPRN("Set: VMXNET3_CMD_GET_CONF_INTR - interrupt configuration");
1630 break;
1631
1632 default:
1633 VMW_CBPRN("Received unknown command: %" PRIx64, cmd);
1634 break;
1635 }
1636 }
1637
1638 static uint64_t vmxnet3_get_command_status(VMXNET3State *s)
1639 {
1640 uint64_t ret;
1641
1642 switch (s->last_command) {
1643 case VMXNET3_CMD_ACTIVATE_DEV:
1644 ret = (s->device_active) ? 0 : -1;
1645 VMW_CFPRN("Device active: %" PRIx64, ret);
1646 break;
1647
1648 case VMXNET3_CMD_RESET_DEV:
1649 case VMXNET3_CMD_QUIESCE_DEV:
1650 case VMXNET3_CMD_GET_QUEUE_STATUS:
1651 ret = 0;
1652 break;
1653
1654 case VMXNET3_CMD_GET_LINK:
1655 ret = s->link_status_and_speed;
1656 VMW_CFPRN("Link and speed: %" PRIx64, ret);
1657 break;
1658
1659 case VMXNET3_CMD_GET_PERM_MAC_LO:
1660 ret = vmxnet3_get_mac_low(&s->perm_mac);
1661 break;
1662
1663 case VMXNET3_CMD_GET_PERM_MAC_HI:
1664 ret = vmxnet3_get_mac_high(&s->perm_mac);
1665 break;
1666
1667 case VMXNET3_CMD_GET_CONF_INTR:
1668 ret = vmxnet3_get_interrupt_config(s);
1669 break;
1670
1671 default:
1672 VMW_WRPRN("Received request for unknown command: %x", s->last_command);
1673 ret = -1;
1674 break;
1675 }
1676
1677 return ret;
1678 }
1679
1680 static void vmxnet3_set_events(VMXNET3State *s, uint32_t val)
1681 {
1682 uint32_t events;
1683
1684 VMW_CBPRN("Setting events: 0x%x", val);
1685 events = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, ecr) | val;
1686 VMXNET3_WRITE_DRV_SHARED32(s->drv_shmem, ecr, events);
1687 }
1688
1689 static void vmxnet3_ack_events(VMXNET3State *s, uint32_t val)
1690 {
1691 uint32_t events;
1692
1693 VMW_CBPRN("Clearing events: 0x%x", val);
1694 events = VMXNET3_READ_DRV_SHARED32(s->drv_shmem, ecr) & ~val;
1695 VMXNET3_WRITE_DRV_SHARED32(s->drv_shmem, ecr, events);
1696 }
1697
1698 static void
1699 vmxnet3_io_bar1_write(void *opaque,
1700 hwaddr addr,
1701 uint64_t val,
1702 unsigned size)
1703 {
1704 VMXNET3State *s = opaque;
1705
1706 switch (addr) {
1707 /* Vmxnet3 Revision Report Selection */
1708 case VMXNET3_REG_VRRS:
1709 VMW_CBPRN("Write BAR1 [VMXNET3_REG_VRRS] = %" PRIx64 ", size %d",
1710 val, size);
1711 break;
1712
1713 /* UPT Version Report Selection */
1714 case VMXNET3_REG_UVRS:
1715 VMW_CBPRN("Write BAR1 [VMXNET3_REG_UVRS] = %" PRIx64 ", size %d",
1716 val, size);
1717 break;
1718
1719 /* Driver Shared Address Low */
1720 case VMXNET3_REG_DSAL:
1721 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAL] = %" PRIx64 ", size %d",
1722 val, size);
1723 /*
1724 * Guest driver will first write the low part of the shared
1725 * memory address. We save it to temp variable and set the
1726 * shared address only after we get the high part
1727 */
1728 if (val == 0) {
1729 s->device_active = false;
1730 }
1731 s->temp_shared_guest_driver_memory = val;
1732 s->drv_shmem = 0;
1733 break;
1734
1735 /* Driver Shared Address High */
1736 case VMXNET3_REG_DSAH:
1737 VMW_CBPRN("Write BAR1 [VMXNET3_REG_DSAH] = %" PRIx64 ", size %d",
1738 val, size);
1739 /*
1740 * Set the shared memory between guest driver and device.
1741 * We already should have low address part.
1742 */
1743 s->drv_shmem = s->temp_shared_guest_driver_memory | (val << 32);
1744 break;
1745
1746 /* Command */
1747 case VMXNET3_REG_CMD:
1748 VMW_CBPRN("Write BAR1 [VMXNET3_REG_CMD] = %" PRIx64 ", size %d",
1749 val, size);
1750 vmxnet3_handle_command(s, val);
1751 break;
1752
1753 /* MAC Address Low */
1754 case VMXNET3_REG_MACL:
1755 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACL] = %" PRIx64 ", size %d",
1756 val, size);
1757 s->temp_mac = val;
1758 break;
1759
1760 /* MAC Address High */
1761 case VMXNET3_REG_MACH:
1762 VMW_CBPRN("Write BAR1 [VMXNET3_REG_MACH] = %" PRIx64 ", size %d",
1763 val, size);
1764 vmxnet3_set_variable_mac(s, val, s->temp_mac);
1765 break;
1766
1767 /* Interrupt Cause Register */
1768 case VMXNET3_REG_ICR:
1769 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ICR] = %" PRIx64 ", size %d",
1770 val, size);
1771 g_assert_not_reached();
1772 break;
1773
1774 /* Event Cause Register */
1775 case VMXNET3_REG_ECR:
1776 VMW_CBPRN("Write BAR1 [VMXNET3_REG_ECR] = %" PRIx64 ", size %d",
1777 val, size);
1778 vmxnet3_ack_events(s, val);
1779 break;
1780
1781 default:
1782 VMW_CBPRN("Unknown Write to BAR1 [%" PRIx64 "] = %" PRIx64 ", size %d",
1783 addr, val, size);
1784 break;
1785 }
1786 }
1787
1788 static uint64_t
1789 vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsigned size)
1790 {
1791 VMXNET3State *s = opaque;
1792 uint64_t ret = 0;
1793
1794 switch (addr) {
1795 /* Vmxnet3 Revision Report Selection */
1796 case VMXNET3_REG_VRRS:
1797 VMW_CBPRN("Read BAR1 [VMXNET3_REG_VRRS], size %d", size);
1798 ret = VMXNET3_DEVICE_REVISION;
1799 break;
1800
1801 /* UPT Version Report Selection */
1802 case VMXNET3_REG_UVRS:
1803 VMW_CBPRN("Read BAR1 [VMXNET3_REG_UVRS], size %d", size);
1804 ret = VMXNET3_DEVICE_VERSION;
1805 break;
1806
1807 /* Command */
1808 case VMXNET3_REG_CMD:
1809 VMW_CBPRN("Read BAR1 [VMXNET3_REG_CMD], size %d", size);
1810 ret = vmxnet3_get_command_status(s);
1811 break;
1812
1813 /* MAC Address Low */
1814 case VMXNET3_REG_MACL:
1815 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACL], size %d", size);
1816 ret = vmxnet3_get_mac_low(&s->conf.macaddr);
1817 break;
1818
1819 /* MAC Address High */
1820 case VMXNET3_REG_MACH:
1821 VMW_CBPRN("Read BAR1 [VMXNET3_REG_MACH], size %d", size);
1822 ret = vmxnet3_get_mac_high(&s->conf.macaddr);
1823 break;
1824
1825 /*
1826 * Interrupt Cause Register
1827 * Used for legacy interrupts only so interrupt index always 0
1828 */
1829 case VMXNET3_REG_ICR:
1830 VMW_CBPRN("Read BAR1 [VMXNET3_REG_ICR], size %d", size);
1831 if (vmxnet3_interrupt_asserted(s, 0)) {
1832 vmxnet3_clear_interrupt(s, 0);
1833 ret = true;
1834 } else {
1835 ret = false;
1836 }
1837 break;
1838
1839 default:
1840 VMW_CBPRN("Unknow read BAR1[%" PRIx64 "], %d bytes", addr, size);
1841 break;
1842 }
1843
1844 return ret;
1845 }
1846
1847 static int
1848 vmxnet3_can_receive(NetClientState *nc)
1849 {
1850 VMXNET3State *s = qemu_get_nic_opaque(nc);
1851 return s->device_active &&
1852 VMXNET_FLAG_IS_SET(s->link_status_and_speed, VMXNET3_LINK_STATUS_UP);
1853 }
1854
1855 static inline bool
1856 vmxnet3_is_registered_vlan(VMXNET3State *s, const void *data)
1857 {
1858 uint16_t vlan_tag = eth_get_pkt_tci(data) & VLAN_VID_MASK;
1859 if (IS_SPECIAL_VLAN_ID(vlan_tag)) {
1860 return true;
1861 }
1862
1863 return VMXNET3_VFTABLE_ENTRY_IS_SET(s->vlan_table, vlan_tag);
1864 }
1865
1866 static bool
1867 vmxnet3_is_allowed_mcast_group(VMXNET3State *s, const uint8_t *group_mac)
1868 {
1869 int i;
1870 for (i = 0; i < s->mcast_list_len; i++) {
1871 if (!memcmp(group_mac, s->mcast_list[i].a, sizeof(s->mcast_list[i]))) {
1872 return true;
1873 }
1874 }
1875 return false;
1876 }
1877
1878 static bool
1879 vmxnet3_rx_filter_may_indicate(VMXNET3State *s, const void *data,
1880 size_t size)
1881 {
1882 struct eth_header *ehdr = PKT_GET_ETH_HDR(data);
1883
1884 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_PROMISC)) {
1885 return true;
1886 }
1887
1888 if (!vmxnet3_is_registered_vlan(s, data)) {
1889 return false;
1890 }
1891
1892 switch (vmxnet_rx_pkt_get_packet_type(s->rx_pkt)) {
1893 case ETH_PKT_UCAST:
1894 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_UCAST)) {
1895 return false;
1896 }
1897 if (memcmp(s->conf.macaddr.a, ehdr->h_dest, ETH_ALEN)) {
1898 return false;
1899 }
1900 break;
1901
1902 case ETH_PKT_BCAST:
1903 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_BCAST)) {
1904 return false;
1905 }
1906 break;
1907
1908 case ETH_PKT_MCAST:
1909 if (VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_ALL_MULTI)) {
1910 return true;
1911 }
1912 if (!VMXNET_FLAG_IS_SET(s->rx_mode, VMXNET3_RXM_MCAST)) {
1913 return false;
1914 }
1915 if (!vmxnet3_is_allowed_mcast_group(s, ehdr->h_dest)) {
1916 return false;
1917 }
1918 break;
1919
1920 default:
1921 g_assert_not_reached();
1922 }
1923
1924 return true;
1925 }
1926
1927 static ssize_t
1928 vmxnet3_receive(NetClientState *nc, const uint8_t *buf, size_t size)
1929 {
1930 VMXNET3State *s = qemu_get_nic_opaque(nc);
1931 size_t bytes_indicated;
1932 uint8_t min_buf[MIN_BUF_SIZE];
1933
1934 if (!vmxnet3_can_receive(nc)) {
1935 VMW_PKPRN("Cannot receive now");
1936 return -1;
1937 }
1938
1939 if (s->peer_has_vhdr) {
1940 vmxnet_rx_pkt_set_vhdr(s->rx_pkt, (struct virtio_net_hdr *)buf);
1941 buf += sizeof(struct virtio_net_hdr);
1942 size -= sizeof(struct virtio_net_hdr);
1943 }
1944
1945 /* Pad to minimum Ethernet frame length */
1946 if (size < sizeof(min_buf)) {
1947 memcpy(min_buf, buf, size);
1948 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1949 buf = min_buf;
1950 size = sizeof(min_buf);
1951 }
1952
1953 vmxnet_rx_pkt_set_packet_type(s->rx_pkt,
1954 get_eth_packet_type(PKT_GET_ETH_HDR(buf)));
1955
1956 if (vmxnet3_rx_filter_may_indicate(s, buf, size)) {
1957 vmxnet_rx_pkt_set_protocols(s->rx_pkt, buf, size);
1958 vmxnet3_rx_need_csum_calculate(s->rx_pkt, buf, size);
1959 vmxnet_rx_pkt_attach_data(s->rx_pkt, buf, size, s->rx_vlan_stripping);
1960 bytes_indicated = vmxnet3_indicate_packet(s) ? size : -1;
1961 if (bytes_indicated < size) {
1962 VMW_PKPRN("RX: %lu of %lu bytes indicated", bytes_indicated, size);
1963 }
1964 } else {
1965 VMW_PKPRN("Packet dropped by RX filter");
1966 bytes_indicated = size;
1967 }
1968
1969 assert(size > 0);
1970 assert(bytes_indicated != 0);
1971 return bytes_indicated;
1972 }
1973
1974 static void vmxnet3_set_link_status(NetClientState *nc)
1975 {
1976 VMXNET3State *s = qemu_get_nic_opaque(nc);
1977
1978 if (nc->link_down) {
1979 s->link_status_and_speed &= ~VMXNET3_LINK_STATUS_UP;
1980 } else {
1981 s->link_status_and_speed |= VMXNET3_LINK_STATUS_UP;
1982 }
1983
1984 vmxnet3_set_events(s, VMXNET3_ECR_LINK);
1985 vmxnet3_trigger_interrupt(s, s->event_int_idx);
1986 }
1987
1988 static NetClientInfo net_vmxnet3_info = {
1989 .type = NET_CLIENT_OPTIONS_KIND_NIC,
1990 .size = sizeof(NICState),
1991 .can_receive = vmxnet3_can_receive,
1992 .receive = vmxnet3_receive,
1993 .link_status_changed = vmxnet3_set_link_status,
1994 };
1995
1996 static bool vmxnet3_peer_has_vnet_hdr(VMXNET3State *s)
1997 {
1998 NetClientState *nc = qemu_get_queue(s->nic);
1999
2000 if (qemu_has_vnet_hdr(nc->peer)) {
2001 return true;
2002 }
2003
2004 VMW_WRPRN("Peer has no virtio extension. Task offloads will be emulated.");
2005 return false;
2006 }
2007
2008 static void vmxnet3_net_uninit(VMXNET3State *s)
2009 {
2010 g_free(s->mcast_list);
2011 vmxnet_tx_pkt_reset(s->tx_pkt);
2012 vmxnet_tx_pkt_uninit(s->tx_pkt);
2013 vmxnet_rx_pkt_uninit(s->rx_pkt);
2014 qemu_del_nic(s->nic);
2015 }
2016
2017 static void vmxnet3_net_init(VMXNET3State *s)
2018 {
2019 DeviceState *d = DEVICE(s);
2020
2021 VMW_CBPRN("vmxnet3_net_init called...");
2022
2023 qemu_macaddr_default_if_unset(&s->conf.macaddr);
2024
2025 /* Windows guest will query the address that was set on init */
2026 memcpy(&s->perm_mac.a, &s->conf.macaddr.a, sizeof(s->perm_mac.a));
2027
2028 s->mcast_list = NULL;
2029 s->mcast_list_len = 0;
2030
2031 s->link_status_and_speed = VMXNET3_LINK_SPEED | VMXNET3_LINK_STATUS_UP;
2032
2033 VMW_CFPRN("Permanent MAC: " MAC_FMT, MAC_ARG(s->perm_mac.a));
2034
2035 s->nic = qemu_new_nic(&net_vmxnet3_info, &s->conf,
2036 object_get_typename(OBJECT(s)),
2037 d->id, s);
2038
2039 s->peer_has_vhdr = vmxnet3_peer_has_vnet_hdr(s);
2040 s->tx_sop = true;
2041 s->skip_current_tx_pkt = false;
2042 s->tx_pkt = NULL;
2043 s->rx_pkt = NULL;
2044 s->rx_vlan_stripping = false;
2045 s->lro_supported = false;
2046
2047 if (s->peer_has_vhdr) {
2048 qemu_set_vnet_hdr_len(qemu_get_queue(s->nic)->peer,
2049 sizeof(struct virtio_net_hdr));
2050
2051 qemu_using_vnet_hdr(qemu_get_queue(s->nic)->peer, 1);
2052 }
2053
2054 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
2055 }
2056
2057 static void
2058 vmxnet3_unuse_msix_vectors(VMXNET3State *s, int num_vectors)
2059 {
2060 PCIDevice *d = PCI_DEVICE(s);
2061 int i;
2062 for (i = 0; i < num_vectors; i++) {
2063 msix_vector_unuse(d, i);
2064 }
2065 }
2066
2067 static bool
2068 vmxnet3_use_msix_vectors(VMXNET3State *s, int num_vectors)
2069 {
2070 PCIDevice *d = PCI_DEVICE(s);
2071 int i;
2072 for (i = 0; i < num_vectors; i++) {
2073 int res = msix_vector_use(d, i);
2074 if (0 > res) {
2075 VMW_WRPRN("Failed to use MSI-X vector %d, error %d", i, res);
2076 vmxnet3_unuse_msix_vectors(s, i);
2077 return false;
2078 }
2079 }
2080 return true;
2081 }
2082
2083 static bool
2084 vmxnet3_init_msix(VMXNET3State *s)
2085 {
2086 PCIDevice *d = PCI_DEVICE(s);
2087 int res = msix_init(d, VMXNET3_MAX_INTRS,
2088 &s->msix_bar,
2089 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_TABLE,
2090 &s->msix_bar,
2091 VMXNET3_MSIX_BAR_IDX, VMXNET3_OFF_MSIX_PBA,
2092 0);
2093
2094 if (0 > res) {
2095 VMW_WRPRN("Failed to initialize MSI-X, error %d", res);
2096 s->msix_used = false;
2097 } else {
2098 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
2099 VMW_WRPRN("Failed to use MSI-X vectors, error %d", res);
2100 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2101 s->msix_used = false;
2102 } else {
2103 s->msix_used = true;
2104 }
2105 }
2106 return s->msix_used;
2107 }
2108
2109 static void
2110 vmxnet3_cleanup_msix(VMXNET3State *s)
2111 {
2112 PCIDevice *d = PCI_DEVICE(s);
2113
2114 if (s->msix_used) {
2115 vmxnet3_unuse_msix_vectors(s, VMXNET3_MAX_INTRS);
2116 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2117 }
2118 }
2119
2120 #define VMXNET3_MSI_OFFSET (0x50)
2121 #define VMXNET3_USE_64BIT (true)
2122 #define VMXNET3_PER_VECTOR_MASK (false)
2123
2124 static bool
2125 vmxnet3_init_msi(VMXNET3State *s)
2126 {
2127 PCIDevice *d = PCI_DEVICE(s);
2128 int res;
2129
2130 res = msi_init(d, VMXNET3_MSI_OFFSET, VMXNET3_MAX_NMSIX_INTRS,
2131 VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK);
2132 if (0 > res) {
2133 VMW_WRPRN("Failed to initialize MSI, error %d", res);
2134 s->msi_used = false;
2135 } else {
2136 s->msi_used = true;
2137 }
2138
2139 return s->msi_used;
2140 }
2141
2142 static void
2143 vmxnet3_cleanup_msi(VMXNET3State *s)
2144 {
2145 PCIDevice *d = PCI_DEVICE(s);
2146
2147 if (s->msi_used) {
2148 msi_uninit(d);
2149 }
2150 }
2151
2152 static void
2153 vmxnet3_msix_save(QEMUFile *f, void *opaque)
2154 {
2155 PCIDevice *d = PCI_DEVICE(opaque);
2156 msix_save(d, f);
2157 }
2158
2159 static int
2160 vmxnet3_msix_load(QEMUFile *f, void *opaque, int version_id)
2161 {
2162 PCIDevice *d = PCI_DEVICE(opaque);
2163 msix_load(d, f);
2164 return 0;
2165 }
2166
2167 static const MemoryRegionOps b0_ops = {
2168 .read = vmxnet3_io_bar0_read,
2169 .write = vmxnet3_io_bar0_write,
2170 .endianness = DEVICE_LITTLE_ENDIAN,
2171 .impl = {
2172 .min_access_size = 4,
2173 .max_access_size = 4,
2174 },
2175 };
2176
2177 static const MemoryRegionOps b1_ops = {
2178 .read = vmxnet3_io_bar1_read,
2179 .write = vmxnet3_io_bar1_write,
2180 .endianness = DEVICE_LITTLE_ENDIAN,
2181 .impl = {
2182 .min_access_size = 4,
2183 .max_access_size = 4,
2184 },
2185 };
2186
2187 static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp)
2188 {
2189 DeviceState *dev = DEVICE(pci_dev);
2190 VMXNET3State *s = VMXNET3(pci_dev);
2191
2192 VMW_CBPRN("Starting init...");
2193
2194 memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s,
2195 "vmxnet3-b0", VMXNET3_PT_REG_SIZE);
2196 pci_register_bar(pci_dev, VMXNET3_BAR0_IDX,
2197 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
2198
2199 memory_region_init_io(&s->bar1, OBJECT(s), &b1_ops, s,
2200 "vmxnet3-b1", VMXNET3_VD_REG_SIZE);
2201 pci_register_bar(pci_dev, VMXNET3_BAR1_IDX,
2202 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
2203
2204 memory_region_init(&s->msix_bar, OBJECT(s), "vmxnet3-msix-bar",
2205 VMXNET3_MSIX_BAR_SIZE);
2206 pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX,
2207 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar);
2208
2209 vmxnet3_reset_interrupt_states(s);
2210
2211 /* Interrupt pin A */
2212 pci_dev->config[PCI_INTERRUPT_PIN] = 0x01;
2213
2214 if (!vmxnet3_init_msix(s)) {
2215 VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
2216 }
2217
2218 if (!vmxnet3_init_msi(s)) {
2219 VMW_WRPRN("Failed to initialize MSI, configuration is inconsistent.");
2220 }
2221
2222 vmxnet3_net_init(s);
2223
2224 register_savevm(dev, "vmxnet3-msix", -1, 1,
2225 vmxnet3_msix_save, vmxnet3_msix_load, s);
2226 }
2227
2228 static void vmxnet3_instance_init(Object *obj)
2229 {
2230 VMXNET3State *s = VMXNET3(obj);
2231 device_add_bootindex_property(obj, &s->conf.bootindex,
2232 "bootindex", "/ethernet-phy@0",
2233 DEVICE(obj), NULL);
2234 }
2235
2236 static void vmxnet3_pci_uninit(PCIDevice *pci_dev)
2237 {
2238 DeviceState *dev = DEVICE(pci_dev);
2239 VMXNET3State *s = VMXNET3(pci_dev);
2240
2241 VMW_CBPRN("Starting uninit...");
2242
2243 unregister_savevm(dev, "vmxnet3-msix", s);
2244
2245 vmxnet3_net_uninit(s);
2246
2247 vmxnet3_cleanup_msix(s);
2248
2249 vmxnet3_cleanup_msi(s);
2250 }
2251
2252 static void vmxnet3_qdev_reset(DeviceState *dev)
2253 {
2254 PCIDevice *d = PCI_DEVICE(dev);
2255 VMXNET3State *s = VMXNET3(d);
2256
2257 VMW_CBPRN("Starting QDEV reset...");
2258 vmxnet3_reset(s);
2259 }
2260
2261 static bool vmxnet3_mc_list_needed(void *opaque)
2262 {
2263 return true;
2264 }
2265
2266 static int vmxnet3_mcast_list_pre_load(void *opaque)
2267 {
2268 VMXNET3State *s = opaque;
2269
2270 s->mcast_list = g_malloc(s->mcast_list_buff_size);
2271
2272 return 0;
2273 }
2274
2275
2276 static void vmxnet3_pre_save(void *opaque)
2277 {
2278 VMXNET3State *s = opaque;
2279
2280 s->mcast_list_buff_size = s->mcast_list_len * sizeof(MACAddr);
2281 }
2282
2283 static const VMStateDescription vmxstate_vmxnet3_mcast_list = {
2284 .name = "vmxnet3/mcast_list",
2285 .version_id = 1,
2286 .minimum_version_id = 1,
2287 .pre_load = vmxnet3_mcast_list_pre_load,
2288 .needed = vmxnet3_mc_list_needed,
2289 .fields = (VMStateField[]) {
2290 VMSTATE_VBUFFER_UINT32(mcast_list, VMXNET3State, 0, NULL, 0,
2291 mcast_list_buff_size),
2292 VMSTATE_END_OF_LIST()
2293 }
2294 };
2295
2296 static void vmxnet3_get_ring_from_file(QEMUFile *f, Vmxnet3Ring *r)
2297 {
2298 r->pa = qemu_get_be64(f);
2299 r->size = qemu_get_be32(f);
2300 r->cell_size = qemu_get_be32(f);
2301 r->next = qemu_get_be32(f);
2302 r->gen = qemu_get_byte(f);
2303 }
2304
2305 static void vmxnet3_put_ring_to_file(QEMUFile *f, Vmxnet3Ring *r)
2306 {
2307 qemu_put_be64(f, r->pa);
2308 qemu_put_be32(f, r->size);
2309 qemu_put_be32(f, r->cell_size);
2310 qemu_put_be32(f, r->next);
2311 qemu_put_byte(f, r->gen);
2312 }
2313
2314 static void vmxnet3_get_tx_stats_from_file(QEMUFile *f,
2315 struct UPT1_TxStats *tx_stat)
2316 {
2317 tx_stat->TSOPktsTxOK = qemu_get_be64(f);
2318 tx_stat->TSOBytesTxOK = qemu_get_be64(f);
2319 tx_stat->ucastPktsTxOK = qemu_get_be64(f);
2320 tx_stat->ucastBytesTxOK = qemu_get_be64(f);
2321 tx_stat->mcastPktsTxOK = qemu_get_be64(f);
2322 tx_stat->mcastBytesTxOK = qemu_get_be64(f);
2323 tx_stat->bcastPktsTxOK = qemu_get_be64(f);
2324 tx_stat->bcastBytesTxOK = qemu_get_be64(f);
2325 tx_stat->pktsTxError = qemu_get_be64(f);
2326 tx_stat->pktsTxDiscard = qemu_get_be64(f);
2327 }
2328
2329 static void vmxnet3_put_tx_stats_to_file(QEMUFile *f,
2330 struct UPT1_TxStats *tx_stat)
2331 {
2332 qemu_put_be64(f, tx_stat->TSOPktsTxOK);
2333 qemu_put_be64(f, tx_stat->TSOBytesTxOK);
2334 qemu_put_be64(f, tx_stat->ucastPktsTxOK);
2335 qemu_put_be64(f, tx_stat->ucastBytesTxOK);
2336 qemu_put_be64(f, tx_stat->mcastPktsTxOK);
2337 qemu_put_be64(f, tx_stat->mcastBytesTxOK);
2338 qemu_put_be64(f, tx_stat->bcastPktsTxOK);
2339 qemu_put_be64(f, tx_stat->bcastBytesTxOK);
2340 qemu_put_be64(f, tx_stat->pktsTxError);
2341 qemu_put_be64(f, tx_stat->pktsTxDiscard);
2342 }
2343
2344 static int vmxnet3_get_txq_descr(QEMUFile *f, void *pv, size_t size)
2345 {
2346 Vmxnet3TxqDescr *r = pv;
2347
2348 vmxnet3_get_ring_from_file(f, &r->tx_ring);
2349 vmxnet3_get_ring_from_file(f, &r->comp_ring);
2350 r->intr_idx = qemu_get_byte(f);
2351 r->tx_stats_pa = qemu_get_be64(f);
2352
2353 vmxnet3_get_tx_stats_from_file(f, &r->txq_stats);
2354
2355 return 0;
2356 }
2357
2358 static void vmxnet3_put_txq_descr(QEMUFile *f, void *pv, size_t size)
2359 {
2360 Vmxnet3TxqDescr *r = pv;
2361
2362 vmxnet3_put_ring_to_file(f, &r->tx_ring);
2363 vmxnet3_put_ring_to_file(f, &r->comp_ring);
2364 qemu_put_byte(f, r->intr_idx);
2365 qemu_put_be64(f, r->tx_stats_pa);
2366 vmxnet3_put_tx_stats_to_file(f, &r->txq_stats);
2367 }
2368
2369 static const VMStateInfo txq_descr_info = {
2370 .name = "txq_descr",
2371 .get = vmxnet3_get_txq_descr,
2372 .put = vmxnet3_put_txq_descr
2373 };
2374
2375 static void vmxnet3_get_rx_stats_from_file(QEMUFile *f,
2376 struct UPT1_RxStats *rx_stat)
2377 {
2378 rx_stat->LROPktsRxOK = qemu_get_be64(f);
2379 rx_stat->LROBytesRxOK = qemu_get_be64(f);
2380 rx_stat->ucastPktsRxOK = qemu_get_be64(f);
2381 rx_stat->ucastBytesRxOK = qemu_get_be64(f);
2382 rx_stat->mcastPktsRxOK = qemu_get_be64(f);
2383 rx_stat->mcastBytesRxOK = qemu_get_be64(f);
2384 rx_stat->bcastPktsRxOK = qemu_get_be64(f);
2385 rx_stat->bcastBytesRxOK = qemu_get_be64(f);
2386 rx_stat->pktsRxOutOfBuf = qemu_get_be64(f);
2387 rx_stat->pktsRxError = qemu_get_be64(f);
2388 }
2389
2390 static void vmxnet3_put_rx_stats_to_file(QEMUFile *f,
2391 struct UPT1_RxStats *rx_stat)
2392 {
2393 qemu_put_be64(f, rx_stat->LROPktsRxOK);
2394 qemu_put_be64(f, rx_stat->LROBytesRxOK);
2395 qemu_put_be64(f, rx_stat->ucastPktsRxOK);
2396 qemu_put_be64(f, rx_stat->ucastBytesRxOK);
2397 qemu_put_be64(f, rx_stat->mcastPktsRxOK);
2398 qemu_put_be64(f, rx_stat->mcastBytesRxOK);
2399 qemu_put_be64(f, rx_stat->bcastPktsRxOK);
2400 qemu_put_be64(f, rx_stat->bcastBytesRxOK);
2401 qemu_put_be64(f, rx_stat->pktsRxOutOfBuf);
2402 qemu_put_be64(f, rx_stat->pktsRxError);
2403 }
2404
2405 static int vmxnet3_get_rxq_descr(QEMUFile *f, void *pv, size_t size)
2406 {
2407 Vmxnet3RxqDescr *r = pv;
2408 int i;
2409
2410 for (i = 0; i < VMXNET3_RX_RINGS_PER_QUEUE; i++) {
2411 vmxnet3_get_ring_from_file(f, &r->rx_ring[i]);
2412 }
2413
2414 vmxnet3_get_ring_from_file(f, &r->comp_ring);
2415 r->intr_idx = qemu_get_byte(f);
2416 r->rx_stats_pa = qemu_get_be64(f);
2417
2418 vmxnet3_get_rx_stats_from_file(f, &r->rxq_stats);
2419
2420 return 0;
2421 }
2422
2423 static void vmxnet3_put_rxq_descr(QEMUFile *f, void *pv, size_t size)
2424 {
2425 Vmxnet3RxqDescr *r = pv;
2426 int i;
2427
2428 for (i = 0; i < VMXNET3_RX_RINGS_PER_QUEUE; i++) {
2429 vmxnet3_put_ring_to_file(f, &r->rx_ring[i]);
2430 }
2431
2432 vmxnet3_put_ring_to_file(f, &r->comp_ring);
2433 qemu_put_byte(f, r->intr_idx);
2434 qemu_put_be64(f, r->rx_stats_pa);
2435 vmxnet3_put_rx_stats_to_file(f, &r->rxq_stats);
2436 }
2437
2438 static int vmxnet3_post_load(void *opaque, int version_id)
2439 {
2440 VMXNET3State *s = opaque;
2441 PCIDevice *d = PCI_DEVICE(s);
2442
2443 vmxnet_tx_pkt_init(&s->tx_pkt, s->max_tx_frags, s->peer_has_vhdr);
2444 vmxnet_rx_pkt_init(&s->rx_pkt, s->peer_has_vhdr);
2445
2446 if (s->msix_used) {
2447 if (!vmxnet3_use_msix_vectors(s, VMXNET3_MAX_INTRS)) {
2448 VMW_WRPRN("Failed to re-use MSI-X vectors");
2449 msix_uninit(d, &s->msix_bar, &s->msix_bar);
2450 s->msix_used = false;
2451 return -1;
2452 }
2453 }
2454
2455 vmxnet3_validate_queues(s);
2456 vmxnet3_validate_interrupts(s);
2457
2458 return 0;
2459 }
2460
2461 static const VMStateInfo rxq_descr_info = {
2462 .name = "rxq_descr",
2463 .get = vmxnet3_get_rxq_descr,
2464 .put = vmxnet3_put_rxq_descr
2465 };
2466
2467 static int vmxnet3_get_int_state(QEMUFile *f, void *pv, size_t size)
2468 {
2469 Vmxnet3IntState *r = pv;
2470
2471 r->is_masked = qemu_get_byte(f);
2472 r->is_pending = qemu_get_byte(f);
2473 r->is_asserted = qemu_get_byte(f);
2474
2475 return 0;
2476 }
2477
2478 static void vmxnet3_put_int_state(QEMUFile *f, void *pv, size_t size)
2479 {
2480 Vmxnet3IntState *r = pv;
2481
2482 qemu_put_byte(f, r->is_masked);
2483 qemu_put_byte(f, r->is_pending);
2484 qemu_put_byte(f, r->is_asserted);
2485 }
2486
2487 static const VMStateInfo int_state_info = {
2488 .name = "int_state",
2489 .get = vmxnet3_get_int_state,
2490 .put = vmxnet3_put_int_state
2491 };
2492
2493 static const VMStateDescription vmstate_vmxnet3 = {
2494 .name = "vmxnet3",
2495 .version_id = 1,
2496 .minimum_version_id = 1,
2497 .pre_save = vmxnet3_pre_save,
2498 .post_load = vmxnet3_post_load,
2499 .fields = (VMStateField[]) {
2500 VMSTATE_PCI_DEVICE(parent_obj, VMXNET3State),
2501 VMSTATE_BOOL(rx_packets_compound, VMXNET3State),
2502 VMSTATE_BOOL(rx_vlan_stripping, VMXNET3State),
2503 VMSTATE_BOOL(lro_supported, VMXNET3State),
2504 VMSTATE_UINT32(rx_mode, VMXNET3State),
2505 VMSTATE_UINT32(mcast_list_len, VMXNET3State),
2506 VMSTATE_UINT32(mcast_list_buff_size, VMXNET3State),
2507 VMSTATE_UINT32_ARRAY(vlan_table, VMXNET3State, VMXNET3_VFT_SIZE),
2508 VMSTATE_UINT32(mtu, VMXNET3State),
2509 VMSTATE_UINT16(max_rx_frags, VMXNET3State),
2510 VMSTATE_UINT32(max_tx_frags, VMXNET3State),
2511 VMSTATE_UINT8(event_int_idx, VMXNET3State),
2512 VMSTATE_BOOL(auto_int_masking, VMXNET3State),
2513 VMSTATE_UINT8(txq_num, VMXNET3State),
2514 VMSTATE_UINT8(rxq_num, VMXNET3State),
2515 VMSTATE_UINT32(device_active, VMXNET3State),
2516 VMSTATE_UINT32(last_command, VMXNET3State),
2517 VMSTATE_UINT32(link_status_and_speed, VMXNET3State),
2518 VMSTATE_UINT32(temp_mac, VMXNET3State),
2519 VMSTATE_UINT64(drv_shmem, VMXNET3State),
2520 VMSTATE_UINT64(temp_shared_guest_driver_memory, VMXNET3State),
2521
2522 VMSTATE_ARRAY(txq_descr, VMXNET3State,
2523 VMXNET3_DEVICE_MAX_TX_QUEUES, 0, txq_descr_info,
2524 Vmxnet3TxqDescr),
2525 VMSTATE_ARRAY(rxq_descr, VMXNET3State,
2526 VMXNET3_DEVICE_MAX_RX_QUEUES, 0, rxq_descr_info,
2527 Vmxnet3RxqDescr),
2528 VMSTATE_ARRAY(interrupt_states, VMXNET3State, VMXNET3_MAX_INTRS,
2529 0, int_state_info, Vmxnet3IntState),
2530
2531 VMSTATE_END_OF_LIST()
2532 },
2533 .subsections = (const VMStateDescription*[]) {
2534 &vmxstate_vmxnet3_mcast_list,
2535 NULL
2536 }
2537 };
2538
2539 static Property vmxnet3_properties[] = {
2540 DEFINE_NIC_PROPERTIES(VMXNET3State, conf),
2541 DEFINE_PROP_END_OF_LIST(),
2542 };
2543
2544 static void vmxnet3_class_init(ObjectClass *class, void *data)
2545 {
2546 DeviceClass *dc = DEVICE_CLASS(class);
2547 PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
2548
2549 c->realize = vmxnet3_pci_realize;
2550 c->exit = vmxnet3_pci_uninit;
2551 c->vendor_id = PCI_VENDOR_ID_VMWARE;
2552 c->device_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
2553 c->revision = PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION;
2554 c->class_id = PCI_CLASS_NETWORK_ETHERNET;
2555 c->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
2556 c->subsystem_id = PCI_DEVICE_ID_VMWARE_VMXNET3;
2557 dc->desc = "VMWare Paravirtualized Ethernet v3";
2558 dc->reset = vmxnet3_qdev_reset;
2559 dc->vmsd = &vmstate_vmxnet3;
2560 dc->props = vmxnet3_properties;
2561 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
2562 }
2563
2564 static const TypeInfo vmxnet3_info = {
2565 .name = TYPE_VMXNET3,
2566 .parent = TYPE_PCI_DEVICE,
2567 .instance_size = sizeof(VMXNET3State),
2568 .class_init = vmxnet3_class_init,
2569 .instance_init = vmxnet3_instance_init,
2570 };
2571
2572 static void vmxnet3_register_types(void)
2573 {
2574 VMW_CBPRN("vmxnet3_register_types called...");
2575 type_register_static(&vmxnet3_info);
2576 }
2577
2578 type_init(vmxnet3_register_types)
QEmu