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virtio-serial: move out discard logic in a separate function
[qemu.git] / hw / pci.c
blob8d0e3df2e5c3573dc03b1452badeb70c6efbab05
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
28 #include "monitor.h"
29 #include "net.h"
30 #include "sysemu.h"
31 #include "loader.h"
32 #include "qemu-objects.h"
33 #include "range.h"
34
35 //#define DEBUG_PCI
36 #ifdef DEBUG_PCI
37 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
38 #else
39 # define PCI_DPRINTF(format, ...) do { } while (0)
40 #endif
41
42 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
43 static char *pcibus_get_dev_path(DeviceState *dev);
44 static char *pcibus_get_fw_dev_path(DeviceState *dev);
45 static int pcibus_reset(BusState *qbus);
46
47 struct BusInfo pci_bus_info = {
48 .name = "PCI",
49 .size = sizeof(PCIBus),
50 .print_dev = pcibus_dev_print,
51 .get_dev_path = pcibus_get_dev_path,
52 .get_fw_dev_path = pcibus_get_fw_dev_path,
53 .reset = pcibus_reset,
54 .props = (Property[]) {
55 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
56 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
57 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
58 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
59 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
60 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
61 QEMU_PCI_CAP_SERR_BITNR, true),
62 DEFINE_PROP_END_OF_LIST()
63 }
64 };
65
66 static void pci_update_mappings(PCIDevice *d);
67 static void pci_set_irq(void *opaque, int irq_num, int level);
68 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
69 static void pci_del_option_rom(PCIDevice *pdev);
70
71 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
72 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
73
74 struct PCIHostBus {
75 int domain;
76 struct PCIBus *bus;
77 QLIST_ENTRY(PCIHostBus) next;
78 };
79 static QLIST_HEAD(, PCIHostBus) host_buses;
80
81 static const VMStateDescription vmstate_pcibus = {
82 .name = "PCIBUS",
83 .version_id = 1,
84 .minimum_version_id = 1,
85 .minimum_version_id_old = 1,
86 .fields = (VMStateField []) {
87 VMSTATE_INT32_EQUAL(nirq, PCIBus),
88 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
89 VMSTATE_END_OF_LIST()
90 }
91 };
92
93 static int pci_bar(PCIDevice *d, int reg)
94 {
95 uint8_t type;
96
97 if (reg != PCI_ROM_SLOT)
98 return PCI_BASE_ADDRESS_0 + reg * 4;
99
100 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
101 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
102 }
103
104 static inline int pci_irq_state(PCIDevice *d, int irq_num)
105 {
106 return (d->irq_state >> irq_num) & 0x1;
107 }
108
109 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
110 {
111 d->irq_state &= ~(0x1 << irq_num);
112 d->irq_state |= level << irq_num;
113 }
114
115 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
116 {
117 PCIBus *bus;
118 for (;;) {
119 bus = pci_dev->bus;
120 irq_num = bus->map_irq(pci_dev, irq_num);
121 if (bus->set_irq)
122 break;
123 pci_dev = bus->parent_dev;
124 }
125 bus->irq_count[irq_num] += change;
126 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
127 }
128
129 /* Update interrupt status bit in config space on interrupt
130 * state change. */
131 static void pci_update_irq_status(PCIDevice *dev)
132 {
133 if (dev->irq_state) {
134 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
135 } else {
136 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
137 }
138 }
139
140 /*
141 * This function is called on #RST and FLR.
142 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
143 */
144 void pci_device_reset(PCIDevice *dev)
145 {
146 int r;
147 /* TODO: call the below unconditionally once all pci devices
148 * are qdevified */
149 if (dev->qdev.info) {
150 qdev_reset_all(&dev->qdev);
151 }
152
153 dev->irq_state = 0;
154 pci_update_irq_status(dev);
155 /* Clear all writeable bits */
156 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
157 pci_get_word(dev->wmask + PCI_COMMAND) |
158 pci_get_word(dev->w1cmask + PCI_COMMAND));
159 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
160 pci_get_word(dev->wmask + PCI_STATUS) |
161 pci_get_word(dev->w1cmask + PCI_STATUS));
162 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
163 dev->config[PCI_INTERRUPT_LINE] = 0x0;
164 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
165 PCIIORegion *region = &dev->io_regions[r];
166 if (!region->size) {
167 continue;
168 }
169
170 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
171 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
172 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
173 } else {
174 pci_set_long(dev->config + pci_bar(dev, r), region->type);
175 }
176 }
177 pci_update_mappings(dev);
178 }
179
180 /*
181 * Trigger pci bus reset under a given bus.
182 * To be called on RST# assert.
183 */
184 void pci_bus_reset(PCIBus *bus)
185 {
186 int i;
187
188 for (i = 0; i < bus->nirq; i++) {
189 bus->irq_count[i] = 0;
190 }
191 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
192 if (bus->devices[i]) {
193 pci_device_reset(bus->devices[i]);
194 }
195 }
196 }
197
198 static int pcibus_reset(BusState *qbus)
199 {
200 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));
201
202 /* topology traverse is done by pci_bus_reset().
203 Tell qbus/qdev walker not to traverse the tree */
204 return 1;
205 }
206
207 static void pci_host_bus_register(int domain, PCIBus *bus)
208 {
209 struct PCIHostBus *host;
210 host = qemu_mallocz(sizeof(*host));
211 host->domain = domain;
212 host->bus = bus;
213 QLIST_INSERT_HEAD(&host_buses, host, next);
214 }
215
216 PCIBus *pci_find_root_bus(int domain)
217 {
218 struct PCIHostBus *host;
219
220 QLIST_FOREACH(host, &host_buses, next) {
221 if (host->domain == domain) {
222 return host->bus;
223 }
224 }
225
226 return NULL;
227 }
228
229 int pci_find_domain(const PCIBus *bus)
230 {
231 PCIDevice *d;
232 struct PCIHostBus *host;
233
234 /* obtain root bus */
235 while ((d = bus->parent_dev) != NULL) {
236 bus = d->bus;
237 }
238
239 QLIST_FOREACH(host, &host_buses, next) {
240 if (host->bus == bus) {
241 return host->domain;
242 }
243 }
244
245 abort(); /* should not be reached */
246 return -1;
247 }
248
249 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
250 const char *name, int devfn_min)
251 {
252 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
253 assert(PCI_FUNC(devfn_min) == 0);
254 bus->devfn_min = devfn_min;
255
256 /* host bridge */
257 QLIST_INIT(&bus->child);
258 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
259
260 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
261 }
262
263 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
264 {
265 PCIBus *bus;
266
267 bus = qemu_mallocz(sizeof(*bus));
268 bus->qbus.qdev_allocated = 1;
269 pci_bus_new_inplace(bus, parent, name, devfn_min);
270 return bus;
271 }
272
273 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
274 void *irq_opaque, int nirq)
275 {
276 bus->set_irq = set_irq;
277 bus->map_irq = map_irq;
278 bus->irq_opaque = irq_opaque;
279 bus->nirq = nirq;
280 bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
281 }
282
283 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
284 {
285 bus->qbus.allow_hotplug = 1;
286 bus->hotplug = hotplug;
287 bus->hotplug_qdev = qdev;
288 }
289
290 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
291 {
292 bus->mem_base = base;
293 }
294
295 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
296 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
297 void *irq_opaque, int devfn_min, int nirq)
298 {
299 PCIBus *bus;
300
301 bus = pci_bus_new(parent, name, devfn_min);
302 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
303 return bus;
304 }
305
306 int pci_bus_num(PCIBus *s)
307 {
308 if (!s->parent_dev)
309 return 0; /* pci host bridge */
310 return s->parent_dev->config[PCI_SECONDARY_BUS];
311 }
312
313 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
314 {
315 PCIDevice *s = container_of(pv, PCIDevice, config);
316 uint8_t *config;
317 int i;
318
319 assert(size == pci_config_size(s));
320 config = qemu_malloc(size);
321
322 qemu_get_buffer(f, config, size);
323 for (i = 0; i < size; ++i) {
324 if ((config[i] ^ s->config[i]) &
325 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
326 qemu_free(config);
327 return -EINVAL;
328 }
329 }
330 memcpy(s->config, config, size);
331
332 pci_update_mappings(s);
333
334 qemu_free(config);
335 return 0;
336 }
337
338 /* just put buffer */
339 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
340 {
341 const uint8_t **v = pv;
342 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
343 qemu_put_buffer(f, *v, size);
344 }
345
346 static VMStateInfo vmstate_info_pci_config = {
347 .name = "pci config",
348 .get = get_pci_config_device,
349 .put = put_pci_config_device,
350 };
351
352 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
353 {
354 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
355 uint32_t irq_state[PCI_NUM_PINS];
356 int i;
357 for (i = 0; i < PCI_NUM_PINS; ++i) {
358 irq_state[i] = qemu_get_be32(f);
359 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
360 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
361 irq_state[i]);
362 return -EINVAL;
363 }
364 }
365
366 for (i = 0; i < PCI_NUM_PINS; ++i) {
367 pci_set_irq_state(s, i, irq_state[i]);
368 }
369
370 return 0;
371 }
372
373 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
374 {
375 int i;
376 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
377
378 for (i = 0; i < PCI_NUM_PINS; ++i) {
379 qemu_put_be32(f, pci_irq_state(s, i));
380 }
381 }
382
383 static VMStateInfo vmstate_info_pci_irq_state = {
384 .name = "pci irq state",
385 .get = get_pci_irq_state,
386 .put = put_pci_irq_state,
387 };
388
389 const VMStateDescription vmstate_pci_device = {
390 .name = "PCIDevice",
391 .version_id = 2,
392 .minimum_version_id = 1,
393 .minimum_version_id_old = 1,
394 .fields = (VMStateField []) {
395 VMSTATE_INT32_LE(version_id, PCIDevice),
396 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
397 vmstate_info_pci_config,
398 PCI_CONFIG_SPACE_SIZE),
399 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
400 vmstate_info_pci_irq_state,
401 PCI_NUM_PINS * sizeof(int32_t)),
402 VMSTATE_END_OF_LIST()
403 }
404 };
405
406 const VMStateDescription vmstate_pcie_device = {
407 .name = "PCIDevice",
408 .version_id = 2,
409 .minimum_version_id = 1,
410 .minimum_version_id_old = 1,
411 .fields = (VMStateField []) {
412 VMSTATE_INT32_LE(version_id, PCIDevice),
413 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
414 vmstate_info_pci_config,
415 PCIE_CONFIG_SPACE_SIZE),
416 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
417 vmstate_info_pci_irq_state,
418 PCI_NUM_PINS * sizeof(int32_t)),
419 VMSTATE_END_OF_LIST()
420 }
421 };
422
423 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
424 {
425 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
426 }
427
428 void pci_device_save(PCIDevice *s, QEMUFile *f)
429 {
430 /* Clear interrupt status bit: it is implicit
431 * in irq_state which we are saving.
432 * This makes us compatible with old devices
433 * which never set or clear this bit. */
434 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
435 vmstate_save_state(f, pci_get_vmstate(s), s);
436 /* Restore the interrupt status bit. */
437 pci_update_irq_status(s);
438 }
439
440 int pci_device_load(PCIDevice *s, QEMUFile *f)
441 {
442 int ret;
443 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
444 /* Restore the interrupt status bit. */
445 pci_update_irq_status(s);
446 return ret;
447 }
448
449 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
450 {
451 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
452 pci_default_sub_vendor_id);
453 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
454 pci_default_sub_device_id);
455 }
456
457 /*
458 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
459 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
460 */
461 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
462 unsigned int *slotp, unsigned int *funcp)
463 {
464 const char *p;
465 char *e;
466 unsigned long val;
467 unsigned long dom = 0, bus = 0;
468 unsigned int slot = 0;
469 unsigned int func = 0;
470
471 p = addr;
472 val = strtoul(p, &e, 16);
473 if (e == p)
474 return -1;
475 if (*e == ':') {
476 bus = val;
477 p = e + 1;
478 val = strtoul(p, &e, 16);
479 if (e == p)
480 return -1;
481 if (*e == ':') {
482 dom = bus;
483 bus = val;
484 p = e + 1;
485 val = strtoul(p, &e, 16);
486 if (e == p)
487 return -1;
488 }
489 }
490
491 slot = val;
492
493 if (funcp != NULL) {
494 if (*e != '.')
495 return -1;
496
497 p = e + 1;
498 val = strtoul(p, &e, 16);
499 if (e == p)
500 return -1;
501
502 func = val;
503 }
504
505 /* if funcp == NULL func is 0 */
506 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
507 return -1;
508
509 if (*e)
510 return -1;
511
512 /* Note: QEMU doesn't implement domains other than 0 */
513 if (!pci_find_bus(pci_find_root_bus(dom), bus))
514 return -1;
515
516 *domp = dom;
517 *busp = bus;
518 *slotp = slot;
519 if (funcp != NULL)
520 *funcp = func;
521 return 0;
522 }
523
524 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
525 unsigned *slotp)
526 {
527 /* strip legacy tag */
528 if (!strncmp(addr, "pci_addr=", 9)) {
529 addr += 9;
530 }
531 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
532 monitor_printf(mon, "Invalid pci address\n");
533 return -1;
534 }
535 return 0;
536 }
537
538 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
539 {
540 int dom, bus;
541 unsigned slot;
542
543 if (!devaddr) {
544 *devfnp = -1;
545 return pci_find_bus(pci_find_root_bus(0), 0);
546 }
547
548 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
549 return NULL;
550 }
551
552 *devfnp = slot << 3;
553 return pci_find_bus(pci_find_root_bus(dom), bus);
554 }
555
556 static void pci_init_cmask(PCIDevice *dev)
557 {
558 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
559 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
560 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
561 dev->cmask[PCI_REVISION_ID] = 0xff;
562 dev->cmask[PCI_CLASS_PROG] = 0xff;
563 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
564 dev->cmask[PCI_HEADER_TYPE] = 0xff;
565 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
566 }
567
568 static void pci_init_wmask(PCIDevice *dev)
569 {
570 int config_size = pci_config_size(dev);
571
572 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
573 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
574 pci_set_word(dev->wmask + PCI_COMMAND,
575 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
576 PCI_COMMAND_INTX_DISABLE);
577 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
578 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
579 }
580
581 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
582 config_size - PCI_CONFIG_HEADER_SIZE);
583 }
584
585 static void pci_init_w1cmask(PCIDevice *dev)
586 {
587 /*
588 * Note: It's okay to set w1cmask even for readonly bits as
589 * long as their value is hardwired to 0.
590 */
591 pci_set_word(dev->w1cmask + PCI_STATUS,
592 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
593 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
594 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
595 }
596
597 static void pci_init_wmask_bridge(PCIDevice *d)
598 {
599 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
600 PCI_SEC_LETENCY_TIMER */
601 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
602
603 /* base and limit */
604 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
605 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
606 pci_set_word(d->wmask + PCI_MEMORY_BASE,
607 PCI_MEMORY_RANGE_MASK & 0xffff);
608 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
609 PCI_MEMORY_RANGE_MASK & 0xffff);
610 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
611 PCI_PREF_RANGE_MASK & 0xffff);
612 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
613 PCI_PREF_RANGE_MASK & 0xffff);
614
615 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
616 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
617
618 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
619 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
620 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
621 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
622 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
623 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
624 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
625 PCI_BRIDGE_CTL_PARITY |
626 PCI_BRIDGE_CTL_SERR |
627 PCI_BRIDGE_CTL_ISA |
628 PCI_BRIDGE_CTL_VGA |
629 PCI_BRIDGE_CTL_VGA_16BIT |
630 PCI_BRIDGE_CTL_MASTER_ABORT |
631 PCI_BRIDGE_CTL_BUS_RESET |
632 PCI_BRIDGE_CTL_FAST_BACK |
633 PCI_BRIDGE_CTL_DISCARD |
634 PCI_BRIDGE_CTL_SEC_DISCARD |
635 PCI_BRIDGE_CTL_DISCARD_STATUS |
636 PCI_BRIDGE_CTL_DISCARD_SERR);
637 /* Below does not do anything as we never set this bit, put here for
638 * completeness. */
639 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
640 PCI_BRIDGE_CTL_DISCARD_STATUS);
641 }
642
643 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
644 {
645 uint8_t slot = PCI_SLOT(dev->devfn);
646 uint8_t func;
647
648 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
649 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
650 }
651
652 /*
653 * multifunction bit is interpreted in two ways as follows.
654 * - all functions must set the bit to 1.
655 * Example: Intel X53
656 * - function 0 must set the bit, but the rest function (> 0)
657 * is allowed to leave the bit to 0.
658 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
659 *
660 * So OS (at least Linux) checks the bit of only function 0,
661 * and doesn't see the bit of function > 0.
662 *
663 * The below check allows both interpretation.
664 */
665 if (PCI_FUNC(dev->devfn)) {
666 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
667 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
668 /* function 0 should set multifunction bit */
669 error_report("PCI: single function device can't be populated "
670 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
671 return -1;
672 }
673 return 0;
674 }
675
676 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
677 return 0;
678 }
679 /* function 0 indicates single function, so function > 0 must be NULL */
680 for (func = 1; func < PCI_FUNC_MAX; ++func) {
681 if (bus->devices[PCI_DEVFN(slot, func)]) {
682 error_report("PCI: %x.0 indicates single function, "
683 "but %x.%x is already populated.",
684 slot, slot, func);
685 return -1;
686 }
687 }
688 return 0;
689 }
690
691 static void pci_config_alloc(PCIDevice *pci_dev)
692 {
693 int config_size = pci_config_size(pci_dev);
694
695 pci_dev->config = qemu_mallocz(config_size);
696 pci_dev->cmask = qemu_mallocz(config_size);
697 pci_dev->wmask = qemu_mallocz(config_size);
698 pci_dev->w1cmask = qemu_mallocz(config_size);
699 pci_dev->used = qemu_mallocz(config_size);
700 }
701
702 static void pci_config_free(PCIDevice *pci_dev)
703 {
704 qemu_free(pci_dev->config);
705 qemu_free(pci_dev->cmask);
706 qemu_free(pci_dev->wmask);
707 qemu_free(pci_dev->w1cmask);
708 qemu_free(pci_dev->used);
709 }
710
711 /* -1 for devfn means auto assign */
712 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
713 const char *name, int devfn,
714 PCIConfigReadFunc *config_read,
715 PCIConfigWriteFunc *config_write,
716 bool is_bridge)
717 {
718 if (devfn < 0) {
719 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
720 devfn += PCI_FUNC_MAX) {
721 if (!bus->devices[devfn])
722 goto found;
723 }
724 error_report("PCI: no slot/function available for %s, all in use", name);
725 return NULL;
726 found: ;
727 } else if (bus->devices[devfn]) {
728 error_report("PCI: slot %d function %d not available for %s, in use by %s",
729 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
730 return NULL;
731 }
732 pci_dev->bus = bus;
733 pci_dev->devfn = devfn;
734 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
735 pci_dev->irq_state = 0;
736 pci_config_alloc(pci_dev);
737
738 if (!is_bridge) {
739 pci_set_default_subsystem_id(pci_dev);
740 }
741 pci_init_cmask(pci_dev);
742 pci_init_wmask(pci_dev);
743 pci_init_w1cmask(pci_dev);
744 if (is_bridge) {
745 pci_init_wmask_bridge(pci_dev);
746 }
747 if (pci_init_multifunction(bus, pci_dev)) {
748 pci_config_free(pci_dev);
749 return NULL;
750 }
751
752 if (!config_read)
753 config_read = pci_default_read_config;
754 if (!config_write)
755 config_write = pci_default_write_config;
756 pci_dev->config_read = config_read;
757 pci_dev->config_write = config_write;
758 bus->devices[devfn] = pci_dev;
759 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
760 pci_dev->version_id = 2; /* Current pci device vmstate version */
761 return pci_dev;
762 }
763
764 static void do_pci_unregister_device(PCIDevice *pci_dev)
765 {
766 qemu_free_irqs(pci_dev->irq);
767 pci_dev->bus->devices[pci_dev->devfn] = NULL;
768 pci_config_free(pci_dev);
769 }
770
771 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
772 int instance_size, int devfn,
773 PCIConfigReadFunc *config_read,
774 PCIConfigWriteFunc *config_write)
775 {
776 PCIDevice *pci_dev;
777
778 pci_dev = qemu_mallocz(instance_size);
779 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
780 config_read, config_write,
781 PCI_HEADER_TYPE_NORMAL);
782 if (pci_dev == NULL) {
783 hw_error("PCI: can't register device\n");
784 }
785 return pci_dev;
786 }
787
788 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
789 target_phys_addr_t addr)
790 {
791 return addr + bus->mem_base;
792 }
793
794 static void pci_unregister_io_regions(PCIDevice *pci_dev)
795 {
796 PCIIORegion *r;
797 int i;
798
799 for(i = 0; i < PCI_NUM_REGIONS; i++) {
800 r = &pci_dev->io_regions[i];
801 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
802 continue;
803 if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
804 isa_unassign_ioport(r->addr, r->filtered_size);
805 } else {
806 cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
807 r->addr),
808 r->filtered_size,
809 IO_MEM_UNASSIGNED);
810 }
811 }
812 }
813
814 static int pci_unregister_device(DeviceState *dev)
815 {
816 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
817 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
818 int ret = 0;
819
820 if (info->exit)
821 ret = info->exit(pci_dev);
822 if (ret)
823 return ret;
824
825 pci_unregister_io_regions(pci_dev);
826 pci_del_option_rom(pci_dev);
827 do_pci_unregister_device(pci_dev);
828 return 0;
829 }
830
831 void pci_register_bar(PCIDevice *pci_dev, int region_num,
832 pcibus_t size, uint8_t type,
833 PCIMapIORegionFunc *map_func)
834 {
835 PCIIORegion *r;
836 uint32_t addr;
837 uint64_t wmask;
838
839 assert(region_num >= 0);
840 assert(region_num < PCI_NUM_REGIONS);
841 if (size & (size-1)) {
842 fprintf(stderr, "ERROR: PCI region size must be pow2 "
843 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
844 exit(1);
845 }
846
847 r = &pci_dev->io_regions[region_num];
848 r->addr = PCI_BAR_UNMAPPED;
849 r->size = size;
850 r->filtered_size = size;
851 r->type = type;
852 r->map_func = map_func;
853
854 wmask = ~(size - 1);
855 addr = pci_bar(pci_dev, region_num);
856 if (region_num == PCI_ROM_SLOT) {
857 /* ROM enable bit is writeable */
858 wmask |= PCI_ROM_ADDRESS_ENABLE;
859 }
860 pci_set_long(pci_dev->config + addr, type);
861 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
862 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
863 pci_set_quad(pci_dev->wmask + addr, wmask);
864 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
865 } else {
866 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
867 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
868 }
869 }
870
871 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
872 uint8_t type)
873 {
874 pcibus_t base = *addr;
875 pcibus_t limit = *addr + *size - 1;
876 PCIDevice *br;
877
878 for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
879 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
880
881 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
882 if (!(cmd & PCI_COMMAND_IO)) {
883 goto no_map;
884 }
885 } else {
886 if (!(cmd & PCI_COMMAND_MEMORY)) {
887 goto no_map;
888 }
889 }
890
891 base = MAX(base, pci_bridge_get_base(br, type));
892 limit = MIN(limit, pci_bridge_get_limit(br, type));
893 }
894
895 if (base > limit) {
896 goto no_map;
897 }
898 *addr = base;
899 *size = limit - base + 1;
900 return;
901 no_map:
902 *addr = PCI_BAR_UNMAPPED;
903 *size = 0;
904 }
905
906 static pcibus_t pci_bar_address(PCIDevice *d,
907 int reg, uint8_t type, pcibus_t size)
908 {
909 pcibus_t new_addr, last_addr;
910 int bar = pci_bar(d, reg);
911 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
912
913 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
914 if (!(cmd & PCI_COMMAND_IO)) {
915 return PCI_BAR_UNMAPPED;
916 }
917 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
918 last_addr = new_addr + size - 1;
919 /* NOTE: we have only 64K ioports on PC */
920 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
921 return PCI_BAR_UNMAPPED;
922 }
923 return new_addr;
924 }
925
926 if (!(cmd & PCI_COMMAND_MEMORY)) {
927 return PCI_BAR_UNMAPPED;
928 }
929 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
930 new_addr = pci_get_quad(d->config + bar);
931 } else {
932 new_addr = pci_get_long(d->config + bar);
933 }
934 /* the ROM slot has a specific enable bit */
935 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
936 return PCI_BAR_UNMAPPED;
937 }
938 new_addr &= ~(size - 1);
939 last_addr = new_addr + size - 1;
940 /* NOTE: we do not support wrapping */
941 /* XXX: as we cannot support really dynamic
942 mappings, we handle specific values as invalid
943 mappings. */
944 if (last_addr <= new_addr || new_addr == 0 ||
945 last_addr == PCI_BAR_UNMAPPED) {
946 return PCI_BAR_UNMAPPED;
947 }
948
949 /* Now pcibus_t is 64bit.
950 * Check if 32 bit BAR wraps around explicitly.
951 * Without this, PC ide doesn't work well.
952 * TODO: remove this work around.
953 */
954 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
955 return PCI_BAR_UNMAPPED;
956 }
957
958 /*
959 * OS is allowed to set BAR beyond its addressable
960 * bits. For example, 32 bit OS can set 64bit bar
961 * to >4G. Check it. TODO: we might need to support
962 * it in the future for e.g. PAE.
963 */
964 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
965 return PCI_BAR_UNMAPPED;
966 }
967
968 return new_addr;
969 }
970
971 static void pci_update_mappings(PCIDevice *d)
972 {
973 PCIIORegion *r;
974 int i;
975 pcibus_t new_addr, filtered_size;
976
977 for(i = 0; i < PCI_NUM_REGIONS; i++) {
978 r = &d->io_regions[i];
979
980 /* this region isn't registered */
981 if (!r->size)
982 continue;
983
984 new_addr = pci_bar_address(d, i, r->type, r->size);
985
986 /* bridge filtering */
987 filtered_size = r->size;
988 if (new_addr != PCI_BAR_UNMAPPED) {
989 pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
990 }
991
992 /* This bar isn't changed */
993 if (new_addr == r->addr && filtered_size == r->filtered_size)
994 continue;
995
996 /* now do the real mapping */
997 if (r->addr != PCI_BAR_UNMAPPED) {
998 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
999 int class;
1000 /* NOTE: specific hack for IDE in PC case:
1001 only one byte must be mapped. */
1002 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1003 if (class == 0x0101 && r->size == 4) {
1004 isa_unassign_ioport(r->addr + 2, 1);
1005 } else {
1006 isa_unassign_ioport(r->addr, r->filtered_size);
1007 }
1008 } else {
1009 cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
1010 r->filtered_size,
1011 IO_MEM_UNASSIGNED);
1012 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
1013 }
1014 }
1015 r->addr = new_addr;
1016 r->filtered_size = filtered_size;
1017 if (r->addr != PCI_BAR_UNMAPPED) {
1018 /*
1019 * TODO: currently almost all the map funcions assumes
1020 * filtered_size == size and addr & ~(size - 1) == addr.
1021 * However with bridge filtering, they aren't always true.
1022 * Teach them such cases, such that filtered_size < size and
1023 * addr & (size - 1) != 0.
1024 */
1025 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1026 r->map_func(d, i, r->addr, r->filtered_size, r->type);
1027 } else {
1028 r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
1029 r->filtered_size, r->type);
1030 }
1031 }
1032 }
1033 }
1034
1035 static inline int pci_irq_disabled(PCIDevice *d)
1036 {
1037 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1038 }
1039
1040 /* Called after interrupt disabled field update in config space,
1041 * assert/deassert interrupts if necessary.
1042 * Gets original interrupt disable bit value (before update). */
1043 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1044 {
1045 int i, disabled = pci_irq_disabled(d);
1046 if (disabled == was_irq_disabled)
1047 return;
1048 for (i = 0; i < PCI_NUM_PINS; ++i) {
1049 int state = pci_irq_state(d, i);
1050 pci_change_irq_level(d, i, disabled ? -state : state);
1051 }
1052 }
1053
1054 uint32_t pci_default_read_config(PCIDevice *d,
1055 uint32_t address, int len)
1056 {
1057 uint32_t val = 0;
1058 assert(len == 1 || len == 2 || len == 4);
1059 len = MIN(len, pci_config_size(d) - address);
1060 memcpy(&val, d->config + address, len);
1061 return le32_to_cpu(val);
1062 }
1063
1064 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1065 {
1066 int i, was_irq_disabled = pci_irq_disabled(d);
1067 uint32_t config_size = pci_config_size(d);
1068
1069 for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
1070 uint8_t wmask = d->wmask[addr + i];
1071 uint8_t w1cmask = d->w1cmask[addr + i];
1072 assert(!(wmask & w1cmask));
1073 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1074 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1075 }
1076 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1077 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1078 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1079 range_covers_byte(addr, l, PCI_COMMAND))
1080 pci_update_mappings(d);
1081
1082 if (range_covers_byte(addr, l, PCI_COMMAND))
1083 pci_update_irq_disabled(d, was_irq_disabled);
1084 }
1085
1086 /***********************************************************/
1087 /* generic PCI irq support */
1088
1089 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1090 static void pci_set_irq(void *opaque, int irq_num, int level)
1091 {
1092 PCIDevice *pci_dev = opaque;
1093 int change;
1094
1095 change = level - pci_irq_state(pci_dev, irq_num);
1096 if (!change)
1097 return;
1098
1099 pci_set_irq_state(pci_dev, irq_num, level);
1100 pci_update_irq_status(pci_dev);
1101 if (pci_irq_disabled(pci_dev))
1102 return;
1103 pci_change_irq_level(pci_dev, irq_num, change);
1104 }
1105
1106 /***********************************************************/
1107 /* monitor info on PCI */
1108
1109 typedef struct {
1110 uint16_t class;
1111 const char *desc;
1112 const char *fw_name;
1113 uint16_t fw_ign_bits;
1114 } pci_class_desc;
1115
1116 static const pci_class_desc pci_class_descriptions[] =
1117 {
1118 { 0x0001, "VGA controller", "display"},
1119 { 0x0100, "SCSI controller", "scsi"},
1120 { 0x0101, "IDE controller", "ide"},
1121 { 0x0102, "Floppy controller", "fdc"},
1122 { 0x0103, "IPI controller", "ipi"},
1123 { 0x0104, "RAID controller", "raid"},
1124 { 0x0106, "SATA controller"},
1125 { 0x0107, "SAS controller"},
1126 { 0x0180, "Storage controller"},
1127 { 0x0200, "Ethernet controller", "ethernet"},
1128 { 0x0201, "Token Ring controller", "token-ring"},
1129 { 0x0202, "FDDI controller", "fddi"},
1130 { 0x0203, "ATM controller", "atm"},
1131 { 0x0280, "Network controller"},
1132 { 0x0300, "VGA controller", "display", 0x00ff},
1133 { 0x0301, "XGA controller"},
1134 { 0x0302, "3D controller"},
1135 { 0x0380, "Display controller"},
1136 { 0x0400, "Video controller", "video"},
1137 { 0x0401, "Audio controller", "sound"},
1138 { 0x0402, "Phone"},
1139 { 0x0480, "Multimedia controller"},
1140 { 0x0500, "RAM controller", "memory"},
1141 { 0x0501, "Flash controller", "flash"},
1142 { 0x0580, "Memory controller"},
1143 { 0x0600, "Host bridge", "host"},
1144 { 0x0601, "ISA bridge", "isa"},
1145 { 0x0602, "EISA bridge", "eisa"},
1146 { 0x0603, "MC bridge", "mca"},
1147 { 0x0604, "PCI bridge", "pci"},
1148 { 0x0605, "PCMCIA bridge", "pcmcia"},
1149 { 0x0606, "NUBUS bridge", "nubus"},
1150 { 0x0607, "CARDBUS bridge", "cardbus"},
1151 { 0x0608, "RACEWAY bridge"},
1152 { 0x0680, "Bridge"},
1153 { 0x0700, "Serial port", "serial"},
1154 { 0x0701, "Parallel port", "parallel"},
1155 { 0x0800, "Interrupt controller", "interrupt-controller"},
1156 { 0x0801, "DMA controller", "dma-controller"},
1157 { 0x0802, "Timer", "timer"},
1158 { 0x0803, "RTC", "rtc"},
1159 { 0x0900, "Keyboard", "keyboard"},
1160 { 0x0901, "Pen", "pen"},
1161 { 0x0902, "Mouse", "mouse"},
1162 { 0x0A00, "Dock station", "dock", 0x00ff},
1163 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1164 { 0x0c00, "Fireware contorller", "fireware"},
1165 { 0x0c01, "Access bus controller", "access-bus"},
1166 { 0x0c02, "SSA controller", "ssa"},
1167 { 0x0c03, "USB controller", "usb"},
1168 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1169 { 0, NULL}
1170 };
1171
1172 static void pci_for_each_device_under_bus(PCIBus *bus,
1173 void (*fn)(PCIBus *b, PCIDevice *d))
1174 {
1175 PCIDevice *d;
1176 int devfn;
1177
1178 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1179 d = bus->devices[devfn];
1180 if (d) {
1181 fn(bus, d);
1182 }
1183 }
1184 }
1185
1186 void pci_for_each_device(PCIBus *bus, int bus_num,
1187 void (*fn)(PCIBus *b, PCIDevice *d))
1188 {
1189 bus = pci_find_bus(bus, bus_num);
1190
1191 if (bus) {
1192 pci_for_each_device_under_bus(bus, fn);
1193 }
1194 }
1195
1196 static void pci_device_print(Monitor *mon, QDict *device)
1197 {
1198 QDict *qdict;
1199 QListEntry *entry;
1200 uint64_t addr, size;
1201
1202 monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1203 monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1204 qdict_get_int(device, "slot"),
1205 qdict_get_int(device, "function"));
1206 monitor_printf(mon, " ");
1207
1208 qdict = qdict_get_qdict(device, "class_info");
1209 if (qdict_haskey(qdict, "desc")) {
1210 monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1211 } else {
1212 monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1213 }
1214
1215 qdict = qdict_get_qdict(device, "id");
1216 monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1217 qdict_get_int(qdict, "device"),
1218 qdict_get_int(qdict, "vendor"));
1219
1220 if (qdict_haskey(device, "irq")) {
1221 monitor_printf(mon, " IRQ %" PRId64 ".\n",
1222 qdict_get_int(device, "irq"));
1223 }
1224
1225 if (qdict_haskey(device, "pci_bridge")) {
1226 QDict *info;
1227
1228 qdict = qdict_get_qdict(device, "pci_bridge");
1229
1230 info = qdict_get_qdict(qdict, "bus");
1231 monitor_printf(mon, " BUS %" PRId64 ".\n",
1232 qdict_get_int(info, "number"));
1233 monitor_printf(mon, " secondary bus %" PRId64 ".\n",
1234 qdict_get_int(info, "secondary"));
1235 monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
1236 qdict_get_int(info, "subordinate"));
1237
1238 info = qdict_get_qdict(qdict, "io_range");
1239 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1240 qdict_get_int(info, "base"),
1241 qdict_get_int(info, "limit"));
1242
1243 info = qdict_get_qdict(qdict, "memory_range");
1244 monitor_printf(mon,
1245 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1246 qdict_get_int(info, "base"),
1247 qdict_get_int(info, "limit"));
1248
1249 info = qdict_get_qdict(qdict, "prefetchable_range");
1250 monitor_printf(mon, " prefetchable memory range "
1251 "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1252 qdict_get_int(info, "base"),
1253 qdict_get_int(info, "limit"));
1254 }
1255
1256 QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1257 qdict = qobject_to_qdict(qlist_entry_obj(entry));
1258 monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1259
1260 addr = qdict_get_int(qdict, "address");
1261 size = qdict_get_int(qdict, "size");
1262
1263 if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1264 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1265 " [0x%04"FMT_PCIBUS"].\n",
1266 addr, addr + size - 1);
1267 } else {
1268 monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1269 " [0x%08"FMT_PCIBUS"].\n",
1270 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1271 qdict_get_bool(qdict, "prefetch") ?
1272 " prefetchable" : "", addr, addr + size - 1);
1273 }
1274 }
1275
1276 monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1277
1278 if (qdict_haskey(device, "pci_bridge")) {
1279 qdict = qdict_get_qdict(device, "pci_bridge");
1280 if (qdict_haskey(qdict, "devices")) {
1281 QListEntry *dev;
1282 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1283 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1284 }
1285 }
1286 }
1287 }
1288
1289 void do_pci_info_print(Monitor *mon, const QObject *data)
1290 {
1291 QListEntry *bus, *dev;
1292
1293 QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1294 QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1295 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1296 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1297 }
1298 }
1299 }
1300
1301 static QObject *pci_get_dev_class(const PCIDevice *dev)
1302 {
1303 int class;
1304 const pci_class_desc *desc;
1305
1306 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1307 desc = pci_class_descriptions;
1308 while (desc->desc && class != desc->class)
1309 desc++;
1310
1311 if (desc->desc) {
1312 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1313 desc->desc, class);
1314 } else {
1315 return qobject_from_jsonf("{ 'class': %d }", class);
1316 }
1317 }
1318
1319 static QObject *pci_get_dev_id(const PCIDevice *dev)
1320 {
1321 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1322 pci_get_word(dev->config + PCI_VENDOR_ID),
1323 pci_get_word(dev->config + PCI_DEVICE_ID));
1324 }
1325
1326 static QObject *pci_get_regions_list(const PCIDevice *dev)
1327 {
1328 int i;
1329 QList *regions_list;
1330
1331 regions_list = qlist_new();
1332
1333 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1334 QObject *obj;
1335 const PCIIORegion *r = &dev->io_regions[i];
1336
1337 if (!r->size) {
1338 continue;
1339 }
1340
1341 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1342 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1343 "'address': %" PRId64 ", "
1344 "'size': %" PRId64 " }",
1345 i, r->addr, r->size);
1346 } else {
1347 int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1348
1349 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1350 "'mem_type_64': %i, 'prefetch': %i, "
1351 "'address': %" PRId64 ", "
1352 "'size': %" PRId64 " }",
1353 i, mem_type_64,
1354 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1355 r->addr, r->size);
1356 }
1357
1358 qlist_append_obj(regions_list, obj);
1359 }
1360
1361 return QOBJECT(regions_list);
1362 }
1363
1364 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1365
1366 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1367 {
1368 uint8_t type;
1369 QObject *obj;
1370
1371 obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1372 " 'qdev_id': %s }",
1373 bus_num,
1374 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1375 pci_get_dev_class(dev), pci_get_dev_id(dev),
1376 pci_get_regions_list(dev),
1377 dev->qdev.id ? dev->qdev.id : "");
1378
1379 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1380 QDict *qdict = qobject_to_qdict(obj);
1381 qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1382 }
1383
1384 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1385 if (type == PCI_HEADER_TYPE_BRIDGE) {
1386 QDict *qdict;
1387 QObject *pci_bridge;
1388
1389 pci_bridge = qobject_from_jsonf("{ 'bus': "
1390 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1391 "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1392 "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1393 "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1394 dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1395 dev->config[PCI_SUBORDINATE_BUS],
1396 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1397 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1398 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1399 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1400 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1401 PCI_BASE_ADDRESS_MEM_PREFETCH),
1402 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1403 PCI_BASE_ADDRESS_MEM_PREFETCH));
1404
1405 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1406 PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1407
1408 if (child_bus) {
1409 qdict = qobject_to_qdict(pci_bridge);
1410 qdict_put_obj(qdict, "devices",
1411 pci_get_devices_list(child_bus,
1412 dev->config[PCI_SECONDARY_BUS]));
1413 }
1414 }
1415 qdict = qobject_to_qdict(obj);
1416 qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1417 }
1418
1419 return obj;
1420 }
1421
1422 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1423 {
1424 int devfn;
1425 PCIDevice *dev;
1426 QList *dev_list;
1427
1428 dev_list = qlist_new();
1429
1430 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1431 dev = bus->devices[devfn];
1432 if (dev) {
1433 qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1434 }
1435 }
1436
1437 return QOBJECT(dev_list);
1438 }
1439
1440 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1441 {
1442 bus = pci_find_bus(bus, bus_num);
1443 if (bus) {
1444 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1445 bus_num, pci_get_devices_list(bus, bus_num));
1446 }
1447
1448 return NULL;
1449 }
1450
1451 void do_pci_info(Monitor *mon, QObject **ret_data)
1452 {
1453 QList *bus_list;
1454 struct PCIHostBus *host;
1455
1456 bus_list = qlist_new();
1457
1458 QLIST_FOREACH(host, &host_buses, next) {
1459 QObject *obj = pci_get_bus_dict(host->bus, 0);
1460 if (obj) {
1461 qlist_append_obj(bus_list, obj);
1462 }
1463 }
1464
1465 *ret_data = QOBJECT(bus_list);
1466 }
1467
1468 static const char * const pci_nic_models[] = {
1469 "ne2k_pci",
1470 "i82551",
1471 "i82557b",
1472 "i82559er",
1473 "rtl8139",
1474 "e1000",
1475 "pcnet",
1476 "virtio",
1477 NULL
1478 };
1479
1480 static const char * const pci_nic_names[] = {
1481 "ne2k_pci",
1482 "i82551",
1483 "i82557b",
1484 "i82559er",
1485 "rtl8139",
1486 "e1000",
1487 "pcnet",
1488 "virtio-net-pci",
1489 NULL
1490 };
1491
1492 /* Initialize a PCI NIC. */
1493 /* FIXME callers should check for failure, but don't */
1494 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1495 const char *default_devaddr)
1496 {
1497 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1498 PCIBus *bus;
1499 int devfn;
1500 PCIDevice *pci_dev;
1501 DeviceState *dev;
1502 int i;
1503
1504 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1505 if (i < 0)
1506 return NULL;
1507
1508 bus = pci_get_bus_devfn(&devfn, devaddr);
1509 if (!bus) {
1510 error_report("Invalid PCI device address %s for device %s",
1511 devaddr, pci_nic_names[i]);
1512 return NULL;
1513 }
1514
1515 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1516 dev = &pci_dev->qdev;
1517 qdev_set_nic_properties(dev, nd);
1518 if (qdev_init(dev) < 0)
1519 return NULL;
1520 return pci_dev;
1521 }
1522
1523 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1524 const char *default_devaddr)
1525 {
1526 PCIDevice *res;
1527
1528 if (qemu_show_nic_models(nd->model, pci_nic_models))
1529 exit(0);
1530
1531 res = pci_nic_init(nd, default_model, default_devaddr);
1532 if (!res)
1533 exit(1);
1534 return res;
1535 }
1536
1537 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1538 {
1539 pci_update_mappings(d);
1540 }
1541
1542 void pci_bridge_update_mappings(PCIBus *b)
1543 {
1544 PCIBus *child;
1545
1546 pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1547
1548 QLIST_FOREACH(child, &b->child, sibling) {
1549 pci_bridge_update_mappings(child);
1550 }
1551 }
1552
1553 /* Whether a given bus number is in range of the secondary
1554 * bus of the given bridge device. */
1555 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1556 {
1557 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1558 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1559 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1560 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1561 }
1562
1563 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1564 {
1565 PCIBus *sec;
1566
1567 if (!bus) {
1568 return NULL;
1569 }
1570
1571 if (pci_bus_num(bus) == bus_num) {
1572 return bus;
1573 }
1574
1575 /* Consider all bus numbers in range for the host pci bridge. */
1576 if (bus->parent_dev &&
1577 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1578 return NULL;
1579 }
1580
1581 /* try child bus */
1582 for (; bus; bus = sec) {
1583 QLIST_FOREACH(sec, &bus->child, sibling) {
1584 assert(sec->parent_dev);
1585 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1586 return sec;
1587 }
1588 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1589 break;
1590 }
1591 }
1592 }
1593
1594 return NULL;
1595 }
1596
1597 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1598 {
1599 bus = pci_find_bus(bus, bus_num);
1600
1601 if (!bus)
1602 return NULL;
1603
1604 return bus->devices[PCI_DEVFN(slot, function)];
1605 }
1606
1607 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1608 {
1609 PCIDevice *pci_dev = (PCIDevice *)qdev;
1610 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1611 PCIBus *bus;
1612 int devfn, rc;
1613 bool is_default_rom;
1614
1615 /* initialize cap_present for pci_is_express() and pci_config_size() */
1616 if (info->is_express) {
1617 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1618 }
1619
1620 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1621 devfn = pci_dev->devfn;
1622 pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1623 info->config_read, info->config_write,
1624 info->is_bridge);
1625 if (pci_dev == NULL)
1626 return -1;
1627 if (qdev->hotplugged && info->no_hotplug) {
1628 qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
1629 do_pci_unregister_device(pci_dev);
1630 return -1;
1631 }
1632 rc = info->init(pci_dev);
1633 if (rc != 0) {
1634 do_pci_unregister_device(pci_dev);
1635 return rc;
1636 }
1637
1638 /* rom loading */
1639 is_default_rom = false;
1640 if (pci_dev->romfile == NULL && info->romfile != NULL) {
1641 pci_dev->romfile = qemu_strdup(info->romfile);
1642 is_default_rom = true;
1643 }
1644 pci_add_option_rom(pci_dev, is_default_rom);
1645
1646 if (bus->hotplug) {
1647 /* Let buses differentiate between hotplug and when device is
1648 * enabled during qemu machine creation. */
1649 rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1650 qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1651 PCI_COLDPLUG_ENABLED);
1652 if (rc != 0) {
1653 int r = pci_unregister_device(&pci_dev->qdev);
1654 assert(!r);
1655 return rc;
1656 }
1657 }
1658 return 0;
1659 }
1660
1661 static int pci_unplug_device(DeviceState *qdev)
1662 {
1663 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1664 PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
1665
1666 if (info->no_hotplug) {
1667 qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
1668 return -1;
1669 }
1670 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1671 PCI_HOTPLUG_DISABLED);
1672 }
1673
1674 void pci_qdev_register(PCIDeviceInfo *info)
1675 {
1676 info->qdev.init = pci_qdev_init;
1677 info->qdev.unplug = pci_unplug_device;
1678 info->qdev.exit = pci_unregister_device;
1679 info->qdev.bus_info = &pci_bus_info;
1680 qdev_register(&info->qdev);
1681 }
1682
1683 void pci_qdev_register_many(PCIDeviceInfo *info)
1684 {
1685 while (info->qdev.name) {
1686 pci_qdev_register(info);
1687 info++;
1688 }
1689 }
1690
1691 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1692 const char *name)
1693 {
1694 DeviceState *dev;
1695
1696 dev = qdev_create(&bus->qbus, name);
1697 qdev_prop_set_uint32(dev, "addr", devfn);
1698 qdev_prop_set_bit(dev, "multifunction", multifunction);
1699 return DO_UPCAST(PCIDevice, qdev, dev);
1700 }
1701
1702 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1703 bool multifunction,
1704 const char *name)
1705 {
1706 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1707 qdev_init_nofail(&dev->qdev);
1708 return dev;
1709 }
1710
1711 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1712 {
1713 return pci_create_multifunction(bus, devfn, false, name);
1714 }
1715
1716 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1717 {
1718 return pci_create_simple_multifunction(bus, devfn, false, name);
1719 }
1720
1721 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1722 {
1723 int config_size = pci_config_size(pdev);
1724 int offset = PCI_CONFIG_HEADER_SIZE;
1725 int i;
1726 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1727 if (pdev->used[i])
1728 offset = i + 1;
1729 else if (i - offset + 1 == size)
1730 return offset;
1731 return 0;
1732 }
1733
1734 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1735 uint8_t *prev_p)
1736 {
1737 uint8_t next, prev;
1738
1739 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1740 return 0;
1741
1742 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1743 prev = next + PCI_CAP_LIST_NEXT)
1744 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1745 break;
1746
1747 if (prev_p)
1748 *prev_p = prev;
1749 return next;
1750 }
1751
1752 static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1753 {
1754 cpu_register_physical_memory(addr, size, pdev->rom_offset);
1755 }
1756
1757 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1758 This is needed for an option rom which is used for more than one device. */
1759 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1760 {
1761 uint16_t vendor_id;
1762 uint16_t device_id;
1763 uint16_t rom_vendor_id;
1764 uint16_t rom_device_id;
1765 uint16_t rom_magic;
1766 uint16_t pcir_offset;
1767 uint8_t checksum;
1768
1769 /* Words in rom data are little endian (like in PCI configuration),
1770 so they can be read / written with pci_get_word / pci_set_word. */
1771
1772 /* Only a valid rom will be patched. */
1773 rom_magic = pci_get_word(ptr);
1774 if (rom_magic != 0xaa55) {
1775 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1776 return;
1777 }
1778 pcir_offset = pci_get_word(ptr + 0x18);
1779 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1780 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1781 return;
1782 }
1783
1784 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1785 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1786 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1787 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1788
1789 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1790 vendor_id, device_id, rom_vendor_id, rom_device_id);
1791
1792 checksum = ptr[6];
1793
1794 if (vendor_id != rom_vendor_id) {
1795 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1796 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1797 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1798 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1799 ptr[6] = checksum;
1800 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1801 }
1802
1803 if (device_id != rom_device_id) {
1804 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1805 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1806 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1807 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1808 ptr[6] = checksum;
1809 pci_set_word(ptr + pcir_offset + 6, device_id);
1810 }
1811 }
1812
1813 /* Add an option rom for the device */
1814 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1815 {
1816 int size;
1817 char *path;
1818 void *ptr;
1819 char name[32];
1820
1821 if (!pdev->romfile)
1822 return 0;
1823 if (strlen(pdev->romfile) == 0)
1824 return 0;
1825
1826 if (!pdev->rom_bar) {
1827 /*
1828 * Load rom via fw_cfg instead of creating a rom bar,
1829 * for 0.11 compatibility.
1830 */
1831 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1832 if (class == 0x0300) {
1833 rom_add_vga(pdev->romfile);
1834 } else {
1835 rom_add_option(pdev->romfile, -1);
1836 }
1837 return 0;
1838 }
1839
1840 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1841 if (path == NULL) {
1842 path = qemu_strdup(pdev->romfile);
1843 }
1844
1845 size = get_image_size(path);
1846 if (size < 0) {
1847 error_report("%s: failed to find romfile \"%s\"",
1848 __FUNCTION__, pdev->romfile);
1849 return -1;
1850 }
1851 if (size & (size - 1)) {
1852 size = 1 << qemu_fls(size);
1853 }
1854
1855 if (pdev->qdev.info->vmsd)
1856 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1857 else
1858 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1859 pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size);
1860
1861 ptr = qemu_get_ram_ptr(pdev->rom_offset);
1862 load_image(path, ptr);
1863 qemu_free(path);
1864
1865 if (is_default_rom) {
1866 /* Only the default rom images will be patched (if needed). */
1867 pci_patch_ids(pdev, ptr, size);
1868 }
1869
1870 pci_register_bar(pdev, PCI_ROM_SLOT, size,
1871 0, pci_map_option_rom);
1872
1873 return 0;
1874 }
1875
1876 static void pci_del_option_rom(PCIDevice *pdev)
1877 {
1878 if (!pdev->rom_offset)
1879 return;
1880
1881 qemu_ram_free(pdev->rom_offset);
1882 pdev->rom_offset = 0;
1883 }
1884
1885 /*
1886 * if !offset
1887 * Reserve space and add capability to the linked list in pci config space
1888 *
1889 * if offset = 0,
1890 * Find and reserve space and add capability to the linked list
1891 * in pci config space */
1892 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1893 uint8_t offset, uint8_t size)
1894 {
1895 uint8_t *config;
1896 if (!offset) {
1897 offset = pci_find_space(pdev, size);
1898 if (!offset) {
1899 return -ENOSPC;
1900 }
1901 }
1902
1903 config = pdev->config + offset;
1904 config[PCI_CAP_LIST_ID] = cap_id;
1905 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1906 pdev->config[PCI_CAPABILITY_LIST] = offset;
1907 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1908 memset(pdev->used + offset, 0xFF, size);
1909 /* Make capability read-only by default */
1910 memset(pdev->wmask + offset, 0, size);
1911 /* Check capability by default */
1912 memset(pdev->cmask + offset, 0xFF, size);
1913 return offset;
1914 }
1915
1916 /* Unlink capability from the pci config space. */
1917 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1918 {
1919 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1920 if (!offset)
1921 return;
1922 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1923 /* Make capability writeable again */
1924 memset(pdev->wmask + offset, 0xff, size);
1925 memset(pdev->w1cmask + offset, 0, size);
1926 /* Clear cmask as device-specific registers can't be checked */
1927 memset(pdev->cmask + offset, 0, size);
1928 memset(pdev->used + offset, 0, size);
1929
1930 if (!pdev->config[PCI_CAPABILITY_LIST])
1931 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1932 }
1933
1934 /* Reserve space for capability at a known offset (to call after load). */
1935 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1936 {
1937 memset(pdev->used + offset, 0xff, size);
1938 }
1939
1940 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1941 {
1942 return pci_find_capability_list(pdev, cap_id, NULL);
1943 }
1944
1945 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1946 {
1947 PCIDevice *d = (PCIDevice *)dev;
1948 const pci_class_desc *desc;
1949 char ctxt[64];
1950 PCIIORegion *r;
1951 int i, class;
1952
1953 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1954 desc = pci_class_descriptions;
1955 while (desc->desc && class != desc->class)
1956 desc++;
1957 if (desc->desc) {
1958 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1959 } else {
1960 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1961 }
1962
1963 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1964 "pci id %04x:%04x (sub %04x:%04x)\n",
1965 indent, "", ctxt, pci_bus_num(d->bus),
1966 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1967 pci_get_word(d->config + PCI_VENDOR_ID),
1968 pci_get_word(d->config + PCI_DEVICE_ID),
1969 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1970 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1971 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1972 r = &d->io_regions[i];
1973 if (!r->size)
1974 continue;
1975 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1976 " [0x%"FMT_PCIBUS"]\n",
1977 indent, "",
1978 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1979 r->addr, r->addr + r->size - 1);
1980 }
1981 }
1982
1983 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
1984 {
1985 PCIDevice *d = (PCIDevice *)dev;
1986 const char *name = NULL;
1987 const pci_class_desc *desc = pci_class_descriptions;
1988 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1989
1990 while (desc->desc &&
1991 (class & ~desc->fw_ign_bits) !=
1992 (desc->class & ~desc->fw_ign_bits)) {
1993 desc++;
1994 }
1995
1996 if (desc->desc) {
1997 name = desc->fw_name;
1998 }
1999
2000 if (name) {
2001 pstrcpy(buf, len, name);
2002 } else {
2003 snprintf(buf, len, "pci%04x,%04x",
2004 pci_get_word(d->config + PCI_VENDOR_ID),
2005 pci_get_word(d->config + PCI_DEVICE_ID));
2006 }
2007
2008 return buf;
2009 }
2010
2011 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2012 {
2013 PCIDevice *d = (PCIDevice *)dev;
2014 char path[50], name[33];
2015 int off;
2016
2017 off = snprintf(path, sizeof(path), "%s@%x",
2018 pci_dev_fw_name(dev, name, sizeof name),
2019 PCI_SLOT(d->devfn));
2020 if (PCI_FUNC(d->devfn))
2021 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2022 return strdup(path);
2023 }
2024
2025 static char *pcibus_get_dev_path(DeviceState *dev)
2026 {
2027 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2028 PCIDevice *t;
2029 int slot_depth;
2030 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2031 * 00 is added here to make this format compatible with
2032 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2033 * Slot.Function list specifies the slot and function numbers for all
2034 * devices on the path from root to the specific device. */
2035 int domain_len = strlen("DDDD:00");
2036 int slot_len = strlen(":SS.F");
2037 int path_len;
2038 char *path, *p;
2039
2040 /* Calculate # of slots on path between device and root. */;
2041 slot_depth = 0;
2042 for (t = d; t; t = t->bus->parent_dev) {
2043 ++slot_depth;
2044 }
2045
2046 path_len = domain_len + slot_len * slot_depth;
2047
2048 /* Allocate memory, fill in the terminating null byte. */
2049 path = malloc(path_len + 1 /* For '\0' */);
2050 path[path_len] = '\0';
2051
2052 /* First field is the domain. */
2053 snprintf(path, domain_len, "%04x:00", pci_find_domain(d->bus));
2054
2055 /* Fill in slot numbers. We walk up from device to root, so need to print
2056 * them in the reverse order, last to first. */
2057 p = path + path_len;
2058 for (t = d; t; t = t->bus->parent_dev) {
2059 p -= slot_len;
2060 snprintf(p, slot_len, ":%02x.%x", PCI_SLOT(t->devfn), PCI_FUNC(d->devfn));
2061 }
2062
2063 return path;
2064 }
2065
2066 static int pci_qdev_find_recursive(PCIBus *bus,
2067 const char *id, PCIDevice **pdev)
2068 {
2069 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2070 if (!qdev) {
2071 return -ENODEV;
2072 }
2073
2074 /* roughly check if given qdev is pci device */
2075 if (qdev->info->init == &pci_qdev_init &&
2076 qdev->parent_bus->info == &pci_bus_info) {
2077 *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
2078 return 0;
2079 }
2080 return -EINVAL;
2081 }
2082
2083 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2084 {
2085 struct PCIHostBus *host;
2086 int rc = -ENODEV;
2087
2088 QLIST_FOREACH(host, &host_buses, next) {
2089 int tmp = pci_qdev_find_recursive(host->bus, id, pdev);
2090 if (!tmp) {
2091 rc = 0;
2092 break;
2093 }
2094 if (tmp != -ENODEV) {
2095 rc = tmp;
2096 }
2097 }
2098
2099 return rc;
2100 }
QEmu