include/hw/riscv/sifive_u.h

   1 /*
   2  * SiFive U series machine interface
   3  *
   4  * Copyright (c) 2017 SiFive, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #ifndef HW_SIFIVE_U_H
  20 #define HW_SIFIVE_U_H
  21
  22 #include "hw/dma/sifive_pdma.h"
  23 #include "hw/net/cadence_gem.h"
  24 #include "hw/riscv/riscv_hart.h"
  25 #include "hw/riscv/sifive_cpu.h"
  26 #include "hw/gpio/sifive_gpio.h"
  27 #include "hw/misc/sifive_u_otp.h"
  28 #include "hw/misc/sifive_u_prci.h"
  29
  30 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
  31 #define RISCV_U_SOC(obj) \
  32     OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC)
  33
  34 typedef struct SiFiveUSoCState {
  35     /*< private >*/
  36     DeviceState parent_obj;
  37
  38     /*< public >*/
  39     CPUClusterState e_cluster;
  40     CPUClusterState u_cluster;
  41     RISCVHartArrayState e_cpus;
  42     RISCVHartArrayState u_cpus;
  43     DeviceState *plic;
  44     SiFiveUPRCIState prci;
  45     SIFIVEGPIOState gpio;
  46     SiFiveUOTPState otp;
  47     SiFivePDMAState dma;
  48     CadenceGEMState gem;
  49
  50     uint32_t serial;
  51     char *cpu_type;
  52 } SiFiveUSoCState;
  53
  54 #define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u")
  55 #define RISCV_U_MACHINE(obj) \
  56     OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE)
  57
  58 typedef struct SiFiveUState {
  59     /*< private >*/
  60     MachineState parent_obj;
  61
  62     /*< public >*/
  63     SiFiveUSoCState soc;
  64
  65     void *fdt;
  66     int fdt_size;
  67
  68     bool start_in_flash;
  69     uint32_t msel;
  70     uint32_t serial;
  71 } SiFiveUState;
  72
  73 enum {
  74     SIFIVE_U_DEV_DEBUG,
  75     SIFIVE_U_DEV_MROM,
  76     SIFIVE_U_DEV_CLINT,
  77     SIFIVE_U_DEV_L2CC,
  78     SIFIVE_U_DEV_PDMA,
  79     SIFIVE_U_DEV_L2LIM,
  80     SIFIVE_U_DEV_PLIC,
  81     SIFIVE_U_DEV_PRCI,
  82     SIFIVE_U_DEV_UART0,
  83     SIFIVE_U_DEV_UART1,
  84     SIFIVE_U_DEV_GPIO,
  85     SIFIVE_U_DEV_OTP,
  86     SIFIVE_U_DEV_DMC,
  87     SIFIVE_U_DEV_FLASH0,
  88     SIFIVE_U_DEV_DRAM,
  89     SIFIVE_U_DEV_GEM,
  90     SIFIVE_U_DEV_GEM_MGMT
  91 };
  92
  93 enum {
  94     SIFIVE_U_L2CC_IRQ0 = 1,
  95     SIFIVE_U_L2CC_IRQ1 = 2,
  96     SIFIVE_U_L2CC_IRQ2 = 3,
  97     SIFIVE_U_UART0_IRQ = 4,
  98     SIFIVE_U_UART1_IRQ = 5,
  99     SIFIVE_U_GPIO_IRQ0 = 7,
 100     SIFIVE_U_GPIO_IRQ1 = 8,
 101     SIFIVE_U_GPIO_IRQ2 = 9,
 102     SIFIVE_U_GPIO_IRQ3 = 10,
 103     SIFIVE_U_GPIO_IRQ4 = 11,
 104     SIFIVE_U_GPIO_IRQ5 = 12,
 105     SIFIVE_U_GPIO_IRQ6 = 13,
 106     SIFIVE_U_GPIO_IRQ7 = 14,
 107     SIFIVE_U_GPIO_IRQ8 = 15,
 108     SIFIVE_U_GPIO_IRQ9 = 16,
 109     SIFIVE_U_GPIO_IRQ10 = 17,
 110     SIFIVE_U_GPIO_IRQ11 = 18,
 111     SIFIVE_U_GPIO_IRQ12 = 19,
 112     SIFIVE_U_GPIO_IRQ13 = 20,
 113     SIFIVE_U_GPIO_IRQ14 = 21,
 114     SIFIVE_U_GPIO_IRQ15 = 22,
 115     SIFIVE_U_PDMA_IRQ0 = 23,
 116     SIFIVE_U_PDMA_IRQ1 = 24,
 117     SIFIVE_U_PDMA_IRQ2 = 25,
 118     SIFIVE_U_PDMA_IRQ3 = 26,
 119     SIFIVE_U_PDMA_IRQ4 = 27,
 120     SIFIVE_U_PDMA_IRQ5 = 28,
 121     SIFIVE_U_PDMA_IRQ6 = 29,
 122     SIFIVE_U_PDMA_IRQ7 = 30,
 123     SIFIVE_U_GEM_IRQ = 0x35
 124 };
 125
 126 enum {
 127     SIFIVE_U_HFCLK_FREQ = 33333333,
 128     SIFIVE_U_RTCCLK_FREQ = 1000000
 129 };
 130
 131 enum {
 132     MSEL_MEMMAP_QSPI0_FLASH = 1,
 133     MSEL_L2LIM_QSPI0_FLASH = 6,
 134     MSEL_L2LIM_QSPI2_SD = 11
 135 };
 136
 137 #define SIFIVE_U_MANAGEMENT_CPU_COUNT   1
 138 #define SIFIVE_U_COMPUTE_CPU_COUNT      4
 139
 140 #define SIFIVE_U_PLIC_HART_CONFIG "MS"
 141 #define SIFIVE_U_PLIC_NUM_SOURCES 54
 142 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7
 143 #define SIFIVE_U_PLIC_PRIORITY_BASE 0x04
 144 #define SIFIVE_U_PLIC_PENDING_BASE 0x1000
 145 #define SIFIVE_U_PLIC_ENABLE_BASE 0x2000
 146 #define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80
 147 #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000
 148 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000
 149
 150 #endif