4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
31 #include "hw/i386/pc.h"
32 #include "hw/i386/apic.h"
33 #include "exec/ioport.h"
34 #include <asm/hyperv.h>
35 #include "hw/pci/pci.h"
40 #define DPRINTF(fmt, ...) \
41 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
43 #define DPRINTF(fmt, ...) \
47 #define MSR_KVM_WALL_CLOCK 0x11
48 #define MSR_KVM_SYSTEM_TIME 0x12
51 #define BUS_MCEERR_AR 4
54 #define BUS_MCEERR_AO 5
57 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
58 KVM_CAP_INFO(SET_TSS_ADDR
),
59 KVM_CAP_INFO(EXT_CPUID
),
60 KVM_CAP_INFO(MP_STATE
),
64 static bool has_msr_star
;
65 static bool has_msr_hsave_pa
;
66 static bool has_msr_tsc_adjust
;
67 static bool has_msr_tsc_deadline
;
68 static bool has_msr_feature_control
;
69 static bool has_msr_async_pf_en
;
70 static bool has_msr_pv_eoi_en
;
71 static bool has_msr_misc_enable
;
72 static bool has_msr_bndcfgs
;
73 static bool has_msr_kvm_steal_time
;
74 static int lm_capable_kernel
;
76 static bool has_msr_architectural_pmu
;
77 static uint32_t num_architectural_pmu_counters
;
79 bool kvm_allows_irq0_override(void)
81 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
84 static struct kvm_cpuid2
*try_get_cpuid(KVMState
*s
, int max
)
86 struct kvm_cpuid2
*cpuid
;
89 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
90 cpuid
= (struct kvm_cpuid2
*)g_malloc0(size
);
92 r
= kvm_ioctl(s
, KVM_GET_SUPPORTED_CPUID
, cpuid
);
93 if (r
== 0 && cpuid
->nent
>= max
) {
101 fprintf(stderr
, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
109 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
112 static struct kvm_cpuid2
*get_supported_cpuid(KVMState
*s
)
114 struct kvm_cpuid2
*cpuid
;
116 while ((cpuid
= try_get_cpuid(s
, max
)) == NULL
) {
122 struct kvm_para_features
{
125 } para_features
[] = {
126 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
127 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
128 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
129 { KVM_CAP_ASYNC_PF
, KVM_FEATURE_ASYNC_PF
},
133 static int get_para_features(KVMState
*s
)
137 for (i
= 0; i
< ARRAY_SIZE(para_features
) - 1; i
++) {
138 if (kvm_check_extension(s
, para_features
[i
].cap
)) {
139 features
|= (1 << para_features
[i
].feature
);
147 /* Returns the value for a specific register on the cpuid entry
149 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2
*entry
, int reg
)
169 /* Find matching entry for function/index on kvm_cpuid2 struct
171 static struct kvm_cpuid_entry2
*cpuid_find_entry(struct kvm_cpuid2
*cpuid
,
176 for (i
= 0; i
< cpuid
->nent
; ++i
) {
177 if (cpuid
->entries
[i
].function
== function
&&
178 cpuid
->entries
[i
].index
== index
) {
179 return &cpuid
->entries
[i
];
186 uint32_t kvm_arch_get_supported_cpuid(KVMState
*s
, uint32_t function
,
187 uint32_t index
, int reg
)
189 struct kvm_cpuid2
*cpuid
;
191 uint32_t cpuid_1_edx
;
194 cpuid
= get_supported_cpuid(s
);
196 struct kvm_cpuid_entry2
*entry
= cpuid_find_entry(cpuid
, function
, index
);
199 ret
= cpuid_entry_get_reg(entry
, reg
);
202 /* Fixups for the data returned by KVM, below */
204 if (function
== 1 && reg
== R_EDX
) {
205 /* KVM before 2.6.30 misreports the following features */
206 ret
|= CPUID_MTRR
| CPUID_PAT
| CPUID_MCE
| CPUID_MCA
;
207 } else if (function
== 1 && reg
== R_ECX
) {
208 /* We can set the hypervisor flag, even if KVM does not return it on
209 * GET_SUPPORTED_CPUID
211 ret
|= CPUID_EXT_HYPERVISOR
;
212 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
213 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
214 * and the irqchip is in the kernel.
216 if (kvm_irqchip_in_kernel() &&
217 kvm_check_extension(s
, KVM_CAP_TSC_DEADLINE_TIMER
)) {
218 ret
|= CPUID_EXT_TSC_DEADLINE_TIMER
;
221 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
222 * without the in-kernel irqchip
224 if (!kvm_irqchip_in_kernel()) {
225 ret
&= ~CPUID_EXT_X2APIC
;
227 } else if (function
== 0x80000001 && reg
== R_EDX
) {
228 /* On Intel, kvm returns cpuid according to the Intel spec,
229 * so add missing bits according to the AMD spec:
231 cpuid_1_edx
= kvm_arch_get_supported_cpuid(s
, 1, 0, R_EDX
);
232 ret
|= cpuid_1_edx
& CPUID_EXT2_AMD_ALIASES
;
237 /* fallback for older kernels */
238 if ((function
== KVM_CPUID_FEATURES
) && !found
) {
239 ret
= get_para_features(s
);
245 typedef struct HWPoisonPage
{
247 QLIST_ENTRY(HWPoisonPage
) list
;
250 static QLIST_HEAD(, HWPoisonPage
) hwpoison_page_list
=
251 QLIST_HEAD_INITIALIZER(hwpoison_page_list
);
253 static void kvm_unpoison_all(void *param
)
255 HWPoisonPage
*page
, *next_page
;
257 QLIST_FOREACH_SAFE(page
, &hwpoison_page_list
, list
, next_page
) {
258 QLIST_REMOVE(page
, list
);
259 qemu_ram_remap(page
->ram_addr
, TARGET_PAGE_SIZE
);
264 static void kvm_hwpoison_page_add(ram_addr_t ram_addr
)
268 QLIST_FOREACH(page
, &hwpoison_page_list
, list
) {
269 if (page
->ram_addr
== ram_addr
) {
273 page
= g_malloc(sizeof(HWPoisonPage
));
274 page
->ram_addr
= ram_addr
;
275 QLIST_INSERT_HEAD(&hwpoison_page_list
, page
, list
);
278 static int kvm_get_mce_cap_supported(KVMState
*s
, uint64_t *mce_cap
,
283 r
= kvm_check_extension(s
, KVM_CAP_MCE
);
286 return kvm_ioctl(s
, KVM_X86_GET_MCE_CAP_SUPPORTED
, mce_cap
);
291 static void kvm_mce_inject(X86CPU
*cpu
, hwaddr paddr
, int code
)
293 CPUX86State
*env
= &cpu
->env
;
294 uint64_t status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
|
295 MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
;
296 uint64_t mcg_status
= MCG_STATUS_MCIP
;
298 if (code
== BUS_MCEERR_AR
) {
299 status
|= MCI_STATUS_AR
| 0x134;
300 mcg_status
|= MCG_STATUS_EIPV
;
303 mcg_status
|= MCG_STATUS_RIPV
;
305 cpu_x86_inject_mce(NULL
, cpu
, 9, status
, mcg_status
, paddr
,
306 (MCM_ADDR_PHYS
<< 6) | 0xc,
307 cpu_x86_support_mca_broadcast(env
) ?
308 MCE_INJECT_BROADCAST
: 0);
311 static void hardware_memory_error(void)
313 fprintf(stderr
, "Hardware memory error!\n");
317 int kvm_arch_on_sigbus_vcpu(CPUState
*c
, int code
, void *addr
)
319 X86CPU
*cpu
= X86_CPU(c
);
320 CPUX86State
*env
= &cpu
->env
;
324 if ((env
->mcg_cap
& MCG_SER_P
) && addr
325 && (code
== BUS_MCEERR_AR
|| code
== BUS_MCEERR_AO
)) {
326 if (qemu_ram_addr_from_host(addr
, &ram_addr
) == NULL
||
327 !kvm_physical_memory_addr_from_host(c
->kvm_state
, addr
, &paddr
)) {
328 fprintf(stderr
, "Hardware memory error for memory used by "
329 "QEMU itself instead of guest system!\n");
330 /* Hope we are lucky for AO MCE */
331 if (code
== BUS_MCEERR_AO
) {
334 hardware_memory_error();
337 kvm_hwpoison_page_add(ram_addr
);
338 kvm_mce_inject(cpu
, paddr
, code
);
340 if (code
== BUS_MCEERR_AO
) {
342 } else if (code
== BUS_MCEERR_AR
) {
343 hardware_memory_error();
351 int kvm_arch_on_sigbus(int code
, void *addr
)
353 X86CPU
*cpu
= X86_CPU(first_cpu
);
355 if ((cpu
->env
.mcg_cap
& MCG_SER_P
) && addr
&& code
== BUS_MCEERR_AO
) {
359 /* Hope we are lucky for AO MCE */
360 if (qemu_ram_addr_from_host(addr
, &ram_addr
) == NULL
||
361 !kvm_physical_memory_addr_from_host(first_cpu
->kvm_state
,
363 fprintf(stderr
, "Hardware memory error for memory used by "
364 "QEMU itself instead of guest system!: %p\n", addr
);
367 kvm_hwpoison_page_add(ram_addr
);
368 kvm_mce_inject(X86_CPU(first_cpu
), paddr
, code
);
370 if (code
== BUS_MCEERR_AO
) {
372 } else if (code
== BUS_MCEERR_AR
) {
373 hardware_memory_error();
381 static int kvm_inject_mce_oldstyle(X86CPU
*cpu
)
383 CPUX86State
*env
= &cpu
->env
;
385 if (!kvm_has_vcpu_events() && env
->exception_injected
== EXCP12_MCHK
) {
386 unsigned int bank
, bank_num
= env
->mcg_cap
& 0xff;
387 struct kvm_x86_mce mce
;
389 env
->exception_injected
= -1;
392 * There must be at least one bank in use if an MCE is pending.
393 * Find it and use its values for the event injection.
395 for (bank
= 0; bank
< bank_num
; bank
++) {
396 if (env
->mce_banks
[bank
* 4 + 1] & MCI_STATUS_VAL
) {
400 assert(bank
< bank_num
);
403 mce
.status
= env
->mce_banks
[bank
* 4 + 1];
404 mce
.mcg_status
= env
->mcg_status
;
405 mce
.addr
= env
->mce_banks
[bank
* 4 + 2];
406 mce
.misc
= env
->mce_banks
[bank
* 4 + 3];
408 return kvm_vcpu_ioctl(CPU(cpu
), KVM_X86_SET_MCE
, &mce
);
413 static void cpu_update_state(void *opaque
, int running
, RunState state
)
415 CPUX86State
*env
= opaque
;
418 env
->tsc_valid
= false;
422 unsigned long kvm_arch_vcpu_id(CPUState
*cs
)
424 X86CPU
*cpu
= X86_CPU(cs
);
425 return cpu
->env
.cpuid_apic_id
;
428 #ifndef KVM_CPUID_SIGNATURE_NEXT
429 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
432 static bool hyperv_hypercall_available(X86CPU
*cpu
)
434 return cpu
->hyperv_vapic
||
435 (cpu
->hyperv_spinlock_attempts
!= HYPERV_SPINLOCK_NEVER_RETRY
);
438 static bool hyperv_enabled(X86CPU
*cpu
)
440 return hyperv_hypercall_available(cpu
) ||
441 cpu
->hyperv_relaxed_timing
;
444 #define KVM_MAX_CPUID_ENTRIES 100
446 int kvm_arch_init_vcpu(CPUState
*cs
)
449 struct kvm_cpuid2 cpuid
;
450 struct kvm_cpuid_entry2 entries
[KVM_MAX_CPUID_ENTRIES
];
451 } QEMU_PACKED cpuid_data
;
452 X86CPU
*cpu
= X86_CPU(cs
);
453 CPUX86State
*env
= &cpu
->env
;
454 uint32_t limit
, i
, j
, cpuid_i
;
456 struct kvm_cpuid_entry2
*c
;
457 uint32_t signature
[3];
460 memset(&cpuid_data
, 0, sizeof(cpuid_data
));
464 /* Paravirtualization CPUIDs */
465 c
= &cpuid_data
.entries
[cpuid_i
++];
466 c
->function
= KVM_CPUID_SIGNATURE
;
467 if (!hyperv_enabled(cpu
)) {
468 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
471 memcpy(signature
, "Microsoft Hv", 12);
472 c
->eax
= HYPERV_CPUID_MIN
;
474 c
->ebx
= signature
[0];
475 c
->ecx
= signature
[1];
476 c
->edx
= signature
[2];
478 c
= &cpuid_data
.entries
[cpuid_i
++];
479 c
->function
= KVM_CPUID_FEATURES
;
480 c
->eax
= env
->features
[FEAT_KVM
];
482 if (hyperv_enabled(cpu
)) {
483 memcpy(signature
, "Hv#1\0\0\0\0\0\0\0\0", 12);
484 c
->eax
= signature
[0];
486 c
= &cpuid_data
.entries
[cpuid_i
++];
487 c
->function
= HYPERV_CPUID_VERSION
;
491 c
= &cpuid_data
.entries
[cpuid_i
++];
492 c
->function
= HYPERV_CPUID_FEATURES
;
493 if (cpu
->hyperv_relaxed_timing
) {
494 c
->eax
|= HV_X64_MSR_HYPERCALL_AVAILABLE
;
496 if (cpu
->hyperv_vapic
) {
497 c
->eax
|= HV_X64_MSR_HYPERCALL_AVAILABLE
;
498 c
->eax
|= HV_X64_MSR_APIC_ACCESS_AVAILABLE
;
501 c
= &cpuid_data
.entries
[cpuid_i
++];
502 c
->function
= HYPERV_CPUID_ENLIGHTMENT_INFO
;
503 if (cpu
->hyperv_relaxed_timing
) {
504 c
->eax
|= HV_X64_RELAXED_TIMING_RECOMMENDED
;
506 if (cpu
->hyperv_vapic
) {
507 c
->eax
|= HV_X64_APIC_ACCESS_RECOMMENDED
;
509 c
->ebx
= cpu
->hyperv_spinlock_attempts
;
511 c
= &cpuid_data
.entries
[cpuid_i
++];
512 c
->function
= HYPERV_CPUID_IMPLEMENT_LIMITS
;
516 c
= &cpuid_data
.entries
[cpuid_i
++];
517 c
->function
= KVM_CPUID_SIGNATURE_NEXT
;
518 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
520 c
->ebx
= signature
[0];
521 c
->ecx
= signature
[1];
522 c
->edx
= signature
[2];
525 has_msr_async_pf_en
= c
->eax
& (1 << KVM_FEATURE_ASYNC_PF
);
527 has_msr_pv_eoi_en
= c
->eax
& (1 << KVM_FEATURE_PV_EOI
);
529 has_msr_kvm_steal_time
= c
->eax
& (1 << KVM_FEATURE_STEAL_TIME
);
531 cpu_x86_cpuid(env
, 0, 0, &limit
, &unused
, &unused
, &unused
);
533 for (i
= 0; i
<= limit
; i
++) {
534 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
535 fprintf(stderr
, "unsupported level value: 0x%x\n", limit
);
538 c
= &cpuid_data
.entries
[cpuid_i
++];
542 /* Keep reading function 2 till all the input is received */
546 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
|
547 KVM_CPUID_FLAG_STATE_READ_NEXT
;
548 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
549 times
= c
->eax
& 0xff;
551 for (j
= 1; j
< times
; ++j
) {
552 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
553 fprintf(stderr
, "cpuid_data is full, no space for "
554 "cpuid(eax:2):eax & 0xf = 0x%x\n", times
);
557 c
= &cpuid_data
.entries
[cpuid_i
++];
559 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
;
560 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
568 if (i
== 0xd && j
== 64) {
572 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
574 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
576 if (i
== 4 && c
->eax
== 0) {
579 if (i
== 0xb && !(c
->ecx
& 0xff00)) {
582 if (i
== 0xd && c
->eax
== 0) {
585 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
586 fprintf(stderr
, "cpuid_data is full, no space for "
587 "cpuid(eax:0x%x,ecx:0x%x)\n", i
, j
);
590 c
= &cpuid_data
.entries
[cpuid_i
++];
596 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
604 cpu_x86_cpuid(env
, 0x0a, 0, &ver
, &unused
, &unused
, &unused
);
605 if ((ver
& 0xff) > 0) {
606 has_msr_architectural_pmu
= true;
607 num_architectural_pmu_counters
= (ver
& 0xff00) >> 8;
609 /* Shouldn't be more than 32, since that's the number of bits
610 * available in EBX to tell us _which_ counters are available.
613 if (num_architectural_pmu_counters
> MAX_GP_COUNTERS
) {
614 num_architectural_pmu_counters
= MAX_GP_COUNTERS
;
619 cpu_x86_cpuid(env
, 0x80000000, 0, &limit
, &unused
, &unused
, &unused
);
621 for (i
= 0x80000000; i
<= limit
; i
++) {
622 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
623 fprintf(stderr
, "unsupported xlevel value: 0x%x\n", limit
);
626 c
= &cpuid_data
.entries
[cpuid_i
++];
630 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
633 /* Call Centaur's CPUID instructions they are supported. */
634 if (env
->cpuid_xlevel2
> 0) {
635 cpu_x86_cpuid(env
, 0xC0000000, 0, &limit
, &unused
, &unused
, &unused
);
637 for (i
= 0xC0000000; i
<= limit
; i
++) {
638 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
639 fprintf(stderr
, "unsupported xlevel2 value: 0x%x\n", limit
);
642 c
= &cpuid_data
.entries
[cpuid_i
++];
646 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
650 cpuid_data
.cpuid
.nent
= cpuid_i
;
652 if (((env
->cpuid_version
>> 8)&0xF) >= 6
653 && (env
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
654 (CPUID_MCE
| CPUID_MCA
)
655 && kvm_check_extension(cs
->kvm_state
, KVM_CAP_MCE
) > 0) {
660 ret
= kvm_get_mce_cap_supported(cs
->kvm_state
, &mcg_cap
, &banks
);
662 fprintf(stderr
, "kvm_get_mce_cap_supported: %s", strerror(-ret
));
666 if (banks
> MCE_BANKS_DEF
) {
667 banks
= MCE_BANKS_DEF
;
669 mcg_cap
&= MCE_CAP_DEF
;
671 ret
= kvm_vcpu_ioctl(cs
, KVM_X86_SETUP_MCE
, &mcg_cap
);
673 fprintf(stderr
, "KVM_X86_SETUP_MCE: %s", strerror(-ret
));
677 env
->mcg_cap
= mcg_cap
;
680 qemu_add_vm_change_state_handler(cpu_update_state
, env
);
682 c
= cpuid_find_entry(&cpuid_data
.cpuid
, 1, 0);
684 has_msr_feature_control
= !!(c
->ecx
& CPUID_EXT_VMX
) ||
685 !!(c
->ecx
& CPUID_EXT_SMX
);
688 cpuid_data
.cpuid
.padding
= 0;
689 r
= kvm_vcpu_ioctl(cs
, KVM_SET_CPUID2
, &cpuid_data
);
694 r
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_TSC_CONTROL
);
695 if (r
&& env
->tsc_khz
) {
696 r
= kvm_vcpu_ioctl(cs
, KVM_SET_TSC_KHZ
, env
->tsc_khz
);
698 fprintf(stderr
, "KVM_SET_TSC_KHZ failed\n");
703 if (kvm_has_xsave()) {
704 env
->kvm_xsave_buf
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
710 void kvm_arch_reset_vcpu(CPUState
*cs
)
712 X86CPU
*cpu
= X86_CPU(cs
);
713 CPUX86State
*env
= &cpu
->env
;
715 env
->exception_injected
= -1;
716 env
->interrupt_injected
= -1;
718 if (kvm_irqchip_in_kernel()) {
719 env
->mp_state
= cpu_is_bsp(cpu
) ? KVM_MP_STATE_RUNNABLE
:
720 KVM_MP_STATE_UNINITIALIZED
;
722 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
726 static int kvm_get_supported_msrs(KVMState
*s
)
728 static int kvm_supported_msrs
;
732 if (kvm_supported_msrs
== 0) {
733 struct kvm_msr_list msr_list
, *kvm_msr_list
;
735 kvm_supported_msrs
= -1;
737 /* Obtain MSR list from KVM. These are the MSRs that we must
740 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, &msr_list
);
741 if (ret
< 0 && ret
!= -E2BIG
) {
744 /* Old kernel modules had a bug and could write beyond the provided
745 memory. Allocate at least a safe amount of 1K. */
746 kvm_msr_list
= g_malloc0(MAX(1024, sizeof(msr_list
) +
748 sizeof(msr_list
.indices
[0])));
750 kvm_msr_list
->nmsrs
= msr_list
.nmsrs
;
751 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, kvm_msr_list
);
755 for (i
= 0; i
< kvm_msr_list
->nmsrs
; i
++) {
756 if (kvm_msr_list
->indices
[i
] == MSR_STAR
) {
760 if (kvm_msr_list
->indices
[i
] == MSR_VM_HSAVE_PA
) {
761 has_msr_hsave_pa
= true;
764 if (kvm_msr_list
->indices
[i
] == MSR_TSC_ADJUST
) {
765 has_msr_tsc_adjust
= true;
768 if (kvm_msr_list
->indices
[i
] == MSR_IA32_TSCDEADLINE
) {
769 has_msr_tsc_deadline
= true;
772 if (kvm_msr_list
->indices
[i
] == MSR_IA32_MISC_ENABLE
) {
773 has_msr_misc_enable
= true;
776 if (kvm_msr_list
->indices
[i
] == MSR_IA32_BNDCFGS
) {
777 has_msr_bndcfgs
= true;
783 g_free(kvm_msr_list
);
789 int kvm_arch_init(KVMState
*s
)
791 uint64_t identity_base
= 0xfffbc000;
794 struct utsname utsname
;
796 ret
= kvm_get_supported_msrs(s
);
802 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
805 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
806 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
807 * Since these must be part of guest physical memory, we need to allocate
808 * them, both by setting their start addresses in the kernel and by
809 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
811 * Older KVM versions may not support setting the identity map base. In
812 * that case we need to stick with the default, i.e. a 256K maximum BIOS
815 if (kvm_check_extension(s
, KVM_CAP_SET_IDENTITY_MAP_ADDR
)) {
816 /* Allows up to 16M BIOSes. */
817 identity_base
= 0xfeffc000;
819 ret
= kvm_vm_ioctl(s
, KVM_SET_IDENTITY_MAP_ADDR
, &identity_base
);
825 /* Set TSS base one page after EPT identity map. */
826 ret
= kvm_vm_ioctl(s
, KVM_SET_TSS_ADDR
, identity_base
+ 0x1000);
831 /* Tell fw_cfg to notify the BIOS to reserve the range. */
832 ret
= e820_add_entry(identity_base
, 0x4000, E820_RESERVED
);
834 fprintf(stderr
, "e820_add_entry() table is full\n");
837 qemu_register_reset(kvm_unpoison_all
, NULL
);
839 shadow_mem
= qemu_opt_get_size(qemu_get_machine_opts(),
840 "kvm_shadow_mem", -1);
841 if (shadow_mem
!= -1) {
843 ret
= kvm_vm_ioctl(s
, KVM_SET_NR_MMU_PAGES
, shadow_mem
);
851 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
853 lhs
->selector
= rhs
->selector
;
854 lhs
->base
= rhs
->base
;
855 lhs
->limit
= rhs
->limit
;
867 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
869 unsigned flags
= rhs
->flags
;
870 lhs
->selector
= rhs
->selector
;
871 lhs
->base
= rhs
->base
;
872 lhs
->limit
= rhs
->limit
;
873 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
874 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
875 lhs
->dpl
= (flags
>> DESC_DPL_SHIFT
) & 3;
876 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
877 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
878 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
879 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
880 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
885 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
887 lhs
->selector
= rhs
->selector
;
888 lhs
->base
= rhs
->base
;
889 lhs
->limit
= rhs
->limit
;
890 lhs
->flags
= (rhs
->type
<< DESC_TYPE_SHIFT
) |
891 (rhs
->present
* DESC_P_MASK
) |
892 (rhs
->dpl
<< DESC_DPL_SHIFT
) |
893 (rhs
->db
<< DESC_B_SHIFT
) |
894 (rhs
->s
* DESC_S_MASK
) |
895 (rhs
->l
<< DESC_L_SHIFT
) |
896 (rhs
->g
* DESC_G_MASK
) |
897 (rhs
->avl
* DESC_AVL_MASK
);
900 static void kvm_getput_reg(__u64
*kvm_reg
, target_ulong
*qemu_reg
, int set
)
903 *kvm_reg
= *qemu_reg
;
905 *qemu_reg
= *kvm_reg
;
909 static int kvm_getput_regs(X86CPU
*cpu
, int set
)
911 CPUX86State
*env
= &cpu
->env
;
912 struct kvm_regs regs
;
916 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_REGS
, ®s
);
922 kvm_getput_reg(®s
.rax
, &env
->regs
[R_EAX
], set
);
923 kvm_getput_reg(®s
.rbx
, &env
->regs
[R_EBX
], set
);
924 kvm_getput_reg(®s
.rcx
, &env
->regs
[R_ECX
], set
);
925 kvm_getput_reg(®s
.rdx
, &env
->regs
[R_EDX
], set
);
926 kvm_getput_reg(®s
.rsi
, &env
->regs
[R_ESI
], set
);
927 kvm_getput_reg(®s
.rdi
, &env
->regs
[R_EDI
], set
);
928 kvm_getput_reg(®s
.rsp
, &env
->regs
[R_ESP
], set
);
929 kvm_getput_reg(®s
.rbp
, &env
->regs
[R_EBP
], set
);
931 kvm_getput_reg(®s
.r8
, &env
->regs
[8], set
);
932 kvm_getput_reg(®s
.r9
, &env
->regs
[9], set
);
933 kvm_getput_reg(®s
.r10
, &env
->regs
[10], set
);
934 kvm_getput_reg(®s
.r11
, &env
->regs
[11], set
);
935 kvm_getput_reg(®s
.r12
, &env
->regs
[12], set
);
936 kvm_getput_reg(®s
.r13
, &env
->regs
[13], set
);
937 kvm_getput_reg(®s
.r14
, &env
->regs
[14], set
);
938 kvm_getput_reg(®s
.r15
, &env
->regs
[15], set
);
941 kvm_getput_reg(®s
.rflags
, &env
->eflags
, set
);
942 kvm_getput_reg(®s
.rip
, &env
->eip
, set
);
945 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_REGS
, ®s
);
951 static int kvm_put_fpu(X86CPU
*cpu
)
953 CPUX86State
*env
= &cpu
->env
;
957 memset(&fpu
, 0, sizeof fpu
);
958 fpu
.fsw
= env
->fpus
& ~(7 << 11);
959 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
961 fpu
.last_opcode
= env
->fpop
;
962 fpu
.last_ip
= env
->fpip
;
963 fpu
.last_dp
= env
->fpdp
;
964 for (i
= 0; i
< 8; ++i
) {
965 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
967 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
968 memcpy(fpu
.xmm
, env
->xmm_regs
, sizeof env
->xmm_regs
);
969 fpu
.mxcsr
= env
->mxcsr
;
971 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_FPU
, &fpu
);
974 #define XSAVE_FCW_FSW 0
975 #define XSAVE_FTW_FOP 1
976 #define XSAVE_CWD_RIP 2
977 #define XSAVE_CWD_RDP 4
978 #define XSAVE_MXCSR 6
979 #define XSAVE_ST_SPACE 8
980 #define XSAVE_XMM_SPACE 40
981 #define XSAVE_XSTATE_BV 128
982 #define XSAVE_YMMH_SPACE 144
983 #define XSAVE_BNDREGS 240
984 #define XSAVE_BNDCSR 256
986 static int kvm_put_xsave(X86CPU
*cpu
)
988 CPUX86State
*env
= &cpu
->env
;
989 struct kvm_xsave
* xsave
= env
->kvm_xsave_buf
;
990 uint16_t cwd
, swd
, twd
;
993 if (!kvm_has_xsave()) {
994 return kvm_put_fpu(cpu
);
997 memset(xsave
, 0, sizeof(struct kvm_xsave
));
999 swd
= env
->fpus
& ~(7 << 11);
1000 swd
|= (env
->fpstt
& 7) << 11;
1002 for (i
= 0; i
< 8; ++i
) {
1003 twd
|= (!env
->fptags
[i
]) << i
;
1005 xsave
->region
[XSAVE_FCW_FSW
] = (uint32_t)(swd
<< 16) + cwd
;
1006 xsave
->region
[XSAVE_FTW_FOP
] = (uint32_t)(env
->fpop
<< 16) + twd
;
1007 memcpy(&xsave
->region
[XSAVE_CWD_RIP
], &env
->fpip
, sizeof(env
->fpip
));
1008 memcpy(&xsave
->region
[XSAVE_CWD_RDP
], &env
->fpdp
, sizeof(env
->fpdp
));
1009 memcpy(&xsave
->region
[XSAVE_ST_SPACE
], env
->fpregs
,
1010 sizeof env
->fpregs
);
1011 memcpy(&xsave
->region
[XSAVE_XMM_SPACE
], env
->xmm_regs
,
1012 sizeof env
->xmm_regs
);
1013 xsave
->region
[XSAVE_MXCSR
] = env
->mxcsr
;
1014 *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
] = env
->xstate_bv
;
1015 memcpy(&xsave
->region
[XSAVE_YMMH_SPACE
], env
->ymmh_regs
,
1016 sizeof env
->ymmh_regs
);
1017 memcpy(&xsave
->region
[XSAVE_BNDREGS
], env
->bnd_regs
,
1018 sizeof env
->bnd_regs
);
1019 memcpy(&xsave
->region
[XSAVE_BNDCSR
], &env
->bndcs_regs
,
1020 sizeof(env
->bndcs_regs
));
1021 r
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XSAVE
, xsave
);
1025 static int kvm_put_xcrs(X86CPU
*cpu
)
1027 CPUX86State
*env
= &cpu
->env
;
1028 struct kvm_xcrs xcrs
;
1030 if (!kvm_has_xcrs()) {
1036 xcrs
.xcrs
[0].xcr
= 0;
1037 xcrs
.xcrs
[0].value
= env
->xcr0
;
1038 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XCRS
, &xcrs
);
1041 static int kvm_put_sregs(X86CPU
*cpu
)
1043 CPUX86State
*env
= &cpu
->env
;
1044 struct kvm_sregs sregs
;
1046 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
1047 if (env
->interrupt_injected
>= 0) {
1048 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
1049 (uint64_t)1 << (env
->interrupt_injected
% 64);
1052 if ((env
->eflags
& VM_MASK
)) {
1053 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
1054 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
1055 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
1056 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
1057 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
1058 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
1060 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
1061 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
1062 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
1063 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
1064 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
1065 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
1068 set_seg(&sregs
.tr
, &env
->tr
);
1069 set_seg(&sregs
.ldt
, &env
->ldt
);
1071 sregs
.idt
.limit
= env
->idt
.limit
;
1072 sregs
.idt
.base
= env
->idt
.base
;
1073 memset(sregs
.idt
.padding
, 0, sizeof sregs
.idt
.padding
);
1074 sregs
.gdt
.limit
= env
->gdt
.limit
;
1075 sregs
.gdt
.base
= env
->gdt
.base
;
1076 memset(sregs
.gdt
.padding
, 0, sizeof sregs
.gdt
.padding
);
1078 sregs
.cr0
= env
->cr
[0];
1079 sregs
.cr2
= env
->cr
[2];
1080 sregs
.cr3
= env
->cr
[3];
1081 sregs
.cr4
= env
->cr
[4];
1083 sregs
.cr8
= cpu_get_apic_tpr(env
->apic_state
);
1084 sregs
.apic_base
= cpu_get_apic_base(env
->apic_state
);
1086 sregs
.efer
= env
->efer
;
1088 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_SREGS
, &sregs
);
1091 static void kvm_msr_entry_set(struct kvm_msr_entry
*entry
,
1092 uint32_t index
, uint64_t value
)
1094 entry
->index
= index
;
1095 entry
->data
= value
;
1098 static int kvm_put_tscdeadline_msr(X86CPU
*cpu
)
1100 CPUX86State
*env
= &cpu
->env
;
1102 struct kvm_msrs info
;
1103 struct kvm_msr_entry entries
[1];
1105 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
1107 if (!has_msr_tsc_deadline
) {
1111 kvm_msr_entry_set(&msrs
[0], MSR_IA32_TSCDEADLINE
, env
->tsc_deadline
);
1113 msr_data
.info
.nmsrs
= 1;
1115 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, &msr_data
);
1119 * Provide a separate write service for the feature control MSR in order to
1120 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1121 * before writing any other state because forcibly leaving nested mode
1122 * invalidates the VCPU state.
1124 static int kvm_put_msr_feature_control(X86CPU
*cpu
)
1127 struct kvm_msrs info
;
1128 struct kvm_msr_entry entry
;
1131 kvm_msr_entry_set(&msr_data
.entry
, MSR_IA32_FEATURE_CONTROL
,
1132 cpu
->env
.msr_ia32_feature_control
);
1133 msr_data
.info
.nmsrs
= 1;
1134 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, &msr_data
);
1137 static int kvm_put_msrs(X86CPU
*cpu
, int level
)
1139 CPUX86State
*env
= &cpu
->env
;
1141 struct kvm_msrs info
;
1142 struct kvm_msr_entry entries
[100];
1144 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
1147 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
1148 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
1149 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
1150 kvm_msr_entry_set(&msrs
[n
++], MSR_PAT
, env
->pat
);
1152 kvm_msr_entry_set(&msrs
[n
++], MSR_STAR
, env
->star
);
1154 if (has_msr_hsave_pa
) {
1155 kvm_msr_entry_set(&msrs
[n
++], MSR_VM_HSAVE_PA
, env
->vm_hsave
);
1157 if (has_msr_tsc_adjust
) {
1158 kvm_msr_entry_set(&msrs
[n
++], MSR_TSC_ADJUST
, env
->tsc_adjust
);
1160 if (has_msr_misc_enable
) {
1161 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_MISC_ENABLE
,
1162 env
->msr_ia32_misc_enable
);
1164 #ifdef TARGET_X86_64
1165 if (lm_capable_kernel
) {
1166 kvm_msr_entry_set(&msrs
[n
++], MSR_CSTAR
, env
->cstar
);
1167 kvm_msr_entry_set(&msrs
[n
++], MSR_KERNELGSBASE
, env
->kernelgsbase
);
1168 kvm_msr_entry_set(&msrs
[n
++], MSR_FMASK
, env
->fmask
);
1169 kvm_msr_entry_set(&msrs
[n
++], MSR_LSTAR
, env
->lstar
);
1173 * The following MSRs have side effects on the guest or are too heavy
1174 * for normal writeback. Limit them to reset or full state updates.
1176 if (level
>= KVM_PUT_RESET_STATE
) {
1177 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_TSC
, env
->tsc
);
1178 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_SYSTEM_TIME
,
1179 env
->system_time_msr
);
1180 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
1181 if (has_msr_async_pf_en
) {
1182 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_ASYNC_PF_EN
,
1183 env
->async_pf_en_msr
);
1185 if (has_msr_pv_eoi_en
) {
1186 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_PV_EOI_EN
,
1187 env
->pv_eoi_en_msr
);
1189 if (has_msr_kvm_steal_time
) {
1190 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_STEAL_TIME
,
1191 env
->steal_time_msr
);
1193 if (has_msr_architectural_pmu
) {
1194 /* Stop the counter. */
1195 kvm_msr_entry_set(&msrs
[n
++], MSR_CORE_PERF_FIXED_CTR_CTRL
, 0);
1196 kvm_msr_entry_set(&msrs
[n
++], MSR_CORE_PERF_GLOBAL_CTRL
, 0);
1198 /* Set the counter values. */
1199 for (i
= 0; i
< MAX_FIXED_COUNTERS
; i
++) {
1200 kvm_msr_entry_set(&msrs
[n
++], MSR_CORE_PERF_FIXED_CTR0
+ i
,
1201 env
->msr_fixed_counters
[i
]);
1203 for (i
= 0; i
< num_architectural_pmu_counters
; i
++) {
1204 kvm_msr_entry_set(&msrs
[n
++], MSR_P6_PERFCTR0
+ i
,
1205 env
->msr_gp_counters
[i
]);
1206 kvm_msr_entry_set(&msrs
[n
++], MSR_P6_EVNTSEL0
+ i
,
1207 env
->msr_gp_evtsel
[i
]);
1209 kvm_msr_entry_set(&msrs
[n
++], MSR_CORE_PERF_GLOBAL_STATUS
,
1210 env
->msr_global_status
);
1211 kvm_msr_entry_set(&msrs
[n
++], MSR_CORE_PERF_GLOBAL_OVF_CTRL
,
1212 env
->msr_global_ovf_ctrl
);
1214 /* Now start the PMU. */
1215 kvm_msr_entry_set(&msrs
[n
++], MSR_CORE_PERF_FIXED_CTR_CTRL
,
1216 env
->msr_fixed_ctr_ctrl
);
1217 kvm_msr_entry_set(&msrs
[n
++], MSR_CORE_PERF_GLOBAL_CTRL
,
1218 env
->msr_global_ctrl
);
1220 if (hyperv_hypercall_available(cpu
)) {
1221 kvm_msr_entry_set(&msrs
[n
++], HV_X64_MSR_GUEST_OS_ID
, 0);
1222 kvm_msr_entry_set(&msrs
[n
++], HV_X64_MSR_HYPERCALL
, 0);
1224 if (cpu
->hyperv_vapic
) {
1225 kvm_msr_entry_set(&msrs
[n
++], HV_X64_MSR_APIC_ASSIST_PAGE
, 0);
1227 if (has_msr_bndcfgs
) {
1228 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_BNDCFGS
, env
->msr_bndcfgs
);
1231 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1232 * kvm_put_msr_feature_control. */
1237 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_STATUS
, env
->mcg_status
);
1238 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_CTL
, env
->mcg_ctl
);
1239 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
1240 kvm_msr_entry_set(&msrs
[n
++], MSR_MC0_CTL
+ i
, env
->mce_banks
[i
]);
1244 msr_data
.info
.nmsrs
= n
;
1246 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, &msr_data
);
1251 static int kvm_get_fpu(X86CPU
*cpu
)
1253 CPUX86State
*env
= &cpu
->env
;
1257 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_FPU
, &fpu
);
1262 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
1263 env
->fpus
= fpu
.fsw
;
1264 env
->fpuc
= fpu
.fcw
;
1265 env
->fpop
= fpu
.last_opcode
;
1266 env
->fpip
= fpu
.last_ip
;
1267 env
->fpdp
= fpu
.last_dp
;
1268 for (i
= 0; i
< 8; ++i
) {
1269 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
1271 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
1272 memcpy(env
->xmm_regs
, fpu
.xmm
, sizeof env
->xmm_regs
);
1273 env
->mxcsr
= fpu
.mxcsr
;
1278 static int kvm_get_xsave(X86CPU
*cpu
)
1280 CPUX86State
*env
= &cpu
->env
;
1281 struct kvm_xsave
* xsave
= env
->kvm_xsave_buf
;
1283 uint16_t cwd
, swd
, twd
;
1285 if (!kvm_has_xsave()) {
1286 return kvm_get_fpu(cpu
);
1289 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XSAVE
, xsave
);
1294 cwd
= (uint16_t)xsave
->region
[XSAVE_FCW_FSW
];
1295 swd
= (uint16_t)(xsave
->region
[XSAVE_FCW_FSW
] >> 16);
1296 twd
= (uint16_t)xsave
->region
[XSAVE_FTW_FOP
];
1297 env
->fpop
= (uint16_t)(xsave
->region
[XSAVE_FTW_FOP
] >> 16);
1298 env
->fpstt
= (swd
>> 11) & 7;
1301 for (i
= 0; i
< 8; ++i
) {
1302 env
->fptags
[i
] = !((twd
>> i
) & 1);
1304 memcpy(&env
->fpip
, &xsave
->region
[XSAVE_CWD_RIP
], sizeof(env
->fpip
));
1305 memcpy(&env
->fpdp
, &xsave
->region
[XSAVE_CWD_RDP
], sizeof(env
->fpdp
));
1306 env
->mxcsr
= xsave
->region
[XSAVE_MXCSR
];
1307 memcpy(env
->fpregs
, &xsave
->region
[XSAVE_ST_SPACE
],
1308 sizeof env
->fpregs
);
1309 memcpy(env
->xmm_regs
, &xsave
->region
[XSAVE_XMM_SPACE
],
1310 sizeof env
->xmm_regs
);
1311 env
->xstate_bv
= *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
];
1312 memcpy(env
->ymmh_regs
, &xsave
->region
[XSAVE_YMMH_SPACE
],
1313 sizeof env
->ymmh_regs
);
1314 memcpy(env
->bnd_regs
, &xsave
->region
[XSAVE_BNDREGS
],
1315 sizeof env
->bnd_regs
);
1316 memcpy(&env
->bndcs_regs
, &xsave
->region
[XSAVE_BNDCSR
],
1317 sizeof(env
->bndcs_regs
));
1321 static int kvm_get_xcrs(X86CPU
*cpu
)
1323 CPUX86State
*env
= &cpu
->env
;
1325 struct kvm_xcrs xcrs
;
1327 if (!kvm_has_xcrs()) {
1331 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XCRS
, &xcrs
);
1336 for (i
= 0; i
< xcrs
.nr_xcrs
; i
++) {
1337 /* Only support xcr0 now */
1338 if (xcrs
.xcrs
[i
].xcr
== 0) {
1339 env
->xcr0
= xcrs
.xcrs
[i
].value
;
1346 static int kvm_get_sregs(X86CPU
*cpu
)
1348 CPUX86State
*env
= &cpu
->env
;
1349 struct kvm_sregs sregs
;
1353 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_SREGS
, &sregs
);
1358 /* There can only be one pending IRQ set in the bitmap at a time, so try
1359 to find it and save its number instead (-1 for none). */
1360 env
->interrupt_injected
= -1;
1361 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
1362 if (sregs
.interrupt_bitmap
[i
]) {
1363 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
1364 env
->interrupt_injected
= i
* 64 + bit
;
1369 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
1370 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
1371 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
1372 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
1373 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
1374 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
1376 get_seg(&env
->tr
, &sregs
.tr
);
1377 get_seg(&env
->ldt
, &sregs
.ldt
);
1379 env
->idt
.limit
= sregs
.idt
.limit
;
1380 env
->idt
.base
= sregs
.idt
.base
;
1381 env
->gdt
.limit
= sregs
.gdt
.limit
;
1382 env
->gdt
.base
= sregs
.gdt
.base
;
1384 env
->cr
[0] = sregs
.cr0
;
1385 env
->cr
[2] = sregs
.cr2
;
1386 env
->cr
[3] = sregs
.cr3
;
1387 env
->cr
[4] = sregs
.cr4
;
1389 env
->efer
= sregs
.efer
;
1391 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1393 #define HFLAG_COPY_MASK \
1394 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1395 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1396 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1397 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1399 hflags
= (env
->segs
[R_CS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
1400 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
1401 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
1402 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
1403 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
1404 hflags
|= (env
->cr
[4] & CR4_OSFXSR_MASK
) <<
1405 (HF_OSFXSR_SHIFT
- CR4_OSFXSR_SHIFT
);
1407 if (env
->efer
& MSR_EFER_LMA
) {
1408 hflags
|= HF_LMA_MASK
;
1411 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
1412 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
1414 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
1415 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
1416 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
1417 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
1418 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
) ||
1419 !(hflags
& HF_CS32_MASK
)) {
1420 hflags
|= HF_ADDSEG_MASK
;
1422 hflags
|= ((env
->segs
[R_DS
].base
| env
->segs
[R_ES
].base
|
1423 env
->segs
[R_SS
].base
) != 0) << HF_ADDSEG_SHIFT
;
1426 env
->hflags
= (env
->hflags
& HFLAG_COPY_MASK
) | hflags
;
1431 static int kvm_get_msrs(X86CPU
*cpu
)
1433 CPUX86State
*env
= &cpu
->env
;
1435 struct kvm_msrs info
;
1436 struct kvm_msr_entry entries
[100];
1438 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
1442 msrs
[n
++].index
= MSR_IA32_SYSENTER_CS
;
1443 msrs
[n
++].index
= MSR_IA32_SYSENTER_ESP
;
1444 msrs
[n
++].index
= MSR_IA32_SYSENTER_EIP
;
1445 msrs
[n
++].index
= MSR_PAT
;
1447 msrs
[n
++].index
= MSR_STAR
;
1449 if (has_msr_hsave_pa
) {
1450 msrs
[n
++].index
= MSR_VM_HSAVE_PA
;
1452 if (has_msr_tsc_adjust
) {
1453 msrs
[n
++].index
= MSR_TSC_ADJUST
;
1455 if (has_msr_tsc_deadline
) {
1456 msrs
[n
++].index
= MSR_IA32_TSCDEADLINE
;
1458 if (has_msr_misc_enable
) {
1459 msrs
[n
++].index
= MSR_IA32_MISC_ENABLE
;
1461 if (has_msr_feature_control
) {
1462 msrs
[n
++].index
= MSR_IA32_FEATURE_CONTROL
;
1464 if (has_msr_bndcfgs
) {
1465 msrs
[n
++].index
= MSR_IA32_BNDCFGS
;
1468 if (!env
->tsc_valid
) {
1469 msrs
[n
++].index
= MSR_IA32_TSC
;
1470 env
->tsc_valid
= !runstate_is_running();
1473 #ifdef TARGET_X86_64
1474 if (lm_capable_kernel
) {
1475 msrs
[n
++].index
= MSR_CSTAR
;
1476 msrs
[n
++].index
= MSR_KERNELGSBASE
;
1477 msrs
[n
++].index
= MSR_FMASK
;
1478 msrs
[n
++].index
= MSR_LSTAR
;
1481 msrs
[n
++].index
= MSR_KVM_SYSTEM_TIME
;
1482 msrs
[n
++].index
= MSR_KVM_WALL_CLOCK
;
1483 if (has_msr_async_pf_en
) {
1484 msrs
[n
++].index
= MSR_KVM_ASYNC_PF_EN
;
1486 if (has_msr_pv_eoi_en
) {
1487 msrs
[n
++].index
= MSR_KVM_PV_EOI_EN
;
1489 if (has_msr_kvm_steal_time
) {
1490 msrs
[n
++].index
= MSR_KVM_STEAL_TIME
;
1492 if (has_msr_architectural_pmu
) {
1493 msrs
[n
++].index
= MSR_CORE_PERF_FIXED_CTR_CTRL
;
1494 msrs
[n
++].index
= MSR_CORE_PERF_GLOBAL_CTRL
;
1495 msrs
[n
++].index
= MSR_CORE_PERF_GLOBAL_STATUS
;
1496 msrs
[n
++].index
= MSR_CORE_PERF_GLOBAL_OVF_CTRL
;
1497 for (i
= 0; i
< MAX_FIXED_COUNTERS
; i
++) {
1498 msrs
[n
++].index
= MSR_CORE_PERF_FIXED_CTR0
+ i
;
1500 for (i
= 0; i
< num_architectural_pmu_counters
; i
++) {
1501 msrs
[n
++].index
= MSR_P6_PERFCTR0
+ i
;
1502 msrs
[n
++].index
= MSR_P6_EVNTSEL0
+ i
;
1507 msrs
[n
++].index
= MSR_MCG_STATUS
;
1508 msrs
[n
++].index
= MSR_MCG_CTL
;
1509 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
1510 msrs
[n
++].index
= MSR_MC0_CTL
+ i
;
1514 msr_data
.info
.nmsrs
= n
;
1515 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_MSRS
, &msr_data
);
1520 for (i
= 0; i
< ret
; i
++) {
1521 uint32_t index
= msrs
[i
].index
;
1523 case MSR_IA32_SYSENTER_CS
:
1524 env
->sysenter_cs
= msrs
[i
].data
;
1526 case MSR_IA32_SYSENTER_ESP
:
1527 env
->sysenter_esp
= msrs
[i
].data
;
1529 case MSR_IA32_SYSENTER_EIP
:
1530 env
->sysenter_eip
= msrs
[i
].data
;
1533 env
->pat
= msrs
[i
].data
;
1536 env
->star
= msrs
[i
].data
;
1538 #ifdef TARGET_X86_64
1540 env
->cstar
= msrs
[i
].data
;
1542 case MSR_KERNELGSBASE
:
1543 env
->kernelgsbase
= msrs
[i
].data
;
1546 env
->fmask
= msrs
[i
].data
;
1549 env
->lstar
= msrs
[i
].data
;
1553 env
->tsc
= msrs
[i
].data
;
1555 case MSR_TSC_ADJUST
:
1556 env
->tsc_adjust
= msrs
[i
].data
;
1558 case MSR_IA32_TSCDEADLINE
:
1559 env
->tsc_deadline
= msrs
[i
].data
;
1561 case MSR_VM_HSAVE_PA
:
1562 env
->vm_hsave
= msrs
[i
].data
;
1564 case MSR_KVM_SYSTEM_TIME
:
1565 env
->system_time_msr
= msrs
[i
].data
;
1567 case MSR_KVM_WALL_CLOCK
:
1568 env
->wall_clock_msr
= msrs
[i
].data
;
1570 case MSR_MCG_STATUS
:
1571 env
->mcg_status
= msrs
[i
].data
;
1574 env
->mcg_ctl
= msrs
[i
].data
;
1576 case MSR_IA32_MISC_ENABLE
:
1577 env
->msr_ia32_misc_enable
= msrs
[i
].data
;
1579 case MSR_IA32_FEATURE_CONTROL
:
1580 env
->msr_ia32_feature_control
= msrs
[i
].data
;
1582 case MSR_IA32_BNDCFGS
:
1583 env
->msr_bndcfgs
= msrs
[i
].data
;
1586 if (msrs
[i
].index
>= MSR_MC0_CTL
&&
1587 msrs
[i
].index
< MSR_MC0_CTL
+ (env
->mcg_cap
& 0xff) * 4) {
1588 env
->mce_banks
[msrs
[i
].index
- MSR_MC0_CTL
] = msrs
[i
].data
;
1591 case MSR_KVM_ASYNC_PF_EN
:
1592 env
->async_pf_en_msr
= msrs
[i
].data
;
1594 case MSR_KVM_PV_EOI_EN
:
1595 env
->pv_eoi_en_msr
= msrs
[i
].data
;
1597 case MSR_KVM_STEAL_TIME
:
1598 env
->steal_time_msr
= msrs
[i
].data
;
1600 case MSR_CORE_PERF_FIXED_CTR_CTRL
:
1601 env
->msr_fixed_ctr_ctrl
= msrs
[i
].data
;
1603 case MSR_CORE_PERF_GLOBAL_CTRL
:
1604 env
->msr_global_ctrl
= msrs
[i
].data
;
1606 case MSR_CORE_PERF_GLOBAL_STATUS
:
1607 env
->msr_global_status
= msrs
[i
].data
;
1609 case MSR_CORE_PERF_GLOBAL_OVF_CTRL
:
1610 env
->msr_global_ovf_ctrl
= msrs
[i
].data
;
1612 case MSR_CORE_PERF_FIXED_CTR0
... MSR_CORE_PERF_FIXED_CTR0
+ MAX_FIXED_COUNTERS
- 1:
1613 env
->msr_fixed_counters
[index
- MSR_CORE_PERF_FIXED_CTR0
] = msrs
[i
].data
;
1615 case MSR_P6_PERFCTR0
... MSR_P6_PERFCTR0
+ MAX_GP_COUNTERS
- 1:
1616 env
->msr_gp_counters
[index
- MSR_P6_PERFCTR0
] = msrs
[i
].data
;
1618 case MSR_P6_EVNTSEL0
... MSR_P6_EVNTSEL0
+ MAX_GP_COUNTERS
- 1:
1619 env
->msr_gp_evtsel
[index
- MSR_P6_EVNTSEL0
] = msrs
[i
].data
;
1627 static int kvm_put_mp_state(X86CPU
*cpu
)
1629 struct kvm_mp_state mp_state
= { .mp_state
= cpu
->env
.mp_state
};
1631 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MP_STATE
, &mp_state
);
1634 static int kvm_get_mp_state(X86CPU
*cpu
)
1636 CPUState
*cs
= CPU(cpu
);
1637 CPUX86State
*env
= &cpu
->env
;
1638 struct kvm_mp_state mp_state
;
1641 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_MP_STATE
, &mp_state
);
1645 env
->mp_state
= mp_state
.mp_state
;
1646 if (kvm_irqchip_in_kernel()) {
1647 cs
->halted
= (mp_state
.mp_state
== KVM_MP_STATE_HALTED
);
1652 static int kvm_get_apic(X86CPU
*cpu
)
1654 CPUX86State
*env
= &cpu
->env
;
1655 DeviceState
*apic
= env
->apic_state
;
1656 struct kvm_lapic_state kapic
;
1659 if (apic
&& kvm_irqchip_in_kernel()) {
1660 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_LAPIC
, &kapic
);
1665 kvm_get_apic_state(apic
, &kapic
);
1670 static int kvm_put_apic(X86CPU
*cpu
)
1672 CPUX86State
*env
= &cpu
->env
;
1673 DeviceState
*apic
= env
->apic_state
;
1674 struct kvm_lapic_state kapic
;
1676 if (apic
&& kvm_irqchip_in_kernel()) {
1677 kvm_put_apic_state(apic
, &kapic
);
1679 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_LAPIC
, &kapic
);
1684 static int kvm_put_vcpu_events(X86CPU
*cpu
, int level
)
1686 CPUX86State
*env
= &cpu
->env
;
1687 struct kvm_vcpu_events events
;
1689 if (!kvm_has_vcpu_events()) {
1693 events
.exception
.injected
= (env
->exception_injected
>= 0);
1694 events
.exception
.nr
= env
->exception_injected
;
1695 events
.exception
.has_error_code
= env
->has_error_code
;
1696 events
.exception
.error_code
= env
->error_code
;
1697 events
.exception
.pad
= 0;
1699 events
.interrupt
.injected
= (env
->interrupt_injected
>= 0);
1700 events
.interrupt
.nr
= env
->interrupt_injected
;
1701 events
.interrupt
.soft
= env
->soft_interrupt
;
1703 events
.nmi
.injected
= env
->nmi_injected
;
1704 events
.nmi
.pending
= env
->nmi_pending
;
1705 events
.nmi
.masked
= !!(env
->hflags2
& HF2_NMI_MASK
);
1708 events
.sipi_vector
= env
->sipi_vector
;
1711 if (level
>= KVM_PUT_RESET_STATE
) {
1713 KVM_VCPUEVENT_VALID_NMI_PENDING
| KVM_VCPUEVENT_VALID_SIPI_VECTOR
;
1716 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_VCPU_EVENTS
, &events
);
1719 static int kvm_get_vcpu_events(X86CPU
*cpu
)
1721 CPUX86State
*env
= &cpu
->env
;
1722 struct kvm_vcpu_events events
;
1725 if (!kvm_has_vcpu_events()) {
1729 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_VCPU_EVENTS
, &events
);
1733 env
->exception_injected
=
1734 events
.exception
.injected
? events
.exception
.nr
: -1;
1735 env
->has_error_code
= events
.exception
.has_error_code
;
1736 env
->error_code
= events
.exception
.error_code
;
1738 env
->interrupt_injected
=
1739 events
.interrupt
.injected
? events
.interrupt
.nr
: -1;
1740 env
->soft_interrupt
= events
.interrupt
.soft
;
1742 env
->nmi_injected
= events
.nmi
.injected
;
1743 env
->nmi_pending
= events
.nmi
.pending
;
1744 if (events
.nmi
.masked
) {
1745 env
->hflags2
|= HF2_NMI_MASK
;
1747 env
->hflags2
&= ~HF2_NMI_MASK
;
1750 env
->sipi_vector
= events
.sipi_vector
;
1755 static int kvm_guest_debug_workarounds(X86CPU
*cpu
)
1757 CPUState
*cs
= CPU(cpu
);
1758 CPUX86State
*env
= &cpu
->env
;
1760 unsigned long reinject_trap
= 0;
1762 if (!kvm_has_vcpu_events()) {
1763 if (env
->exception_injected
== 1) {
1764 reinject_trap
= KVM_GUESTDBG_INJECT_DB
;
1765 } else if (env
->exception_injected
== 3) {
1766 reinject_trap
= KVM_GUESTDBG_INJECT_BP
;
1768 env
->exception_injected
= -1;
1772 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1773 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1774 * by updating the debug state once again if single-stepping is on.
1775 * Another reason to call kvm_update_guest_debug here is a pending debug
1776 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1777 * reinject them via SET_GUEST_DEBUG.
1779 if (reinject_trap
||
1780 (!kvm_has_robust_singlestep() && cs
->singlestep_enabled
)) {
1781 ret
= kvm_update_guest_debug(cs
, reinject_trap
);
1786 static int kvm_put_debugregs(X86CPU
*cpu
)
1788 CPUX86State
*env
= &cpu
->env
;
1789 struct kvm_debugregs dbgregs
;
1792 if (!kvm_has_debugregs()) {
1796 for (i
= 0; i
< 4; i
++) {
1797 dbgregs
.db
[i
] = env
->dr
[i
];
1799 dbgregs
.dr6
= env
->dr
[6];
1800 dbgregs
.dr7
= env
->dr
[7];
1803 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_DEBUGREGS
, &dbgregs
);
1806 static int kvm_get_debugregs(X86CPU
*cpu
)
1808 CPUX86State
*env
= &cpu
->env
;
1809 struct kvm_debugregs dbgregs
;
1812 if (!kvm_has_debugregs()) {
1816 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_DEBUGREGS
, &dbgregs
);
1820 for (i
= 0; i
< 4; i
++) {
1821 env
->dr
[i
] = dbgregs
.db
[i
];
1823 env
->dr
[4] = env
->dr
[6] = dbgregs
.dr6
;
1824 env
->dr
[5] = env
->dr
[7] = dbgregs
.dr7
;
1829 int kvm_arch_put_registers(CPUState
*cpu
, int level
)
1831 X86CPU
*x86_cpu
= X86_CPU(cpu
);
1834 assert(cpu_is_stopped(cpu
) || qemu_cpu_is_self(cpu
));
1836 if (level
>= KVM_PUT_RESET_STATE
&& has_msr_feature_control
) {
1837 ret
= kvm_put_msr_feature_control(x86_cpu
);
1843 ret
= kvm_getput_regs(x86_cpu
, 1);
1847 ret
= kvm_put_xsave(x86_cpu
);
1851 ret
= kvm_put_xcrs(x86_cpu
);
1855 ret
= kvm_put_sregs(x86_cpu
);
1859 /* must be before kvm_put_msrs */
1860 ret
= kvm_inject_mce_oldstyle(x86_cpu
);
1864 ret
= kvm_put_msrs(x86_cpu
, level
);
1868 if (level
>= KVM_PUT_RESET_STATE
) {
1869 ret
= kvm_put_mp_state(x86_cpu
);
1873 ret
= kvm_put_apic(x86_cpu
);
1879 ret
= kvm_put_tscdeadline_msr(x86_cpu
);
1884 ret
= kvm_put_vcpu_events(x86_cpu
, level
);
1888 ret
= kvm_put_debugregs(x86_cpu
);
1893 ret
= kvm_guest_debug_workarounds(x86_cpu
);
1900 int kvm_arch_get_registers(CPUState
*cs
)
1902 X86CPU
*cpu
= X86_CPU(cs
);
1905 assert(cpu_is_stopped(cs
) || qemu_cpu_is_self(cs
));
1907 ret
= kvm_getput_regs(cpu
, 0);
1911 ret
= kvm_get_xsave(cpu
);
1915 ret
= kvm_get_xcrs(cpu
);
1919 ret
= kvm_get_sregs(cpu
);
1923 ret
= kvm_get_msrs(cpu
);
1927 ret
= kvm_get_mp_state(cpu
);
1931 ret
= kvm_get_apic(cpu
);
1935 ret
= kvm_get_vcpu_events(cpu
);
1939 ret
= kvm_get_debugregs(cpu
);
1946 void kvm_arch_pre_run(CPUState
*cpu
, struct kvm_run
*run
)
1948 X86CPU
*x86_cpu
= X86_CPU(cpu
);
1949 CPUX86State
*env
= &x86_cpu
->env
;
1953 if (cpu
->interrupt_request
& CPU_INTERRUPT_NMI
) {
1954 cpu
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
1955 DPRINTF("injected NMI\n");
1956 ret
= kvm_vcpu_ioctl(cpu
, KVM_NMI
);
1958 fprintf(stderr
, "KVM: injection failed, NMI lost (%s)\n",
1963 if (!kvm_irqchip_in_kernel()) {
1964 /* Force the VCPU out of its inner loop to process any INIT requests
1965 * or pending TPR access reports. */
1966 if (cpu
->interrupt_request
&
1967 (CPU_INTERRUPT_INIT
| CPU_INTERRUPT_TPR
)) {
1968 cpu
->exit_request
= 1;
1971 /* Try to inject an interrupt if the guest can accept it */
1972 if (run
->ready_for_interrupt_injection
&&
1973 (cpu
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1974 (env
->eflags
& IF_MASK
)) {
1977 cpu
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
1978 irq
= cpu_get_pic_interrupt(env
);
1980 struct kvm_interrupt intr
;
1983 DPRINTF("injected interrupt %d\n", irq
);
1984 ret
= kvm_vcpu_ioctl(cpu
, KVM_INTERRUPT
, &intr
);
1987 "KVM: injection failed, interrupt lost (%s)\n",
1993 /* If we have an interrupt but the guest is not ready to receive an
1994 * interrupt, request an interrupt window exit. This will
1995 * cause a return to userspace as soon as the guest is ready to
1996 * receive interrupts. */
1997 if ((cpu
->interrupt_request
& CPU_INTERRUPT_HARD
)) {
1998 run
->request_interrupt_window
= 1;
2000 run
->request_interrupt_window
= 0;
2003 DPRINTF("setting tpr\n");
2004 run
->cr8
= cpu_get_apic_tpr(env
->apic_state
);
2008 void kvm_arch_post_run(CPUState
*cpu
, struct kvm_run
*run
)
2010 X86CPU
*x86_cpu
= X86_CPU(cpu
);
2011 CPUX86State
*env
= &x86_cpu
->env
;
2014 env
->eflags
|= IF_MASK
;
2016 env
->eflags
&= ~IF_MASK
;
2018 cpu_set_apic_tpr(env
->apic_state
, run
->cr8
);
2019 cpu_set_apic_base(env
->apic_state
, run
->apic_base
);
2022 int kvm_arch_process_async_events(CPUState
*cs
)
2024 X86CPU
*cpu
= X86_CPU(cs
);
2025 CPUX86State
*env
= &cpu
->env
;
2027 if (cs
->interrupt_request
& CPU_INTERRUPT_MCE
) {
2028 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2029 assert(env
->mcg_cap
);
2031 cs
->interrupt_request
&= ~CPU_INTERRUPT_MCE
;
2033 kvm_cpu_synchronize_state(cs
);
2035 if (env
->exception_injected
== EXCP08_DBLE
) {
2036 /* this means triple fault */
2037 qemu_system_reset_request();
2038 cs
->exit_request
= 1;
2041 env
->exception_injected
= EXCP12_MCHK
;
2042 env
->has_error_code
= 0;
2045 if (kvm_irqchip_in_kernel() && env
->mp_state
== KVM_MP_STATE_HALTED
) {
2046 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
2050 if (kvm_irqchip_in_kernel()) {
2054 if (cs
->interrupt_request
& CPU_INTERRUPT_POLL
) {
2055 cs
->interrupt_request
&= ~CPU_INTERRUPT_POLL
;
2056 apic_poll_irq(env
->apic_state
);
2058 if (((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
2059 (env
->eflags
& IF_MASK
)) ||
2060 (cs
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
2063 if (cs
->interrupt_request
& CPU_INTERRUPT_INIT
) {
2064 kvm_cpu_synchronize_state(cs
);
2067 if (cs
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
2068 kvm_cpu_synchronize_state(cs
);
2071 if (cs
->interrupt_request
& CPU_INTERRUPT_TPR
) {
2072 cs
->interrupt_request
&= ~CPU_INTERRUPT_TPR
;
2073 kvm_cpu_synchronize_state(cs
);
2074 apic_handle_tpr_access_report(env
->apic_state
, env
->eip
,
2075 env
->tpr_access_type
);
2081 static int kvm_handle_halt(X86CPU
*cpu
)
2083 CPUState
*cs
= CPU(cpu
);
2084 CPUX86State
*env
= &cpu
->env
;
2086 if (!((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
2087 (env
->eflags
& IF_MASK
)) &&
2088 !(cs
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
2096 static int kvm_handle_tpr_access(X86CPU
*cpu
)
2098 CPUX86State
*env
= &cpu
->env
;
2099 CPUState
*cs
= CPU(cpu
);
2100 struct kvm_run
*run
= cs
->kvm_run
;
2102 apic_handle_tpr_access_report(env
->apic_state
, run
->tpr_access
.rip
,
2103 run
->tpr_access
.is_write
? TPR_ACCESS_WRITE
2108 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
2110 static const uint8_t int3
= 0xcc;
2112 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
2113 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&int3
, 1, 1)) {
2119 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
2123 if (cpu_memory_rw_debug(cs
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
2124 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1)) {
2136 static int nb_hw_breakpoint
;
2138 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
2142 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
2143 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
2144 (hw_breakpoint
[n
].len
== len
|| len
== -1)) {
2151 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
2152 target_ulong len
, int type
)
2155 case GDB_BREAKPOINT_HW
:
2158 case GDB_WATCHPOINT_WRITE
:
2159 case GDB_WATCHPOINT_ACCESS
:
2166 if (addr
& (len
- 1)) {
2178 if (nb_hw_breakpoint
== 4) {
2181 if (find_hw_breakpoint(addr
, len
, type
) >= 0) {
2184 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
2185 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
2186 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
2192 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
2193 target_ulong len
, int type
)
2197 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
2202 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
2207 void kvm_arch_remove_all_hw_breakpoints(void)
2209 nb_hw_breakpoint
= 0;
2212 static CPUWatchpoint hw_watchpoint
;
2214 static int kvm_handle_debug(X86CPU
*cpu
,
2215 struct kvm_debug_exit_arch
*arch_info
)
2217 CPUState
*cs
= CPU(cpu
);
2218 CPUX86State
*env
= &cpu
->env
;
2222 if (arch_info
->exception
== 1) {
2223 if (arch_info
->dr6
& (1 << 14)) {
2224 if (cs
->singlestep_enabled
) {
2228 for (n
= 0; n
< 4; n
++) {
2229 if (arch_info
->dr6
& (1 << n
)) {
2230 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
2236 env
->watchpoint_hit
= &hw_watchpoint
;
2237 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
2238 hw_watchpoint
.flags
= BP_MEM_WRITE
;
2242 env
->watchpoint_hit
= &hw_watchpoint
;
2243 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
2244 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
2250 } else if (kvm_find_sw_breakpoint(CPU(cpu
), arch_info
->pc
)) {
2254 cpu_synchronize_state(CPU(cpu
));
2255 assert(env
->exception_injected
== -1);
2258 env
->exception_injected
= arch_info
->exception
;
2259 env
->has_error_code
= 0;
2265 void kvm_arch_update_guest_debug(CPUState
*cpu
, struct kvm_guest_debug
*dbg
)
2267 const uint8_t type_code
[] = {
2268 [GDB_BREAKPOINT_HW
] = 0x0,
2269 [GDB_WATCHPOINT_WRITE
] = 0x1,
2270 [GDB_WATCHPOINT_ACCESS
] = 0x3
2272 const uint8_t len_code
[] = {
2273 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2277 if (kvm_sw_breakpoints_active(cpu
)) {
2278 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
2280 if (nb_hw_breakpoint
> 0) {
2281 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
2282 dbg
->arch
.debugreg
[7] = 0x0600;
2283 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
2284 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
2285 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
2286 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
2287 ((uint32_t)len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
2292 static bool host_supports_vmx(void)
2294 uint32_t ecx
, unused
;
2296 host_cpuid(1, 0, &unused
, &unused
, &ecx
, &unused
);
2297 return ecx
& CPUID_EXT_VMX
;
2300 #define VMX_INVALID_GUEST_STATE 0x80000021
2302 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
2304 X86CPU
*cpu
= X86_CPU(cs
);
2308 switch (run
->exit_reason
) {
2310 DPRINTF("handle_hlt\n");
2311 ret
= kvm_handle_halt(cpu
);
2313 case KVM_EXIT_SET_TPR
:
2316 case KVM_EXIT_TPR_ACCESS
:
2317 ret
= kvm_handle_tpr_access(cpu
);
2319 case KVM_EXIT_FAIL_ENTRY
:
2320 code
= run
->fail_entry
.hardware_entry_failure_reason
;
2321 fprintf(stderr
, "KVM: entry failed, hardware error 0x%" PRIx64
"\n",
2323 if (host_supports_vmx() && code
== VMX_INVALID_GUEST_STATE
) {
2325 "\nIf you're running a guest on an Intel machine without "
2326 "unrestricted mode\n"
2327 "support, the failure can be most likely due to the guest "
2328 "entering an invalid\n"
2329 "state for Intel VT. For example, the guest maybe running "
2330 "in big real mode\n"
2331 "which is not supported on less recent Intel processors."
2336 case KVM_EXIT_EXCEPTION
:
2337 fprintf(stderr
, "KVM: exception %d exit (error code 0x%x)\n",
2338 run
->ex
.exception
, run
->ex
.error_code
);
2341 case KVM_EXIT_DEBUG
:
2342 DPRINTF("kvm_exit_debug\n");
2343 ret
= kvm_handle_debug(cpu
, &run
->debug
.arch
);
2346 fprintf(stderr
, "KVM: unknown exit reason %d\n", run
->exit_reason
);
2354 bool kvm_arch_stop_on_emulation_error(CPUState
*cs
)
2356 X86CPU
*cpu
= X86_CPU(cs
);
2357 CPUX86State
*env
= &cpu
->env
;
2359 kvm_cpu_synchronize_state(cs
);
2360 return !(env
->cr
[0] & CR0_PE_MASK
) ||
2361 ((env
->segs
[R_CS
].selector
& 3) != 3);
2364 void kvm_arch_init_irq_routing(KVMState
*s
)
2366 if (!kvm_check_extension(s
, KVM_CAP_IRQ_ROUTING
)) {
2367 /* If kernel can't do irq routing, interrupt source
2368 * override 0->2 cannot be set up as required by HPET.
2369 * So we have to disable it.
2373 /* We know at this point that we're using the in-kernel
2374 * irqchip, so we can use irqfds, and on x86 we know
2375 * we can use msi via irqfd and GSI routing.
2377 kvm_irqfds_allowed
= true;
2378 kvm_msi_via_irqfd_allowed
= true;
2379 kvm_gsi_routing_allowed
= true;
2382 /* Classic KVM device assignment interface. Will remain x86 only. */
2383 int kvm_device_pci_assign(KVMState
*s
, PCIHostDeviceAddress
*dev_addr
,
2384 uint32_t flags
, uint32_t *dev_id
)
2386 struct kvm_assigned_pci_dev dev_data
= {
2387 .segnr
= dev_addr
->domain
,
2388 .busnr
= dev_addr
->bus
,
2389 .devfn
= PCI_DEVFN(dev_addr
->slot
, dev_addr
->function
),
2394 dev_data
.assigned_dev_id
=
2395 (dev_addr
->domain
<< 16) | (dev_addr
->bus
<< 8) | dev_data
.devfn
;
2397 ret
= kvm_vm_ioctl(s
, KVM_ASSIGN_PCI_DEVICE
, &dev_data
);
2402 *dev_id
= dev_data
.assigned_dev_id
;
2407 int kvm_device_pci_deassign(KVMState
*s
, uint32_t dev_id
)
2409 struct kvm_assigned_pci_dev dev_data
= {
2410 .assigned_dev_id
= dev_id
,
2413 return kvm_vm_ioctl(s
, KVM_DEASSIGN_PCI_DEVICE
, &dev_data
);
2416 static int kvm_assign_irq_internal(KVMState
*s
, uint32_t dev_id
,
2417 uint32_t irq_type
, uint32_t guest_irq
)
2419 struct kvm_assigned_irq assigned_irq
= {
2420 .assigned_dev_id
= dev_id
,
2421 .guest_irq
= guest_irq
,
2425 if (kvm_check_extension(s
, KVM_CAP_ASSIGN_DEV_IRQ
)) {
2426 return kvm_vm_ioctl(s
, KVM_ASSIGN_DEV_IRQ
, &assigned_irq
);
2428 return kvm_vm_ioctl(s
, KVM_ASSIGN_IRQ
, &assigned_irq
);
2432 int kvm_device_intx_assign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
,
2435 uint32_t irq_type
= KVM_DEV_IRQ_GUEST_INTX
|
2436 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
);
2438 return kvm_assign_irq_internal(s
, dev_id
, irq_type
, guest_irq
);
2441 int kvm_device_intx_set_mask(KVMState
*s
, uint32_t dev_id
, bool masked
)
2443 struct kvm_assigned_pci_dev dev_data
= {
2444 .assigned_dev_id
= dev_id
,
2445 .flags
= masked
? KVM_DEV_ASSIGN_MASK_INTX
: 0,
2448 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_INTX_MASK
, &dev_data
);
2451 static int kvm_deassign_irq_internal(KVMState
*s
, uint32_t dev_id
,
2454 struct kvm_assigned_irq assigned_irq
= {
2455 .assigned_dev_id
= dev_id
,
2459 return kvm_vm_ioctl(s
, KVM_DEASSIGN_DEV_IRQ
, &assigned_irq
);
2462 int kvm_device_intx_deassign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
)
2464 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_INTX
|
2465 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
));
2468 int kvm_device_msi_assign(KVMState
*s
, uint32_t dev_id
, int virq
)
2470 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSI
|
2471 KVM_DEV_IRQ_GUEST_MSI
, virq
);
2474 int kvm_device_msi_deassign(KVMState
*s
, uint32_t dev_id
)
2476 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSI
|
2477 KVM_DEV_IRQ_HOST_MSI
);
2480 bool kvm_device_msix_supported(KVMState
*s
)
2482 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2483 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2484 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, NULL
) == -EFAULT
;
2487 int kvm_device_msix_init_vectors(KVMState
*s
, uint32_t dev_id
,
2488 uint32_t nr_vectors
)
2490 struct kvm_assigned_msix_nr msix_nr
= {
2491 .assigned_dev_id
= dev_id
,
2492 .entry_nr
= nr_vectors
,
2495 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, &msix_nr
);
2498 int kvm_device_msix_set_vector(KVMState
*s
, uint32_t dev_id
, uint32_t vector
,
2501 struct kvm_assigned_msix_entry msix_entry
= {
2502 .assigned_dev_id
= dev_id
,
2507 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_ENTRY
, &msix_entry
);
2510 int kvm_device_msix_assign(KVMState
*s
, uint32_t dev_id
)
2512 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSIX
|
2513 KVM_DEV_IRQ_GUEST_MSIX
, 0);
2516 int kvm_device_msix_deassign(KVMState
*s
, uint32_t dev_id
)
2518 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSIX
|
2519 KVM_DEV_IRQ_HOST_MSIX
);