fpu/softfloat-specialize.h

   1 /*
   2  * QEMU float support
   3  *
   4  * The code in this source file is derived from release 2a of the SoftFloat
   5  * IEC/IEEE Floating-point Arithmetic Package. Those parts of the code (and
   6  * some later contributions) are provided under that license, as detailed below.
   7  * It has subsequently been modified by contributors to the QEMU Project,
   8  * so some portions are provided under:
   9  *  the SoftFloat-2a license
  10  *  the BSD license
  11  *  GPL-v2-or-later
  12  *
  13  * Any future contributions to this file after December 1st 2014 will be
  14  * taken to be licensed under the Softfloat-2a license unless specifically
  15  * indicated otherwise.
  16  */
  17
  18 /*
  19 ===============================================================================
  20 This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
  21 Arithmetic Package, Release 2a.
  22
  23 Written by John R. Hauser.  This work was made possible in part by the
  24 International Computer Science Institute, located at Suite 600, 1947 Center
  25 Street, Berkeley, California 94704.  Funding was partially provided by the
  26 National Science Foundation under grant MIP-9311980.  The original version
  27 of this code was written as part of a project to build a fixed-point vector
  28 processor in collaboration with the University of California at Berkeley,
  29 overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
  30 is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
  31 arithmetic/SoftFloat.html'.
  32
  33 THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort
  34 has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
  35 TIMES RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO
  36 PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
  37 AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
  38
  39 Derivative works are acceptable, even for commercial purposes, so long as
  40 (1) they include prominent notice that the work is derivative, and (2) they
  41 include prominent notice akin to these four paragraphs for those parts of
  42 this code that are retained.
  43
  44 ===============================================================================
  45 */
  46
  47 /* BSD licensing:
  48  * Copyright (c) 2006, Fabrice Bellard
  49  * All rights reserved.
  50  *
  51  * Redistribution and use in source and binary forms, with or without
  52  * modification, are permitted provided that the following conditions are met:
  53  *
  54  * 1. Redistributions of source code must retain the above copyright notice,
  55  * this list of conditions and the following disclaimer.
  56  *
  57  * 2. Redistributions in binary form must reproduce the above copyright notice,
  58  * this list of conditions and the following disclaimer in the documentation
  59  * and/or other materials provided with the distribution.
  60  *
  61  * 3. Neither the name of the copyright holder nor the names of its contributors
  62  * may be used to endorse or promote products derived from this software without
  63  * specific prior written permission.
  64  *
  65  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  66  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  67  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  68  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  69  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  70  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  71  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  72  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  73  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  74  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  75  * THE POSSIBILITY OF SUCH DAMAGE.
  76  */
  77
  78 /* Portions of this work are licensed under the terms of the GNU GPL,
  79  * version 2 or later. See the COPYING file in the top-level directory.
  80  */
  81
  82 #if defined(TARGET_XTENSA)
  83 /* Define for architectures which deviate from IEEE in not supporting
  84  * signaling NaNs (so all NaNs are treated as quiet).
  85  */
  86 #define NO_SIGNALING_NANS 1
  87 #endif
  88
  89 /*----------------------------------------------------------------------------
  90 | The pattern for a default generated half-precision NaN.
  91 *----------------------------------------------------------------------------*/
  92 float16 float16_default_nan(float_status *status)
  93 {
  94 #if defined(TARGET_ARM)
  95     return const_float16(0x7E00);
  96 #else
  97     if (status->snan_bit_is_one) {
  98         return const_float16(0x7DFF);
  99     } else {
 100 #if defined(TARGET_MIPS)
 101         return const_float16(0x7E00);
 102 #else
 103         return const_float16(0xFE00);
 104 #endif
 105     }
 106 #endif
 107 }
 108
 109 /*----------------------------------------------------------------------------
 110 | The pattern for a default generated single-precision NaN.
 111 *----------------------------------------------------------------------------*/
 112 float32 float32_default_nan(float_status *status)
 113 {
 114 #if defined(TARGET_SPARC) || defined(TARGET_M68K)
 115     return const_float32(0x7FFFFFFF);
 116 #elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
 117       defined(TARGET_XTENSA) || defined(TARGET_S390X) || defined(TARGET_TRICORE)
 118     return const_float32(0x7FC00000);
 119 #elif defined(TARGET_HPPA)
 120     return const_float32(0x7FA00000);
 121 #else
 122     if (status->snan_bit_is_one) {
 123         return const_float32(0x7FBFFFFF);
 124     } else {
 125 #if defined(TARGET_MIPS)
 126         return const_float32(0x7FC00000);
 127 #else
 128         return const_float32(0xFFC00000);
 129 #endif
 130     }
 131 #endif
 132 }
 133
 134 /*----------------------------------------------------------------------------
 135 | The pattern for a default generated double-precision NaN.
 136 *----------------------------------------------------------------------------*/
 137 float64 float64_default_nan(float_status *status)
 138 {
 139 #if defined(TARGET_SPARC) || defined(TARGET_M68K)
 140     return const_float64(LIT64(0x7FFFFFFFFFFFFFFF));
 141 #elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
 142       defined(TARGET_S390X)
 143     return const_float64(LIT64(0x7FF8000000000000));
 144 #elif defined(TARGET_HPPA)
 145     return const_float64(LIT64(0x7FF4000000000000));
 146 #else
 147     if (status->snan_bit_is_one) {
 148         return const_float64(LIT64(0x7FF7FFFFFFFFFFFF));
 149     } else {
 150 #if defined(TARGET_MIPS)
 151         return const_float64(LIT64(0x7FF8000000000000));
 152 #else
 153         return const_float64(LIT64(0xFFF8000000000000));
 154 #endif
 155     }
 156 #endif
 157 }
 158
 159 /*----------------------------------------------------------------------------
 160 | The pattern for a default generated extended double-precision NaN.
 161 *----------------------------------------------------------------------------*/
 162 floatx80 floatx80_default_nan(float_status *status)
 163 {
 164     floatx80 r;
 165 #if defined(TARGET_M68K)
 166     r.low = LIT64(0xFFFFFFFFFFFFFFFF);
 167     r.high = 0x7FFF;
 168 #else
 169     if (status->snan_bit_is_one) {
 170         r.low = LIT64(0xBFFFFFFFFFFFFFFF);
 171         r.high = 0x7FFF;
 172     } else {
 173         r.low = LIT64(0xC000000000000000);
 174         r.high = 0xFFFF;
 175     }
 176 #endif
 177     return r;
 178 }
 179
 180 /*----------------------------------------------------------------------------
 181 | The pattern for a default generated extended double-precision inf.
 182 *----------------------------------------------------------------------------*/
 183
 184 #define floatx80_infinity_high 0x7FFF
 185 #if defined(TARGET_M68K)
 186 #define floatx80_infinity_low  LIT64(0x0000000000000000)
 187 #else
 188 #define floatx80_infinity_low  LIT64(0x8000000000000000)
 189 #endif
 190
 191 const floatx80 floatx80_infinity
 192     = make_floatx80_init(floatx80_infinity_high, floatx80_infinity_low);
 193
 194 /*----------------------------------------------------------------------------
 195 | The pattern for a default generated quadruple-precision NaN.
 196 *----------------------------------------------------------------------------*/
 197 float128 float128_default_nan(float_status *status)
 198 {
 199     float128 r;
 200
 201     if (status->snan_bit_is_one) {
 202         r.low = LIT64(0xFFFFFFFFFFFFFFFF);
 203         r.high = LIT64(0x7FFF7FFFFFFFFFFF);
 204     } else {
 205         r.low = LIT64(0x0000000000000000);
 206 #if defined(TARGET_S390X) || defined(TARGET_PPC)
 207         r.high = LIT64(0x7FFF800000000000);
 208 #else
 209         r.high = LIT64(0xFFFF800000000000);
 210 #endif
 211     }
 212     return r;
 213 }
 214
 215 /*----------------------------------------------------------------------------
 216 | Raises the exceptions specified by `flags'.  Floating-point traps can be
 217 | defined here if desired.  It is currently not possible for such a trap
 218 | to substitute a result value.  If traps are not implemented, this routine
 219 | should be simply `float_exception_flags |= flags;'.
 220 *----------------------------------------------------------------------------*/
 221
 222 void float_raise(uint8_t flags, float_status *status)
 223 {
 224     status->float_exception_flags |= flags;
 225 }
 226
 227 /*----------------------------------------------------------------------------
 228 | Internal canonical NaN format.
 229 *----------------------------------------------------------------------------*/
 230 typedef struct {
 231     flag sign;
 232     uint64_t high, low;
 233 } commonNaNT;
 234
 235 #ifdef NO_SIGNALING_NANS
 236 int float16_is_quiet_nan(float16 a_, float_status *status)
 237 {
 238     return float16_is_any_nan(a_);
 239 }
 240
 241 int float16_is_signaling_nan(float16 a_, float_status *status)
 242 {
 243     return 0;
 244 }
 245 #else
 246 /*----------------------------------------------------------------------------
 247 | Returns 1 if the half-precision floating-point value `a' is a quiet
 248 | NaN; otherwise returns 0.
 249 *----------------------------------------------------------------------------*/
 250
 251 int float16_is_quiet_nan(float16 a_, float_status *status)
 252 {
 253     uint16_t a = float16_val(a_);
 254     if (status->snan_bit_is_one) {
 255         return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
 256     } else {
 257         return ((a & ~0x8000) >= 0x7C80);
 258     }
 259 }
 260
 261 /*----------------------------------------------------------------------------
 262 | Returns 1 if the half-precision floating-point value `a' is a signaling
 263 | NaN; otherwise returns 0.
 264 *----------------------------------------------------------------------------*/
 265
 266 int float16_is_signaling_nan(float16 a_, float_status *status)
 267 {
 268     uint16_t a = float16_val(a_);
 269     if (status->snan_bit_is_one) {
 270         return ((a & ~0x8000) >= 0x7C80);
 271     } else {
 272         return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
 273     }
 274 }
 275 #endif
 276
 277 /*----------------------------------------------------------------------------
 278 | Returns a quiet NaN if the half-precision floating point value `a' is a
 279 | signaling NaN; otherwise returns `a'.
 280 *----------------------------------------------------------------------------*/
 281 float16 float16_maybe_silence_nan(float16 a_, float_status *status)
 282 {
 283     if (float16_is_signaling_nan(a_, status)) {
 284         if (status->snan_bit_is_one) {
 285             return float16_default_nan(status);
 286         } else {
 287             uint16_t a = float16_val(a_);
 288             a |= (1 << 9);
 289             return make_float16(a);
 290         }
 291     }
 292     return a_;
 293 }
 294
 295 /*----------------------------------------------------------------------------
 296 | Returns the result of converting the half-precision floating-point NaN
 297 | `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
 298 | exception is raised.
 299 *----------------------------------------------------------------------------*/
 300
 301 static commonNaNT float16ToCommonNaN(float16 a, float_status *status)
 302 {
 303     commonNaNT z;
 304
 305     if (float16_is_signaling_nan(a, status)) {
 306         float_raise(float_flag_invalid, status);
 307     }
 308     z.sign = float16_val(a) >> 15;
 309     z.low = 0;
 310     z.high = ((uint64_t) float16_val(a)) << 54;
 311     return z;
 312 }
 313
 314 /*----------------------------------------------------------------------------
 315 | Returns the result of converting the canonical NaN `a' to the half-
 316 | precision floating-point format.
 317 *----------------------------------------------------------------------------*/
 318
 319 static float16 commonNaNToFloat16(commonNaNT a, float_status *status)
 320 {
 321     uint16_t mantissa = a.high >> 54;
 322
 323     if (status->default_nan_mode) {
 324         return float16_default_nan(status);
 325     }
 326
 327     if (mantissa) {
 328         return make_float16(((((uint16_t) a.sign) << 15)
 329                              | (0x1F << 10) | mantissa));
 330     } else {
 331         return float16_default_nan(status);
 332     }
 333 }
 334
 335 #ifdef NO_SIGNALING_NANS
 336 int float32_is_quiet_nan(float32 a_, float_status *status)
 337 {
 338     return float32_is_any_nan(a_);
 339 }
 340
 341 int float32_is_signaling_nan(float32 a_, float_status *status)
 342 {
 343     return 0;
 344 }
 345 #else
 346 /*----------------------------------------------------------------------------
 347 | Returns 1 if the single-precision floating-point value `a' is a quiet
 348 | NaN; otherwise returns 0.
 349 *----------------------------------------------------------------------------*/
 350
 351 int float32_is_quiet_nan(float32 a_, float_status *status)
 352 {
 353     uint32_t a = float32_val(a_);
 354     if (status->snan_bit_is_one) {
 355         return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
 356     } else {
 357         return ((uint32_t)(a << 1) >= 0xFF800000);
 358     }
 359 }
 360
 361 /*----------------------------------------------------------------------------
 362 | Returns 1 if the single-precision floating-point value `a' is a signaling
 363 | NaN; otherwise returns 0.
 364 *----------------------------------------------------------------------------*/
 365
 366 int float32_is_signaling_nan(float32 a_, float_status *status)
 367 {
 368     uint32_t a = float32_val(a_);
 369     if (status->snan_bit_is_one) {
 370         return ((uint32_t)(a << 1) >= 0xFF800000);
 371     } else {
 372         return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF);
 373     }
 374 }
 375 #endif
 376
 377 /*----------------------------------------------------------------------------
 378 | Returns a quiet NaN if the single-precision floating point value `a' is a
 379 | signaling NaN; otherwise returns `a'.
 380 *----------------------------------------------------------------------------*/
 381
 382 float32 float32_maybe_silence_nan(float32 a_, float_status *status)
 383 {
 384     if (float32_is_signaling_nan(a_, status)) {
 385         if (status->snan_bit_is_one) {
 386 #ifdef TARGET_HPPA
 387             uint32_t a = float32_val(a_);
 388             a &= ~0x00400000;
 389             a |=  0x00200000;
 390             return make_float32(a);
 391 #else
 392             return float32_default_nan(status);
 393 #endif
 394         } else {
 395             uint32_t a = float32_val(a_);
 396             a |= (1 << 22);
 397             return make_float32(a);
 398         }
 399     }
 400     return a_;
 401 }
 402
 403 /*----------------------------------------------------------------------------
 404 | Returns the result of converting the single-precision floating-point NaN
 405 | `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
 406 | exception is raised.
 407 *----------------------------------------------------------------------------*/
 408
 409 static commonNaNT float32ToCommonNaN(float32 a, float_status *status)
 410 {
 411     commonNaNT z;
 412
 413     if (float32_is_signaling_nan(a, status)) {
 414         float_raise(float_flag_invalid, status);
 415     }
 416     z.sign = float32_val(a) >> 31;
 417     z.low = 0;
 418     z.high = ((uint64_t)float32_val(a)) << 41;
 419     return z;
 420 }
 421
 422 /*----------------------------------------------------------------------------
 423 | Returns the result of converting the canonical NaN `a' to the single-
 424 | precision floating-point format.
 425 *----------------------------------------------------------------------------*/
 426
 427 static float32 commonNaNToFloat32(commonNaNT a, float_status *status)
 428 {
 429     uint32_t mantissa = a.high >> 41;
 430
 431     if (status->default_nan_mode) {
 432         return float32_default_nan(status);
 433     }
 434
 435     if (mantissa) {
 436         return make_float32(
 437             (((uint32_t)a.sign) << 31) | 0x7F800000 | (a.high >> 41));
 438     } else {
 439         return float32_default_nan(status);
 440     }
 441 }
 442
 443 /*----------------------------------------------------------------------------
 444 | Select which NaN to propagate for a two-input operation.
 445 | IEEE754 doesn't specify all the details of this, so the
 446 | algorithm is target-specific.
 447 | The routine is passed various bits of information about the
 448 | two NaNs and should return 0 to select NaN a and 1 for NaN b.
 449 | Note that signalling NaNs are always squashed to quiet NaNs
 450 | by the caller, by calling floatXX_maybe_silence_nan() before
 451 | returning them.
 452 |
 453 | aIsLargerSignificand is only valid if both a and b are NaNs
 454 | of some kind, and is true if a has the larger significand,
 455 | or if both a and b have the same significand but a is
 456 | positive but b is negative. It is only needed for the x87
 457 | tie-break rule.
 458 *----------------------------------------------------------------------------*/
 459
 460 #if defined(TARGET_ARM)
 461 static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 462                    flag aIsLargerSignificand)
 463 {
 464     /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take
 465      * the first of:
 466      *  1. A if it is signaling
 467      *  2. B if it is signaling
 468      *  3. A (quiet)
 469      *  4. B (quiet)
 470      * A signaling NaN is always quietened before returning it.
 471      */
 472     if (aIsSNaN) {
 473         return 0;
 474     } else if (bIsSNaN) {
 475         return 1;
 476     } else if (aIsQNaN) {
 477         return 0;
 478     } else {
 479         return 1;
 480     }
 481 }
 482 #elif defined(TARGET_MIPS) || defined(TARGET_HPPA)
 483 static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 484                     flag aIsLargerSignificand)
 485 {
 486     /* According to MIPS specifications, if one of the two operands is
 487      * a sNaN, a new qNaN has to be generated. This is done in
 488      * floatXX_maybe_silence_nan(). For qNaN inputs the specifications
 489      * says: "When possible, this QNaN result is one of the operand QNaN
 490      * values." In practice it seems that most implementations choose
 491      * the first operand if both operands are qNaN. In short this gives
 492      * the following rules:
 493      *  1. A if it is signaling
 494      *  2. B if it is signaling
 495      *  3. A (quiet)
 496      *  4. B (quiet)
 497      * A signaling NaN is always silenced before returning it.
 498      */
 499     if (aIsSNaN) {
 500         return 0;
 501     } else if (bIsSNaN) {
 502         return 1;
 503     } else if (aIsQNaN) {
 504         return 0;
 505     } else {
 506         return 1;
 507     }
 508 }
 509 #elif defined(TARGET_PPC) || defined(TARGET_XTENSA)
 510 static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 511                    flag aIsLargerSignificand)
 512 {
 513     /* PowerPC propagation rules:
 514      *  1. A if it sNaN or qNaN
 515      *  2. B if it sNaN or qNaN
 516      * A signaling NaN is always silenced before returning it.
 517      */
 518     if (aIsSNaN || aIsQNaN) {
 519         return 0;
 520     } else {
 521         return 1;
 522     }
 523 }
 524 #elif defined(TARGET_M68K)
 525 static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 526                    flag aIsLargerSignificand)
 527 {
 528     /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
 529      * 3.4 FLOATING-POINT INSTRUCTION DETAILS
 530      * If either operand, but not both operands, of an operation is a
 531      * nonsignaling NaN, then that NaN is returned as the result. If both
 532      * operands are nonsignaling NaNs, then the destination operand
 533      * nonsignaling NaN is returned as the result.
 534      * If either operand to an operation is a signaling NaN (SNaN), then the
 535      * SNaN bit is set in the FPSR EXC byte. If the SNaN exception enable bit
 536      * is set in the FPCR ENABLE byte, then the exception is taken and the
 537      * destination is not modified. If the SNaN exception enable bit is not
 538      * set, setting the SNaN bit in the operand to a one converts the SNaN to
 539      * a nonsignaling NaN. The operation then continues as described in the
 540      * preceding paragraph for nonsignaling NaNs.
 541      */
 542     if (aIsQNaN || aIsSNaN) { /* a is the destination operand */
 543         return 0; /* return the destination operand */
 544     } else {
 545         return 1; /* return b */
 546     }
 547 }
 548 #else
 549 static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 550                     flag aIsLargerSignificand)
 551 {
 552     /* This implements x87 NaN propagation rules:
 553      * SNaN + QNaN => return the QNaN
 554      * two SNaNs => return the one with the larger significand, silenced
 555      * two QNaNs => return the one with the larger significand
 556      * SNaN and a non-NaN => return the SNaN, silenced
 557      * QNaN and a non-NaN => return the QNaN
 558      *
 559      * If we get down to comparing significands and they are the same,
 560      * return the NaN with the positive sign bit (if any).
 561      */
 562     if (aIsSNaN) {
 563         if (bIsSNaN) {
 564             return aIsLargerSignificand ? 0 : 1;
 565         }
 566         return bIsQNaN ? 1 : 0;
 567     } else if (aIsQNaN) {
 568         if (bIsSNaN || !bIsQNaN) {
 569             return 0;
 570         } else {
 571             return aIsLargerSignificand ? 0 : 1;
 572         }
 573     } else {
 574         return 1;
 575     }
 576 }
 577 #endif
 578
 579 /*----------------------------------------------------------------------------
 580 | Select which NaN to propagate for a three-input operation.
 581 | For the moment we assume that no CPU needs the 'larger significand'
 582 | information.
 583 | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
 584 *----------------------------------------------------------------------------*/
 585 #if defined(TARGET_ARM)
 586 static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 587                          flag cIsQNaN, flag cIsSNaN, flag infzero,
 588                          float_status *status)
 589 {
 590     /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
 591      * the default NaN
 592      */
 593     if (infzero && cIsQNaN) {
 594         float_raise(float_flag_invalid, status);
 595         return 3;
 596     }
 597
 598     /* This looks different from the ARM ARM pseudocode, because the ARM ARM
 599      * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
 600      */
 601     if (cIsSNaN) {
 602         return 2;
 603     } else if (aIsSNaN) {
 604         return 0;
 605     } else if (bIsSNaN) {
 606         return 1;
 607     } else if (cIsQNaN) {
 608         return 2;
 609     } else if (aIsQNaN) {
 610         return 0;
 611     } else {
 612         return 1;
 613     }
 614 }
 615 #elif defined(TARGET_MIPS)
 616 static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 617                          flag cIsQNaN, flag cIsSNaN, flag infzero,
 618                          float_status *status)
 619 {
 620     /* For MIPS, the (inf,zero,qnan) case sets InvalidOp and returns
 621      * the default NaN
 622      */
 623     if (infzero) {
 624         float_raise(float_flag_invalid, status);
 625         return 3;
 626     }
 627
 628     if (status->snan_bit_is_one) {
 629         /* Prefer sNaN over qNaN, in the a, b, c order. */
 630         if (aIsSNaN) {
 631             return 0;
 632         } else if (bIsSNaN) {
 633             return 1;
 634         } else if (cIsSNaN) {
 635             return 2;
 636         } else if (aIsQNaN) {
 637             return 0;
 638         } else if (bIsQNaN) {
 639             return 1;
 640         } else {
 641             return 2;
 642         }
 643     } else {
 644         /* Prefer sNaN over qNaN, in the c, a, b order. */
 645         if (cIsSNaN) {
 646             return 2;
 647         } else if (aIsSNaN) {
 648             return 0;
 649         } else if (bIsSNaN) {
 650             return 1;
 651         } else if (cIsQNaN) {
 652             return 2;
 653         } else if (aIsQNaN) {
 654             return 0;
 655         } else {
 656             return 1;
 657         }
 658     }
 659 }
 660 #elif defined(TARGET_PPC)
 661 static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 662                          flag cIsQNaN, flag cIsSNaN, flag infzero,
 663                          float_status *status)
 664 {
 665     /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
 666      * to return an input NaN if we have one (ie c) rather than generating
 667      * a default NaN
 668      */
 669     if (infzero) {
 670         float_raise(float_flag_invalid, status);
 671         return 2;
 672     }
 673
 674     /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
 675      * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
 676      */
 677     if (aIsSNaN || aIsQNaN) {
 678         return 0;
 679     } else if (cIsSNaN || cIsQNaN) {
 680         return 2;
 681     } else {
 682         return 1;
 683     }
 684 }
 685 #else
 686 /* A default implementation: prefer a to b to c.
 687  * This is unlikely to actually match any real implementation.
 688  */
 689 static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
 690                          flag cIsQNaN, flag cIsSNaN, flag infzero,
 691                          float_status *status)
 692 {
 693     if (aIsSNaN || aIsQNaN) {
 694         return 0;
 695     } else if (bIsSNaN || bIsQNaN) {
 696         return 1;
 697     } else {
 698         return 2;
 699     }
 700 }
 701 #endif
 702
 703 /*----------------------------------------------------------------------------
 704 | Takes two single-precision floating-point values `a' and `b', one of which
 705 | is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a
 706 | signaling NaN, the invalid exception is raised.
 707 *----------------------------------------------------------------------------*/
 708
 709 static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status)
 710 {
 711     flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
 712     flag aIsLargerSignificand;
 713     uint32_t av, bv;
 714
 715     aIsQuietNaN = float32_is_quiet_nan(a, status);
 716     aIsSignalingNaN = float32_is_signaling_nan(a, status);
 717     bIsQuietNaN = float32_is_quiet_nan(b, status);
 718     bIsSignalingNaN = float32_is_signaling_nan(b, status);
 719     av = float32_val(a);
 720     bv = float32_val(b);
 721
 722     if (aIsSignalingNaN | bIsSignalingNaN) {
 723         float_raise(float_flag_invalid, status);
 724     }
 725
 726     if (status->default_nan_mode) {
 727         return float32_default_nan(status);
 728     }
 729
 730     if ((uint32_t)(av << 1) < (uint32_t)(bv << 1)) {
 731         aIsLargerSignificand = 0;
 732     } else if ((uint32_t)(bv << 1) < (uint32_t)(av << 1)) {
 733         aIsLargerSignificand = 1;
 734     } else {
 735         aIsLargerSignificand = (av < bv) ? 1 : 0;
 736     }
 737
 738     if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
 739                 aIsLargerSignificand)) {
 740         return float32_maybe_silence_nan(b, status);
 741     } else {
 742         return float32_maybe_silence_nan(a, status);
 743     }
 744 }
 745
 746 #ifdef NO_SIGNALING_NANS
 747 int float64_is_quiet_nan(float64 a_, float_status *status)
 748 {
 749     return float64_is_any_nan(a_);
 750 }
 751
 752 int float64_is_signaling_nan(float64 a_, float_status *status)
 753 {
 754     return 0;
 755 }
 756 #else
 757 /*----------------------------------------------------------------------------
 758 | Returns 1 if the double-precision floating-point value `a' is a quiet
 759 | NaN; otherwise returns 0.
 760 *----------------------------------------------------------------------------*/
 761
 762 int float64_is_quiet_nan(float64 a_, float_status *status)
 763 {
 764     uint64_t a = float64_val(a_);
 765     if (status->snan_bit_is_one) {
 766         return (((a >> 51) & 0xFFF) == 0xFFE)
 767             && (a & 0x0007FFFFFFFFFFFFULL);
 768     } else {
 769         return ((a << 1) >= 0xFFF0000000000000ULL);
 770     }
 771 }
 772
 773 /*----------------------------------------------------------------------------
 774 | Returns 1 if the double-precision floating-point value `a' is a signaling
 775 | NaN; otherwise returns 0.
 776 *----------------------------------------------------------------------------*/
 777
 778 int float64_is_signaling_nan(float64 a_, float_status *status)
 779 {
 780     uint64_t a = float64_val(a_);
 781     if (status->snan_bit_is_one) {
 782         return ((a << 1) >= 0xFFF0000000000000ULL);
 783     } else {
 784         return (((a >> 51) & 0xFFF) == 0xFFE)
 785             && (a & LIT64(0x0007FFFFFFFFFFFF));
 786     }
 787 }
 788 #endif
 789
 790 /*----------------------------------------------------------------------------
 791 | Returns a quiet NaN if the double-precision floating point value `a' is a
 792 | signaling NaN; otherwise returns `a'.
 793 *----------------------------------------------------------------------------*/
 794
 795 float64 float64_maybe_silence_nan(float64 a_, float_status *status)
 796 {
 797     if (float64_is_signaling_nan(a_, status)) {
 798         if (status->snan_bit_is_one) {
 799 #ifdef TARGET_HPPA
 800             uint64_t a = float64_val(a_);
 801             a &= ~0x0008000000000000ULL;
 802             a |=  0x0004000000000000ULL;
 803             return make_float64(a);
 804 #else
 805             return float64_default_nan(status);
 806 #endif
 807         } else {
 808             uint64_t a = float64_val(a_);
 809             a |= LIT64(0x0008000000000000);
 810             return make_float64(a);
 811         }
 812     }
 813     return a_;
 814 }
 815
 816 /*----------------------------------------------------------------------------
 817 | Returns the result of converting the double-precision floating-point NaN
 818 | `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
 819 | exception is raised.
 820 *----------------------------------------------------------------------------*/
 821
 822 static commonNaNT float64ToCommonNaN(float64 a, float_status *status)
 823 {
 824     commonNaNT z;
 825
 826     if (float64_is_signaling_nan(a, status)) {
 827         float_raise(float_flag_invalid, status);
 828     }
 829     z.sign = float64_val(a) >> 63;
 830     z.low = 0;
 831     z.high = float64_val(a) << 12;
 832     return z;
 833 }
 834
 835 /*----------------------------------------------------------------------------
 836 | Returns the result of converting the canonical NaN `a' to the double-
 837 | precision floating-point format.
 838 *----------------------------------------------------------------------------*/
 839
 840 static float64 commonNaNToFloat64(commonNaNT a, float_status *status)
 841 {
 842     uint64_t mantissa = a.high >> 12;
 843
 844     if (status->default_nan_mode) {
 845         return float64_default_nan(status);
 846     }
 847
 848     if (mantissa) {
 849         return make_float64(
 850               (((uint64_t) a.sign) << 63)
 851             | LIT64(0x7FF0000000000000)
 852             | (a.high >> 12));
 853     } else {
 854         return float64_default_nan(status);
 855     }
 856 }
 857
 858 /*----------------------------------------------------------------------------
 859 | Takes two double-precision floating-point values `a' and `b', one of which
 860 | is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a
 861 | signaling NaN, the invalid exception is raised.
 862 *----------------------------------------------------------------------------*/
 863
 864 static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status)
 865 {
 866     flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
 867     flag aIsLargerSignificand;
 868     uint64_t av, bv;
 869
 870     aIsQuietNaN = float64_is_quiet_nan(a, status);
 871     aIsSignalingNaN = float64_is_signaling_nan(a, status);
 872     bIsQuietNaN = float64_is_quiet_nan(b, status);
 873     bIsSignalingNaN = float64_is_signaling_nan(b, status);
 874     av = float64_val(a);
 875     bv = float64_val(b);
 876
 877     if (aIsSignalingNaN | bIsSignalingNaN) {
 878         float_raise(float_flag_invalid, status);
 879     }
 880
 881     if (status->default_nan_mode) {
 882         return float64_default_nan(status);
 883     }
 884
 885     if ((uint64_t)(av << 1) < (uint64_t)(bv << 1)) {
 886         aIsLargerSignificand = 0;
 887     } else if ((uint64_t)(bv << 1) < (uint64_t)(av << 1)) {
 888         aIsLargerSignificand = 1;
 889     } else {
 890         aIsLargerSignificand = (av < bv) ? 1 : 0;
 891     }
 892
 893     if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
 894                 aIsLargerSignificand)) {
 895         return float64_maybe_silence_nan(b, status);
 896     } else {
 897         return float64_maybe_silence_nan(a, status);
 898     }
 899 }
 900
 901 #ifdef NO_SIGNALING_NANS
 902 int floatx80_is_quiet_nan(floatx80 a_, float_status *status)
 903 {
 904     return floatx80_is_any_nan(a_);
 905 }
 906
 907 int floatx80_is_signaling_nan(floatx80 a_, float_status *status)
 908 {
 909     return 0;
 910 }
 911 #else
 912 /*----------------------------------------------------------------------------
 913 | Returns 1 if the extended double-precision floating-point value `a' is a
 914 | quiet NaN; otherwise returns 0. This slightly differs from the same
 915 | function for other types as floatx80 has an explicit bit.
 916 *----------------------------------------------------------------------------*/
 917
 918 int floatx80_is_quiet_nan(floatx80 a, float_status *status)
 919 {
 920     if (status->snan_bit_is_one) {
 921         uint64_t aLow;
 922
 923         aLow = a.low & ~0x4000000000000000ULL;
 924         return ((a.high & 0x7FFF) == 0x7FFF)
 925             && (aLow << 1)
 926             && (a.low == aLow);
 927     } else {
 928         return ((a.high & 0x7FFF) == 0x7FFF)
 929             && (LIT64(0x8000000000000000) <= ((uint64_t)(a.low << 1)));
 930     }
 931 }
 932
 933 /*----------------------------------------------------------------------------
 934 | Returns 1 if the extended double-precision floating-point value `a' is a
 935 | signaling NaN; otherwise returns 0. This slightly differs from the same
 936 | function for other types as floatx80 has an explicit bit.
 937 *----------------------------------------------------------------------------*/
 938
 939 int floatx80_is_signaling_nan(floatx80 a, float_status *status)
 940 {
 941     if (status->snan_bit_is_one) {
 942         return ((a.high & 0x7FFF) == 0x7FFF)
 943             && ((a.low << 1) >= 0x8000000000000000ULL);
 944     } else {
 945         uint64_t aLow;
 946
 947         aLow = a.low & ~LIT64(0x4000000000000000);
 948         return ((a.high & 0x7FFF) == 0x7FFF)
 949             && (uint64_t)(aLow << 1)
 950             && (a.low == aLow);
 951     }
 952 }
 953 #endif
 954
 955 /*----------------------------------------------------------------------------
 956 | Returns a quiet NaN if the extended double-precision floating point value
 957 | `a' is a signaling NaN; otherwise returns `a'.
 958 *----------------------------------------------------------------------------*/
 959
 960 floatx80 floatx80_maybe_silence_nan(floatx80 a, float_status *status)
 961 {
 962     if (floatx80_is_signaling_nan(a, status)) {
 963         if (status->snan_bit_is_one) {
 964             a = floatx80_default_nan(status);
 965         } else {
 966             a.low |= LIT64(0xC000000000000000);
 967             return a;
 968         }
 969     }
 970     return a;
 971 }
 972
 973 /*----------------------------------------------------------------------------
 974 | Returns the result of converting the extended double-precision floating-
 975 | point NaN `a' to the canonical NaN format.  If `a' is a signaling NaN, the
 976 | invalid exception is raised.
 977 *----------------------------------------------------------------------------*/
 978
 979 static commonNaNT floatx80ToCommonNaN(floatx80 a, float_status *status)
 980 {
 981     floatx80 dflt;
 982     commonNaNT z;
 983
 984     if (floatx80_is_signaling_nan(a, status)) {
 985         float_raise(float_flag_invalid, status);
 986     }
 987     if (a.low >> 63) {
 988         z.sign = a.high >> 15;
 989         z.low = 0;
 990         z.high = a.low << 1;
 991     } else {
 992         dflt = floatx80_default_nan(status);
 993         z.sign = dflt.high >> 15;
 994         z.low = 0;
 995         z.high = dflt.low << 1;
 996     }
 997     return z;
 998 }
 999
1000 /*----------------------------------------------------------------------------
1001 | Returns the result of converting the canonical NaN `a' to the extended
1002 | double-precision floating-point format.
1003 *----------------------------------------------------------------------------*/
1004
1005 static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status)
1006 {
1007     floatx80 z;
1008
1009     if (status->default_nan_mode) {
1010         return floatx80_default_nan(status);
1011     }
1012
1013     if (a.high >> 1) {
1014         z.low = LIT64(0x8000000000000000) | a.high >> 1;
1015         z.high = (((uint16_t)a.sign) << 15) | 0x7FFF;
1016     } else {
1017         z = floatx80_default_nan(status);
1018     }
1019     return z;
1020 }
1021
1022 /*----------------------------------------------------------------------------
1023 | Takes two extended double-precision floating-point values `a' and `b', one
1024 | of which is a NaN, and returns the appropriate NaN result.  If either `a' or
1025 | `b' is a signaling NaN, the invalid exception is raised.
1026 *----------------------------------------------------------------------------*/
1027
1028 floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
1029 {
1030     flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
1031     flag aIsLargerSignificand;
1032
1033     aIsQuietNaN = floatx80_is_quiet_nan(a, status);
1034     aIsSignalingNaN = floatx80_is_signaling_nan(a, status);
1035     bIsQuietNaN = floatx80_is_quiet_nan(b, status);
1036     bIsSignalingNaN = floatx80_is_signaling_nan(b, status);
1037
1038     if (aIsSignalingNaN | bIsSignalingNaN) {
1039         float_raise(float_flag_invalid, status);
1040     }
1041
1042     if (status->default_nan_mode) {
1043         return floatx80_default_nan(status);
1044     }
1045
1046     if (a.low < b.low) {
1047         aIsLargerSignificand = 0;
1048     } else if (b.low < a.low) {
1049         aIsLargerSignificand = 1;
1050     } else {
1051         aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
1052     }
1053
1054     if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
1055                 aIsLargerSignificand)) {
1056         return floatx80_maybe_silence_nan(b, status);
1057     } else {
1058         return floatx80_maybe_silence_nan(a, status);
1059     }
1060 }
1061
1062 #ifdef NO_SIGNALING_NANS
1063 int float128_is_quiet_nan(float128 a_, float_status *status)
1064 {
1065     return float128_is_any_nan(a_);
1066 }
1067
1068 int float128_is_signaling_nan(float128 a_, float_status *status)
1069 {
1070     return 0;
1071 }
1072 #else
1073 /*----------------------------------------------------------------------------
1074 | Returns 1 if the quadruple-precision floating-point value `a' is a quiet
1075 | NaN; otherwise returns 0.
1076 *----------------------------------------------------------------------------*/
1077
1078 int float128_is_quiet_nan(float128 a, float_status *status)
1079 {
1080     if (status->snan_bit_is_one) {
1081         return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
1082             && (a.low || (a.high & 0x00007FFFFFFFFFFFULL));
1083     } else {
1084         return ((a.high << 1) >= 0xFFFF000000000000ULL)
1085             && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
1086     }
1087 }
1088
1089 /*----------------------------------------------------------------------------
1090 | Returns 1 if the quadruple-precision floating-point value `a' is a
1091 | signaling NaN; otherwise returns 0.
1092 *----------------------------------------------------------------------------*/
1093
1094 int float128_is_signaling_nan(float128 a, float_status *status)
1095 {
1096     if (status->snan_bit_is_one) {
1097         return ((a.high << 1) >= 0xFFFF000000000000ULL)
1098             && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL));
1099     } else {
1100         return (((a.high >> 47) & 0xFFFF) == 0xFFFE)
1101             && (a.low || (a.high & LIT64(0x00007FFFFFFFFFFF)));
1102     }
1103 }
1104 #endif
1105
1106 /*----------------------------------------------------------------------------
1107 | Returns a quiet NaN if the quadruple-precision floating point value `a' is
1108 | a signaling NaN; otherwise returns `a'.
1109 *----------------------------------------------------------------------------*/
1110
1111 float128 float128_maybe_silence_nan(float128 a, float_status *status)
1112 {
1113     if (float128_is_signaling_nan(a, status)) {
1114         if (status->snan_bit_is_one) {
1115             a = float128_default_nan(status);
1116         } else {
1117             a.high |= LIT64(0x0000800000000000);
1118             return a;
1119         }
1120     }
1121     return a;
1122 }
1123
1124 /*----------------------------------------------------------------------------
1125 | Returns the result of converting the quadruple-precision floating-point NaN
1126 | `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
1127 | exception is raised.
1128 *----------------------------------------------------------------------------*/
1129
1130 static commonNaNT float128ToCommonNaN(float128 a, float_status *status)
1131 {
1132     commonNaNT z;
1133
1134     if (float128_is_signaling_nan(a, status)) {
1135         float_raise(float_flag_invalid, status);
1136     }
1137     z.sign = a.high >> 63;
1138     shortShift128Left(a.high, a.low, 16, &z.high, &z.low);
1139     return z;
1140 }
1141
1142 /*----------------------------------------------------------------------------
1143 | Returns the result of converting the canonical NaN `a' to the quadruple-
1144 | precision floating-point format.
1145 *----------------------------------------------------------------------------*/
1146
1147 static float128 commonNaNToFloat128(commonNaNT a, float_status *status)
1148 {
1149     float128 z;
1150
1151     if (status->default_nan_mode) {
1152         return float128_default_nan(status);
1153     }
1154
1155     shift128Right(a.high, a.low, 16, &z.high, &z.low);
1156     z.high |= (((uint64_t)a.sign) << 63) | LIT64(0x7FFF000000000000);
1157     return z;
1158 }
1159
1160 /*----------------------------------------------------------------------------
1161 | Takes two quadruple-precision floating-point values `a' and `b', one of
1162 | which is a NaN, and returns the appropriate NaN result.  If either `a' or
1163 | `b' is a signaling NaN, the invalid exception is raised.
1164 *----------------------------------------------------------------------------*/
1165
1166 static float128 propagateFloat128NaN(float128 a, float128 b,
1167                                      float_status *status)
1168 {
1169     flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
1170     flag aIsLargerSignificand;
1171
1172     aIsQuietNaN = float128_is_quiet_nan(a, status);
1173     aIsSignalingNaN = float128_is_signaling_nan(a, status);
1174     bIsQuietNaN = float128_is_quiet_nan(b, status);
1175     bIsSignalingNaN = float128_is_signaling_nan(b, status);
1176
1177     if (aIsSignalingNaN | bIsSignalingNaN) {
1178         float_raise(float_flag_invalid, status);
1179     }
1180
1181     if (status->default_nan_mode) {
1182         return float128_default_nan(status);
1183     }
1184
1185     if (lt128(a.high << 1, a.low, b.high << 1, b.low)) {
1186         aIsLargerSignificand = 0;
1187     } else if (lt128(b.high << 1, b.low, a.high << 1, a.low)) {
1188         aIsLargerSignificand = 1;
1189     } else {
1190         aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
1191     }
1192
1193     if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
1194                 aIsLargerSignificand)) {
1195         return float128_maybe_silence_nan(b, status);
1196     } else {
1197         return float128_maybe_silence_nan(a, status);
1198     }
1199 }