hw/char/lm32_uart.c

   1 /*
   2  *  QEMU model of the LatticeMico32 UART block.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://www.latticesemi.com/documents/mico32uart.pdf
  22  */
  23
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/hw.h"
  27 #include "hw/sysbus.h"
  28 #include "trace.h"
  29 #include "sysemu/char.h"
  30 #include "qemu/error-report.h"
  31
  32 enum {
  33     R_RXTX = 0,
  34     R_IER,
  35     R_IIR,
  36     R_LCR,
  37     R_MCR,
  38     R_LSR,
  39     R_MSR,
  40     R_DIV,
  41     R_MAX
  42 };
  43
  44 enum {
  45     IER_RBRI = (1<<0),
  46     IER_THRI = (1<<1),
  47     IER_RLSI = (1<<2),
  48     IER_MSI  = (1<<3),
  49 };
  50
  51 enum {
  52     IIR_STAT = (1<<0),
  53     IIR_ID0  = (1<<1),
  54     IIR_ID1  = (1<<2),
  55 };
  56
  57 enum {
  58     LCR_WLS0 = (1<<0),
  59     LCR_WLS1 = (1<<1),
  60     LCR_STB  = (1<<2),
  61     LCR_PEN  = (1<<3),
  62     LCR_EPS  = (1<<4),
  63     LCR_SP   = (1<<5),
  64     LCR_SB   = (1<<6),
  65 };
  66
  67 enum {
  68     MCR_DTR  = (1<<0),
  69     MCR_RTS  = (1<<1),
  70 };
  71
  72 enum {
  73     LSR_DR   = (1<<0),
  74     LSR_OE   = (1<<1),
  75     LSR_PE   = (1<<2),
  76     LSR_FE   = (1<<3),
  77     LSR_BI   = (1<<4),
  78     LSR_THRE = (1<<5),
  79     LSR_TEMT = (1<<6),
  80 };
  81
  82 enum {
  83     MSR_DCTS = (1<<0),
  84     MSR_DDSR = (1<<1),
  85     MSR_TERI = (1<<2),
  86     MSR_DDCD = (1<<3),
  87     MSR_CTS  = (1<<4),
  88     MSR_DSR  = (1<<5),
  89     MSR_RI   = (1<<6),
  90     MSR_DCD  = (1<<7),
  91 };
  92
  93 #define TYPE_LM32_UART "lm32-uart"
  94 #define LM32_UART(obj) OBJECT_CHECK(LM32UartState, (obj), TYPE_LM32_UART)
  95
  96 struct LM32UartState {
  97     SysBusDevice parent_obj;
  98
  99     MemoryRegion iomem;
 100     CharDriverState *chr;
 101     qemu_irq irq;
 102
 103     uint32_t regs[R_MAX];
 104 };
 105 typedef struct LM32UartState LM32UartState;
 106
 107 static void uart_update_irq(LM32UartState *s)
 108 {
 109     unsigned int irq;
 110
 111     if ((s->regs[R_LSR] & (LSR_OE | LSR_PE | LSR_FE | LSR_BI))
 112             && (s->regs[R_IER] & IER_RLSI)) {
 113         irq = 1;
 114         s->regs[R_IIR] = IIR_ID1 | IIR_ID0;
 115     } else if ((s->regs[R_LSR] & LSR_DR) && (s->regs[R_IER] & IER_RBRI)) {
 116         irq = 1;
 117         s->regs[R_IIR] = IIR_ID1;
 118     } else if ((s->regs[R_LSR] & LSR_THRE) && (s->regs[R_IER] & IER_THRI)) {
 119         irq = 1;
 120         s->regs[R_IIR] = IIR_ID0;
 121     } else if ((s->regs[R_MSR] & 0x0f) && (s->regs[R_IER] & IER_MSI)) {
 122         irq = 1;
 123         s->regs[R_IIR] = 0;
 124     } else {
 125         irq = 0;
 126         s->regs[R_IIR] = IIR_STAT;
 127     }
 128
 129     trace_lm32_uart_irq_state(irq);
 130     qemu_set_irq(s->irq, irq);
 131 }
 132
 133 static uint64_t uart_read(void *opaque, hwaddr addr,
 134                           unsigned size)
 135 {
 136     LM32UartState *s = opaque;
 137     uint32_t r = 0;
 138
 139     addr >>= 2;
 140     switch (addr) {
 141     case R_RXTX:
 142         r = s->regs[R_RXTX];
 143         s->regs[R_LSR] &= ~LSR_DR;
 144         uart_update_irq(s);
 145         qemu_chr_accept_input(s->chr);
 146         break;
 147     case R_IIR:
 148     case R_LSR:
 149     case R_MSR:
 150         r = s->regs[addr];
 151         break;
 152     case R_IER:
 153     case R_LCR:
 154     case R_MCR:
 155     case R_DIV:
 156         error_report("lm32_uart: read access to write only register 0x"
 157                 TARGET_FMT_plx, addr << 2);
 158         break;
 159     default:
 160         error_report("lm32_uart: read access to unknown register 0x"
 161                 TARGET_FMT_plx, addr << 2);
 162         break;
 163     }
 164
 165     trace_lm32_uart_memory_read(addr << 2, r);
 166     return r;
 167 }
 168
 169 static void uart_write(void *opaque, hwaddr addr,
 170                        uint64_t value, unsigned size)
 171 {
 172     LM32UartState *s = opaque;
 173     unsigned char ch = value;
 174
 175     trace_lm32_uart_memory_write(addr, value);
 176
 177     addr >>= 2;
 178     switch (addr) {
 179     case R_RXTX:
 180         if (s->chr) {
 181             /* XXX this blocks entire thread. Rewrite to use
 182              * qemu_chr_fe_write and background I/O callbacks */
 183             qemu_chr_fe_write_all(s->chr, &ch, 1);
 184         }
 185         break;
 186     case R_IER:
 187     case R_LCR:
 188     case R_MCR:
 189     case R_DIV:
 190         s->regs[addr] = value;
 191         break;
 192     case R_IIR:
 193     case R_LSR:
 194     case R_MSR:
 195         error_report("lm32_uart: write access to read only register 0x"
 196                 TARGET_FMT_plx, addr << 2);
 197         break;
 198     default:
 199         error_report("lm32_uart: write access to unknown register 0x"
 200                 TARGET_FMT_plx, addr << 2);
 201         break;
 202     }
 203     uart_update_irq(s);
 204 }
 205
 206 static const MemoryRegionOps uart_ops = {
 207     .read = uart_read,
 208     .write = uart_write,
 209     .endianness = DEVICE_NATIVE_ENDIAN,
 210     .valid = {
 211         .min_access_size = 4,
 212         .max_access_size = 4,
 213     },
 214 };
 215
 216 static void uart_rx(void *opaque, const uint8_t *buf, int size)
 217 {
 218     LM32UartState *s = opaque;
 219
 220     if (s->regs[R_LSR] & LSR_DR) {
 221         s->regs[R_LSR] |= LSR_OE;
 222     }
 223
 224     s->regs[R_LSR] |= LSR_DR;
 225     s->regs[R_RXTX] = *buf;
 226
 227     uart_update_irq(s);
 228 }
 229
 230 static int uart_can_rx(void *opaque)
 231 {
 232     LM32UartState *s = opaque;
 233
 234     return !(s->regs[R_LSR] & LSR_DR);
 235 }
 236
 237 static void uart_event(void *opaque, int event)
 238 {
 239 }
 240
 241 static void uart_reset(DeviceState *d)
 242 {
 243     LM32UartState *s = LM32_UART(d);
 244     int i;
 245
 246     for (i = 0; i < R_MAX; i++) {
 247         s->regs[i] = 0;
 248     }
 249
 250     /* defaults */
 251     s->regs[R_LSR] = LSR_THRE | LSR_TEMT;
 252 }
 253
 254 static void lm32_uart_init(Object *obj)
 255 {
 256     LM32UartState *s = LM32_UART(obj);
 257     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 258
 259     sysbus_init_irq(dev, &s->irq);
 260
 261     memory_region_init_io(&s->iomem, obj, &uart_ops, s,
 262                           "uart", R_MAX * 4);
 263     sysbus_init_mmio(dev, &s->iomem);
 264 }
 265
 266 static void lm32_uart_realize(DeviceState *dev, Error **errp)
 267 {
 268     LM32UartState *s = LM32_UART(dev);
 269
 270     if (s->chr) {
 271         qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
 272     }
 273 }
 274
 275 static const VMStateDescription vmstate_lm32_uart = {
 276     .name = "lm32-uart",
 277     .version_id = 1,
 278     .minimum_version_id = 1,
 279     .fields = (VMStateField[]) {
 280         VMSTATE_UINT32_ARRAY(regs, LM32UartState, R_MAX),
 281         VMSTATE_END_OF_LIST()
 282     }
 283 };
 284
 285 static Property lm32_uart_properties[] = {
 286     DEFINE_PROP_CHR("chardev", LM32UartState, chr),
 287     DEFINE_PROP_END_OF_LIST(),
 288 };
 289
 290 static void lm32_uart_class_init(ObjectClass *klass, void *data)
 291 {
 292     DeviceClass *dc = DEVICE_CLASS(klass);
 293
 294     dc->reset = uart_reset;
 295     dc->vmsd = &vmstate_lm32_uart;
 296     dc->props = lm32_uart_properties;
 297     dc->realize = lm32_uart_realize;
 298 }
 299
 300 static const TypeInfo lm32_uart_info = {
 301     .name          = TYPE_LM32_UART,
 302     .parent        = TYPE_SYS_BUS_DEVICE,
 303     .instance_size = sizeof(LM32UartState),
 304     .instance_init = lm32_uart_init,
 305     .class_init    = lm32_uart_class_init,
 306 };
 307
 308 static void lm32_uart_register_types(void)
 309 {
 310     type_register_static(&lm32_uart_info);
 311 }
 312
 313 type_init(lm32_uart_register_types)