4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
28 #include "translate.h"
29 #include "qemu/host-utils.h"
31 #include "exec/gen-icount.h"
37 static TCGv_i64 cpu_X
[32];
38 static TCGv_i64 cpu_pc
;
39 static TCGv_i32 cpu_NF
, cpu_ZF
, cpu_CF
, cpu_VF
;
41 /* Load/store exclusive handling */
42 static TCGv_i64 cpu_exclusive_addr
;
43 static TCGv_i64 cpu_exclusive_val
;
44 static TCGv_i64 cpu_exclusive_high
;
45 #ifdef CONFIG_USER_ONLY
46 static TCGv_i64 cpu_exclusive_test
;
47 static TCGv_i32 cpu_exclusive_info
;
50 static const char *regnames
[] = {
51 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
52 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
53 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
54 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
58 A64_SHIFT_TYPE_LSL
= 0,
59 A64_SHIFT_TYPE_LSR
= 1,
60 A64_SHIFT_TYPE_ASR
= 2,
61 A64_SHIFT_TYPE_ROR
= 3
64 /* initialize TCG globals. */
65 void a64_translate_init(void)
69 cpu_pc
= tcg_global_mem_new_i64(TCG_AREG0
,
70 offsetof(CPUARMState
, pc
),
72 for (i
= 0; i
< 32; i
++) {
73 cpu_X
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
74 offsetof(CPUARMState
, xregs
[i
]),
78 cpu_NF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, NF
), "NF");
79 cpu_ZF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, ZF
), "ZF");
80 cpu_CF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, CF
), "CF");
81 cpu_VF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, VF
), "VF");
83 cpu_exclusive_addr
= tcg_global_mem_new_i64(TCG_AREG0
,
84 offsetof(CPUARMState
, exclusive_addr
), "exclusive_addr");
85 cpu_exclusive_val
= tcg_global_mem_new_i64(TCG_AREG0
,
86 offsetof(CPUARMState
, exclusive_val
), "exclusive_val");
87 cpu_exclusive_high
= tcg_global_mem_new_i64(TCG_AREG0
,
88 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
89 #ifdef CONFIG_USER_ONLY
90 cpu_exclusive_test
= tcg_global_mem_new_i64(TCG_AREG0
,
91 offsetof(CPUARMState
, exclusive_test
), "exclusive_test");
92 cpu_exclusive_info
= tcg_global_mem_new_i32(TCG_AREG0
,
93 offsetof(CPUARMState
, exclusive_info
), "exclusive_info");
97 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
98 fprintf_function cpu_fprintf
, int flags
)
100 ARMCPU
*cpu
= ARM_CPU(cs
);
101 CPUARMState
*env
= &cpu
->env
;
102 uint32_t psr
= pstate_read(env
);
105 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
106 env
->pc
, env
->xregs
[31]);
107 for (i
= 0; i
< 31; i
++) {
108 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
110 cpu_fprintf(f
, "\n");
115 cpu_fprintf(f
, "PSTATE=%08x (flags %c%c%c%c)\n",
117 psr
& PSTATE_N
? 'N' : '-',
118 psr
& PSTATE_Z
? 'Z' : '-',
119 psr
& PSTATE_C
? 'C' : '-',
120 psr
& PSTATE_V
? 'V' : '-');
121 cpu_fprintf(f
, "\n");
123 if (flags
& CPU_DUMP_FPU
) {
125 for (i
= 0; i
< numvfpregs
; i
+= 2) {
126 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
127 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
128 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
130 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
131 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
132 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
135 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
136 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
140 static int get_mem_index(DisasContext
*s
)
142 #ifdef CONFIG_USER_ONLY
149 void gen_a64_set_pc_im(uint64_t val
)
151 tcg_gen_movi_i64(cpu_pc
, val
);
154 static void gen_exception(int excp
)
156 TCGv_i32 tmp
= tcg_temp_new_i32();
157 tcg_gen_movi_i32(tmp
, excp
);
158 gen_helper_exception(cpu_env
, tmp
);
159 tcg_temp_free_i32(tmp
);
162 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
)
164 gen_a64_set_pc_im(s
->pc
- offset
);
166 s
->is_jmp
= DISAS_EXC
;
169 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
171 /* No direct tb linking with singlestep or deterministic io */
172 if (s
->singlestep_enabled
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
176 /* Only link tbs from inside the same guest page */
177 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
184 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
186 TranslationBlock
*tb
;
189 if (use_goto_tb(s
, n
, dest
)) {
191 gen_a64_set_pc_im(dest
);
192 tcg_gen_exit_tb((tcg_target_long
)tb
+ n
);
193 s
->is_jmp
= DISAS_TB_JUMP
;
195 gen_a64_set_pc_im(dest
);
196 if (s
->singlestep_enabled
) {
197 gen_exception(EXCP_DEBUG
);
200 s
->is_jmp
= DISAS_JUMP
;
204 static void unallocated_encoding(DisasContext
*s
)
206 gen_exception_insn(s
, 4, EXCP_UDEF
);
209 #define unsupported_encoding(s, insn) \
211 qemu_log_mask(LOG_UNIMP, \
212 "%s:%d: unsupported instruction encoding 0x%08x " \
213 "at pc=%016" PRIx64 "\n", \
214 __FILE__, __LINE__, insn, s->pc - 4); \
215 unallocated_encoding(s); \
218 static void init_tmp_a64_array(DisasContext
*s
)
220 #ifdef CONFIG_DEBUG_TCG
222 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
223 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
226 s
->tmp_a64_count
= 0;
229 static void free_tmp_a64(DisasContext
*s
)
232 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
233 tcg_temp_free_i64(s
->tmp_a64
[i
]);
235 init_tmp_a64_array(s
);
238 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
240 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
241 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
244 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
246 TCGv_i64 t
= new_tmp_a64(s
);
247 tcg_gen_movi_i64(t
, 0);
252 * Register access functions
254 * These functions are used for directly accessing a register in where
255 * changes to the final register value are likely to be made. If you
256 * need to use a register for temporary calculation (e.g. index type
257 * operations) use the read_* form.
259 * B1.2.1 Register mappings
261 * In instruction register encoding 31 can refer to ZR (zero register) or
262 * the SP (stack pointer) depending on context. In QEMU's case we map SP
263 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
264 * This is the point of the _sp forms.
266 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
269 return new_tmp_a64_zero(s
);
275 /* register access for when 31 == SP */
276 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
281 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
282 * representing the register contents. This TCGv is an auto-freed
283 * temporary so it need not be explicitly freed, and may be modified.
285 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
287 TCGv_i64 v
= new_tmp_a64(s
);
290 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
292 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
295 tcg_gen_movi_i64(v
, 0);
300 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
302 TCGv_i64 v
= new_tmp_a64(s
);
304 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
306 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
311 /* Return the offset into CPUARMState of a slice (from
312 * the least significant end) of FP register Qn (ie
314 * (Note that this is not the same mapping as for A32; see cpu.h)
316 static inline int fp_reg_offset(int regno
, TCGMemOp size
)
318 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
319 #ifdef HOST_WORDS_BIGENDIAN
320 offs
+= (8 - (1 << size
));
325 /* Offset of the high half of the 128 bit vector Qn */
326 static inline int fp_reg_hi_offset(int regno
)
328 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
331 /* Convenience accessors for reading and writing single and double
332 * FP registers. Writing clears the upper parts of the associated
333 * 128 bit vector register, as required by the architecture.
334 * Note that unlike the GP register accessors, the values returned
335 * by the read functions must be manually freed.
337 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
339 TCGv_i64 v
= tcg_temp_new_i64();
341 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(reg
, MO_64
));
345 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
347 TCGv_i32 v
= tcg_temp_new_i32();
349 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(reg
, MO_32
));
353 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
355 TCGv_i64 tcg_zero
= tcg_const_i64(0);
357 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(reg
, MO_64
));
358 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(reg
));
359 tcg_temp_free_i64(tcg_zero
);
362 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
364 TCGv_i64 tmp
= tcg_temp_new_i64();
366 tcg_gen_extu_i32_i64(tmp
, v
);
367 write_fp_dreg(s
, reg
, tmp
);
368 tcg_temp_free_i64(tmp
);
371 static TCGv_ptr
get_fpstatus_ptr(void)
373 TCGv_ptr statusptr
= tcg_temp_new_ptr();
376 /* In A64 all instructions (both FP and Neon) use the FPCR;
377 * there is no equivalent of the A32 Neon "standard FPSCR value"
378 * and all operations use vfp.fp_status.
380 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
381 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
385 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
386 * than the 32 bit equivalent.
388 static inline void gen_set_NZ64(TCGv_i64 result
)
390 TCGv_i64 flag
= tcg_temp_new_i64();
392 tcg_gen_setcondi_i64(TCG_COND_NE
, flag
, result
, 0);
393 tcg_gen_trunc_i64_i32(cpu_ZF
, flag
);
394 tcg_gen_shri_i64(flag
, result
, 32);
395 tcg_gen_trunc_i64_i32(cpu_NF
, flag
);
396 tcg_temp_free_i64(flag
);
399 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
400 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
403 gen_set_NZ64(result
);
405 tcg_gen_trunc_i64_i32(cpu_ZF
, result
);
406 tcg_gen_trunc_i64_i32(cpu_NF
, result
);
408 tcg_gen_movi_i32(cpu_CF
, 0);
409 tcg_gen_movi_i32(cpu_VF
, 0);
412 /* dest = T0 + T1; compute C, N, V and Z flags */
413 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
416 TCGv_i64 result
, flag
, tmp
;
417 result
= tcg_temp_new_i64();
418 flag
= tcg_temp_new_i64();
419 tmp
= tcg_temp_new_i64();
421 tcg_gen_movi_i64(tmp
, 0);
422 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
424 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
426 gen_set_NZ64(result
);
428 tcg_gen_xor_i64(flag
, result
, t0
);
429 tcg_gen_xor_i64(tmp
, t0
, t1
);
430 tcg_gen_andc_i64(flag
, flag
, tmp
);
431 tcg_temp_free_i64(tmp
);
432 tcg_gen_shri_i64(flag
, flag
, 32);
433 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
435 tcg_gen_mov_i64(dest
, result
);
436 tcg_temp_free_i64(result
);
437 tcg_temp_free_i64(flag
);
439 /* 32 bit arithmetic */
440 TCGv_i32 t0_32
= tcg_temp_new_i32();
441 TCGv_i32 t1_32
= tcg_temp_new_i32();
442 TCGv_i32 tmp
= tcg_temp_new_i32();
444 tcg_gen_movi_i32(tmp
, 0);
445 tcg_gen_trunc_i64_i32(t0_32
, t0
);
446 tcg_gen_trunc_i64_i32(t1_32
, t1
);
447 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
448 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
449 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
450 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
451 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
452 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
454 tcg_temp_free_i32(tmp
);
455 tcg_temp_free_i32(t0_32
);
456 tcg_temp_free_i32(t1_32
);
460 /* dest = T0 - T1; compute C, N, V and Z flags */
461 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
464 /* 64 bit arithmetic */
465 TCGv_i64 result
, flag
, tmp
;
467 result
= tcg_temp_new_i64();
468 flag
= tcg_temp_new_i64();
469 tcg_gen_sub_i64(result
, t0
, t1
);
471 gen_set_NZ64(result
);
473 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
474 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
476 tcg_gen_xor_i64(flag
, result
, t0
);
477 tmp
= tcg_temp_new_i64();
478 tcg_gen_xor_i64(tmp
, t0
, t1
);
479 tcg_gen_and_i64(flag
, flag
, tmp
);
480 tcg_temp_free_i64(tmp
);
481 tcg_gen_shri_i64(flag
, flag
, 32);
482 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
483 tcg_gen_mov_i64(dest
, result
);
484 tcg_temp_free_i64(flag
);
485 tcg_temp_free_i64(result
);
487 /* 32 bit arithmetic */
488 TCGv_i32 t0_32
= tcg_temp_new_i32();
489 TCGv_i32 t1_32
= tcg_temp_new_i32();
492 tcg_gen_trunc_i64_i32(t0_32
, t0
);
493 tcg_gen_trunc_i64_i32(t1_32
, t1
);
494 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
495 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
496 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
497 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
498 tmp
= tcg_temp_new_i32();
499 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
500 tcg_temp_free_i32(t0_32
);
501 tcg_temp_free_i32(t1_32
);
502 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
503 tcg_temp_free_i32(tmp
);
504 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
508 /* dest = T0 + T1 + CF; do not compute flags. */
509 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
511 TCGv_i64 flag
= tcg_temp_new_i64();
512 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
513 tcg_gen_add_i64(dest
, t0
, t1
);
514 tcg_gen_add_i64(dest
, dest
, flag
);
515 tcg_temp_free_i64(flag
);
518 tcg_gen_ext32u_i64(dest
, dest
);
522 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
523 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
526 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
527 result
= tcg_temp_new_i64();
528 cf_64
= tcg_temp_new_i64();
529 vf_64
= tcg_temp_new_i64();
530 tmp
= tcg_const_i64(0);
532 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
533 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
534 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
535 tcg_gen_trunc_i64_i32(cpu_CF
, cf_64
);
536 gen_set_NZ64(result
);
538 tcg_gen_xor_i64(vf_64
, result
, t0
);
539 tcg_gen_xor_i64(tmp
, t0
, t1
);
540 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
541 tcg_gen_shri_i64(vf_64
, vf_64
, 32);
542 tcg_gen_trunc_i64_i32(cpu_VF
, vf_64
);
544 tcg_gen_mov_i64(dest
, result
);
546 tcg_temp_free_i64(tmp
);
547 tcg_temp_free_i64(vf_64
);
548 tcg_temp_free_i64(cf_64
);
549 tcg_temp_free_i64(result
);
551 TCGv_i32 t0_32
, t1_32
, tmp
;
552 t0_32
= tcg_temp_new_i32();
553 t1_32
= tcg_temp_new_i32();
554 tmp
= tcg_const_i32(0);
556 tcg_gen_trunc_i64_i32(t0_32
, t0
);
557 tcg_gen_trunc_i64_i32(t1_32
, t1
);
558 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
559 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
561 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
562 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
563 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
564 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
565 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
567 tcg_temp_free_i32(tmp
);
568 tcg_temp_free_i32(t1_32
);
569 tcg_temp_free_i32(t0_32
);
574 * Load/Store generators
578 * Store from GPR register to memory
580 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
581 TCGv_i64 tcg_addr
, int size
)
584 tcg_gen_qemu_st_i64(source
, tcg_addr
, get_mem_index(s
), MO_TE
+ size
);
588 * Load from memory to GPR register
590 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
591 int size
, bool is_signed
, bool extend
)
593 TCGMemOp memop
= MO_TE
+ size
;
601 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, get_mem_index(s
), memop
);
603 if (extend
&& is_signed
) {
605 tcg_gen_ext32u_i64(dest
, dest
);
610 * Store from FP register to memory
612 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
614 /* This writes the bottom N bits of a 128 bit wide vector to memory */
615 TCGv_i64 tmp
= tcg_temp_new_i64();
616 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(srcidx
, MO_64
));
618 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TE
+ size
);
620 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
621 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
622 tcg_gen_qemu_st64(tmp
, tcg_addr
, get_mem_index(s
));
623 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(srcidx
));
624 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
625 tcg_gen_qemu_st_i64(tmp
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
626 tcg_temp_free_i64(tcg_hiaddr
);
629 tcg_temp_free_i64(tmp
);
633 * Load from memory to FP register
635 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
637 /* This always zero-extends and writes to a full 128 bit wide vector */
638 TCGv_i64 tmplo
= tcg_temp_new_i64();
642 TCGMemOp memop
= MO_TE
+ size
;
643 tmphi
= tcg_const_i64(0);
644 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
647 tmphi
= tcg_temp_new_i64();
648 tcg_hiaddr
= tcg_temp_new_i64();
650 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
651 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
652 tcg_gen_qemu_ld_i64(tmphi
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
653 tcg_temp_free_i64(tcg_hiaddr
);
656 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(destidx
, MO_64
));
657 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(destidx
));
659 tcg_temp_free_i64(tmplo
);
660 tcg_temp_free_i64(tmphi
);
664 * This utility function is for doing register extension with an
665 * optional shift. You will likely want to pass a temporary for the
666 * destination register. See DecodeRegExtend() in the ARM ARM.
668 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
669 int option
, unsigned int shift
)
671 int extsize
= extract32(option
, 0, 2);
672 bool is_signed
= extract32(option
, 2, 1);
677 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
680 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
683 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
686 tcg_gen_mov_i64(tcg_out
, tcg_in
);
692 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
695 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
698 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
701 tcg_gen_mov_i64(tcg_out
, tcg_in
);
707 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
711 static inline void gen_check_sp_alignment(DisasContext
*s
)
713 /* The AArch64 architecture mandates that (if enabled via PSTATE
714 * or SCTLR bits) there is a check that SP is 16-aligned on every
715 * SP-relative load or store (with an exception generated if it is not).
716 * In line with general QEMU practice regarding misaligned accesses,
717 * we omit these checks for the sake of guest program performance.
718 * This function is provided as a hook so we can more easily add these
719 * checks in future (possibly as a "favour catching guest program bugs
720 * over speed" user selectable option).
725 * the instruction disassembly implemented here matches
726 * the instruction encoding classifications in chapter 3 (C3)
727 * of the ARM Architecture Reference Manual (DDI0487A_a)
730 /* C3.2.7 Unconditional branch (immediate)
732 * +----+-----------+-------------------------------------+
733 * | op | 0 0 1 0 1 | imm26 |
734 * +----+-----------+-------------------------------------+
736 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
738 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
740 if (insn
& (1 << 31)) {
741 /* C5.6.26 BL Branch with link */
742 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
745 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
746 gen_goto_tb(s
, 0, addr
);
749 /* C3.2.1 Compare & branch (immediate)
750 * 31 30 25 24 23 5 4 0
751 * +----+-------------+----+---------------------+--------+
752 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
753 * +----+-------------+----+---------------------+--------+
755 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
757 unsigned int sf
, op
, rt
;
762 sf
= extract32(insn
, 31, 1);
763 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
764 rt
= extract32(insn
, 0, 5);
765 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
767 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
768 label_match
= gen_new_label();
770 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
771 tcg_cmp
, 0, label_match
);
773 gen_goto_tb(s
, 0, s
->pc
);
774 gen_set_label(label_match
);
775 gen_goto_tb(s
, 1, addr
);
778 /* C3.2.5 Test & branch (immediate)
779 * 31 30 25 24 23 19 18 5 4 0
780 * +----+-------------+----+-------+-------------+------+
781 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
782 * +----+-------------+----+-------+-------------+------+
784 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
786 unsigned int bit_pos
, op
, rt
;
791 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
792 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
793 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
794 rt
= extract32(insn
, 0, 5);
796 tcg_cmp
= tcg_temp_new_i64();
797 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
798 label_match
= gen_new_label();
799 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
800 tcg_cmp
, 0, label_match
);
801 tcg_temp_free_i64(tcg_cmp
);
802 gen_goto_tb(s
, 0, s
->pc
);
803 gen_set_label(label_match
);
804 gen_goto_tb(s
, 1, addr
);
807 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
808 * 31 25 24 23 5 4 3 0
809 * +---------------+----+---------------------+----+------+
810 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
811 * +---------------+----+---------------------+----+------+
813 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
818 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
819 unallocated_encoding(s
);
822 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
823 cond
= extract32(insn
, 0, 4);
826 /* genuinely conditional branches */
827 int label_match
= gen_new_label();
828 arm_gen_test_cc(cond
, label_match
);
829 gen_goto_tb(s
, 0, s
->pc
);
830 gen_set_label(label_match
);
831 gen_goto_tb(s
, 1, addr
);
833 /* 0xe and 0xf are both "always" conditions */
834 gen_goto_tb(s
, 0, addr
);
839 static void handle_hint(DisasContext
*s
, uint32_t insn
,
840 unsigned int op1
, unsigned int op2
, unsigned int crm
)
842 unsigned int selector
= crm
<< 3 | op2
;
845 unallocated_encoding(s
);
857 /* we treat all as NOP at least for now */
860 /* default specified as NOP equivalent */
865 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
867 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
870 /* CLREX, DSB, DMB, ISB */
871 static void handle_sync(DisasContext
*s
, uint32_t insn
,
872 unsigned int op1
, unsigned int op2
, unsigned int crm
)
875 unallocated_encoding(s
);
886 /* We don't emulate caches so barriers are no-ops */
889 unallocated_encoding(s
);
894 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
895 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
896 unsigned int op1
, unsigned int op2
, unsigned int crm
)
898 unsupported_encoding(s
, insn
);
901 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
903 TCGv_i32 tmp
= tcg_temp_new_i32();
904 TCGv_i32 nzcv
= tcg_temp_new_i32();
906 /* build bit 31, N */
907 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1 << 31));
908 /* build bit 30, Z */
909 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
910 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
911 /* build bit 29, C */
912 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
913 /* build bit 28, V */
914 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
915 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
916 /* generate result */
917 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
919 tcg_temp_free_i32(nzcv
);
920 tcg_temp_free_i32(tmp
);
923 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
926 TCGv_i32 nzcv
= tcg_temp_new_i32();
928 /* take NZCV from R[t] */
929 tcg_gen_trunc_i64_i32(nzcv
, tcg_rt
);
932 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1 << 31));
934 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
935 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
937 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
938 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
940 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
941 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
942 tcg_temp_free_i32(nzcv
);
945 /* C5.6.129 MRS - move from system register
946 * C5.6.131 MSR (register) - move to system register
949 * These are all essentially the same insn in 'read' and 'write'
950 * versions, with varying op0 fields.
952 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
953 unsigned int op0
, unsigned int op1
, unsigned int op2
,
954 unsigned int crn
, unsigned int crm
, unsigned int rt
)
956 const ARMCPRegInfo
*ri
;
959 ri
= get_arm_cp_reginfo(s
->cp_regs
,
960 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
961 crn
, crm
, op0
, op1
, op2
));
964 /* Unknown register */
965 unallocated_encoding(s
);
969 /* Check access permissions */
970 if (!cp_access_ok(s
->current_pl
, ri
, isread
)) {
971 unallocated_encoding(s
);
975 /* Handle special cases first */
976 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
980 tcg_rt
= cpu_reg(s
, rt
);
982 gen_get_nzcv(tcg_rt
);
984 gen_set_nzcv(tcg_rt
);
991 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
995 tcg_rt
= cpu_reg(s
, rt
);
998 if (ri
->type
& ARM_CP_CONST
) {
999 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1000 } else if (ri
->readfn
) {
1002 gen_a64_set_pc_im(s
->pc
- 4);
1003 tmpptr
= tcg_const_ptr(ri
);
1004 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1005 tcg_temp_free_ptr(tmpptr
);
1007 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1010 if (ri
->type
& ARM_CP_CONST
) {
1011 /* If not forbidden by access permissions, treat as WI */
1013 } else if (ri
->writefn
) {
1015 gen_a64_set_pc_im(s
->pc
- 4);
1016 tmpptr
= tcg_const_ptr(ri
);
1017 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1018 tcg_temp_free_ptr(tmpptr
);
1020 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1024 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
1025 /* I/O operations must end the TB here (whether read or write) */
1027 s
->is_jmp
= DISAS_UPDATE
;
1028 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1029 /* We default to ending the TB on a coprocessor register write,
1030 * but allow this to be suppressed by the register definition
1031 * (usually only necessary to work around guest bugs).
1033 s
->is_jmp
= DISAS_UPDATE
;
1038 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1039 * +---------------------+---+-----+-----+-------+-------+-----+------+
1040 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1041 * +---------------------+---+-----+-----+-------+-------+-----+------+
1043 static void disas_system(DisasContext
*s
, uint32_t insn
)
1045 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1046 l
= extract32(insn
, 21, 1);
1047 op0
= extract32(insn
, 19, 2);
1048 op1
= extract32(insn
, 16, 3);
1049 crn
= extract32(insn
, 12, 4);
1050 crm
= extract32(insn
, 8, 4);
1051 op2
= extract32(insn
, 5, 3);
1052 rt
= extract32(insn
, 0, 5);
1055 if (l
|| rt
!= 31) {
1056 unallocated_encoding(s
);
1060 case 2: /* C5.6.68 HINT */
1061 handle_hint(s
, insn
, op1
, op2
, crm
);
1063 case 3: /* CLREX, DSB, DMB, ISB */
1064 handle_sync(s
, insn
, op1
, op2
, crm
);
1066 case 4: /* C5.6.130 MSR (immediate) */
1067 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1070 unallocated_encoding(s
);
1075 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1078 /* C3.2.3 Exception generation
1080 * 31 24 23 21 20 5 4 2 1 0
1081 * +-----------------+-----+------------------------+-----+----+
1082 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1083 * +-----------------------+------------------------+----------+
1085 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1087 int opc
= extract32(insn
, 21, 3);
1088 int op2_ll
= extract32(insn
, 0, 5);
1092 /* SVC, HVC, SMC; since we don't support the Virtualization
1093 * or TrustZone extensions these all UNDEF except SVC.
1096 unallocated_encoding(s
);
1099 gen_exception_insn(s
, 0, EXCP_SWI
);
1103 unallocated_encoding(s
);
1107 gen_exception_insn(s
, 0, EXCP_BKPT
);
1111 unallocated_encoding(s
);
1115 unsupported_encoding(s
, insn
);
1118 if (op2_ll
< 1 || op2_ll
> 3) {
1119 unallocated_encoding(s
);
1122 /* DCPS1, DCPS2, DCPS3 */
1123 unsupported_encoding(s
, insn
);
1126 unallocated_encoding(s
);
1131 /* C3.2.7 Unconditional branch (register)
1132 * 31 25 24 21 20 16 15 10 9 5 4 0
1133 * +---------------+-------+-------+-------+------+-------+
1134 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1135 * +---------------+-------+-------+-------+------+-------+
1137 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1139 unsigned int opc
, op2
, op3
, rn
, op4
;
1141 opc
= extract32(insn
, 21, 4);
1142 op2
= extract32(insn
, 16, 5);
1143 op3
= extract32(insn
, 10, 6);
1144 rn
= extract32(insn
, 5, 5);
1145 op4
= extract32(insn
, 0, 5);
1147 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1148 unallocated_encoding(s
);
1157 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1162 unallocated_encoding(s
);
1164 unsupported_encoding(s
, insn
);
1168 unallocated_encoding(s
);
1172 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1173 s
->is_jmp
= DISAS_JUMP
;
1176 /* C3.2 Branches, exception generating and system instructions */
1177 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1179 switch (extract32(insn
, 25, 7)) {
1180 case 0x0a: case 0x0b:
1181 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1182 disas_uncond_b_imm(s
, insn
);
1184 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1185 disas_comp_b_imm(s
, insn
);
1187 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1188 disas_test_b_imm(s
, insn
);
1190 case 0x2a: /* Conditional branch (immediate) */
1191 disas_cond_b_imm(s
, insn
);
1193 case 0x6a: /* Exception generation / System */
1194 if (insn
& (1 << 24)) {
1195 disas_system(s
, insn
);
1200 case 0x6b: /* Unconditional branch (register) */
1201 disas_uncond_b_reg(s
, insn
);
1204 unallocated_encoding(s
);
1210 * Load/Store exclusive instructions are implemented by remembering
1211 * the value/address loaded, and seeing if these are the same
1212 * when the store is performed. This is not actually the architecturally
1213 * mandated semantics, but it works for typical guest code sequences
1214 * and avoids having to monitor regular stores.
1216 * In system emulation mode only one CPU will be running at once, so
1217 * this sequence is effectively atomic. In user emulation mode we
1218 * throw an exception and handle the atomic operation elsewhere.
1220 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1221 TCGv_i64 addr
, int size
, bool is_pair
)
1223 TCGv_i64 tmp
= tcg_temp_new_i64();
1224 TCGMemOp memop
= MO_TE
+ size
;
1226 g_assert(size
<= 3);
1227 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), memop
);
1230 TCGv_i64 addr2
= tcg_temp_new_i64();
1231 TCGv_i64 hitmp
= tcg_temp_new_i64();
1233 g_assert(size
>= 2);
1234 tcg_gen_addi_i64(addr2
, addr
, 1 << size
);
1235 tcg_gen_qemu_ld_i64(hitmp
, addr2
, get_mem_index(s
), memop
);
1236 tcg_temp_free_i64(addr2
);
1237 tcg_gen_mov_i64(cpu_exclusive_high
, hitmp
);
1238 tcg_gen_mov_i64(cpu_reg(s
, rt2
), hitmp
);
1239 tcg_temp_free_i64(hitmp
);
1242 tcg_gen_mov_i64(cpu_exclusive_val
, tmp
);
1243 tcg_gen_mov_i64(cpu_reg(s
, rt
), tmp
);
1245 tcg_temp_free_i64(tmp
);
1246 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1249 #ifdef CONFIG_USER_ONLY
1250 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1251 TCGv_i64 addr
, int size
, int is_pair
)
1253 tcg_gen_mov_i64(cpu_exclusive_test
, addr
);
1254 tcg_gen_movi_i32(cpu_exclusive_info
,
1255 size
| is_pair
<< 2 | (rd
<< 4) | (rt
<< 9) | (rt2
<< 14));
1256 gen_exception_insn(s
, 4, EXCP_STREX
);
1259 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1260 TCGv_i64 addr
, int size
, int is_pair
)
1262 qemu_log_mask(LOG_UNIMP
,
1263 "%s:%d: system mode store_exclusive unsupported "
1264 "at pc=%016" PRIx64
"\n",
1265 __FILE__
, __LINE__
, s
->pc
- 4);
1269 /* C3.3.6 Load/store exclusive
1271 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1272 * +-----+-------------+----+---+----+------+----+-------+------+------+
1273 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1274 * +-----+-------------+----+---+----+------+----+-------+------+------+
1276 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1277 * L: 0 -> store, 1 -> load
1278 * o2: 0 -> exclusive, 1 -> not
1279 * o1: 0 -> single register, 1 -> register pair
1280 * o0: 1 -> load-acquire/store-release, 0 -> not
1282 * o0 == 0 AND o2 == 1 is un-allocated
1283 * o1 == 1 is un-allocated except for 32 and 64 bit sizes
1285 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1287 int rt
= extract32(insn
, 0, 5);
1288 int rn
= extract32(insn
, 5, 5);
1289 int rt2
= extract32(insn
, 10, 5);
1290 int is_lasr
= extract32(insn
, 15, 1);
1291 int rs
= extract32(insn
, 16, 5);
1292 int is_pair
= extract32(insn
, 21, 1);
1293 int is_store
= !extract32(insn
, 22, 1);
1294 int is_excl
= !extract32(insn
, 23, 1);
1295 int size
= extract32(insn
, 30, 2);
1298 if ((!is_excl
&& !is_lasr
) ||
1299 (is_pair
&& size
< 2)) {
1300 unallocated_encoding(s
);
1305 gen_check_sp_alignment(s
);
1307 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1309 /* Note that since TCG is single threaded load-acquire/store-release
1310 * semantics require no extra if (is_lasr) { ... } handling.
1315 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1317 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1320 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1322 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1324 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false);
1327 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt
);
1328 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1330 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
1332 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, false, false);
1339 * C3.3.5 Load register (literal)
1341 * 31 30 29 27 26 25 24 23 5 4 0
1342 * +-----+-------+---+-----+-------------------+-------+
1343 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
1344 * +-----+-------+---+-----+-------------------+-------+
1346 * V: 1 -> vector (simd/fp)
1347 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
1348 * 10-> 32 bit signed, 11 -> prefetch
1349 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
1351 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
1353 int rt
= extract32(insn
, 0, 5);
1354 int64_t imm
= sextract32(insn
, 5, 19) << 2;
1355 bool is_vector
= extract32(insn
, 26, 1);
1356 int opc
= extract32(insn
, 30, 2);
1357 bool is_signed
= false;
1359 TCGv_i64 tcg_rt
, tcg_addr
;
1363 unallocated_encoding(s
);
1369 /* PRFM (literal) : prefetch */
1372 size
= 2 + extract32(opc
, 0, 1);
1373 is_signed
= extract32(opc
, 1, 1);
1376 tcg_rt
= cpu_reg(s
, rt
);
1378 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
1380 do_fp_ld(s
, rt
, tcg_addr
, size
);
1382 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1384 tcg_temp_free_i64(tcg_addr
);
1388 * C5.6.80 LDNP (Load Pair - non-temporal hint)
1389 * C5.6.81 LDP (Load Pair - non vector)
1390 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
1391 * C5.6.176 STNP (Store Pair - non-temporal hint)
1392 * C5.6.177 STP (Store Pair - non vector)
1393 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
1394 * C6.3.165 LDP (Load Pair of SIMD&FP)
1395 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
1396 * C6.3.284 STP (Store Pair of SIMD&FP)
1398 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
1399 * +-----+-------+---+---+-------+---+-----------------------------+
1400 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
1401 * +-----+-------+---+---+-------+---+-------+-------+------+------+
1403 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
1405 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
1406 * V: 0 -> GPR, 1 -> Vector
1407 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
1408 * 10 -> signed offset, 11 -> pre-index
1409 * L: 0 -> Store 1 -> Load
1411 * Rt, Rt2 = GPR or SIMD registers to be stored
1412 * Rn = general purpose register containing address
1413 * imm7 = signed offset (multiple of 4 or 8 depending on size)
1415 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
1417 int rt
= extract32(insn
, 0, 5);
1418 int rn
= extract32(insn
, 5, 5);
1419 int rt2
= extract32(insn
, 10, 5);
1420 int64_t offset
= sextract32(insn
, 15, 7);
1421 int index
= extract32(insn
, 23, 2);
1422 bool is_vector
= extract32(insn
, 26, 1);
1423 bool is_load
= extract32(insn
, 22, 1);
1424 int opc
= extract32(insn
, 30, 2);
1426 bool is_signed
= false;
1427 bool postindex
= false;
1430 TCGv_i64 tcg_addr
; /* calculated address */
1434 unallocated_encoding(s
);
1441 size
= 2 + extract32(opc
, 1, 1);
1442 is_signed
= extract32(opc
, 0, 1);
1443 if (!is_load
&& is_signed
) {
1444 unallocated_encoding(s
);
1450 case 1: /* post-index */
1455 /* signed offset with "non-temporal" hint. Since we don't emulate
1456 * caches we don't care about hints to the cache system about
1457 * data access patterns, and handle this identically to plain
1461 /* There is no non-temporal-hint version of LDPSW */
1462 unallocated_encoding(s
);
1467 case 2: /* signed offset, rn not updated */
1470 case 3: /* pre-index */
1479 gen_check_sp_alignment(s
);
1482 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1485 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
1490 do_fp_ld(s
, rt
, tcg_addr
, size
);
1492 do_fp_st(s
, rt
, tcg_addr
, size
);
1495 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1497 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1499 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1502 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1505 do_fp_ld(s
, rt2
, tcg_addr
, size
);
1507 do_fp_st(s
, rt2
, tcg_addr
, size
);
1510 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
1512 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false);
1514 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
1520 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
1522 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1524 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
1529 * C3.3.8 Load/store (immediate post-indexed)
1530 * C3.3.9 Load/store (immediate pre-indexed)
1531 * C3.3.12 Load/store (unscaled immediate)
1533 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
1534 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1535 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
1536 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1538 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
1539 * V = 0 -> non-vector
1540 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
1541 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1543 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
)
1545 int rt
= extract32(insn
, 0, 5);
1546 int rn
= extract32(insn
, 5, 5);
1547 int imm9
= sextract32(insn
, 12, 9);
1548 int opc
= extract32(insn
, 22, 2);
1549 int size
= extract32(insn
, 30, 2);
1550 int idx
= extract32(insn
, 10, 2);
1551 bool is_signed
= false;
1552 bool is_store
= false;
1553 bool is_extended
= false;
1554 bool is_vector
= extract32(insn
, 26, 1);
1561 size
|= (opc
& 2) << 1;
1563 unallocated_encoding(s
);
1566 is_store
= ((opc
& 1) == 0);
1568 if (size
== 3 && opc
== 2) {
1569 /* PRFM - prefetch */
1572 if (opc
== 3 && size
> 1) {
1573 unallocated_encoding(s
);
1576 is_store
= (opc
== 0);
1577 is_signed
= opc
& (1<<1);
1578 is_extended
= (size
< 3) && (opc
& 1);
1600 gen_check_sp_alignment(s
);
1602 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1605 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
1610 do_fp_st(s
, rt
, tcg_addr
, size
);
1612 do_fp_ld(s
, rt
, tcg_addr
, size
);
1615 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1617 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1619 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
1624 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
1626 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
1628 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
1633 * C3.3.10 Load/store (register offset)
1635 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
1636 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
1637 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
1638 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
1641 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
1642 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1644 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
1645 * opc<0>: 0 -> store, 1 -> load
1646 * V: 1 -> vector/simd
1647 * opt: extend encoding (see DecodeRegExtend)
1648 * S: if S=1 then scale (essentially index by sizeof(size))
1649 * Rt: register to transfer into/out of
1650 * Rn: address register or SP for base
1651 * Rm: offset register or ZR for offset
1653 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
)
1655 int rt
= extract32(insn
, 0, 5);
1656 int rn
= extract32(insn
, 5, 5);
1657 int shift
= extract32(insn
, 12, 1);
1658 int rm
= extract32(insn
, 16, 5);
1659 int opc
= extract32(insn
, 22, 2);
1660 int opt
= extract32(insn
, 13, 3);
1661 int size
= extract32(insn
, 30, 2);
1662 bool is_signed
= false;
1663 bool is_store
= false;
1664 bool is_extended
= false;
1665 bool is_vector
= extract32(insn
, 26, 1);
1670 if (extract32(opt
, 1, 1) == 0) {
1671 unallocated_encoding(s
);
1676 size
|= (opc
& 2) << 1;
1678 unallocated_encoding(s
);
1681 is_store
= !extract32(opc
, 0, 1);
1683 if (size
== 3 && opc
== 2) {
1684 /* PRFM - prefetch */
1687 if (opc
== 3 && size
> 1) {
1688 unallocated_encoding(s
);
1691 is_store
= (opc
== 0);
1692 is_signed
= extract32(opc
, 1, 1);
1693 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
1697 gen_check_sp_alignment(s
);
1699 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1701 tcg_rm
= read_cpu_reg(s
, rm
, 1);
1702 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
1704 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
1708 do_fp_st(s
, rt
, tcg_addr
, size
);
1710 do_fp_ld(s
, rt
, tcg_addr
, size
);
1713 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1715 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1717 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
1723 * C3.3.13 Load/store (unsigned immediate)
1725 * 31 30 29 27 26 25 24 23 22 21 10 9 5
1726 * +----+-------+---+-----+-----+------------+-------+------+
1727 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
1728 * +----+-------+---+-----+-----+------------+-------+------+
1731 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
1732 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1734 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
1735 * opc<0>: 0 -> store, 1 -> load
1736 * Rn: base address register (inc SP)
1737 * Rt: target register
1739 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
)
1741 int rt
= extract32(insn
, 0, 5);
1742 int rn
= extract32(insn
, 5, 5);
1743 unsigned int imm12
= extract32(insn
, 10, 12);
1744 bool is_vector
= extract32(insn
, 26, 1);
1745 int size
= extract32(insn
, 30, 2);
1746 int opc
= extract32(insn
, 22, 2);
1747 unsigned int offset
;
1752 bool is_signed
= false;
1753 bool is_extended
= false;
1756 size
|= (opc
& 2) << 1;
1758 unallocated_encoding(s
);
1761 is_store
= !extract32(opc
, 0, 1);
1763 if (size
== 3 && opc
== 2) {
1764 /* PRFM - prefetch */
1767 if (opc
== 3 && size
> 1) {
1768 unallocated_encoding(s
);
1771 is_store
= (opc
== 0);
1772 is_signed
= extract32(opc
, 1, 1);
1773 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
1777 gen_check_sp_alignment(s
);
1779 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1780 offset
= imm12
<< size
;
1781 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
1785 do_fp_st(s
, rt
, tcg_addr
, size
);
1787 do_fp_ld(s
, rt
, tcg_addr
, size
);
1790 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1792 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1794 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
1799 /* Load/store register (immediate forms) */
1800 static void disas_ldst_reg_imm(DisasContext
*s
, uint32_t insn
)
1802 switch (extract32(insn
, 10, 2)) {
1803 case 0: case 1: case 3:
1804 /* Load/store register (unscaled immediate) */
1805 /* Load/store immediate pre/post-indexed */
1806 disas_ldst_reg_imm9(s
, insn
);
1809 /* Load/store register unprivileged */
1810 unsupported_encoding(s
, insn
);
1813 unallocated_encoding(s
);
1818 /* Load/store register (all forms) */
1819 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
1821 switch (extract32(insn
, 24, 2)) {
1823 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
1824 disas_ldst_reg_roffset(s
, insn
);
1826 disas_ldst_reg_imm(s
, insn
);
1830 disas_ldst_reg_unsigned_imm(s
, insn
);
1833 unallocated_encoding(s
);
1838 /* AdvSIMD load/store multiple structures */
1839 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
1841 unsupported_encoding(s
, insn
);
1844 /* AdvSIMD load/store single structure */
1845 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
1847 unsupported_encoding(s
, insn
);
1850 /* C3.3 Loads and stores */
1851 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
1853 switch (extract32(insn
, 24, 6)) {
1854 case 0x08: /* Load/store exclusive */
1855 disas_ldst_excl(s
, insn
);
1857 case 0x18: case 0x1c: /* Load register (literal) */
1858 disas_ld_lit(s
, insn
);
1860 case 0x28: case 0x29:
1861 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
1862 disas_ldst_pair(s
, insn
);
1864 case 0x38: case 0x39:
1865 case 0x3c: case 0x3d: /* Load/store register (all forms) */
1866 disas_ldst_reg(s
, insn
);
1868 case 0x0c: /* AdvSIMD load/store multiple structures */
1869 disas_ldst_multiple_struct(s
, insn
);
1871 case 0x0d: /* AdvSIMD load/store single structure */
1872 disas_ldst_single_struct(s
, insn
);
1875 unallocated_encoding(s
);
1880 /* C3.4.6 PC-rel. addressing
1881 * 31 30 29 28 24 23 5 4 0
1882 * +----+-------+-----------+-------------------+------+
1883 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
1884 * +----+-------+-----------+-------------------+------+
1886 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
1888 unsigned int page
, rd
;
1892 page
= extract32(insn
, 31, 1);
1893 /* SignExtend(immhi:immlo) -> offset */
1894 offset
= ((int64_t)sextract32(insn
, 5, 19) << 2) | extract32(insn
, 29, 2);
1895 rd
= extract32(insn
, 0, 5);
1899 /* ADRP (page based) */
1904 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
1908 * C3.4.1 Add/subtract (immediate)
1910 * 31 30 29 28 24 23 22 21 10 9 5 4 0
1911 * +--+--+--+-----------+-----+-------------+-----+-----+
1912 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
1913 * +--+--+--+-----------+-----+-------------+-----+-----+
1915 * sf: 0 -> 32bit, 1 -> 64bit
1916 * op: 0 -> add , 1 -> sub
1918 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
1920 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
1922 int rd
= extract32(insn
, 0, 5);
1923 int rn
= extract32(insn
, 5, 5);
1924 uint64_t imm
= extract32(insn
, 10, 12);
1925 int shift
= extract32(insn
, 22, 2);
1926 bool setflags
= extract32(insn
, 29, 1);
1927 bool sub_op
= extract32(insn
, 30, 1);
1928 bool is_64bit
= extract32(insn
, 31, 1);
1930 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
1931 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
1932 TCGv_i64 tcg_result
;
1941 unallocated_encoding(s
);
1945 tcg_result
= tcg_temp_new_i64();
1948 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
1950 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
1953 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
1955 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
1957 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
1959 tcg_temp_free_i64(tcg_imm
);
1963 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
1965 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
1968 tcg_temp_free_i64(tcg_result
);
1971 /* The input should be a value in the bottom e bits (with higher
1972 * bits zero); returns that value replicated into every element
1973 * of size e in a 64 bit integer.
1975 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
1985 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
1986 static inline uint64_t bitmask64(unsigned int length
)
1988 assert(length
> 0 && length
<= 64);
1989 return ~0ULL >> (64 - length
);
1992 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
1993 * only require the wmask. Returns false if the imms/immr/immn are a reserved
1994 * value (ie should cause a guest UNDEF exception), and true if they are
1995 * valid, in which case the decoded bit pattern is written to result.
1997 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
1998 unsigned int imms
, unsigned int immr
)
2001 unsigned e
, levels
, s
, r
;
2004 assert(immn
< 2 && imms
< 64 && immr
< 64);
2006 /* The bit patterns we create here are 64 bit patterns which
2007 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
2008 * 64 bits each. Each element contains the same value: a run
2009 * of between 1 and e-1 non-zero bits, rotated within the
2010 * element by between 0 and e-1 bits.
2012 * The element size and run length are encoded into immn (1 bit)
2013 * and imms (6 bits) as follows:
2014 * 64 bit elements: immn = 1, imms = <length of run - 1>
2015 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
2016 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
2017 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
2018 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
2019 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
2020 * Notice that immn = 0, imms = 11111x is the only combination
2021 * not covered by one of the above options; this is reserved.
2022 * Further, <length of run - 1> all-ones is a reserved pattern.
2024 * In all cases the rotation is by immr % e (and immr is 6 bits).
2027 /* First determine the element size */
2028 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
2030 /* This is the immn == 0, imms == 0x11111x case */
2040 /* <length of run - 1> mustn't be all-ones. */
2044 /* Create the value of one element: s+1 set bits rotated
2045 * by r within the element (which is e bits wide)...
2047 mask
= bitmask64(s
+ 1);
2048 mask
= (mask
>> r
) | (mask
<< (e
- r
));
2049 /* ...then replicate the element over the whole 64 bit value */
2050 mask
= bitfield_replicate(mask
, e
);
2055 /* C3.4.4 Logical (immediate)
2056 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2057 * +----+-----+-------------+---+------+------+------+------+
2058 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
2059 * +----+-----+-------------+---+------+------+------+------+
2061 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
2063 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
2064 TCGv_i64 tcg_rd
, tcg_rn
;
2066 bool is_and
= false;
2068 sf
= extract32(insn
, 31, 1);
2069 opc
= extract32(insn
, 29, 2);
2070 is_n
= extract32(insn
, 22, 1);
2071 immr
= extract32(insn
, 16, 6);
2072 imms
= extract32(insn
, 10, 6);
2073 rn
= extract32(insn
, 5, 5);
2074 rd
= extract32(insn
, 0, 5);
2077 unallocated_encoding(s
);
2081 if (opc
== 0x3) { /* ANDS */
2082 tcg_rd
= cpu_reg(s
, rd
);
2084 tcg_rd
= cpu_reg_sp(s
, rd
);
2086 tcg_rn
= cpu_reg(s
, rn
);
2088 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
2089 /* some immediate field values are reserved */
2090 unallocated_encoding(s
);
2095 wmask
&= 0xffffffff;
2099 case 0x3: /* ANDS */
2101 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
2105 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
2108 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
2111 assert(FALSE
); /* must handle all above */
2115 if (!sf
&& !is_and
) {
2116 /* zero extend final result; we know we can skip this for AND
2117 * since the immediate had the high 32 bits clear.
2119 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2122 if (opc
== 3) { /* ANDS */
2123 gen_logic_CC(sf
, tcg_rd
);
2128 * C3.4.5 Move wide (immediate)
2130 * 31 30 29 28 23 22 21 20 5 4 0
2131 * +--+-----+-------------+-----+----------------+------+
2132 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
2133 * +--+-----+-------------+-----+----------------+------+
2135 * sf: 0 -> 32 bit, 1 -> 64 bit
2136 * opc: 00 -> N, 10 -> Z, 11 -> K
2137 * hw: shift/16 (0,16, and sf only 32, 48)
2139 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
2141 int rd
= extract32(insn
, 0, 5);
2142 uint64_t imm
= extract32(insn
, 5, 16);
2143 int sf
= extract32(insn
, 31, 1);
2144 int opc
= extract32(insn
, 29, 2);
2145 int pos
= extract32(insn
, 21, 2) << 4;
2146 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2149 if (!sf
&& (pos
>= 32)) {
2150 unallocated_encoding(s
);
2164 tcg_gen_movi_i64(tcg_rd
, imm
);
2167 tcg_imm
= tcg_const_i64(imm
);
2168 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
2169 tcg_temp_free_i64(tcg_imm
);
2171 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2175 unallocated_encoding(s
);
2181 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2182 * +----+-----+-------------+---+------+------+------+------+
2183 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
2184 * +----+-----+-------------+---+------+------+------+------+
2186 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
2188 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
2189 TCGv_i64 tcg_rd
, tcg_tmp
;
2191 sf
= extract32(insn
, 31, 1);
2192 opc
= extract32(insn
, 29, 2);
2193 n
= extract32(insn
, 22, 1);
2194 ri
= extract32(insn
, 16, 6);
2195 si
= extract32(insn
, 10, 6);
2196 rn
= extract32(insn
, 5, 5);
2197 rd
= extract32(insn
, 0, 5);
2198 bitsize
= sf
? 64 : 32;
2200 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
2201 unallocated_encoding(s
);
2205 tcg_rd
= cpu_reg(s
, rd
);
2206 tcg_tmp
= read_cpu_reg(s
, rn
, sf
);
2208 /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
2210 if (opc
!= 1) { /* SBFM or UBFM */
2211 tcg_gen_movi_i64(tcg_rd
, 0);
2214 /* do the bit move operation */
2216 /* Wd<s-r:0> = Wn<s:r> */
2217 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
2219 len
= (si
- ri
) + 1;
2221 /* Wd<32+s-r,32-r> = Wn<s:0> */
2226 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
2228 if (opc
== 0) { /* SBFM - sign extend the destination field */
2229 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
2230 tcg_gen_sari_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
2233 if (!sf
) { /* zero extend final result */
2234 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2239 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
2240 * +----+------+-------------+---+----+------+--------+------+------+
2241 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
2242 * +----+------+-------------+---+----+------+--------+------+------+
2244 static void disas_extract(DisasContext
*s
, uint32_t insn
)
2246 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
2248 sf
= extract32(insn
, 31, 1);
2249 n
= extract32(insn
, 22, 1);
2250 rm
= extract32(insn
, 16, 5);
2251 imm
= extract32(insn
, 10, 6);
2252 rn
= extract32(insn
, 5, 5);
2253 rd
= extract32(insn
, 0, 5);
2254 op21
= extract32(insn
, 29, 2);
2255 op0
= extract32(insn
, 21, 1);
2256 bitsize
= sf
? 64 : 32;
2258 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
2259 unallocated_encoding(s
);
2261 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
2263 tcg_rd
= cpu_reg(s
, rd
);
2266 /* OPTME: we can special case rm==rn as a rotate */
2267 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
2268 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
2269 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
2270 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
2271 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
2273 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2276 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
2277 * so an extract from bit 0 is a special case.
2280 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
2282 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
2289 /* C3.4 Data processing - immediate */
2290 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
2292 switch (extract32(insn
, 23, 6)) {
2293 case 0x20: case 0x21: /* PC-rel. addressing */
2294 disas_pc_rel_adr(s
, insn
);
2296 case 0x22: case 0x23: /* Add/subtract (immediate) */
2297 disas_add_sub_imm(s
, insn
);
2299 case 0x24: /* Logical (immediate) */
2300 disas_logic_imm(s
, insn
);
2302 case 0x25: /* Move wide (immediate) */
2303 disas_movw_imm(s
, insn
);
2305 case 0x26: /* Bitfield */
2306 disas_bitfield(s
, insn
);
2308 case 0x27: /* Extract */
2309 disas_extract(s
, insn
);
2312 unallocated_encoding(s
);
2317 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
2318 * Note that it is the caller's responsibility to ensure that the
2319 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
2320 * mandated semantics for out of range shifts.
2322 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
2323 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
2325 switch (shift_type
) {
2326 case A64_SHIFT_TYPE_LSL
:
2327 tcg_gen_shl_i64(dst
, src
, shift_amount
);
2329 case A64_SHIFT_TYPE_LSR
:
2330 tcg_gen_shr_i64(dst
, src
, shift_amount
);
2332 case A64_SHIFT_TYPE_ASR
:
2334 tcg_gen_ext32s_i64(dst
, src
);
2336 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
2338 case A64_SHIFT_TYPE_ROR
:
2340 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
2343 t0
= tcg_temp_new_i32();
2344 t1
= tcg_temp_new_i32();
2345 tcg_gen_trunc_i64_i32(t0
, src
);
2346 tcg_gen_trunc_i64_i32(t1
, shift_amount
);
2347 tcg_gen_rotr_i32(t0
, t0
, t1
);
2348 tcg_gen_extu_i32_i64(dst
, t0
);
2349 tcg_temp_free_i32(t0
);
2350 tcg_temp_free_i32(t1
);
2354 assert(FALSE
); /* all shift types should be handled */
2358 if (!sf
) { /* zero extend final result */
2359 tcg_gen_ext32u_i64(dst
, dst
);
2363 /* Shift a TCGv src by immediate, put result in dst.
2364 * The shift amount must be in range (this should always be true as the
2365 * relevant instructions will UNDEF on bad shift immediates).
2367 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
2368 enum a64_shift_type shift_type
, unsigned int shift_i
)
2370 assert(shift_i
< (sf
? 64 : 32));
2373 tcg_gen_mov_i64(dst
, src
);
2375 TCGv_i64 shift_const
;
2377 shift_const
= tcg_const_i64(shift_i
);
2378 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
2379 tcg_temp_free_i64(shift_const
);
2383 /* C3.5.10 Logical (shifted register)
2384 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
2385 * +----+-----+-----------+-------+---+------+--------+------+------+
2386 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
2387 * +----+-----+-----------+-------+---+------+--------+------+------+
2389 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
2391 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
2392 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
2394 sf
= extract32(insn
, 31, 1);
2395 opc
= extract32(insn
, 29, 2);
2396 shift_type
= extract32(insn
, 22, 2);
2397 invert
= extract32(insn
, 21, 1);
2398 rm
= extract32(insn
, 16, 5);
2399 shift_amount
= extract32(insn
, 10, 6);
2400 rn
= extract32(insn
, 5, 5);
2401 rd
= extract32(insn
, 0, 5);
2403 if (!sf
&& (shift_amount
& (1 << 5))) {
2404 unallocated_encoding(s
);
2408 tcg_rd
= cpu_reg(s
, rd
);
2410 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
2411 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
2412 * register-register MOV and MVN, so it is worth special casing.
2414 tcg_rm
= cpu_reg(s
, rm
);
2416 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
2418 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2422 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
2424 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
2430 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
2433 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
2436 tcg_rn
= cpu_reg(s
, rn
);
2438 switch (opc
| (invert
<< 2)) {
2441 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
2444 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
2447 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
2451 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
2454 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
2457 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
2465 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2469 gen_logic_CC(sf
, tcg_rd
);
2474 * C3.5.1 Add/subtract (extended register)
2476 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
2477 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
2478 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
2479 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
2481 * sf: 0 -> 32bit, 1 -> 64bit
2482 * op: 0 -> add , 1 -> sub
2485 * option: extension type (see DecodeRegExtend)
2486 * imm3: optional shift to Rm
2488 * Rd = Rn + LSL(extend(Rm), amount)
2490 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
2492 int rd
= extract32(insn
, 0, 5);
2493 int rn
= extract32(insn
, 5, 5);
2494 int imm3
= extract32(insn
, 10, 3);
2495 int option
= extract32(insn
, 13, 3);
2496 int rm
= extract32(insn
, 16, 5);
2497 bool setflags
= extract32(insn
, 29, 1);
2498 bool sub_op
= extract32(insn
, 30, 1);
2499 bool sf
= extract32(insn
, 31, 1);
2501 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
2503 TCGv_i64 tcg_result
;
2506 unallocated_encoding(s
);
2510 /* non-flag setting ops may use SP */
2512 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
2513 tcg_rd
= cpu_reg_sp(s
, rd
);
2515 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
2516 tcg_rd
= cpu_reg(s
, rd
);
2519 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
2520 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
2522 tcg_result
= tcg_temp_new_i64();
2526 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
2528 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
2532 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
2534 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
2539 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2541 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2544 tcg_temp_free_i64(tcg_result
);
2548 * C3.5.2 Add/subtract (shifted register)
2550 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
2551 * +--+--+--+-----------+-----+--+-------+---------+------+------+
2552 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
2553 * +--+--+--+-----------+-----+--+-------+---------+------+------+
2555 * sf: 0 -> 32bit, 1 -> 64bit
2556 * op: 0 -> add , 1 -> sub
2558 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
2559 * imm6: Shift amount to apply to Rm before the add/sub
2561 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
2563 int rd
= extract32(insn
, 0, 5);
2564 int rn
= extract32(insn
, 5, 5);
2565 int imm6
= extract32(insn
, 10, 6);
2566 int rm
= extract32(insn
, 16, 5);
2567 int shift_type
= extract32(insn
, 22, 2);
2568 bool setflags
= extract32(insn
, 29, 1);
2569 bool sub_op
= extract32(insn
, 30, 1);
2570 bool sf
= extract32(insn
, 31, 1);
2572 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2573 TCGv_i64 tcg_rn
, tcg_rm
;
2574 TCGv_i64 tcg_result
;
2576 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
2577 unallocated_encoding(s
);
2581 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
2582 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
2584 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
2586 tcg_result
= tcg_temp_new_i64();
2590 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
2592 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
2596 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
2598 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
2603 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2605 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2608 tcg_temp_free_i64(tcg_result
);
2611 /* C3.5.9 Data-processing (3 source)
2613 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
2614 +--+------+-----------+------+------+----+------+------+------+
2615 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
2616 +--+------+-----------+------+------+----+------+------+------+
2619 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
2621 int rd
= extract32(insn
, 0, 5);
2622 int rn
= extract32(insn
, 5, 5);
2623 int ra
= extract32(insn
, 10, 5);
2624 int rm
= extract32(insn
, 16, 5);
2625 int op_id
= (extract32(insn
, 29, 3) << 4) |
2626 (extract32(insn
, 21, 3) << 1) |
2627 extract32(insn
, 15, 1);
2628 bool sf
= extract32(insn
, 31, 1);
2629 bool is_sub
= extract32(op_id
, 0, 1);
2630 bool is_high
= extract32(op_id
, 2, 1);
2631 bool is_signed
= false;
2636 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
2638 case 0x42: /* SMADDL */
2639 case 0x43: /* SMSUBL */
2640 case 0x44: /* SMULH */
2643 case 0x0: /* MADD (32bit) */
2644 case 0x1: /* MSUB (32bit) */
2645 case 0x40: /* MADD (64bit) */
2646 case 0x41: /* MSUB (64bit) */
2647 case 0x4a: /* UMADDL */
2648 case 0x4b: /* UMSUBL */
2649 case 0x4c: /* UMULH */
2652 unallocated_encoding(s
);
2657 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
2658 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2659 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
2660 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
2663 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
2665 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
2668 tcg_temp_free_i64(low_bits
);
2672 tcg_op1
= tcg_temp_new_i64();
2673 tcg_op2
= tcg_temp_new_i64();
2674 tcg_tmp
= tcg_temp_new_i64();
2677 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
2678 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
2681 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
2682 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
2684 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
2685 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
2689 if (ra
== 31 && !is_sub
) {
2690 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
2691 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
2693 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
2695 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
2697 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
2702 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
2705 tcg_temp_free_i64(tcg_op1
);
2706 tcg_temp_free_i64(tcg_op2
);
2707 tcg_temp_free_i64(tcg_tmp
);
2710 /* C3.5.3 - Add/subtract (with carry)
2711 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
2712 * +--+--+--+------------------------+------+---------+------+-----+
2713 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
2714 * +--+--+--+------------------------+------+---------+------+-----+
2718 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
2720 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
2721 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
2723 if (extract32(insn
, 10, 6) != 0) {
2724 unallocated_encoding(s
);
2728 sf
= extract32(insn
, 31, 1);
2729 op
= extract32(insn
, 30, 1);
2730 setflags
= extract32(insn
, 29, 1);
2731 rm
= extract32(insn
, 16, 5);
2732 rn
= extract32(insn
, 5, 5);
2733 rd
= extract32(insn
, 0, 5);
2735 tcg_rd
= cpu_reg(s
, rd
);
2736 tcg_rn
= cpu_reg(s
, rn
);
2739 tcg_y
= new_tmp_a64(s
);
2740 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
2742 tcg_y
= cpu_reg(s
, rm
);
2746 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
2748 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
2752 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
2753 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
2754 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
2755 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
2756 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
2759 static void disas_cc(DisasContext
*s
, uint32_t insn
)
2761 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
2762 int label_continue
= -1;
2763 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
2765 if (!extract32(insn
, 29, 1)) {
2766 unallocated_encoding(s
);
2769 if (insn
& (1 << 10 | 1 << 4)) {
2770 unallocated_encoding(s
);
2773 sf
= extract32(insn
, 31, 1);
2774 op
= extract32(insn
, 30, 1);
2775 is_imm
= extract32(insn
, 11, 1);
2776 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
2777 cond
= extract32(insn
, 12, 4);
2778 rn
= extract32(insn
, 5, 5);
2779 nzcv
= extract32(insn
, 0, 4);
2781 if (cond
< 0x0e) { /* not always */
2782 int label_match
= gen_new_label();
2783 label_continue
= gen_new_label();
2784 arm_gen_test_cc(cond
, label_match
);
2786 tcg_tmp
= tcg_temp_new_i64();
2787 tcg_gen_movi_i64(tcg_tmp
, nzcv
<< 28);
2788 gen_set_nzcv(tcg_tmp
);
2789 tcg_temp_free_i64(tcg_tmp
);
2790 tcg_gen_br(label_continue
);
2791 gen_set_label(label_match
);
2793 /* match, or condition is always */
2795 tcg_y
= new_tmp_a64(s
);
2796 tcg_gen_movi_i64(tcg_y
, y
);
2798 tcg_y
= cpu_reg(s
, y
);
2800 tcg_rn
= cpu_reg(s
, rn
);
2802 tcg_tmp
= tcg_temp_new_i64();
2804 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
2806 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
2808 tcg_temp_free_i64(tcg_tmp
);
2810 if (cond
< 0x0e) { /* continue */
2811 gen_set_label(label_continue
);
2815 /* C3.5.6 Conditional select
2816 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
2817 * +----+----+---+-----------------+------+------+-----+------+------+
2818 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
2819 * +----+----+---+-----------------+------+------+-----+------+------+
2821 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
2823 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
2824 TCGv_i64 tcg_rd
, tcg_src
;
2826 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
2827 /* S == 1 or op2<1> == 1 */
2828 unallocated_encoding(s
);
2831 sf
= extract32(insn
, 31, 1);
2832 else_inv
= extract32(insn
, 30, 1);
2833 rm
= extract32(insn
, 16, 5);
2834 cond
= extract32(insn
, 12, 4);
2835 else_inc
= extract32(insn
, 10, 1);
2836 rn
= extract32(insn
, 5, 5);
2837 rd
= extract32(insn
, 0, 5);
2840 /* silly no-op write; until we use movcond we must special-case
2841 * this to avoid a dead temporary across basic blocks.
2846 tcg_rd
= cpu_reg(s
, rd
);
2848 if (cond
>= 0x0e) { /* condition "always" */
2849 tcg_src
= read_cpu_reg(s
, rn
, sf
);
2850 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
2852 /* OPTME: we could use movcond here, at the cost of duplicating
2853 * a lot of the arm_gen_test_cc() logic.
2855 int label_match
= gen_new_label();
2856 int label_continue
= gen_new_label();
2858 arm_gen_test_cc(cond
, label_match
);
2860 tcg_src
= cpu_reg(s
, rm
);
2862 if (else_inv
&& else_inc
) {
2863 tcg_gen_neg_i64(tcg_rd
, tcg_src
);
2864 } else if (else_inv
) {
2865 tcg_gen_not_i64(tcg_rd
, tcg_src
);
2866 } else if (else_inc
) {
2867 tcg_gen_addi_i64(tcg_rd
, tcg_src
, 1);
2869 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
2872 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2874 tcg_gen_br(label_continue
);
2876 gen_set_label(label_match
);
2877 tcg_src
= read_cpu_reg(s
, rn
, sf
);
2878 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
2880 gen_set_label(label_continue
);
2884 static void handle_clz(DisasContext
*s
, unsigned int sf
,
2885 unsigned int rn
, unsigned int rd
)
2887 TCGv_i64 tcg_rd
, tcg_rn
;
2888 tcg_rd
= cpu_reg(s
, rd
);
2889 tcg_rn
= cpu_reg(s
, rn
);
2892 gen_helper_clz64(tcg_rd
, tcg_rn
);
2894 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
2895 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
2896 gen_helper_clz(tcg_tmp32
, tcg_tmp32
);
2897 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
2898 tcg_temp_free_i32(tcg_tmp32
);
2902 static void handle_cls(DisasContext
*s
, unsigned int sf
,
2903 unsigned int rn
, unsigned int rd
)
2905 TCGv_i64 tcg_rd
, tcg_rn
;
2906 tcg_rd
= cpu_reg(s
, rd
);
2907 tcg_rn
= cpu_reg(s
, rn
);
2910 gen_helper_cls64(tcg_rd
, tcg_rn
);
2912 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
2913 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
2914 gen_helper_cls32(tcg_tmp32
, tcg_tmp32
);
2915 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
2916 tcg_temp_free_i32(tcg_tmp32
);
2920 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
2921 unsigned int rn
, unsigned int rd
)
2923 TCGv_i64 tcg_rd
, tcg_rn
;
2924 tcg_rd
= cpu_reg(s
, rd
);
2925 tcg_rn
= cpu_reg(s
, rn
);
2928 gen_helper_rbit64(tcg_rd
, tcg_rn
);
2930 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
2931 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
2932 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
2933 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
2934 tcg_temp_free_i32(tcg_tmp32
);
2938 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
2939 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
2940 unsigned int rn
, unsigned int rd
)
2943 unallocated_encoding(s
);
2946 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
2949 /* C5.6.149 REV with sf==0, opcode==2
2950 * C5.6.151 REV32 (sf==1, opcode==2)
2952 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
2953 unsigned int rn
, unsigned int rd
)
2955 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2958 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2959 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
2961 /* bswap32_i64 requires zero high word */
2962 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
2963 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
2964 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
2965 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
2966 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
2968 tcg_temp_free_i64(tcg_tmp
);
2970 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
2971 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
2975 /* C5.6.150 REV16 (opcode==1) */
2976 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
2977 unsigned int rn
, unsigned int rd
)
2979 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2980 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2981 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
2983 tcg_gen_andi_i64(tcg_tmp
, tcg_rn
, 0xffff);
2984 tcg_gen_bswap16_i64(tcg_rd
, tcg_tmp
);
2986 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 16);
2987 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
2988 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
2989 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 16, 16);
2992 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
2993 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
2994 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
2995 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 32, 16);
2997 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 48);
2998 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
2999 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 48, 16);
3002 tcg_temp_free_i64(tcg_tmp
);
3005 /* C3.5.7 Data-processing (1 source)
3006 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3007 * +----+---+---+-----------------+---------+--------+------+------+
3008 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
3009 * +----+---+---+-----------------+---------+--------+------+------+
3011 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
3013 unsigned int sf
, opcode
, rn
, rd
;
3015 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
3016 unallocated_encoding(s
);
3020 sf
= extract32(insn
, 31, 1);
3021 opcode
= extract32(insn
, 10, 6);
3022 rn
= extract32(insn
, 5, 5);
3023 rd
= extract32(insn
, 0, 5);
3027 handle_rbit(s
, sf
, rn
, rd
);
3030 handle_rev16(s
, sf
, rn
, rd
);
3033 handle_rev32(s
, sf
, rn
, rd
);
3036 handle_rev64(s
, sf
, rn
, rd
);
3039 handle_clz(s
, sf
, rn
, rd
);
3042 handle_cls(s
, sf
, rn
, rd
);
3047 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
3048 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3050 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
3051 tcg_rd
= cpu_reg(s
, rd
);
3053 if (!sf
&& is_signed
) {
3054 tcg_n
= new_tmp_a64(s
);
3055 tcg_m
= new_tmp_a64(s
);
3056 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
3057 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
3059 tcg_n
= read_cpu_reg(s
, rn
, sf
);
3060 tcg_m
= read_cpu_reg(s
, rm
, sf
);
3064 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
3066 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
3069 if (!sf
) { /* zero extend final result */
3070 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3074 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
3075 static void handle_shift_reg(DisasContext
*s
,
3076 enum a64_shift_type shift_type
, unsigned int sf
,
3077 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3079 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
3080 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3081 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3083 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
3084 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
3085 tcg_temp_free_i64(tcg_shift
);
3088 /* C3.5.8 Data-processing (2 source)
3089 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3090 * +----+---+---+-----------------+------+--------+------+------+
3091 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
3092 * +----+---+---+-----------------+------+--------+------+------+
3094 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
3096 unsigned int sf
, rm
, opcode
, rn
, rd
;
3097 sf
= extract32(insn
, 31, 1);
3098 rm
= extract32(insn
, 16, 5);
3099 opcode
= extract32(insn
, 10, 6);
3100 rn
= extract32(insn
, 5, 5);
3101 rd
= extract32(insn
, 0, 5);
3103 if (extract32(insn
, 29, 1)) {
3104 unallocated_encoding(s
);
3110 handle_div(s
, false, sf
, rm
, rn
, rd
);
3113 handle_div(s
, true, sf
, rm
, rn
, rd
);
3116 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
3119 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
3122 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
3125 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
3134 case 23: /* CRC32 */
3135 unsupported_encoding(s
, insn
);
3138 unallocated_encoding(s
);
3143 /* C3.5 Data processing - register */
3144 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
3146 switch (extract32(insn
, 24, 5)) {
3147 case 0x0a: /* Logical (shifted register) */
3148 disas_logic_reg(s
, insn
);
3150 case 0x0b: /* Add/subtract */
3151 if (insn
& (1 << 21)) { /* (extended register) */
3152 disas_add_sub_ext_reg(s
, insn
);
3154 disas_add_sub_reg(s
, insn
);
3157 case 0x1b: /* Data-processing (3 source) */
3158 disas_data_proc_3src(s
, insn
);
3161 switch (extract32(insn
, 21, 3)) {
3162 case 0x0: /* Add/subtract (with carry) */
3163 disas_adc_sbc(s
, insn
);
3165 case 0x2: /* Conditional compare */
3166 disas_cc(s
, insn
); /* both imm and reg forms */
3168 case 0x4: /* Conditional select */
3169 disas_cond_select(s
, insn
);
3171 case 0x6: /* Data-processing */
3172 if (insn
& (1 << 30)) { /* (1 source) */
3173 disas_data_proc_1src(s
, insn
);
3174 } else { /* (2 source) */
3175 disas_data_proc_2src(s
, insn
);
3179 unallocated_encoding(s
);
3184 unallocated_encoding(s
);
3189 /* Convert ARM rounding mode to softfloat */
3190 static inline int arm_rmode_to_sf(int rmode
)
3193 case FPROUNDING_TIEAWAY
:
3194 rmode
= float_round_ties_away
;
3196 case FPROUNDING_ODD
:
3197 /* FIXME: add support for TIEAWAY and ODD */
3198 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
3200 case FPROUNDING_TIEEVEN
:
3202 rmode
= float_round_nearest_even
;
3204 case FPROUNDING_POSINF
:
3205 rmode
= float_round_up
;
3207 case FPROUNDING_NEGINF
:
3208 rmode
= float_round_down
;
3210 case FPROUNDING_ZERO
:
3211 rmode
= float_round_to_zero
;
3217 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
3218 unsigned int rn
, unsigned int rm
,
3219 bool cmp_with_zero
, bool signal_all_nans
)
3221 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
3222 TCGv_ptr fpst
= get_fpstatus_ptr();
3225 TCGv_i64 tcg_vn
, tcg_vm
;
3227 tcg_vn
= read_fp_dreg(s
, rn
);
3228 if (cmp_with_zero
) {
3229 tcg_vm
= tcg_const_i64(0);
3231 tcg_vm
= read_fp_dreg(s
, rm
);
3233 if (signal_all_nans
) {
3234 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3236 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3238 tcg_temp_free_i64(tcg_vn
);
3239 tcg_temp_free_i64(tcg_vm
);
3241 TCGv_i32 tcg_vn
, tcg_vm
;
3243 tcg_vn
= read_fp_sreg(s
, rn
);
3244 if (cmp_with_zero
) {
3245 tcg_vm
= tcg_const_i32(0);
3247 tcg_vm
= read_fp_sreg(s
, rm
);
3249 if (signal_all_nans
) {
3250 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3252 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3254 tcg_temp_free_i32(tcg_vn
);
3255 tcg_temp_free_i32(tcg_vm
);
3258 tcg_temp_free_ptr(fpst
);
3260 gen_set_nzcv(tcg_flags
);
3262 tcg_temp_free_i64(tcg_flags
);
3265 /* C3.6.22 Floating point compare
3266 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
3267 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
3268 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
3269 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
3271 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
3273 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
3275 mos
= extract32(insn
, 29, 3);
3276 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
3277 rm
= extract32(insn
, 16, 5);
3278 op
= extract32(insn
, 14, 2);
3279 rn
= extract32(insn
, 5, 5);
3280 opc
= extract32(insn
, 3, 2);
3281 op2r
= extract32(insn
, 0, 3);
3283 if (mos
|| op
|| op2r
|| type
> 1) {
3284 unallocated_encoding(s
);
3288 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
3291 /* C3.6.23 Floating point conditional compare
3292 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3293 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
3294 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
3295 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
3297 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
3299 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
3301 int label_continue
= -1;
3303 mos
= extract32(insn
, 29, 3);
3304 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
3305 rm
= extract32(insn
, 16, 5);
3306 cond
= extract32(insn
, 12, 4);
3307 rn
= extract32(insn
, 5, 5);
3308 op
= extract32(insn
, 4, 1);
3309 nzcv
= extract32(insn
, 0, 4);
3311 if (mos
|| type
> 1) {
3312 unallocated_encoding(s
);
3316 if (cond
< 0x0e) { /* not always */
3317 int label_match
= gen_new_label();
3318 label_continue
= gen_new_label();
3319 arm_gen_test_cc(cond
, label_match
);
3321 tcg_flags
= tcg_const_i64(nzcv
<< 28);
3322 gen_set_nzcv(tcg_flags
);
3323 tcg_temp_free_i64(tcg_flags
);
3324 tcg_gen_br(label_continue
);
3325 gen_set_label(label_match
);
3328 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
3331 gen_set_label(label_continue
);
3335 /* copy src FP register to dst FP register; type specifies single or double */
3336 static void gen_mov_fp2fp(DisasContext
*s
, int type
, int dst
, int src
)
3339 TCGv_i64 v
= read_fp_dreg(s
, src
);
3340 write_fp_dreg(s
, dst
, v
);
3341 tcg_temp_free_i64(v
);
3343 TCGv_i32 v
= read_fp_sreg(s
, src
);
3344 write_fp_sreg(s
, dst
, v
);
3345 tcg_temp_free_i32(v
);
3349 /* C3.6.24 Floating point conditional select
3350 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
3351 * +---+---+---+-----------+------+---+------+------+-----+------+------+
3352 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
3353 * +---+---+---+-----------+------+---+------+------+-----+------+------+
3355 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
3357 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
3358 int label_continue
= -1;
3360 mos
= extract32(insn
, 29, 3);
3361 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
3362 rm
= extract32(insn
, 16, 5);
3363 cond
= extract32(insn
, 12, 4);
3364 rn
= extract32(insn
, 5, 5);
3365 rd
= extract32(insn
, 0, 5);
3367 if (mos
|| type
> 1) {
3368 unallocated_encoding(s
);
3372 if (cond
< 0x0e) { /* not always */
3373 int label_match
= gen_new_label();
3374 label_continue
= gen_new_label();
3375 arm_gen_test_cc(cond
, label_match
);
3377 gen_mov_fp2fp(s
, type
, rd
, rm
);
3378 tcg_gen_br(label_continue
);
3379 gen_set_label(label_match
);
3382 gen_mov_fp2fp(s
, type
, rd
, rn
);
3384 if (cond
< 0x0e) { /* continue */
3385 gen_set_label(label_continue
);
3389 /* C3.6.25 Floating point data-processing (1 source)
3390 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
3391 * +---+---+---+-----------+------+---+--------+-----------+------+------+
3392 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
3393 * +---+---+---+-----------+------+---+--------+-----------+------+------+
3395 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
3397 unsupported_encoding(s
, insn
);
3400 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
3401 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
3402 int rd
, int rn
, int rm
)
3409 tcg_res
= tcg_temp_new_i32();
3410 fpst
= get_fpstatus_ptr();
3411 tcg_op1
= read_fp_sreg(s
, rn
);
3412 tcg_op2
= read_fp_sreg(s
, rm
);
3415 case 0x0: /* FMUL */
3416 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
3418 case 0x1: /* FDIV */
3419 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
3421 case 0x2: /* FADD */
3422 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
3424 case 0x3: /* FSUB */
3425 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
3427 case 0x4: /* FMAX */
3428 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
3430 case 0x5: /* FMIN */
3431 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
3433 case 0x6: /* FMAXNM */
3434 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
3436 case 0x7: /* FMINNM */
3437 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
3439 case 0x8: /* FNMUL */
3440 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
3441 gen_helper_vfp_negs(tcg_res
, tcg_res
);
3445 write_fp_sreg(s
, rd
, tcg_res
);
3447 tcg_temp_free_ptr(fpst
);
3448 tcg_temp_free_i32(tcg_op1
);
3449 tcg_temp_free_i32(tcg_op2
);
3450 tcg_temp_free_i32(tcg_res
);
3453 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
3454 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
3455 int rd
, int rn
, int rm
)
3462 tcg_res
= tcg_temp_new_i64();
3463 fpst
= get_fpstatus_ptr();
3464 tcg_op1
= read_fp_dreg(s
, rn
);
3465 tcg_op2
= read_fp_dreg(s
, rm
);
3468 case 0x0: /* FMUL */
3469 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
3471 case 0x1: /* FDIV */
3472 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
3474 case 0x2: /* FADD */
3475 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
3477 case 0x3: /* FSUB */
3478 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
3480 case 0x4: /* FMAX */
3481 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
3483 case 0x5: /* FMIN */
3484 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
3486 case 0x6: /* FMAXNM */
3487 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
3489 case 0x7: /* FMINNM */
3490 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
3492 case 0x8: /* FNMUL */
3493 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
3494 gen_helper_vfp_negd(tcg_res
, tcg_res
);
3498 write_fp_dreg(s
, rd
, tcg_res
);
3500 tcg_temp_free_ptr(fpst
);
3501 tcg_temp_free_i64(tcg_op1
);
3502 tcg_temp_free_i64(tcg_op2
);
3503 tcg_temp_free_i64(tcg_res
);
3506 /* C3.6.26 Floating point data-processing (2 source)
3507 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
3508 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
3509 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
3510 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
3512 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
3514 int type
= extract32(insn
, 22, 2);
3515 int rd
= extract32(insn
, 0, 5);
3516 int rn
= extract32(insn
, 5, 5);
3517 int rm
= extract32(insn
, 16, 5);
3518 int opcode
= extract32(insn
, 12, 4);
3521 unallocated_encoding(s
);
3527 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
3530 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
3533 unallocated_encoding(s
);
3537 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
3538 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
3539 int rd
, int rn
, int rm
, int ra
)
3541 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
3542 TCGv_i32 tcg_res
= tcg_temp_new_i32();
3543 TCGv_ptr fpst
= get_fpstatus_ptr();
3545 tcg_op1
= read_fp_sreg(s
, rn
);
3546 tcg_op2
= read_fp_sreg(s
, rm
);
3547 tcg_op3
= read_fp_sreg(s
, ra
);
3549 /* These are fused multiply-add, and must be done as one
3550 * floating point operation with no rounding between the
3551 * multiplication and addition steps.
3552 * NB that doing the negations here as separate steps is
3553 * correct : an input NaN should come out with its sign bit
3554 * flipped if it is a negated-input.
3557 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
3561 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
3564 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
3566 write_fp_sreg(s
, rd
, tcg_res
);
3568 tcg_temp_free_ptr(fpst
);
3569 tcg_temp_free_i32(tcg_op1
);
3570 tcg_temp_free_i32(tcg_op2
);
3571 tcg_temp_free_i32(tcg_op3
);
3572 tcg_temp_free_i32(tcg_res
);
3575 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
3576 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
3577 int rd
, int rn
, int rm
, int ra
)
3579 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
3580 TCGv_i64 tcg_res
= tcg_temp_new_i64();
3581 TCGv_ptr fpst
= get_fpstatus_ptr();
3583 tcg_op1
= read_fp_dreg(s
, rn
);
3584 tcg_op2
= read_fp_dreg(s
, rm
);
3585 tcg_op3
= read_fp_dreg(s
, ra
);
3587 /* These are fused multiply-add, and must be done as one
3588 * floating point operation with no rounding between the
3589 * multiplication and addition steps.
3590 * NB that doing the negations here as separate steps is
3591 * correct : an input NaN should come out with its sign bit
3592 * flipped if it is a negated-input.
3595 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
3599 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
3602 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
3604 write_fp_dreg(s
, rd
, tcg_res
);
3606 tcg_temp_free_ptr(fpst
);
3607 tcg_temp_free_i64(tcg_op1
);
3608 tcg_temp_free_i64(tcg_op2
);
3609 tcg_temp_free_i64(tcg_op3
);
3610 tcg_temp_free_i64(tcg_res
);
3613 /* C3.6.27 Floating point data-processing (3 source)
3614 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
3615 * +---+---+---+-----------+------+----+------+----+------+------+------+
3616 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
3617 * +---+---+---+-----------+------+----+------+----+------+------+------+
3619 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
3621 int type
= extract32(insn
, 22, 2);
3622 int rd
= extract32(insn
, 0, 5);
3623 int rn
= extract32(insn
, 5, 5);
3624 int ra
= extract32(insn
, 10, 5);
3625 int rm
= extract32(insn
, 16, 5);
3626 bool o0
= extract32(insn
, 15, 1);
3627 bool o1
= extract32(insn
, 21, 1);
3631 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
3634 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
3637 unallocated_encoding(s
);
3641 /* C3.6.28 Floating point immediate
3642 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
3643 * +---+---+---+-----------+------+---+------------+-------+------+------+
3644 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
3645 * +---+---+---+-----------+------+---+------------+-------+------+------+
3647 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
3649 int rd
= extract32(insn
, 0, 5);
3650 int imm8
= extract32(insn
, 13, 8);
3651 int is_double
= extract32(insn
, 22, 2);
3655 if (is_double
> 1) {
3656 unallocated_encoding(s
);
3660 /* The imm8 encodes the sign bit, enough bits to represent
3661 * an exponent in the range 01....1xx to 10....0xx,
3662 * and the most significant 4 bits of the mantissa; see
3663 * VFPExpandImm() in the v8 ARM ARM.
3666 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
3667 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
3668 extract32(imm8
, 0, 6);
3671 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
3672 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
3673 (extract32(imm8
, 0, 6) << 3);
3677 tcg_res
= tcg_const_i64(imm
);
3678 write_fp_dreg(s
, rd
, tcg_res
);
3679 tcg_temp_free_i64(tcg_res
);
3682 /* Handle floating point <=> fixed point conversions. Note that we can
3683 * also deal with fp <=> integer conversions as a special case (scale == 64)
3684 * OPTME: consider handling that special case specially or at least skipping
3685 * the call to scalbn in the helpers for zero shifts.
3687 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
3688 bool itof
, int rmode
, int scale
, int sf
, int type
)
3690 bool is_signed
= !(opcode
& 1);
3691 bool is_double
= type
;
3692 TCGv_ptr tcg_fpstatus
;
3695 tcg_fpstatus
= get_fpstatus_ptr();
3697 tcg_shift
= tcg_const_i32(64 - scale
);
3700 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
3702 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
3705 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
3707 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
3710 tcg_int
= tcg_extend
;
3714 TCGv_i64 tcg_double
= tcg_temp_new_i64();
3716 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
3717 tcg_shift
, tcg_fpstatus
);
3719 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
3720 tcg_shift
, tcg_fpstatus
);
3722 write_fp_dreg(s
, rd
, tcg_double
);
3723 tcg_temp_free_i64(tcg_double
);
3725 TCGv_i32 tcg_single
= tcg_temp_new_i32();
3727 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
3728 tcg_shift
, tcg_fpstatus
);
3730 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
3731 tcg_shift
, tcg_fpstatus
);
3733 write_fp_sreg(s
, rd
, tcg_single
);
3734 tcg_temp_free_i32(tcg_single
);
3737 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
3740 if (extract32(opcode
, 2, 1)) {
3741 /* There are too many rounding modes to all fit into rmode,
3742 * so FCVTA[US] is a special case.
3744 rmode
= FPROUNDING_TIEAWAY
;
3747 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
3749 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
3752 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
3755 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
3756 tcg_shift
, tcg_fpstatus
);
3758 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
3759 tcg_shift
, tcg_fpstatus
);
3763 gen_helper_vfp_tould(tcg_int
, tcg_double
,
3764 tcg_shift
, tcg_fpstatus
);
3766 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
3767 tcg_shift
, tcg_fpstatus
);
3770 tcg_temp_free_i64(tcg_double
);
3772 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
3775 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
3776 tcg_shift
, tcg_fpstatus
);
3778 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
3779 tcg_shift
, tcg_fpstatus
);
3782 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
3784 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
3785 tcg_shift
, tcg_fpstatus
);
3787 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
3788 tcg_shift
, tcg_fpstatus
);
3790 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
3791 tcg_temp_free_i32(tcg_dest
);
3793 tcg_temp_free_i32(tcg_single
);
3796 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
3797 tcg_temp_free_i32(tcg_rmode
);
3800 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
3804 tcg_temp_free_ptr(tcg_fpstatus
);
3805 tcg_temp_free_i32(tcg_shift
);
3808 /* C3.6.29 Floating point <-> fixed point conversions
3809 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
3810 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
3811 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
3812 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
3814 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
3816 int rd
= extract32(insn
, 0, 5);
3817 int rn
= extract32(insn
, 5, 5);
3818 int scale
= extract32(insn
, 10, 6);
3819 int opcode
= extract32(insn
, 16, 3);
3820 int rmode
= extract32(insn
, 19, 2);
3821 int type
= extract32(insn
, 22, 2);
3822 bool sbit
= extract32(insn
, 29, 1);
3823 bool sf
= extract32(insn
, 31, 1);
3826 if (sbit
|| (type
> 1)
3827 || (!sf
&& scale
< 32)) {
3828 unallocated_encoding(s
);
3832 switch ((rmode
<< 3) | opcode
) {
3833 case 0x2: /* SCVTF */
3834 case 0x3: /* UCVTF */
3837 case 0x18: /* FCVTZS */
3838 case 0x19: /* FCVTZU */
3842 unallocated_encoding(s
);
3846 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
3849 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
3851 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
3852 * without conversion.
3856 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3862 TCGv_i64 tmp
= tcg_temp_new_i64();
3863 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
3864 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(rd
, MO_64
));
3865 tcg_gen_movi_i64(tmp
, 0);
3866 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(rd
));
3867 tcg_temp_free_i64(tmp
);
3873 TCGv_i64 tmp
= tcg_const_i64(0);
3874 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(rd
, MO_64
));
3875 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(rd
));
3876 tcg_temp_free_i64(tmp
);
3880 /* 64 bit to top half. */
3881 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(rd
));
3885 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3890 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(rn
, MO_32
));
3894 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(rn
, MO_64
));
3897 /* 64 bits from top half */
3898 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(rn
));
3904 /* C3.6.30 Floating point <-> integer conversions
3905 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
3906 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
3907 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
3908 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
3910 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
3912 int rd
= extract32(insn
, 0, 5);
3913 int rn
= extract32(insn
, 5, 5);
3914 int opcode
= extract32(insn
, 16, 3);
3915 int rmode
= extract32(insn
, 19, 2);
3916 int type
= extract32(insn
, 22, 2);
3917 bool sbit
= extract32(insn
, 29, 1);
3918 bool sf
= extract32(insn
, 31, 1);
3921 unallocated_encoding(s
);
3927 bool itof
= opcode
& 1;
3930 unallocated_encoding(s
);
3934 switch (sf
<< 3 | type
<< 1 | rmode
) {
3935 case 0x0: /* 32 bit */
3936 case 0xa: /* 64 bit */
3937 case 0xd: /* 64 bit to top half of quad */
3940 /* all other sf/type/rmode combinations are invalid */
3941 unallocated_encoding(s
);
3945 handle_fmov(s
, rd
, rn
, type
, itof
);
3947 /* actual FP conversions */
3948 bool itof
= extract32(opcode
, 1, 1);
3950 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
3951 unallocated_encoding(s
);
3955 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
3959 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
3960 * 31 30 29 28 25 24 0
3961 * +---+---+---+---------+-----------------------------+
3962 * | | 0 | | 1 1 1 1 | |
3963 * +---+---+---+---------+-----------------------------+
3965 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
3967 if (extract32(insn
, 24, 1)) {
3968 /* Floating point data-processing (3 source) */
3969 disas_fp_3src(s
, insn
);
3970 } else if (extract32(insn
, 21, 1) == 0) {
3971 /* Floating point to fixed point conversions */
3972 disas_fp_fixed_conv(s
, insn
);
3974 switch (extract32(insn
, 10, 2)) {
3976 /* Floating point conditional compare */
3977 disas_fp_ccomp(s
, insn
);
3980 /* Floating point data-processing (2 source) */
3981 disas_fp_2src(s
, insn
);
3984 /* Floating point conditional select */
3985 disas_fp_csel(s
, insn
);
3988 switch (ctz32(extract32(insn
, 12, 4))) {
3989 case 0: /* [15:12] == xxx1 */
3990 /* Floating point immediate */
3991 disas_fp_imm(s
, insn
);
3993 case 1: /* [15:12] == xx10 */
3994 /* Floating point compare */
3995 disas_fp_compare(s
, insn
);
3997 case 2: /* [15:12] == x100 */
3998 /* Floating point data-processing (1 source) */
3999 disas_fp_1src(s
, insn
);
4001 case 3: /* [15:12] == 1000 */
4002 unallocated_encoding(s
);
4004 default: /* [15:12] == 0000 */
4005 /* Floating point <-> integer conversions */
4006 disas_fp_int_conv(s
, insn
);
4014 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
4016 /* Note that this is called with all non-FP cases from
4017 * table C3-6 so it must UNDEF for entries not specifically
4018 * allocated to instructions in that table.
4020 unsupported_encoding(s
, insn
);
4023 /* C3.6 Data processing - SIMD and floating point */
4024 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
4026 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
4027 disas_data_proc_fp(s
, insn
);
4029 /* SIMD, including crypto */
4030 disas_data_proc_simd(s
, insn
);
4034 /* C3.1 A64 instruction index by encoding */
4035 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
4039 insn
= arm_ldl_code(env
, s
->pc
, s
->bswap_code
);
4043 switch (extract32(insn
, 25, 4)) {
4044 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
4045 unallocated_encoding(s
);
4047 case 0x8: case 0x9: /* Data processing - immediate */
4048 disas_data_proc_imm(s
, insn
);
4050 case 0xa: case 0xb: /* Branch, exception generation and system insns */
4051 disas_b_exc_sys(s
, insn
);
4056 case 0xe: /* Loads and stores */
4057 disas_ldst(s
, insn
);
4060 case 0xd: /* Data processing - register */
4061 disas_data_proc_reg(s
, insn
);
4064 case 0xf: /* Data processing - SIMD and floating point */
4065 disas_data_proc_simd_fp(s
, insn
);
4068 assert(FALSE
); /* all 15 cases should be handled above */
4072 /* if we allocated any temporaries, free them here */
4076 void gen_intermediate_code_internal_a64(ARMCPU
*cpu
,
4077 TranslationBlock
*tb
,
4080 CPUState
*cs
= CPU(cpu
);
4081 CPUARMState
*env
= &cpu
->env
;
4082 DisasContext dc1
, *dc
= &dc1
;
4084 uint16_t *gen_opc_end
;
4086 target_ulong pc_start
;
4087 target_ulong next_page_start
;
4095 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
4097 dc
->is_jmp
= DISAS_NEXT
;
4099 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
4105 dc
->condexec_mask
= 0;
4106 dc
->condexec_cond
= 0;
4107 #if !defined(CONFIG_USER_ONLY)
4110 dc
->vfp_enabled
= 0;
4113 dc
->cp_regs
= cpu
->cp_regs
;
4114 dc
->current_pl
= arm_current_pl(env
);
4116 init_tmp_a64_array(dc
);
4118 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
4121 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
4122 if (max_insns
== 0) {
4123 max_insns
= CF_COUNT_MASK
;
4128 tcg_clear_temp_count();
4131 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
4132 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
4133 if (bp
->pc
== dc
->pc
) {
4134 gen_exception_insn(dc
, 0, EXCP_DEBUG
);
4135 /* Advance PC so that clearing the breakpoint will
4136 invalidate this TB. */
4138 goto done_generating
;
4144 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
4148 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
4151 tcg_ctx
.gen_opc_pc
[lj
] = dc
->pc
;
4152 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
4153 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
4156 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
4160 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
4161 tcg_gen_debug_insn_start(dc
->pc
);
4164 disas_a64_insn(env
, dc
);
4166 if (tcg_check_temp_count()) {
4167 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
4171 /* Translation stops when a conditional branch is encountered.
4172 * Otherwise the subsequent code could get translated several times.
4173 * Also stop translation when a page boundary is reached. This
4174 * ensures prefetch aborts occur at the right place.
4177 } while (!dc
->is_jmp
&& tcg_ctx
.gen_opc_ptr
< gen_opc_end
&&
4178 !cs
->singlestep_enabled
&&
4180 dc
->pc
< next_page_start
&&
4181 num_insns
< max_insns
);
4183 if (tb
->cflags
& CF_LAST_IO
) {
4187 if (unlikely(cs
->singlestep_enabled
) && dc
->is_jmp
!= DISAS_EXC
) {
4188 /* Note that this means single stepping WFI doesn't halt the CPU.
4189 * For conditional branch insns this is harmless unreachable code as
4190 * gen_goto_tb() has already handled emitting the debug exception
4191 * (and thus a tb-jump is not possible when singlestepping).
4193 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
4194 if (dc
->is_jmp
!= DISAS_JUMP
) {
4195 gen_a64_set_pc_im(dc
->pc
);
4197 gen_exception(EXCP_DEBUG
);
4199 switch (dc
->is_jmp
) {
4201 gen_goto_tb(dc
, 1, dc
->pc
);
4205 gen_a64_set_pc_im(dc
->pc
);
4208 /* indicate that the hash table must be used to find the next TB */
4216 /* This is a special case because we don't want to just halt the CPU
4217 * if trying to debug across a WFI.
4219 gen_helper_wfi(cpu_env
);
4225 gen_tb_end(tb
, num_insns
);
4226 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
4229 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
4230 qemu_log("----------------\n");
4231 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
4232 log_target_disas(env
, pc_start
, dc
->pc
- pc_start
,
4233 dc
->thumb
| (dc
->bswap_code
<< 1));
4238 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
4241 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
4244 tb
->size
= dc
->pc
- pc_start
;
4245 tb
->icount
= num_insns
;