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Only compile sd0303 when one target uses it
[qemu.git] / tcg / ppc / tcg-target.c
blob07e6941fed1e4e04d3ac17daa540b9d609ae651f
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 static uint8_t *tb_ret_addr;
26
27 #ifdef __APPLE__
28 #define LINKAGE_AREA_SIZE 24
29 #define LR_OFFSET 8
30 #elif defined _AIX
31 #define LINKAGE_AREA_SIZE 52
32 #define LR_OFFSET 8
33 #else
34 #define LINKAGE_AREA_SIZE 8
35 #define LR_OFFSET 4
36 #endif
37
38 #define FAST_PATH
39 #if TARGET_PHYS_ADDR_BITS <= 32
40 #define ADDEND_OFFSET 0
41 #else
42 #define ADDEND_OFFSET 4
43 #endif
44
45 #ifndef GUEST_BASE
46 #define GUEST_BASE 0
47 #endif
48
49 #ifdef CONFIG_USE_GUEST_BASE
50 #define TCG_GUEST_BASE_REG 30
51 #else
52 #define TCG_GUEST_BASE_REG 0
53 #endif
54
55 #ifndef NDEBUG
56 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
57 "r0",
58 "r1",
59 "rp",
60 "r3",
61 "r4",
62 "r5",
63 "r6",
64 "r7",
65 "r8",
66 "r9",
67 "r10",
68 "r11",
69 "r12",
70 "r13",
71 "r14",
72 "r15",
73 "r16",
74 "r17",
75 "r18",
76 "r19",
77 "r20",
78 "r21",
79 "r22",
80 "r23",
81 "r24",
82 "r25",
83 "r26",
84 "r27",
85 "r28",
86 "r29",
87 "r30",
88 "r31"
89 };
90 #endif
91
92 static const int tcg_target_reg_alloc_order[] = {
93 TCG_REG_R14,
94 TCG_REG_R15,
95 TCG_REG_R16,
96 TCG_REG_R17,
97 TCG_REG_R18,
98 TCG_REG_R19,
99 TCG_REG_R20,
100 TCG_REG_R21,
101 TCG_REG_R22,
102 TCG_REG_R23,
103 TCG_REG_R28,
104 TCG_REG_R29,
105 TCG_REG_R30,
106 TCG_REG_R31,
107 #ifdef __APPLE__
108 TCG_REG_R2,
109 #endif
110 TCG_REG_R3,
111 TCG_REG_R4,
112 TCG_REG_R5,
113 TCG_REG_R6,
114 TCG_REG_R7,
115 TCG_REG_R8,
116 TCG_REG_R9,
117 TCG_REG_R10,
118 #ifndef __APPLE__
119 TCG_REG_R11,
120 #endif
121 TCG_REG_R12,
122 #ifndef __linux__
123 TCG_REG_R13,
124 #endif
125 TCG_REG_R24,
126 TCG_REG_R25,
127 TCG_REG_R26,
128 TCG_REG_R27
129 };
130
131 static const int tcg_target_call_iarg_regs[] = {
132 TCG_REG_R3,
133 TCG_REG_R4,
134 TCG_REG_R5,
135 TCG_REG_R6,
136 TCG_REG_R7,
137 TCG_REG_R8,
138 TCG_REG_R9,
139 TCG_REG_R10
140 };
141
142 static const int tcg_target_call_oarg_regs[2] = {
143 TCG_REG_R3,
144 TCG_REG_R4
145 };
146
147 static const int tcg_target_callee_save_regs[] = {
148 #ifdef __APPLE__
149 TCG_REG_R11,
150 TCG_REG_R13,
151 #endif
152 #ifdef _AIX
153 TCG_REG_R13,
154 #endif
155 TCG_REG_R14,
156 TCG_REG_R15,
157 TCG_REG_R16,
158 TCG_REG_R17,
159 TCG_REG_R18,
160 TCG_REG_R19,
161 TCG_REG_R20,
162 TCG_REG_R21,
163 TCG_REG_R22,
164 TCG_REG_R23,
165 TCG_REG_R24,
166 TCG_REG_R25,
167 TCG_REG_R26,
168 /* TCG_REG_R27, */ /* currently used for the global env, so no
169 need to save */
170 TCG_REG_R28,
171 TCG_REG_R29,
172 TCG_REG_R30,
173 TCG_REG_R31
174 };
175
176 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
177 {
178 tcg_target_long disp;
179
180 disp = target - (tcg_target_long) pc;
181 if ((disp << 6) >> 6 != disp)
182 tcg_abort ();
183
184 return disp & 0x3fffffc;
185 }
186
187 static void reloc_pc24 (void *pc, tcg_target_long target)
188 {
189 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
190 | reloc_pc24_val (pc, target);
191 }
192
193 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
194 {
195 tcg_target_long disp;
196
197 disp = target - (tcg_target_long) pc;
198 if (disp != (int16_t) disp)
199 tcg_abort ();
200
201 return disp & 0xfffc;
202 }
203
204 static void reloc_pc14 (void *pc, tcg_target_long target)
205 {
206 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
207 | reloc_pc14_val (pc, target);
208 }
209
210 static void patch_reloc(uint8_t *code_ptr, int type,
211 tcg_target_long value, tcg_target_long addend)
212 {
213 value += addend;
214 switch (type) {
215 case R_PPC_REL14:
216 reloc_pc14 (code_ptr, value);
217 break;
218 case R_PPC_REL24:
219 reloc_pc24 (code_ptr, value);
220 break;
221 default:
222 tcg_abort();
223 }
224 }
225
226 /* maximum number of register used for input function arguments */
227 static int tcg_target_get_call_iarg_regs_count(int flags)
228 {
229 return ARRAY_SIZE (tcg_target_call_iarg_regs);
230 }
231
232 /* parse target specific constraints */
233 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
234 {
235 const char *ct_str;
236
237 ct_str = *pct_str;
238 switch (ct_str[0]) {
239 case 'A': case 'B': case 'C': case 'D':
240 ct->ct |= TCG_CT_REG;
241 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
242 break;
243 case 'r':
244 ct->ct |= TCG_CT_REG;
245 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
246 break;
247 #ifdef CONFIG_SOFTMMU
248 case 'L': /* qemu_ld constraint */
249 ct->ct |= TCG_CT_REG;
250 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
251 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
252 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
253 break;
254 case 'K': /* qemu_st[8..32] constraint */
255 ct->ct |= TCG_CT_REG;
256 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
257 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
258 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
259 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
260 #if TARGET_LONG_BITS == 64
261 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
262 #endif
263 break;
264 case 'M': /* qemu_st64 constraint */
265 ct->ct |= TCG_CT_REG;
266 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
267 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
268 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
269 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
270 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
271 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7);
272 break;
273 #else
274 case 'L':
275 case 'K':
276 ct->ct |= TCG_CT_REG;
277 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
278 break;
279 case 'M':
280 ct->ct |= TCG_CT_REG;
281 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
282 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
283 break;
284 #endif
285 default:
286 return -1;
287 }
288 ct_str++;
289 *pct_str = ct_str;
290 return 0;
291 }
292
293 /* test if a constant matches the constraint */
294 static int tcg_target_const_match(tcg_target_long val,
295 const TCGArgConstraint *arg_ct)
296 {
297 int ct;
298
299 ct = arg_ct->ct;
300 if (ct & TCG_CT_CONST)
301 return 1;
302 return 0;
303 }
304
305 #define OPCD(opc) ((opc)<<26)
306 #define XO31(opc) (OPCD(31)|((opc)<<1))
307 #define XO19(opc) (OPCD(19)|((opc)<<1))
308
309 #define B OPCD(18)
310 #define BC OPCD(16)
311 #define LBZ OPCD(34)
312 #define LHZ OPCD(40)
313 #define LHA OPCD(42)
314 #define LWZ OPCD(32)
315 #define STB OPCD(38)
316 #define STH OPCD(44)
317 #define STW OPCD(36)
318
319 #define ADDI OPCD(14)
320 #define ADDIS OPCD(15)
321 #define ORI OPCD(24)
322 #define ORIS OPCD(25)
323 #define XORI OPCD(26)
324 #define XORIS OPCD(27)
325 #define ANDI OPCD(28)
326 #define ANDIS OPCD(29)
327 #define MULLI OPCD( 7)
328 #define CMPLI OPCD(10)
329 #define CMPI OPCD(11)
330
331 #define LWZU OPCD(33)
332 #define STWU OPCD(37)
333
334 #define RLWINM OPCD(21)
335
336 #define BCLR XO19( 16)
337 #define BCCTR XO19(528)
338 #define CRAND XO19(257)
339 #define CRANDC XO19(129)
340 #define CRNAND XO19(225)
341 #define CROR XO19(449)
342
343 #define EXTSB XO31(954)
344 #define EXTSH XO31(922)
345 #define ADD XO31(266)
346 #define ADDE XO31(138)
347 #define ADDC XO31( 10)
348 #define AND XO31( 28)
349 #define SUBF XO31( 40)
350 #define SUBFC XO31( 8)
351 #define SUBFE XO31(136)
352 #define OR XO31(444)
353 #define XOR XO31(316)
354 #define MULLW XO31(235)
355 #define MULHWU XO31( 11)
356 #define DIVW XO31(491)
357 #define DIVWU XO31(459)
358 #define CMP XO31( 0)
359 #define CMPL XO31( 32)
360 #define LHBRX XO31(790)
361 #define LWBRX XO31(534)
362 #define STHBRX XO31(918)
363 #define STWBRX XO31(662)
364 #define MFSPR XO31(339)
365 #define MTSPR XO31(467)
366 #define SRAWI XO31(824)
367 #define NEG XO31(104)
368
369 #define LBZX XO31( 87)
370 #define LHZX XO31(279)
371 #define LHAX XO31(343)
372 #define LWZX XO31( 23)
373 #define STBX XO31(215)
374 #define STHX XO31(407)
375 #define STWX XO31(151)
376
377 #define SPR(a,b) ((((a)<<5)|(b))<<11)
378 #define LR SPR(8, 0)
379 #define CTR SPR(9, 0)
380
381 #define SLW XO31( 24)
382 #define SRW XO31(536)
383 #define SRAW XO31(792)
384
385 #define TW XO31(4)
386 #define TRAP (TW | TO (31))
387
388 #define RT(r) ((r)<<21)
389 #define RS(r) ((r)<<21)
390 #define RA(r) ((r)<<16)
391 #define RB(r) ((r)<<11)
392 #define TO(t) ((t)<<21)
393 #define SH(s) ((s)<<11)
394 #define MB(b) ((b)<<6)
395 #define ME(e) ((e)<<1)
396 #define BO(o) ((o)<<21)
397
398 #define LK 1
399
400 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
401 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
402
403 #define BF(n) ((n)<<23)
404 #define BI(n, c) (((c)+((n)*4))<<16)
405 #define BT(n, c) (((c)+((n)*4))<<21)
406 #define BA(n, c) (((c)+((n)*4))<<16)
407 #define BB(n, c) (((c)+((n)*4))<<11)
408
409 #define BO_COND_TRUE BO (12)
410 #define BO_COND_FALSE BO (4)
411 #define BO_ALWAYS BO (20)
412
413 enum {
414 CR_LT,
415 CR_GT,
416 CR_EQ,
417 CR_SO
418 };
419
420 static const uint32_t tcg_to_bc[10] = {
421 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
422 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
423 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
424 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
425 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
426 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
427 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
428 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
429 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
430 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
431 };
432
433 static void tcg_out_mov(TCGContext *s, int ret, int arg)
434 {
435 tcg_out32 (s, OR | SAB (arg, ret, arg));
436 }
437
438 static void tcg_out_movi(TCGContext *s, TCGType type,
439 int ret, tcg_target_long arg)
440 {
441 if (arg == (int16_t) arg)
442 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
443 else {
444 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
445 if (arg & 0xffff)
446 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
447 }
448 }
449
450 static void tcg_out_ldst (TCGContext *s, int ret, int addr,
451 int offset, int op1, int op2)
452 {
453 if (offset == (int16_t) offset)
454 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
455 else {
456 tcg_out_movi (s, TCG_TYPE_I32, 0, offset);
457 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
458 }
459 }
460
461 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
462 {
463 tcg_target_long disp;
464
465 disp = target - (tcg_target_long) s->code_ptr;
466 if ((disp << 6) >> 6 == disp)
467 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
468 else {
469 tcg_out_movi (s, TCG_TYPE_I32, 0, (tcg_target_long) target);
470 tcg_out32 (s, MTSPR | RS (0) | CTR);
471 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
472 }
473 }
474
475 static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
476 {
477 #ifdef _AIX
478 int reg;
479
480 if (const_arg) {
481 reg = 2;
482 tcg_out_movi (s, TCG_TYPE_I32, reg, arg);
483 }
484 else reg = arg;
485
486 tcg_out32 (s, LWZ | RT (0) | RA (reg));
487 tcg_out32 (s, MTSPR | RA (0) | CTR);
488 tcg_out32 (s, LWZ | RT (2) | RA (reg) | 4);
489 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
490 #else
491 if (const_arg) {
492 tcg_out_b (s, LK, arg);
493 }
494 else {
495 tcg_out32 (s, MTSPR | RS (arg) | LR);
496 tcg_out32 (s, BCLR | BO_ALWAYS | LK);
497 }
498 #endif
499 }
500
501 #if defined(CONFIG_SOFTMMU)
502
503 #include "../../softmmu_defs.h"
504
505 static void *qemu_ld_helpers[4] = {
506 __ldb_mmu,
507 __ldw_mmu,
508 __ldl_mmu,
509 __ldq_mmu,
510 };
511
512 static void *qemu_st_helpers[4] = {
513 __stb_mmu,
514 __stw_mmu,
515 __stl_mmu,
516 __stq_mmu,
517 };
518 #endif
519
520 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
521 {
522 int addr_reg, data_reg, data_reg2, r0, r1, rbase, mem_index, s_bits, bswap;
523 #ifdef CONFIG_SOFTMMU
524 int r2;
525 void *label1_ptr, *label2_ptr;
526 #endif
527 #if TARGET_LONG_BITS == 64
528 int addr_reg2;
529 #endif
530
531 data_reg = *args++;
532 if (opc == 3)
533 data_reg2 = *args++;
534 else
535 data_reg2 = 0;
536 addr_reg = *args++;
537 #if TARGET_LONG_BITS == 64
538 addr_reg2 = *args++;
539 #endif
540 mem_index = *args;
541 s_bits = opc & 3;
542
543 #ifdef CONFIG_SOFTMMU
544 r0 = 3;
545 r1 = 4;
546 r2 = 0;
547 rbase = 0;
548
549 tcg_out32 (s, (RLWINM
550 | RA (r0)
551 | RS (addr_reg)
552 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
553 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
554 | ME (31 - CPU_TLB_ENTRY_BITS)
555 )
556 );
557 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
558 tcg_out32 (s, (LWZU
559 | RT (r1)
560 | RA (r0)
561 | offsetof (CPUState, tlb_table[mem_index][0].addr_read)
562 )
563 );
564 tcg_out32 (s, (RLWINM
565 | RA (r2)
566 | RS (addr_reg)
567 | SH (0)
568 | MB ((32 - s_bits) & 31)
569 | ME (31 - TARGET_PAGE_BITS)
570 )
571 );
572
573 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
574 #if TARGET_LONG_BITS == 64
575 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
576 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
577 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
578 #endif
579
580 label1_ptr = s->code_ptr;
581 #ifdef FAST_PATH
582 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
583 #endif
584
585 /* slow path */
586 #if TARGET_LONG_BITS == 32
587 tcg_out_mov (s, 3, addr_reg);
588 tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index);
589 #else
590 tcg_out_mov (s, 3, addr_reg2);
591 tcg_out_mov (s, 4, addr_reg);
592 tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index);
593 #endif
594
595 tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
596 switch (opc) {
597 case 0|4:
598 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
599 break;
600 case 1|4:
601 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
602 break;
603 case 0:
604 case 1:
605 case 2:
606 if (data_reg != 3)
607 tcg_out_mov (s, data_reg, 3);
608 break;
609 case 3:
610 if (data_reg == 3) {
611 if (data_reg2 == 4) {
612 tcg_out_mov (s, 0, 4);
613 tcg_out_mov (s, 4, 3);
614 tcg_out_mov (s, 3, 0);
615 }
616 else {
617 tcg_out_mov (s, data_reg2, 3);
618 tcg_out_mov (s, 3, 4);
619 }
620 }
621 else {
622 if (data_reg != 4) tcg_out_mov (s, data_reg, 4);
623 if (data_reg2 != 3) tcg_out_mov (s, data_reg2, 3);
624 }
625 break;
626 }
627 label2_ptr = s->code_ptr;
628 tcg_out32 (s, B);
629
630 /* label1: fast path */
631 #ifdef FAST_PATH
632 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
633 #endif
634
635 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
636 tcg_out32 (s, (LWZ
637 | RT (r0)
638 | RA (r0)
639 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
640 - offsetof (CPUTLBEntry, addr_read))
641 ));
642 /* r0 = env->tlb_table[mem_index][index].addend */
643 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
644 /* r0 = env->tlb_table[mem_index][index].addend + addr */
645
646 #else /* !CONFIG_SOFTMMU */
647 r0 = addr_reg;
648 r1 = 3;
649 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
650 #endif
651
652 #ifdef TARGET_WORDS_BIGENDIAN
653 bswap = 0;
654 #else
655 bswap = 1;
656 #endif
657
658 switch (opc) {
659 default:
660 case 0:
661 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
662 break;
663 case 0|4:
664 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
665 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
666 break;
667 case 1:
668 if (bswap)
669 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
670 else
671 tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0));
672 break;
673 case 1|4:
674 if (bswap) {
675 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
676 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
677 }
678 else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
679 break;
680 case 2:
681 if (bswap)
682 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
683 else
684 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0));
685 break;
686 case 3:
687 if (bswap) {
688 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
689 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
690 tcg_out32 (s, LWBRX | TAB (data_reg2, rbase, r1));
691 }
692 else {
693 #ifdef CONFIG_USE_GUEST_BASE
694 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
695 tcg_out32 (s, LWZX | TAB (data_reg2, rbase, r0));
696 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r1));
697 #else
698 if (r0 == data_reg2) {
699 tcg_out32 (s, LWZ | RT (0) | RA (r0));
700 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
701 tcg_out_mov (s, data_reg2, 0);
702 }
703 else {
704 tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
705 tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
706 }
707 #endif
708 }
709 break;
710 }
711
712 #ifdef CONFIG_SOFTMMU
713 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
714 #endif
715 }
716
717 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
718 {
719 int addr_reg, r0, r1, data_reg, data_reg2, mem_index, bswap, rbase;
720 #ifdef CONFIG_SOFTMMU
721 int r2, ir;
722 void *label1_ptr, *label2_ptr;
723 #endif
724 #if TARGET_LONG_BITS == 64
725 int addr_reg2;
726 #endif
727
728 data_reg = *args++;
729 if (opc == 3)
730 data_reg2 = *args++;
731 else
732 data_reg2 = 0;
733 addr_reg = *args++;
734 #if TARGET_LONG_BITS == 64
735 addr_reg2 = *args++;
736 #endif
737 mem_index = *args;
738
739 #ifdef CONFIG_SOFTMMU
740 r0 = 3;
741 r1 = 4;
742 r2 = 0;
743 rbase = 0;
744
745 tcg_out32 (s, (RLWINM
746 | RA (r0)
747 | RS (addr_reg)
748 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
749 | MB (32 - (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS))
750 | ME (31 - CPU_TLB_ENTRY_BITS)
751 )
752 );
753 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
754 tcg_out32 (s, (LWZU
755 | RT (r1)
756 | RA (r0)
757 | offsetof (CPUState, tlb_table[mem_index][0].addr_write)
758 )
759 );
760 tcg_out32 (s, (RLWINM
761 | RA (r2)
762 | RS (addr_reg)
763 | SH (0)
764 | MB ((32 - opc) & 31)
765 | ME (31 - TARGET_PAGE_BITS)
766 )
767 );
768
769 tcg_out32 (s, CMP | (7 << 23) | RA (r2) | RB (r1));
770 #if TARGET_LONG_BITS == 64
771 tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
772 tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
773 tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
774 #endif
775
776 label1_ptr = s->code_ptr;
777 #ifdef FAST_PATH
778 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
779 #endif
780
781 /* slow path */
782 #if TARGET_LONG_BITS == 32
783 tcg_out_mov (s, 3, addr_reg);
784 ir = 4;
785 #else
786 tcg_out_mov (s, 3, addr_reg2);
787 tcg_out_mov (s, 4, addr_reg);
788 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
789 ir = 5;
790 #else
791 ir = 4;
792 #endif
793 #endif
794
795 switch (opc) {
796 case 0:
797 tcg_out32 (s, (RLWINM
798 | RA (ir)
799 | RS (data_reg)
800 | SH (0)
801 | MB (24)
802 | ME (31)));
803 break;
804 case 1:
805 tcg_out32 (s, (RLWINM
806 | RA (ir)
807 | RS (data_reg)
808 | SH (0)
809 | MB (16)
810 | ME (31)));
811 break;
812 case 2:
813 tcg_out_mov (s, ir, data_reg);
814 break;
815 case 3:
816 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
817 ir = 5;
818 #endif
819 tcg_out_mov (s, ir++, data_reg2);
820 tcg_out_mov (s, ir, data_reg);
821 break;
822 }
823 ir++;
824
825 tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
826 tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
827 label2_ptr = s->code_ptr;
828 tcg_out32 (s, B);
829
830 /* label1: fast path */
831 #ifdef FAST_PATH
832 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
833 #endif
834
835 tcg_out32 (s, (LWZ
836 | RT (r0)
837 | RA (r0)
838 | (ADDEND_OFFSET + offsetof (CPUTLBEntry, addend)
839 - offsetof (CPUTLBEntry, addr_write))
840 ));
841 /* r0 = env->tlb_table[mem_index][index].addend */
842 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
843 /* r0 = env->tlb_table[mem_index][index].addend + addr */
844
845 #else /* !CONFIG_SOFTMMU */
846 r0 = addr_reg;
847 r1 = 3;
848 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
849 #endif
850
851 #ifdef TARGET_WORDS_BIGENDIAN
852 bswap = 0;
853 #else
854 bswap = 1;
855 #endif
856 switch (opc) {
857 case 0:
858 tcg_out32 (s, STBX | SAB (data_reg, rbase, r0));
859 break;
860 case 1:
861 if (bswap)
862 tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0));
863 else
864 tcg_out32 (s, STHX | SAB (data_reg, rbase, r0));
865 break;
866 case 2:
867 if (bswap)
868 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
869 else
870 tcg_out32 (s, STWX | SAB (data_reg, rbase, r0));
871 break;
872 case 3:
873 if (bswap) {
874 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
875 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
876 tcg_out32 (s, STWBRX | SAB (data_reg2, rbase, r1));
877 }
878 else {
879 #ifdef CONFIG_USE_GUEST_BASE
880 tcg_out32 (s, STWX | SAB (data_reg2, rbase, r0));
881 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
882 tcg_out32 (s, STWX | SAB (data_reg, rbase, r1));
883 #else
884 tcg_out32 (s, STW | RS (data_reg2) | RA (r0));
885 tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
886 #endif
887 }
888 break;
889 }
890
891 #ifdef CONFIG_SOFTMMU
892 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
893 #endif
894 }
895
896 void tcg_target_qemu_prologue (TCGContext *s)
897 {
898 int i, frame_size;
899
900 frame_size = 0
901 + LINKAGE_AREA_SIZE
902 + TCG_STATIC_CALL_ARGS_SIZE
903 + ARRAY_SIZE (tcg_target_callee_save_regs) * 4
904 ;
905 frame_size = (frame_size + 15) & ~15;
906
907 #ifdef _AIX
908 {
909 uint32_t addr;
910
911 /* First emit adhoc function descriptor */
912 addr = (uint32_t) s->code_ptr + 12;
913 tcg_out32 (s, addr); /* entry point */
914 s->code_ptr += 8; /* skip TOC and environment pointer */
915 }
916 #endif
917 tcg_out32 (s, MFSPR | RT (0) | LR);
918 tcg_out32 (s, STWU | RS (1) | RA (1) | (-frame_size & 0xffff));
919 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
920 tcg_out32 (s, (STW
921 | RS (tcg_target_callee_save_regs[i])
922 | RA (1)
923 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
924 )
925 );
926 tcg_out32 (s, STW | RS (0) | RA (1) | (frame_size + LR_OFFSET));
927
928 #ifdef CONFIG_USE_GUEST_BASE
929 tcg_out_movi (s, TCG_TYPE_I32, TCG_GUEST_BASE_REG, GUEST_BASE);
930 #endif
931
932 tcg_out32 (s, MTSPR | RS (3) | CTR);
933 tcg_out32 (s, BCCTR | BO_ALWAYS);
934 tb_ret_addr = s->code_ptr;
935
936 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
937 tcg_out32 (s, (LWZ
938 | RT (tcg_target_callee_save_regs[i])
939 | RA (1)
940 | (i * 4 + LINKAGE_AREA_SIZE + TCG_STATIC_CALL_ARGS_SIZE)
941 )
942 );
943 tcg_out32 (s, LWZ | RT (0) | RA (1) | (frame_size + LR_OFFSET));
944 tcg_out32 (s, MTSPR | RS (0) | LR);
945 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
946 tcg_out32 (s, BCLR | BO_ALWAYS);
947 }
948
949 static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
950 tcg_target_long arg2)
951 {
952 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
953 }
954
955 static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
956 tcg_target_long arg2)
957 {
958 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
959 }
960
961 static void ppc_addi (TCGContext *s, int rt, int ra, tcg_target_long si)
962 {
963 if (!si && rt == ra)
964 return;
965
966 if (si == (int16_t) si)
967 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
968 else {
969 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
970 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
971 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
972 }
973 }
974
975 static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
976 {
977 ppc_addi (s, reg, reg, val);
978 }
979
980 static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
981 int const_arg2, int cr)
982 {
983 int imm;
984 uint32_t op;
985
986 switch (cond) {
987 case TCG_COND_EQ:
988 case TCG_COND_NE:
989 if (const_arg2) {
990 if ((int16_t) arg2 == arg2) {
991 op = CMPI;
992 imm = 1;
993 break;
994 }
995 else if ((uint16_t) arg2 == arg2) {
996 op = CMPLI;
997 imm = 1;
998 break;
999 }
1000 }
1001 op = CMPL;
1002 imm = 0;
1003 break;
1004
1005 case TCG_COND_LT:
1006 case TCG_COND_GE:
1007 case TCG_COND_LE:
1008 case TCG_COND_GT:
1009 if (const_arg2) {
1010 if ((int16_t) arg2 == arg2) {
1011 op = CMPI;
1012 imm = 1;
1013 break;
1014 }
1015 }
1016 op = CMP;
1017 imm = 0;
1018 break;
1019
1020 case TCG_COND_LTU:
1021 case TCG_COND_GEU:
1022 case TCG_COND_LEU:
1023 case TCG_COND_GTU:
1024 if (const_arg2) {
1025 if ((uint16_t) arg2 == arg2) {
1026 op = CMPLI;
1027 imm = 1;
1028 break;
1029 }
1030 }
1031 op = CMPL;
1032 imm = 0;
1033 break;
1034
1035 default:
1036 tcg_abort ();
1037 }
1038 op |= BF (cr);
1039
1040 if (imm)
1041 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
1042 else {
1043 if (const_arg2) {
1044 tcg_out_movi (s, TCG_TYPE_I32, 0, arg2);
1045 tcg_out32 (s, op | RA (arg1) | RB (0));
1046 }
1047 else
1048 tcg_out32 (s, op | RA (arg1) | RB (arg2));
1049 }
1050
1051 }
1052
1053 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
1054 {
1055 TCGLabel *l = &s->labels[label_index];
1056
1057 if (l->has_value)
1058 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
1059 else {
1060 uint16_t val = *(uint16_t *) &s->code_ptr[2];
1061
1062 /* Thanks to Andrzej Zaborowski */
1063 tcg_out32 (s, bc | (val & 0xfffc));
1064 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
1065 }
1066 }
1067
1068 static void tcg_out_brcond (TCGContext *s, int cond,
1069 TCGArg arg1, TCGArg arg2, int const_arg2,
1070 int label_index)
1071 {
1072 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7);
1073 tcg_out_bc (s, tcg_to_bc[cond], label_index);
1074 }
1075
1076 /* XXX: we implement it at the target level to avoid having to
1077 handle cross basic blocks temporaries */
1078 static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1079 const int *const_args)
1080 {
1081 int cond = args[4], label_index = args[5], op;
1082 struct { int bit1; int bit2; int cond2; } bits[] = {
1083 [TCG_COND_LT ] = { CR_LT, CR_LT, TCG_COND_LT },
1084 [TCG_COND_LE ] = { CR_LT, CR_GT, TCG_COND_LT },
1085 [TCG_COND_GT ] = { CR_GT, CR_GT, TCG_COND_GT },
1086 [TCG_COND_GE ] = { CR_GT, CR_LT, TCG_COND_GT },
1087 [TCG_COND_LTU] = { CR_LT, CR_LT, TCG_COND_LTU },
1088 [TCG_COND_LEU] = { CR_LT, CR_GT, TCG_COND_LTU },
1089 [TCG_COND_GTU] = { CR_GT, CR_GT, TCG_COND_GTU },
1090 [TCG_COND_GEU] = { CR_GT, CR_LT, TCG_COND_GTU },
1091 }, *b = &bits[cond];
1092
1093 switch (cond) {
1094 case TCG_COND_EQ:
1095 case TCG_COND_NE:
1096 op = (cond == TCG_COND_EQ) ? CRAND : CRNAND;
1097 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 6);
1098 tcg_out_cmp (s, cond, args[1], args[3], const_args[3], 7);
1099 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
1100 break;
1101 case TCG_COND_LT:
1102 case TCG_COND_LE:
1103 case TCG_COND_GT:
1104 case TCG_COND_GE:
1105 case TCG_COND_LTU:
1106 case TCG_COND_LEU:
1107 case TCG_COND_GTU:
1108 case TCG_COND_GEU:
1109 op = (b->bit1 != b->bit2) ? CRANDC : CRAND;
1110 tcg_out_cmp (s, b->cond2, args[1], args[3], const_args[3], 5);
1111 tcg_out_cmp (s, TCG_COND_EQ, args[1], args[3], const_args[3], 6);
1112 tcg_out_cmp (s, cond, args[0], args[2], const_args[2], 7);
1113 tcg_out32 (s, op | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, b->bit2));
1114 tcg_out32 (s, CROR | BT (7, CR_EQ) | BA (5, b->bit1) | BB (7, CR_EQ));
1115 break;
1116 default:
1117 tcg_abort();
1118 }
1119
1120 tcg_out_bc (s, (BC | BI (7, CR_EQ) | BO_COND_TRUE), label_index);
1121 }
1122
1123 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1124 {
1125 uint32_t *ptr;
1126 long disp = addr - jmp_addr;
1127 unsigned long patch_size;
1128
1129 ptr = (uint32_t *)jmp_addr;
1130
1131 if ((disp << 6) >> 6 != disp) {
1132 ptr[0] = 0x3c000000 | (addr >> 16); /* lis 0,addr@ha */
1133 ptr[1] = 0x60000000 | (addr & 0xffff); /* la 0,addr@l(0) */
1134 ptr[2] = 0x7c0903a6; /* mtctr 0 */
1135 ptr[3] = 0x4e800420; /* brctr */
1136 patch_size = 16;
1137 } else {
1138 /* patch the branch destination */
1139 if (disp != 16) {
1140 *ptr = 0x48000000 | (disp & 0x03fffffc); /* b disp */
1141 patch_size = 4;
1142 } else {
1143 ptr[0] = 0x60000000; /* nop */
1144 ptr[1] = 0x60000000;
1145 ptr[2] = 0x60000000;
1146 ptr[3] = 0x60000000;
1147 patch_size = 16;
1148 }
1149 }
1150 /* flush icache */
1151 flush_icache_range(jmp_addr, jmp_addr + patch_size);
1152 }
1153
1154 static void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
1155 const int *const_args)
1156 {
1157 switch (opc) {
1158 case INDEX_op_exit_tb:
1159 tcg_out_movi (s, TCG_TYPE_I32, TCG_REG_R3, args[0]);
1160 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1161 break;
1162 case INDEX_op_goto_tb:
1163 if (s->tb_jmp_offset) {
1164 /* direct jump method */
1165
1166 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1167 s->code_ptr += 16;
1168 }
1169 else {
1170 tcg_abort ();
1171 }
1172 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1173 break;
1174 case INDEX_op_br:
1175 {
1176 TCGLabel *l = &s->labels[args[0]];
1177
1178 if (l->has_value) {
1179 tcg_out_b (s, 0, l->u.value);
1180 }
1181 else {
1182 uint32_t val = *(uint32_t *) s->code_ptr;
1183
1184 /* Thanks to Andrzej Zaborowski */
1185 tcg_out32 (s, B | (val & 0x3fffffc));
1186 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1187 }
1188 }
1189 break;
1190 case INDEX_op_call:
1191 tcg_out_call (s, args[0], const_args[0]);
1192 break;
1193 case INDEX_op_jmp:
1194 if (const_args[0]) {
1195 tcg_out_b (s, 0, args[0]);
1196 }
1197 else {
1198 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1199 tcg_out32 (s, BCCTR | BO_ALWAYS);
1200 }
1201 break;
1202 case INDEX_op_movi_i32:
1203 tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1204 break;
1205 case INDEX_op_ld8u_i32:
1206 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1207 break;
1208 case INDEX_op_ld8s_i32:
1209 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1210 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1211 break;
1212 case INDEX_op_ld16u_i32:
1213 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1214 break;
1215 case INDEX_op_ld16s_i32:
1216 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1217 break;
1218 case INDEX_op_ld_i32:
1219 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1220 break;
1221 case INDEX_op_st8_i32:
1222 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1223 break;
1224 case INDEX_op_st16_i32:
1225 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1226 break;
1227 case INDEX_op_st_i32:
1228 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1229 break;
1230
1231 case INDEX_op_add_i32:
1232 if (const_args[2])
1233 ppc_addi (s, args[0], args[1], args[2]);
1234 else
1235 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1236 break;
1237 case INDEX_op_sub_i32:
1238 if (const_args[2])
1239 ppc_addi (s, args[0], args[1], -args[2]);
1240 else
1241 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1242 break;
1243
1244 case INDEX_op_and_i32:
1245 if (const_args[2]) {
1246 uint32_t c;
1247
1248 c = args[2];
1249
1250 if (!c) {
1251 tcg_out_movi (s, TCG_TYPE_I32, args[0], 0);
1252 break;
1253 }
1254 #ifdef __PPU__
1255 uint32_t t, n;
1256 int mb, me;
1257
1258 n = c ^ -(c & 1);
1259 t = n + (n & -n);
1260
1261 if ((t & (t - 1)) == 0) {
1262 int lzc, tzc;
1263
1264 if ((c & 0x80000001) == 0x80000001) {
1265 lzc = clz32 (n);
1266 tzc = ctz32 (n);
1267
1268 mb = 32 - tzc;
1269 me = lzc - 1;
1270 }
1271 else {
1272 lzc = clz32 (c);
1273 tzc = ctz32 (c);
1274
1275 mb = lzc;
1276 me = 31 - tzc;
1277 }
1278
1279 tcg_out32 (s, (RLWINM
1280 | RA (args[0])
1281 | RS (args[1])
1282 | SH (0)
1283 | MB (mb)
1284 | ME (me)
1285 )
1286 );
1287 }
1288 else
1289 #endif /* !__PPU__ */
1290 {
1291 if ((c & 0xffff) == c)
1292 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | c);
1293 else if ((c & 0xffff0000) == c)
1294 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1295 | ((c >> 16) & 0xffff));
1296 else {
1297 tcg_out_movi (s, TCG_TYPE_I32, 0, c);
1298 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1299 }
1300 }
1301 }
1302 else
1303 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1304 break;
1305 case INDEX_op_or_i32:
1306 if (const_args[2]) {
1307 if (args[2] & 0xffff) {
1308 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1309 | (args[2] & 0xffff));
1310 if (args[2] >> 16)
1311 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1312 | ((args[2] >> 16) & 0xffff));
1313 }
1314 else {
1315 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1316 | ((args[2] >> 16) & 0xffff));
1317 }
1318 }
1319 else
1320 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1321 break;
1322 case INDEX_op_xor_i32:
1323 if (const_args[2]) {
1324 if ((args[2] & 0xffff) == args[2])
1325 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1326 | (args[2] & 0xffff));
1327 else if ((args[2] & 0xffff0000) == args[2])
1328 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1329 | ((args[2] >> 16) & 0xffff));
1330 else {
1331 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1332 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1333 }
1334 }
1335 else
1336 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1337 break;
1338
1339 case INDEX_op_mul_i32:
1340 if (const_args[2]) {
1341 if (args[2] == (int16_t) args[2])
1342 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1343 | (args[2] & 0xffff));
1344 else {
1345 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1346 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1347 }
1348 }
1349 else
1350 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1351 break;
1352
1353 case INDEX_op_div_i32:
1354 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1355 break;
1356
1357 case INDEX_op_divu_i32:
1358 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1359 break;
1360
1361 case INDEX_op_rem_i32:
1362 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1363 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1364 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1365 break;
1366
1367 case INDEX_op_remu_i32:
1368 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1369 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1370 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1371 break;
1372
1373 case INDEX_op_mulu2_i32:
1374 if (args[0] == args[2] || args[0] == args[3]) {
1375 tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
1376 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1377 tcg_out_mov (s, args[0], 0);
1378 }
1379 else {
1380 tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3]));
1381 tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
1382 }
1383 break;
1384
1385 case INDEX_op_shl_i32:
1386 if (const_args[2]) {
1387 tcg_out32 (s, (RLWINM
1388 | RA (args[0])
1389 | RS (args[1])
1390 | SH (args[2])
1391 | MB (0)
1392 | ME (31 - args[2])
1393 )
1394 );
1395 }
1396 else
1397 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1398 break;
1399 case INDEX_op_shr_i32:
1400 if (const_args[2]) {
1401 tcg_out32 (s, (RLWINM
1402 | RA (args[0])
1403 | RS (args[1])
1404 | SH (32 - args[2])
1405 | MB (args[2])
1406 | ME (31)
1407 )
1408 );
1409 }
1410 else
1411 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1412 break;
1413 case INDEX_op_sar_i32:
1414 if (const_args[2])
1415 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1416 else
1417 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1418 break;
1419
1420 case INDEX_op_add2_i32:
1421 if (args[0] == args[3] || args[0] == args[5]) {
1422 tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
1423 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1424 tcg_out_mov (s, args[0], 0);
1425 }
1426 else {
1427 tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
1428 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
1429 }
1430 break;
1431 case INDEX_op_sub2_i32:
1432 if (args[0] == args[3] || args[0] == args[5]) {
1433 tcg_out32 (s, SUBFC | TAB (0, args[4], args[2]));
1434 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1435 tcg_out_mov (s, args[0], 0);
1436 }
1437 else {
1438 tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2]));
1439 tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
1440 }
1441 break;
1442
1443 case INDEX_op_brcond_i32:
1444 /*
1445 args[0] = r0
1446 args[1] = r1
1447 args[2] = cond
1448 args[3] = r1 is const
1449 args[4] = label_index
1450 */
1451 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3]);
1452 break;
1453 case INDEX_op_brcond2_i32:
1454 tcg_out_brcond2(s, args, const_args);
1455 break;
1456
1457 case INDEX_op_neg_i32:
1458 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1459 break;
1460
1461 case INDEX_op_qemu_ld8u:
1462 tcg_out_qemu_ld(s, args, 0);
1463 break;
1464 case INDEX_op_qemu_ld8s:
1465 tcg_out_qemu_ld(s, args, 0 | 4);
1466 break;
1467 case INDEX_op_qemu_ld16u:
1468 tcg_out_qemu_ld(s, args, 1);
1469 break;
1470 case INDEX_op_qemu_ld16s:
1471 tcg_out_qemu_ld(s, args, 1 | 4);
1472 break;
1473 case INDEX_op_qemu_ld32u:
1474 tcg_out_qemu_ld(s, args, 2);
1475 break;
1476 case INDEX_op_qemu_ld64:
1477 tcg_out_qemu_ld(s, args, 3);
1478 break;
1479 case INDEX_op_qemu_st8:
1480 tcg_out_qemu_st(s, args, 0);
1481 break;
1482 case INDEX_op_qemu_st16:
1483 tcg_out_qemu_st(s, args, 1);
1484 break;
1485 case INDEX_op_qemu_st32:
1486 tcg_out_qemu_st(s, args, 2);
1487 break;
1488 case INDEX_op_qemu_st64:
1489 tcg_out_qemu_st(s, args, 3);
1490 break;
1491
1492 case INDEX_op_ext8s_i32:
1493 tcg_out32 (s, EXTSB | RS (args[1]) | RA (args[0]));
1494 break;
1495 case INDEX_op_ext16s_i32:
1496 tcg_out32 (s, EXTSH | RS (args[1]) | RA (args[0]));
1497 break;
1498
1499 default:
1500 tcg_dump_ops (s, stderr);
1501 tcg_abort ();
1502 }
1503 }
1504
1505 static const TCGTargetOpDef ppc_op_defs[] = {
1506 { INDEX_op_exit_tb, { } },
1507 { INDEX_op_goto_tb, { } },
1508 { INDEX_op_call, { "ri" } },
1509 { INDEX_op_jmp, { "ri" } },
1510 { INDEX_op_br, { } },
1511
1512 { INDEX_op_mov_i32, { "r", "r" } },
1513 { INDEX_op_movi_i32, { "r" } },
1514 { INDEX_op_ld8u_i32, { "r", "r" } },
1515 { INDEX_op_ld8s_i32, { "r", "r" } },
1516 { INDEX_op_ld16u_i32, { "r", "r" } },
1517 { INDEX_op_ld16s_i32, { "r", "r" } },
1518 { INDEX_op_ld_i32, { "r", "r" } },
1519 { INDEX_op_st8_i32, { "r", "r" } },
1520 { INDEX_op_st16_i32, { "r", "r" } },
1521 { INDEX_op_st_i32, { "r", "r" } },
1522
1523 { INDEX_op_add_i32, { "r", "r", "ri" } },
1524 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1525 { INDEX_op_div_i32, { "r", "r", "r" } },
1526 { INDEX_op_divu_i32, { "r", "r", "r" } },
1527 { INDEX_op_rem_i32, { "r", "r", "r" } },
1528 { INDEX_op_remu_i32, { "r", "r", "r" } },
1529 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1530 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1531 { INDEX_op_and_i32, { "r", "r", "ri" } },
1532 { INDEX_op_or_i32, { "r", "r", "ri" } },
1533 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1534
1535 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1536 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1537 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1538
1539 { INDEX_op_brcond_i32, { "r", "ri" } },
1540
1541 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1542 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1543 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1544
1545 { INDEX_op_neg_i32, { "r", "r" } },
1546
1547 #if TARGET_LONG_BITS == 32
1548 { INDEX_op_qemu_ld8u, { "r", "L" } },
1549 { INDEX_op_qemu_ld8s, { "r", "L" } },
1550 { INDEX_op_qemu_ld16u, { "r", "L" } },
1551 { INDEX_op_qemu_ld16s, { "r", "L" } },
1552 { INDEX_op_qemu_ld32u, { "r", "L" } },
1553 { INDEX_op_qemu_ld32s, { "r", "L" } },
1554 { INDEX_op_qemu_ld64, { "r", "r", "L" } },
1555
1556 { INDEX_op_qemu_st8, { "K", "K" } },
1557 { INDEX_op_qemu_st16, { "K", "K" } },
1558 { INDEX_op_qemu_st32, { "K", "K" } },
1559 { INDEX_op_qemu_st64, { "M", "M", "M" } },
1560 #else
1561 { INDEX_op_qemu_ld8u, { "r", "L", "L" } },
1562 { INDEX_op_qemu_ld8s, { "r", "L", "L" } },
1563 { INDEX_op_qemu_ld16u, { "r", "L", "L" } },
1564 { INDEX_op_qemu_ld16s, { "r", "L", "L" } },
1565 { INDEX_op_qemu_ld32u, { "r", "L", "L" } },
1566 { INDEX_op_qemu_ld32s, { "r", "L", "L" } },
1567 { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
1568
1569 { INDEX_op_qemu_st8, { "K", "K", "K" } },
1570 { INDEX_op_qemu_st16, { "K", "K", "K" } },
1571 { INDEX_op_qemu_st32, { "K", "K", "K" } },
1572 { INDEX_op_qemu_st64, { "M", "M", "M", "M" } },
1573 #endif
1574
1575 { INDEX_op_ext8s_i32, { "r", "r" } },
1576 { INDEX_op_ext16s_i32, { "r", "r" } },
1577
1578 { -1 },
1579 };
1580
1581 void tcg_target_init(TCGContext *s)
1582 {
1583 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1584 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1585 (1 << TCG_REG_R0) |
1586 #ifdef __APPLE__
1587 (1 << TCG_REG_R2) |
1588 #endif
1589 (1 << TCG_REG_R3) |
1590 (1 << TCG_REG_R4) |
1591 (1 << TCG_REG_R5) |
1592 (1 << TCG_REG_R6) |
1593 (1 << TCG_REG_R7) |
1594 (1 << TCG_REG_R8) |
1595 (1 << TCG_REG_R9) |
1596 (1 << TCG_REG_R10) |
1597 (1 << TCG_REG_R11) |
1598 (1 << TCG_REG_R12)
1599 );
1600
1601 tcg_regset_clear(s->reserved_regs);
1602 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);
1603 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);
1604 #ifndef __APPLE__
1605 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);
1606 #endif
1607 #ifdef __linux__
1608 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13);
1609 #endif
1610 #ifdef CONFIG_USE_GUEST_BASE
1611 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1612 #endif
1613
1614 tcg_add_target_add_op_defs(ppc_op_defs);
1615 }
QEmu