4 /* CPU interfaces that are target indpendent. */
6 #if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) || defined(__ia64__)
10 #ifdef TARGET_PHYS_ADDR_BITS
19 #include "qemu-queue.h"
21 #if !defined(CONFIG_USER_ONLY)
29 /* address in the RAM (different from a physical address) */
30 typedef unsigned long ram_addr_t
;
34 typedef void CPUWriteMemoryFunc(void *opaque
, target_phys_addr_t addr
, uint32_t value
);
35 typedef uint32_t CPUReadMemoryFunc(void *opaque
, target_phys_addr_t addr
);
37 void cpu_register_physical_memory_log(target_phys_addr_t start_addr
,
39 ram_addr_t phys_offset
,
40 ram_addr_t region_offset
,
43 static inline void cpu_register_physical_memory_offset(target_phys_addr_t start_addr
,
45 ram_addr_t phys_offset
,
46 ram_addr_t region_offset
)
48 cpu_register_physical_memory_log(start_addr
, size
, phys_offset
,
49 region_offset
, false);
52 static inline void cpu_register_physical_memory(target_phys_addr_t start_addr
,
54 ram_addr_t phys_offset
)
56 cpu_register_physical_memory_offset(start_addr
, size
, phys_offset
, 0);
59 ram_addr_t
cpu_get_physical_page_desc(target_phys_addr_t addr
);
60 ram_addr_t
qemu_ram_alloc_from_ptr(DeviceState
*dev
, const char *name
,
61 ram_addr_t size
, void *host
);
62 ram_addr_t
qemu_ram_alloc(DeviceState
*dev
, const char *name
, ram_addr_t size
);
63 void qemu_ram_free(ram_addr_t addr
);
64 void qemu_ram_free_from_ptr(ram_addr_t addr
);
65 void qemu_ram_remap(ram_addr_t addr
, ram_addr_t length
);
66 /* This should only be used for ram local to a device. */
67 void *qemu_get_ram_ptr(ram_addr_t addr
);
68 void *qemu_ram_ptr_length(target_phys_addr_t addr
, target_phys_addr_t
*size
);
69 /* Same but slower, to use for migration, where the order of
70 * RAMBlocks must not change. */
71 void *qemu_safe_ram_ptr(ram_addr_t addr
);
72 void qemu_put_ram_ptr(void *addr
);
73 /* This should not be used by devices. */
74 int qemu_ram_addr_from_host(void *ptr
, ram_addr_t
*ram_addr
);
75 ram_addr_t
qemu_ram_addr_from_host_nofail(void *ptr
);
77 int cpu_register_io_memory(CPUReadMemoryFunc
* const *mem_read
,
78 CPUWriteMemoryFunc
* const *mem_write
,
79 void *opaque
, enum device_endian endian
);
80 void cpu_unregister_io_memory(int table_address
);
82 void cpu_physical_memory_rw(target_phys_addr_t addr
, uint8_t *buf
,
83 int len
, int is_write
);
84 static inline void cpu_physical_memory_read(target_phys_addr_t addr
,
87 cpu_physical_memory_rw(addr
, buf
, len
, 0);
89 static inline void cpu_physical_memory_write(target_phys_addr_t addr
,
90 const void *buf
, int len
)
92 cpu_physical_memory_rw(addr
, (void *)buf
, len
, 1);
94 void *cpu_physical_memory_map(target_phys_addr_t addr
,
95 target_phys_addr_t
*plen
,
97 void cpu_physical_memory_unmap(void *buffer
, target_phys_addr_t len
,
98 int is_write
, target_phys_addr_t access_len
);
99 void *cpu_register_map_client(void *opaque
, void (*callback
)(void *opaque
));
100 void cpu_unregister_map_client(void *cookie
);
102 struct CPUPhysMemoryClient
;
103 typedef struct CPUPhysMemoryClient CPUPhysMemoryClient
;
104 struct CPUPhysMemoryClient
{
105 void (*set_memory
)(struct CPUPhysMemoryClient
*client
,
106 target_phys_addr_t start_addr
,
108 ram_addr_t phys_offset
,
110 int (*sync_dirty_bitmap
)(struct CPUPhysMemoryClient
*client
,
111 target_phys_addr_t start_addr
,
112 target_phys_addr_t end_addr
);
113 int (*migration_log
)(struct CPUPhysMemoryClient
*client
,
115 int (*log_start
)(struct CPUPhysMemoryClient
*client
,
116 target_phys_addr_t phys_addr
, ram_addr_t size
);
117 int (*log_stop
)(struct CPUPhysMemoryClient
*client
,
118 target_phys_addr_t phys_addr
, ram_addr_t size
);
119 QLIST_ENTRY(CPUPhysMemoryClient
) list
;
122 void cpu_register_phys_memory_client(CPUPhysMemoryClient
*);
123 void cpu_unregister_phys_memory_client(CPUPhysMemoryClient
*);
125 /* Coalesced MMIO regions are areas where write operations can be reordered.
126 * This usually implies that write operations are side-effect free. This allows
127 * batching which can make a major impact on performance when using
130 void qemu_register_coalesced_mmio(target_phys_addr_t addr
, ram_addr_t size
);
132 void qemu_unregister_coalesced_mmio(target_phys_addr_t addr
, ram_addr_t size
);
134 void qemu_flush_coalesced_mmio_buffer(void);
136 uint32_t ldub_phys(target_phys_addr_t addr
);
137 uint32_t lduw_phys(target_phys_addr_t addr
);
138 uint32_t ldl_phys(target_phys_addr_t addr
);
139 uint64_t ldq_phys(target_phys_addr_t addr
);
140 void stl_phys_notdirty(target_phys_addr_t addr
, uint32_t val
);
141 void stq_phys_notdirty(target_phys_addr_t addr
, uint64_t val
);
142 void stb_phys(target_phys_addr_t addr
, uint32_t val
);
143 void stw_phys(target_phys_addr_t addr
, uint32_t val
);
144 void stl_phys(target_phys_addr_t addr
, uint32_t val
);
145 void stq_phys(target_phys_addr_t addr
, uint64_t val
);
147 void cpu_physical_memory_write_rom(target_phys_addr_t addr
,
148 const uint8_t *buf
, int len
);
150 #define IO_MEM_SHIFT 3
152 #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
153 #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
154 #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
155 #define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT)
157 /* Acts like a ROM when read and like a device when written. */
158 #define IO_MEM_ROMD (1)
159 #define IO_MEM_SUBPAGE (2)
163 #endif /* !CPU_COMMON_H */