target-i386/arch_memory_mapping.c

   1 /*
   2  * i386 memory mapping
   3  *
   4  * Copyright Fujitsu, Corp. 2011, 2012
   5  *
   6  * Authors:
   7  *     Wen Congyang <wency@cn.fujitsu.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10  * See the COPYING file in the top-level directory.
  11  *
  12  */
  13
  14 #include "cpu.h"
  15 #include "exec/cpu-all.h"
  16 #include "sysemu/memory_mapping.h"
  17
  18 /* PAE Paging or IA-32e Paging */
  19 static void walk_pte(MemoryMappingList *list, hwaddr pte_start_addr,
  20                      int32_t a20_mask, target_ulong start_line_addr)
  21 {
  22     hwaddr pte_addr, start_paddr;
  23     uint64_t pte;
  24     target_ulong start_vaddr;
  25     int i;
  26
  27     for (i = 0; i < 512; i++) {
  28         pte_addr = (pte_start_addr + i * 8) & a20_mask;
  29         pte = ldq_phys(pte_addr);
  30         if (!(pte & PG_PRESENT_MASK)) {
  31             /* not present */
  32             continue;
  33         }
  34
  35         start_paddr = (pte & ~0xfff) & ~(0x1ULL << 63);
  36         if (cpu_physical_memory_is_io(start_paddr)) {
  37             /* I/O region */
  38             continue;
  39         }
  40
  41         start_vaddr = start_line_addr | ((i & 0x1fff) << 12);
  42         memory_mapping_list_add_merge_sorted(list, start_paddr,
  43                                              start_vaddr, 1 << 12);
  44     }
  45 }
  46
  47 /* 32-bit Paging */
  48 static void walk_pte2(MemoryMappingList *list,
  49                       hwaddr pte_start_addr, int32_t a20_mask,
  50                       target_ulong start_line_addr)
  51 {
  52     hwaddr pte_addr, start_paddr;
  53     uint32_t pte;
  54     target_ulong start_vaddr;
  55     int i;
  56
  57     for (i = 0; i < 1024; i++) {
  58         pte_addr = (pte_start_addr + i * 4) & a20_mask;
  59         pte = ldl_phys(pte_addr);
  60         if (!(pte & PG_PRESENT_MASK)) {
  61             /* not present */
  62             continue;
  63         }
  64
  65         start_paddr = pte & ~0xfff;
  66         if (cpu_physical_memory_is_io(start_paddr)) {
  67             /* I/O region */
  68             continue;
  69         }
  70
  71         start_vaddr = start_line_addr | ((i & 0x3ff) << 12);
  72         memory_mapping_list_add_merge_sorted(list, start_paddr,
  73                                              start_vaddr, 1 << 12);
  74     }
  75 }
  76
  77 /* PAE Paging or IA-32e Paging */
  78 static void walk_pde(MemoryMappingList *list, hwaddr pde_start_addr,
  79                      int32_t a20_mask, target_ulong start_line_addr)
  80 {
  81     hwaddr pde_addr, pte_start_addr, start_paddr;
  82     uint64_t pde;
  83     target_ulong line_addr, start_vaddr;
  84     int i;
  85
  86     for (i = 0; i < 512; i++) {
  87         pde_addr = (pde_start_addr + i * 8) & a20_mask;
  88         pde = ldq_phys(pde_addr);
  89         if (!(pde & PG_PRESENT_MASK)) {
  90             /* not present */
  91             continue;
  92         }
  93
  94         line_addr = start_line_addr | ((i & 0x1ff) << 21);
  95         if (pde & PG_PSE_MASK) {
  96             /* 2 MB page */
  97             start_paddr = (pde & ~0x1fffff) & ~(0x1ULL << 63);
  98             if (cpu_physical_memory_is_io(start_paddr)) {
  99                 /* I/O region */
 100                 continue;
 101             }
 102             start_vaddr = line_addr;
 103             memory_mapping_list_add_merge_sorted(list, start_paddr,
 104                                                  start_vaddr, 1 << 21);
 105             continue;
 106         }
 107
 108         pte_start_addr = (pde & ~0xfff) & a20_mask;
 109         walk_pte(list, pte_start_addr, a20_mask, line_addr);
 110     }
 111 }
 112
 113 /* 32-bit Paging */
 114 static void walk_pde2(MemoryMappingList *list,
 115                       hwaddr pde_start_addr, int32_t a20_mask,
 116                       bool pse)
 117 {
 118     hwaddr pde_addr, pte_start_addr, start_paddr, high_paddr;
 119     uint32_t pde;
 120     target_ulong line_addr, start_vaddr;
 121     int i;
 122
 123     for (i = 0; i < 1024; i++) {
 124         pde_addr = (pde_start_addr + i * 4) & a20_mask;
 125         pde = ldl_phys(pde_addr);
 126         if (!(pde & PG_PRESENT_MASK)) {
 127             /* not present */
 128             continue;
 129         }
 130
 131         line_addr = (((unsigned int)i & 0x3ff) << 22);
 132         if ((pde & PG_PSE_MASK) && pse) {
 133             /*
 134              * 4 MB page:
 135              * bits 39:32 are bits 20:13 of the PDE
 136              * bit3 31:22 are bits 31:22 of the PDE
 137              */
 138             high_paddr = ((hwaddr)(pde & 0x1fe000) << 19);
 139             start_paddr = (pde & ~0x3fffff) | high_paddr;
 140             if (cpu_physical_memory_is_io(start_paddr)) {
 141                 /* I/O region */
 142                 continue;
 143             }
 144             start_vaddr = line_addr;
 145             memory_mapping_list_add_merge_sorted(list, start_paddr,
 146                                                  start_vaddr, 1 << 22);
 147             continue;
 148         }
 149
 150         pte_start_addr = (pde & ~0xfff) & a20_mask;
 151         walk_pte2(list, pte_start_addr, a20_mask, line_addr);
 152     }
 153 }
 154
 155 /* PAE Paging */
 156 static void walk_pdpe2(MemoryMappingList *list,
 157                        hwaddr pdpe_start_addr, int32_t a20_mask)
 158 {
 159     hwaddr pdpe_addr, pde_start_addr;
 160     uint64_t pdpe;
 161     target_ulong line_addr;
 162     int i;
 163
 164     for (i = 0; i < 4; i++) {
 165         pdpe_addr = (pdpe_start_addr + i * 8) & a20_mask;
 166         pdpe = ldq_phys(pdpe_addr);
 167         if (!(pdpe & PG_PRESENT_MASK)) {
 168             /* not present */
 169             continue;
 170         }
 171
 172         line_addr = (((unsigned int)i & 0x3) << 30);
 173         pde_start_addr = (pdpe & ~0xfff) & a20_mask;
 174         walk_pde(list, pde_start_addr, a20_mask, line_addr);
 175     }
 176 }
 177
 178 #ifdef TARGET_X86_64
 179 /* IA-32e Paging */
 180 static void walk_pdpe(MemoryMappingList *list,
 181                       hwaddr pdpe_start_addr, int32_t a20_mask,
 182                       target_ulong start_line_addr)
 183 {
 184     hwaddr pdpe_addr, pde_start_addr, start_paddr;
 185     uint64_t pdpe;
 186     target_ulong line_addr, start_vaddr;
 187     int i;
 188
 189     for (i = 0; i < 512; i++) {
 190         pdpe_addr = (pdpe_start_addr + i * 8) & a20_mask;
 191         pdpe = ldq_phys(pdpe_addr);
 192         if (!(pdpe & PG_PRESENT_MASK)) {
 193             /* not present */
 194             continue;
 195         }
 196
 197         line_addr = start_line_addr | ((i & 0x1ffULL) << 30);
 198         if (pdpe & PG_PSE_MASK) {
 199             /* 1 GB page */
 200             start_paddr = (pdpe & ~0x3fffffff) & ~(0x1ULL << 63);
 201             if (cpu_physical_memory_is_io(start_paddr)) {
 202                 /* I/O region */
 203                 continue;
 204             }
 205             start_vaddr = line_addr;
 206             memory_mapping_list_add_merge_sorted(list, start_paddr,
 207                                                  start_vaddr, 1 << 30);
 208             continue;
 209         }
 210
 211         pde_start_addr = (pdpe & ~0xfff) & a20_mask;
 212         walk_pde(list, pde_start_addr, a20_mask, line_addr);
 213     }
 214 }
 215
 216 /* IA-32e Paging */
 217 static void walk_pml4e(MemoryMappingList *list,
 218                        hwaddr pml4e_start_addr, int32_t a20_mask)
 219 {
 220     hwaddr pml4e_addr, pdpe_start_addr;
 221     uint64_t pml4e;
 222     target_ulong line_addr;
 223     int i;
 224
 225     for (i = 0; i < 512; i++) {
 226         pml4e_addr = (pml4e_start_addr + i * 8) & a20_mask;
 227         pml4e = ldq_phys(pml4e_addr);
 228         if (!(pml4e & PG_PRESENT_MASK)) {
 229             /* not present */
 230             continue;
 231         }
 232
 233         line_addr = ((i & 0x1ffULL) << 39) | (0xffffULL << 48);
 234         pdpe_start_addr = (pml4e & ~0xfff) & a20_mask;
 235         walk_pdpe(list, pdpe_start_addr, a20_mask, line_addr);
 236     }
 237 }
 238 #endif
 239
 240 int cpu_get_memory_mapping(MemoryMappingList *list, CPUArchState *env)
 241 {
 242     if (!cpu_paging_enabled(env)) {
 243         /* paging is disabled */
 244         return 0;
 245     }
 246
 247     if (env->cr[4] & CR4_PAE_MASK) {
 248 #ifdef TARGET_X86_64
 249         if (env->hflags & HF_LMA_MASK) {
 250             hwaddr pml4e_addr;
 251
 252             pml4e_addr = (env->cr[3] & ~0xfff) & env->a20_mask;
 253             walk_pml4e(list, pml4e_addr, env->a20_mask);
 254         } else
 255 #endif
 256         {
 257             hwaddr pdpe_addr;
 258
 259             pdpe_addr = (env->cr[3] & ~0x1f) & env->a20_mask;
 260             walk_pdpe2(list, pdpe_addr, env->a20_mask);
 261         }
 262     } else {
 263         hwaddr pde_addr;
 264         bool pse;
 265
 266         pde_addr = (env->cr[3] & ~0xfff) & env->a20_mask;
 267         pse = !!(env->cr[4] & CR4_PSE_MASK);
 268         walk_pde2(list, pde_addr, env->a20_mask, pse);
 269     }
 270
 271     return 0;
 272 }
 273
 274 bool cpu_paging_enabled(CPUArchState *env)
 275 {
 276     return env->cr[0] & CR0_PG_MASK;
 277 }