vmdk: Add option to create zeroed-grain image
[qemu.git] / target-i386 / arch_dump.c
blob83898cd00fa1f797818ef983ec7192a0008fcd56
1 /*
2 * i386 memory mapping
4 * Copyright Fujitsu, Corp. 2011, 2012
6 * Authors:
7 * Wen Congyang <wency@cn.fujitsu.com>
9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
10 * See the COPYING file in the top-level directory.
14 #include "cpu.h"
15 #include "exec/cpu-all.h"
16 #include "sysemu/dump.h"
17 #include "elf.h"
19 #ifdef TARGET_X86_64
20 typedef struct {
21 target_ulong r15, r14, r13, r12, rbp, rbx, r11, r10;
22 target_ulong r9, r8, rax, rcx, rdx, rsi, rdi, orig_rax;
23 target_ulong rip, cs, eflags;
24 target_ulong rsp, ss;
25 target_ulong fs_base, gs_base;
26 target_ulong ds, es, fs, gs;
27 } x86_64_user_regs_struct;
29 typedef struct {
30 char pad1[32];
31 uint32_t pid;
32 char pad2[76];
33 x86_64_user_regs_struct regs;
34 char pad3[8];
35 } x86_64_elf_prstatus;
37 static int x86_64_write_elf64_note(WriteCoreDumpFunction f,
38 CPUArchState *env, int id,
39 void *opaque)
41 x86_64_user_regs_struct regs;
42 Elf64_Nhdr *note;
43 char *buf;
44 int descsz, note_size, name_size = 5;
45 const char *name = "CORE";
46 int ret;
48 regs.r15 = env->regs[15];
49 regs.r14 = env->regs[14];
50 regs.r13 = env->regs[13];
51 regs.r12 = env->regs[12];
52 regs.r11 = env->regs[11];
53 regs.r10 = env->regs[10];
54 regs.r9 = env->regs[9];
55 regs.r8 = env->regs[8];
56 regs.rbp = env->regs[R_EBP];
57 regs.rsp = env->regs[R_ESP];
58 regs.rdi = env->regs[R_EDI];
59 regs.rsi = env->regs[R_ESI];
60 regs.rdx = env->regs[R_EDX];
61 regs.rcx = env->regs[R_ECX];
62 regs.rbx = env->regs[R_EBX];
63 regs.rax = env->regs[R_EAX];
64 regs.rip = env->eip;
65 regs.eflags = env->eflags;
67 regs.orig_rax = 0; /* FIXME */
68 regs.cs = env->segs[R_CS].selector;
69 regs.ss = env->segs[R_SS].selector;
70 regs.fs_base = env->segs[R_FS].base;
71 regs.gs_base = env->segs[R_GS].base;
72 regs.ds = env->segs[R_DS].selector;
73 regs.es = env->segs[R_ES].selector;
74 regs.fs = env->segs[R_FS].selector;
75 regs.gs = env->segs[R_GS].selector;
77 descsz = sizeof(x86_64_elf_prstatus);
78 note_size = ((sizeof(Elf64_Nhdr) + 3) / 4 + (name_size + 3) / 4 +
79 (descsz + 3) / 4) * 4;
80 note = g_malloc(note_size);
82 memset(note, 0, note_size);
83 note->n_namesz = cpu_to_le32(name_size);
84 note->n_descsz = cpu_to_le32(descsz);
85 note->n_type = cpu_to_le32(NT_PRSTATUS);
86 buf = (char *)note;
87 buf += ((sizeof(Elf64_Nhdr) + 3) / 4) * 4;
88 memcpy(buf, name, name_size);
89 buf += ((name_size + 3) / 4) * 4;
90 memcpy(buf + 32, &id, 4); /* pr_pid */
91 buf += descsz - sizeof(x86_64_user_regs_struct)-sizeof(target_ulong);
92 memcpy(buf, &regs, sizeof(x86_64_user_regs_struct));
94 ret = f(note, note_size, opaque);
95 g_free(note);
96 if (ret < 0) {
97 return -1;
100 return 0;
102 #endif
104 typedef struct {
105 uint32_t ebx, ecx, edx, esi, edi, ebp, eax;
106 unsigned short ds, __ds, es, __es;
107 unsigned short fs, __fs, gs, __gs;
108 uint32_t orig_eax, eip;
109 unsigned short cs, __cs;
110 uint32_t eflags, esp;
111 unsigned short ss, __ss;
112 } x86_user_regs_struct;
114 typedef struct {
115 char pad1[24];
116 uint32_t pid;
117 char pad2[44];
118 x86_user_regs_struct regs;
119 char pad3[4];
120 } x86_elf_prstatus;
122 static void x86_fill_elf_prstatus(x86_elf_prstatus *prstatus, CPUArchState *env,
123 int id)
125 memset(prstatus, 0, sizeof(x86_elf_prstatus));
126 prstatus->regs.ebp = env->regs[R_EBP] & 0xffffffff;
127 prstatus->regs.esp = env->regs[R_ESP] & 0xffffffff;
128 prstatus->regs.edi = env->regs[R_EDI] & 0xffffffff;
129 prstatus->regs.esi = env->regs[R_ESI] & 0xffffffff;
130 prstatus->regs.edx = env->regs[R_EDX] & 0xffffffff;
131 prstatus->regs.ecx = env->regs[R_ECX] & 0xffffffff;
132 prstatus->regs.ebx = env->regs[R_EBX] & 0xffffffff;
133 prstatus->regs.eax = env->regs[R_EAX] & 0xffffffff;
134 prstatus->regs.eip = env->eip & 0xffffffff;
135 prstatus->regs.eflags = env->eflags & 0xffffffff;
137 prstatus->regs.cs = env->segs[R_CS].selector;
138 prstatus->regs.ss = env->segs[R_SS].selector;
139 prstatus->regs.ds = env->segs[R_DS].selector;
140 prstatus->regs.es = env->segs[R_ES].selector;
141 prstatus->regs.fs = env->segs[R_FS].selector;
142 prstatus->regs.gs = env->segs[R_GS].selector;
144 prstatus->pid = id;
147 static int x86_write_elf64_note(WriteCoreDumpFunction f, CPUArchState *env,
148 int id, void *opaque)
150 x86_elf_prstatus prstatus;
151 Elf64_Nhdr *note;
152 char *buf;
153 int descsz, note_size, name_size = 5;
154 const char *name = "CORE";
155 int ret;
157 x86_fill_elf_prstatus(&prstatus, env, id);
158 descsz = sizeof(x86_elf_prstatus);
159 note_size = ((sizeof(Elf64_Nhdr) + 3) / 4 + (name_size + 3) / 4 +
160 (descsz + 3) / 4) * 4;
161 note = g_malloc(note_size);
163 memset(note, 0, note_size);
164 note->n_namesz = cpu_to_le32(name_size);
165 note->n_descsz = cpu_to_le32(descsz);
166 note->n_type = cpu_to_le32(NT_PRSTATUS);
167 buf = (char *)note;
168 buf += ((sizeof(Elf64_Nhdr) + 3) / 4) * 4;
169 memcpy(buf, name, name_size);
170 buf += ((name_size + 3) / 4) * 4;
171 memcpy(buf, &prstatus, sizeof(prstatus));
173 ret = f(note, note_size, opaque);
174 g_free(note);
175 if (ret < 0) {
176 return -1;
179 return 0;
182 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
183 int cpuid, void *opaque)
185 X86CPU *cpu = X86_CPU(cs);
186 int ret;
187 #ifdef TARGET_X86_64
188 bool lma = !!(first_cpu->hflags & HF_LMA_MASK);
190 if (lma) {
191 ret = x86_64_write_elf64_note(f, &cpu->env, cpuid, opaque);
192 } else {
193 #endif
194 ret = x86_write_elf64_note(f, &cpu->env, cpuid, opaque);
195 #ifdef TARGET_X86_64
197 #endif
199 return ret;
202 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
203 int cpuid, void *opaque)
205 X86CPU *cpu = X86_CPU(cs);
206 x86_elf_prstatus prstatus;
207 Elf32_Nhdr *note;
208 char *buf;
209 int descsz, note_size, name_size = 5;
210 const char *name = "CORE";
211 int ret;
213 x86_fill_elf_prstatus(&prstatus, &cpu->env, cpuid);
214 descsz = sizeof(x86_elf_prstatus);
215 note_size = ((sizeof(Elf32_Nhdr) + 3) / 4 + (name_size + 3) / 4 +
216 (descsz + 3) / 4) * 4;
217 note = g_malloc(note_size);
219 memset(note, 0, note_size);
220 note->n_namesz = cpu_to_le32(name_size);
221 note->n_descsz = cpu_to_le32(descsz);
222 note->n_type = cpu_to_le32(NT_PRSTATUS);
223 buf = (char *)note;
224 buf += ((sizeof(Elf32_Nhdr) + 3) / 4) * 4;
225 memcpy(buf, name, name_size);
226 buf += ((name_size + 3) / 4) * 4;
227 memcpy(buf, &prstatus, sizeof(prstatus));
229 ret = f(note, note_size, opaque);
230 g_free(note);
231 if (ret < 0) {
232 return -1;
235 return 0;
239 * please count up QEMUCPUSTATE_VERSION if you have changed definition of
240 * QEMUCPUState, and modify the tools using this information accordingly.
242 #define QEMUCPUSTATE_VERSION (1)
244 struct QEMUCPUSegment {
245 uint32_t selector;
246 uint32_t limit;
247 uint32_t flags;
248 uint32_t pad;
249 uint64_t base;
252 typedef struct QEMUCPUSegment QEMUCPUSegment;
254 struct QEMUCPUState {
255 uint32_t version;
256 uint32_t size;
257 uint64_t rax, rbx, rcx, rdx, rsi, rdi, rsp, rbp;
258 uint64_t r8, r9, r10, r11, r12, r13, r14, r15;
259 uint64_t rip, rflags;
260 QEMUCPUSegment cs, ds, es, fs, gs, ss;
261 QEMUCPUSegment ldt, tr, gdt, idt;
262 uint64_t cr[5];
265 typedef struct QEMUCPUState QEMUCPUState;
267 static void copy_segment(QEMUCPUSegment *d, SegmentCache *s)
269 d->pad = 0;
270 d->selector = s->selector;
271 d->limit = s->limit;
272 d->flags = s->flags;
273 d->base = s->base;
276 static void qemu_get_cpustate(QEMUCPUState *s, CPUArchState *env)
278 memset(s, 0, sizeof(QEMUCPUState));
280 s->version = QEMUCPUSTATE_VERSION;
281 s->size = sizeof(QEMUCPUState);
283 s->rax = env->regs[R_EAX];
284 s->rbx = env->regs[R_EBX];
285 s->rcx = env->regs[R_ECX];
286 s->rdx = env->regs[R_EDX];
287 s->rsi = env->regs[R_ESI];
288 s->rdi = env->regs[R_EDI];
289 s->rsp = env->regs[R_ESP];
290 s->rbp = env->regs[R_EBP];
291 #ifdef TARGET_X86_64
292 s->r8 = env->regs[8];
293 s->r9 = env->regs[9];
294 s->r10 = env->regs[10];
295 s->r11 = env->regs[11];
296 s->r12 = env->regs[12];
297 s->r13 = env->regs[13];
298 s->r14 = env->regs[14];
299 s->r15 = env->regs[15];
300 #endif
301 s->rip = env->eip;
302 s->rflags = env->eflags;
304 copy_segment(&s->cs, &env->segs[R_CS]);
305 copy_segment(&s->ds, &env->segs[R_DS]);
306 copy_segment(&s->es, &env->segs[R_ES]);
307 copy_segment(&s->fs, &env->segs[R_FS]);
308 copy_segment(&s->gs, &env->segs[R_GS]);
309 copy_segment(&s->ss, &env->segs[R_SS]);
310 copy_segment(&s->ldt, &env->ldt);
311 copy_segment(&s->tr, &env->tr);
312 copy_segment(&s->gdt, &env->gdt);
313 copy_segment(&s->idt, &env->idt);
315 s->cr[0] = env->cr[0];
316 s->cr[1] = env->cr[1];
317 s->cr[2] = env->cr[2];
318 s->cr[3] = env->cr[3];
319 s->cr[4] = env->cr[4];
322 static inline int cpu_write_qemu_note(WriteCoreDumpFunction f,
323 CPUArchState *env,
324 void *opaque,
325 int type)
327 QEMUCPUState state;
328 Elf64_Nhdr *note64;
329 Elf32_Nhdr *note32;
330 void *note;
331 char *buf;
332 int descsz, note_size, name_size = 5, note_head_size;
333 const char *name = "QEMU";
334 int ret;
336 qemu_get_cpustate(&state, env);
338 descsz = sizeof(state);
339 if (type == 0) {
340 note_head_size = sizeof(Elf32_Nhdr);
341 } else {
342 note_head_size = sizeof(Elf64_Nhdr);
344 note_size = ((note_head_size + 3) / 4 + (name_size + 3) / 4 +
345 (descsz + 3) / 4) * 4;
346 note = g_malloc(note_size);
348 memset(note, 0, note_size);
349 if (type == 0) {
350 note32 = note;
351 note32->n_namesz = cpu_to_le32(name_size);
352 note32->n_descsz = cpu_to_le32(descsz);
353 note32->n_type = 0;
354 } else {
355 note64 = note;
356 note64->n_namesz = cpu_to_le32(name_size);
357 note64->n_descsz = cpu_to_le32(descsz);
358 note64->n_type = 0;
360 buf = note;
361 buf += ((note_head_size + 3) / 4) * 4;
362 memcpy(buf, name, name_size);
363 buf += ((name_size + 3) / 4) * 4;
364 memcpy(buf, &state, sizeof(state));
366 ret = f(note, note_size, opaque);
367 g_free(note);
368 if (ret < 0) {
369 return -1;
372 return 0;
375 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cs,
376 void *opaque)
378 X86CPU *cpu = X86_CPU(cs);
380 return cpu_write_qemu_note(f, &cpu->env, opaque, 1);
383 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cs,
384 void *opaque)
386 X86CPU *cpu = X86_CPU(cs);
388 return cpu_write_qemu_note(f, &cpu->env, opaque, 0);
391 int cpu_get_dump_info(ArchDumpInfo *info)
393 bool lma = false;
394 RAMBlock *block;
396 #ifdef TARGET_X86_64
397 lma = !!(first_cpu->hflags & HF_LMA_MASK);
398 #endif
400 if (lma) {
401 info->d_machine = EM_X86_64;
402 } else {
403 info->d_machine = EM_386;
405 info->d_endian = ELFDATA2LSB;
407 if (lma) {
408 info->d_class = ELFCLASS64;
409 } else {
410 info->d_class = ELFCLASS32;
412 QTAILQ_FOREACH(block, &ram_list.blocks, next) {
413 if (block->offset + block->length > UINT_MAX) {
414 /* The memory size is greater than 4G */
415 info->d_class = ELFCLASS64;
416 break;
421 return 0;
424 ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
426 int name_size = 5; /* "CORE" or "QEMU" */
427 size_t elf_note_size = 0;
428 size_t qemu_note_size = 0;
429 int elf_desc_size = 0;
430 int qemu_desc_size = 0;
431 int note_head_size;
433 if (class == ELFCLASS32) {
434 note_head_size = sizeof(Elf32_Nhdr);
435 } else {
436 note_head_size = sizeof(Elf64_Nhdr);
439 if (machine == EM_386) {
440 elf_desc_size = sizeof(x86_elf_prstatus);
442 #ifdef TARGET_X86_64
443 else {
444 elf_desc_size = sizeof(x86_64_elf_prstatus);
446 #endif
447 qemu_desc_size = sizeof(QEMUCPUState);
449 elf_note_size = ((note_head_size + 3) / 4 + (name_size + 3) / 4 +
450 (elf_desc_size + 3) / 4) * 4;
451 qemu_note_size = ((note_head_size + 3) / 4 + (name_size + 3) / 4 +
452 (qemu_desc_size + 3) / 4) * 4;
454 return (elf_note_size + qemu_note_size) * nr_cpus;