hw/ppc_prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25 #include "m48t59.h"
  26
  27 //#define HARD_DEBUG_PPC_IO
  28 //#define DEBUG_PPC_IO
  29
  30 extern int loglevel;
  31 extern FILE *logfile;
  32
  33 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
  34 #define DEBUG_PPC_IO
  35 #endif
  36
  37 #if defined (HARD_DEBUG_PPC_IO)
  38 #define PPC_IO_DPRINTF(fmt, args...)                     \
  39 do {                                                     \
  40     if (loglevel > 0) {                                  \
  41         fprintf(logfile, "%s: " fmt, __func__ , ##args); \
  42     } else {                                             \
  43         printf("%s : " fmt, __func__ , ##args);          \
  44     }                                                    \
  45 } while (0)
  46 #elif defined (DEBUG_PPC_IO)
  47 #define PPC_IO_DPRINTF(fmt, args...)                     \
  48 do {                                                     \
  49     if (loglevel > 0) {                                  \
  50         fprintf(logfile, "%s: " fmt, __func__ , ##args); \
  51     }                                                    \
  52 } while (0)
  53 #else
  54 #define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
  55 #endif
  56
  57 #define BIOS_FILENAME "ppc_rom.bin"
  58
  59 #define KERNEL_LOAD_ADDR    0x00000000
  60 #define KERNEL_STACK_ADDR   0x00400000
  61 #define INITRD_LOAD_ADDR    0x00800000
  62
  63 int load_kernel(const char *filename, uint8_t *addr,
  64                 uint8_t *real_addr)
  65 {
  66     int fd, size;
  67     int setup_sects;
  68
  69     fd = open(filename, O_RDONLY);
  70     if (fd < 0)
  71         return -1;
  72
  73     /* load 16 bit code */
  74     if (read(fd, real_addr, 512) != 512)
  75         goto fail;
  76     setup_sects = real_addr[0x1F1];
  77     if (!setup_sects)
  78         setup_sects = 4;
  79     if (read(fd, real_addr + 512, setup_sects * 512) !=
  80         setup_sects * 512)
  81         goto fail;
  82
  83     /* load 32 bit code */
  84     size = read(fd, addr, 16 * 1024 * 1024);
  85     if (size < 0)
  86         goto fail;
  87     close(fd);
  88     return size;
  89  fail:
  90     close(fd);
  91     return -1;
  92 }
  93
  94 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  95 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  96 static const int ide_irq[2] = { 13, 13 };
  97
  98 #define NE2000_NB_MAX 6
  99
 100 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
 101 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 102
 103 /* IO ports emulation */
 104 #define PPC_IO_BASE 0x80000000
 105
 106 static void PPC_io_writeb (target_phys_addr_t addr, uint32_t value)
 107 {
 108     /* Don't polute serial port output */
 109 #if 0
 110     if ((addr < 0x800003F0 || addr > 0x80000400) &&
 111         (addr < 0x80000074 || addr > 0x80000077) &&
 112         (addr < 0x80000020 || addr > 0x80000021) &&
 113         (addr < 0x800000a0 || addr > 0x800000a1) &&
 114         (addr < 0x800001f0 || addr > 0x800001f7) &&
 115         (addr < 0x80000170 || addr > 0x80000177))
 116 #endif
 117     {
 118         PPC_IO_DPRINTF("0x%08x => 0x%02x\n", addr - PPC_IO_BASE, value);
 119     }
 120     cpu_outb(NULL, addr - PPC_IO_BASE, value);
 121 }
 122
 123 static uint32_t PPC_io_readb (target_phys_addr_t addr)
 124 {
 125     uint32_t ret = cpu_inb(NULL, addr - PPC_IO_BASE);
 126
 127 #if 0
 128     if ((addr < 0x800003F0 || addr > 0x80000400) &&
 129         (addr < 0x80000074 || addr > 0x80000077) &&
 130         (addr < 0x80000020 || addr > 0x80000021) &&
 131         (addr < 0x800000a0 || addr > 0x800000a1) &&
 132         (addr < 0x800001f0 || addr > 0x800001f7) &&
 133         (addr < 0x80000170 || addr > 0x80000177) &&
 134         (addr < 0x8000060 || addr > 0x8000064))
 135 #endif
 136     {
 137         PPC_IO_DPRINTF("0x%08x <= 0x%02x\n", addr - PPC_IO_BASE, ret);
 138     }
 139     return ret;
 140 }
 141
 142 static void PPC_io_writew (target_phys_addr_t addr, uint32_t value)
 143 {
 144     if ((addr < 0x800001f0 || addr > 0x800001f7) &&
 145         (addr < 0x80000170 || addr > 0x80000177)) {
 146         PPC_IO_DPRINTF("0x%08x => 0x%04x\n", addr - PPC_IO_BASE, value);
 147     }
 148 #ifdef TARGET_WORDS_BIGENDIAN
 149     value = bswap16(value);
 150 #endif
 151     cpu_outw(NULL, addr - PPC_IO_BASE, value);
 152 }
 153
 154 static uint32_t PPC_io_readw (target_phys_addr_t addr)
 155 {
 156     uint32_t ret = cpu_inw(NULL, addr - PPC_IO_BASE);
 157 #ifdef TARGET_WORDS_BIGENDIAN
 158     ret = bswap16(ret);
 159 #endif
 160     if ((addr < 0x800001f0 || addr > 0x800001f7) &&
 161         (addr < 0x80000170 || addr > 0x80000177)) {
 162         PPC_IO_DPRINTF("0x%08x <= 0x%04x\n", addr - PPC_IO_BASE, ret);
 163     }
 164     return ret;
 165 }
 166
 167 static void PPC_io_writel (target_phys_addr_t addr, uint32_t value)
 168 {
 169     PPC_IO_DPRINTF("0x%08x => 0x%08x\n", addr - PPC_IO_BASE, value);
 170 #ifdef TARGET_WORDS_BIGENDIAN
 171     value = bswap32(value);
 172 #endif
 173     cpu_outl(NULL, addr - PPC_IO_BASE, value);
 174 }
 175
 176 static uint32_t PPC_io_readl (target_phys_addr_t addr)
 177 {
 178     uint32_t ret = cpu_inl(NULL, addr - PPC_IO_BASE);
 179
 180 #ifdef TARGET_WORDS_BIGENDIAN
 181     ret = bswap32(ret);
 182 #endif
 183     PPC_IO_DPRINTF("0x%08x <= 0x%08x\n", addr - PPC_IO_BASE, ret);
 184     return ret;
 185 }
 186
 187 static CPUWriteMemoryFunc *PPC_io_write[] = {
 188     &PPC_io_writeb,
 189     &PPC_io_writew,
 190     &PPC_io_writel,
 191 };
 192
 193 static CPUReadMemoryFunc *PPC_io_read[] = {
 194     &PPC_io_readb,
 195     &PPC_io_readw,
 196     &PPC_io_readl,
 197 };
 198
 199 /* Read-only register (?) */
 200 static void _PPC_ioB_write (target_phys_addr_t addr, uint32_t value)
 201 {
 202     //    printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
 203 }
 204
 205 static uint32_t _PPC_ioB_read (target_phys_addr_t addr)
 206 {
 207     uint32_t retval = 0;
 208
 209     if (addr == 0xBFFFFFF0)
 210         retval = pic_intack_read(NULL);
 211        //   printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
 212
 213     return retval;
 214 }
 215
 216 static CPUWriteMemoryFunc *PPC_ioB_write[] = {
 217     &_PPC_ioB_write,
 218     &_PPC_ioB_write,
 219     &_PPC_ioB_write,
 220 };
 221
 222 static CPUReadMemoryFunc *PPC_ioB_read[] = {
 223     &_PPC_ioB_read,
 224     &_PPC_ioB_read,
 225     &_PPC_ioB_read,
 226 };
 227
 228 #if 0
 229 static CPUWriteMemoryFunc *PPC_io3_write[] = {
 230     &PPC_io3_writeb,
 231     &PPC_io3_writew,
 232     &PPC_io3_writel,
 233 };
 234
 235 static CPUReadMemoryFunc *PPC_io3_read[] = {
 236     &PPC_io3_readb,
 237     &PPC_io3_readw,
 238     &PPC_io3_readl,
 239 };
 240 #endif
 241
 242 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 243 static uint8_t PREP_fake_io[2];
 244 static uint8_t NVRAM_lock;
 245
 246 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
 247 {
 248     PPC_IO_DPRINTF("0x%08x => 0x%08x\n", addr - PPC_IO_BASE, val);
 249     PREP_fake_io[addr - 0x0398] = val;
 250 }
 251
 252 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
 253 {
 254     PPC_IO_DPRINTF("0x%08x <= 0x%08x\n", addr - PPC_IO_BASE, PREP_fake_io[addr - 0x0398]);
 255     return PREP_fake_io[addr - 0x0398];
 256 }
 257
 258 static uint8_t syscontrol;
 259
 260 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 261 {
 262     PPC_IO_DPRINTF("0x%08x => 0x%08x\n", addr - PPC_IO_BASE, val);
 263     switch (addr) {
 264     case 0x0092:
 265         /* Special port 92 */
 266         /* Check soft reset asked */
 267         if (val & 0x80) {
 268             printf("Soft reset asked... Stop emulation\n");
 269             abort();
 270         }
 271         /* Check LE mode */
 272         if (val & 0x40) {
 273             printf("Little Endian mode isn't supported (yet ?)\n");
 274             abort();
 275         }
 276         break;
 277     case 0x0808:
 278         /* Hardfile light register: don't care */
 279         break;
 280     case 0x0810:
 281         /* Password protect 1 register */
 282         NVRAM_lock ^= 0x01;
 283         break;
 284     case 0x0812:
 285         /* Password protect 2 register */
 286         NVRAM_lock ^= 0x02;
 287         break;
 288     case 0x0814:
 289         /* L2 invalidate register: don't care */
 290         break;
 291     case 0x081C:
 292         /* system control register */
 293         syscontrol = val;
 294         break;
 295     case 0x0850:
 296         /* I/O map type register */
 297         if (val & 0x80) {
 298             printf("No support for non-continuous I/O map mode\n");
 299             abort();
 300         }
 301         break;
 302     default:
 303         break;
 304     }
 305 }
 306
 307 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 308 {
 309     uint32_t retval = 0xFF;
 310
 311     switch (addr) {
 312     case 0x0092:
 313         /* Special port 92 */
 314         retval = 0x40;
 315         break;
 316     case 0x080C:
 317         /* Equipment present register:
 318          *  no L2 cache
 319          *  no upgrade processor
 320          *  no cards in PCI slots
 321          *  SCSI fuse is bad
 322          */
 323         retval = 0xFC;
 324         break;
 325     case 0x0818:
 326         /* Keylock */
 327         retval = 0x00;
 328         break;
 329     case 0x081C:
 330         /* system control register
 331          * 7 - 6 / 1 - 0: L2 cache enable
 332          */
 333         retval = syscontrol;
 334         break;
 335     case 0x0823:
 336         /* */
 337         retval = 0x03; /* no L2 cache */
 338         break;
 339     case 0x0850:
 340         /* I/O map type register */
 341         retval = 0x00;
 342         break;
 343     default:
 344         break;
 345     }
 346     PPC_IO_DPRINTF("0x%08x <= 0x%08x\n", addr - PPC_IO_BASE, retval);
 347
 348     return retval;
 349 }
 350
 351 #define NVRAM_SIZE        0x2000
 352 #define NVRAM_END         0x1FF0
 353 #define NVRAM_OSAREA_SIZE 512
 354 #define NVRAM_CONFSIZE    1024
 355
 356 static inline void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
 357 {
 358     m48t59_set_addr(nvram, addr);
 359     m48t59_write(nvram, value);
 360 }
 361
 362 static inline uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
 363 {
 364     m48t59_set_addr(nvram, addr);
 365     return m48t59_read(nvram);
 366 }
 367
 368 static inline void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
 369 {
 370     m48t59_set_addr(nvram, addr);
 371     m48t59_write(nvram, value >> 8);
 372     m48t59_set_addr(nvram, addr + 1);
 373     m48t59_write(nvram, value & 0xFF);
 374 }
 375
 376 static inline uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
 377 {
 378     uint16_t tmp;
 379
 380     m48t59_set_addr(nvram, addr);
 381     tmp = m48t59_read(nvram) << 8;
 382     m48t59_set_addr(nvram, addr + 1);
 383     tmp |= m48t59_read(nvram);
 384
 385     return tmp;
 386 }
 387
 388 static inline void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr,
 389                                     uint32_t value)
 390 {
 391     m48t59_set_addr(nvram, addr);
 392     m48t59_write(nvram, value >> 24);
 393     m48t59_set_addr(nvram, addr + 1);
 394     m48t59_write(nvram, (value >> 16) & 0xFF);
 395     m48t59_set_addr(nvram, addr + 2);
 396     m48t59_write(nvram, (value >> 8) & 0xFF);
 397     m48t59_set_addr(nvram, addr + 3);
 398     m48t59_write(nvram, value & 0xFF);
 399 }
 400
 401 static inline uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
 402 {
 403     uint32_t tmp;
 404
 405     m48t59_set_addr(nvram, addr);
 406     tmp = m48t59_read(nvram) << 24;
 407     m48t59_set_addr(nvram, addr + 1);
 408     tmp |= m48t59_read(nvram) << 16;
 409     m48t59_set_addr(nvram, addr + 2);
 410     tmp |= m48t59_read(nvram) << 8;
 411     m48t59_set_addr(nvram, addr + 3);
 412     tmp |= m48t59_read(nvram);
 413
 414     return tmp;
 415 }
 416
 417 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
 418 {
 419     uint16_t tmp;
 420     uint16_t pd, pd1, pd2;
 421
 422     tmp = prev >> 8;
 423     pd = prev ^ value;
 424     pd1 = pd & 0x000F;
 425     pd2 = ((pd >> 4) & 0x000F) ^ pd1;
 426     tmp ^= (pd1 << 3) | (pd1 << 8);
 427     tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
 428
 429     return tmp;
 430 }
 431
 432 static void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
 433                            uint32_t start, uint32_t count)
 434 {
 435     uint32_t i;
 436     uint16_t crc = 0xFFFF;
 437     int odd = 0;
 438
 439     if (count & 1)
 440         odd = 1;
 441     count &= ~1;
 442     for (i = 0; i != count; i++) {
 443         crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
 444     }
 445     if (odd) {
 446         crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
 447     }
 448     NVRAM_set_word(nvram, addr, crc);
 449 }
 450
 451 static void prep_NVRAM_init (void)
 452 {
 453     m48t59_t *nvram;
 454
 455     nvram = m48t59_init(8, 0x0074, NVRAM_SIZE);
 456     /* NVRAM header */
 457     /* 0x00: NVRAM size in kB */
 458     NVRAM_set_word(nvram, 0x00, NVRAM_SIZE >> 10);
 459     /* 0x02: NVRAM version */
 460     NVRAM_set_byte(nvram, 0x02, 0x01);
 461     /* 0x03: NVRAM revision */
 462     NVRAM_set_byte(nvram, 0x03, 0x01);
 463     /* 0x08: last OS */
 464     NVRAM_set_byte(nvram, 0x08, 0x00); /* Unknown */
 465     /* 0x09: endian */
 466     NVRAM_set_byte(nvram, 0x09, 'B');  /* Big-endian */
 467     /* 0x0A: OSArea usage */
 468     NVRAM_set_byte(nvram, 0x0A, 0x00); /* Empty */
 469     /* 0x0B: PM mode */
 470     NVRAM_set_byte(nvram, 0x0B, 0x00); /* Normal */
 471     /* Restart block description record */
 472     /* 0x0C: restart block version */
 473     NVRAM_set_word(nvram, 0x0C, 0x01);
 474     /* 0x0E: restart block revision */
 475     NVRAM_set_word(nvram, 0x0E, 0x01);
 476     /* 0x20: restart address */
 477     NVRAM_set_lword(nvram, 0x20, 0x00);
 478     /* 0x24: save area address */
 479     NVRAM_set_lword(nvram, 0x24, 0x00);
 480     /* 0x28: save area length */
 481     NVRAM_set_lword(nvram, 0x28, 0x00);
 482     /* 0x1C: checksum of restart block */
 483     NVRAM_set_crc(nvram, 0x1C, 0x0C, 32);
 484
 485     /* Security section */
 486     /* Set all to zero */
 487     /* 0xC4: pointer to global environment area */
 488     NVRAM_set_lword(nvram, 0xC4, 0x0100);
 489     /* 0xC8: size of global environment area */
 490     NVRAM_set_lword(nvram, 0xC8,
 491                     NVRAM_END - NVRAM_OSAREA_SIZE - NVRAM_CONFSIZE - 0x0100);
 492     /* 0xD4: pointer to configuration area */
 493     NVRAM_set_lword(nvram, 0xD4, NVRAM_END - NVRAM_CONFSIZE);
 494     /* 0xD8: size of configuration area */
 495     NVRAM_set_lword(nvram, 0xD8, NVRAM_CONFSIZE);
 496     /* 0xE8: pointer to OS specific area */
 497     NVRAM_set_lword(nvram, 0xE8,
 498                     NVRAM_END - NVRAM_CONFSIZE - NVRAM_OSAREA_SIZE);
 499     /* 0xD8: size of OS specific area */
 500     NVRAM_set_lword(nvram, 0xEC, NVRAM_OSAREA_SIZE);
 501
 502     /* Configuration area */
 503     /* RTC init */
 504     //    NVRAM_set_lword(nvram, 0x1FFC, 0x50);
 505
 506     /* 0x04: checksum 0 => OS area   */
 507     NVRAM_set_crc(nvram, 0x04, 0x00,
 508                   NVRAM_END - NVRAM_CONFSIZE - NVRAM_OSAREA_SIZE);
 509     /* 0x06: checksum of config area */
 510     NVRAM_set_crc(nvram, 0x06, NVRAM_END - NVRAM_CONFSIZE, NVRAM_CONFSIZE);
 511 }
 512
 513 int load_initrd (const char *filename, uint8_t *addr)
 514 {
 515     int fd, size;
 516
 517     printf("Load initrd\n");
 518     fd = open(filename, O_RDONLY);
 519     if (fd < 0)
 520         return -1;
 521     size = read(fd, addr, 16 * 1024 * 1024);
 522     if (size < 0)
 523         goto fail;
 524     close(fd);
 525     printf("Load initrd: %d\n", size);
 526     return size;
 527  fail:
 528     close(fd);
 529     printf("Load initrd failed\n");
 530     return -1;
 531 }
 532
 533 /* Quick hack for PPC memory infos... */
 534 static void put_long (void *addr, uint32_t l)
 535 {
 536     char *pos = addr;
 537     pos[0] = (l >> 24) & 0xFF;
 538     pos[1] = (l >> 16) & 0xFF;
 539     pos[2] = (l >> 8) & 0xFF;
 540     pos[3] = l & 0xFF;
 541 }
 542
 543 /* bootloader infos are in the form:
 544  * uint32_t TAG
 545  * uint32_t TAG_size (from TAG to next TAG).
 546  * data
 547  * ....
 548  */
 549 #if !defined (USE_OPEN_FIRMWARE)
 550 static void *set_bootinfo_tag (void *addr, uint32_t tag, uint32_t size,
 551                                void *data)
 552 {
 553     char *pos = addr;
 554
 555     put_long(pos, tag);
 556     pos += 4;
 557     put_long(pos, size + 8);
 558     pos += 4;
 559     memcpy(pos, data, size);
 560     pos += size;
 561
 562     return pos;
 563 }
 564 #endif
 565
 566 typedef struct boot_dev_t {
 567     const unsigned char *name;
 568     int major;
 569     int minor;
 570 } boot_dev_t;
 571
 572 static boot_dev_t boot_devs[] =
 573 {
 574     { "/dev/fd0", 2, 0, },
 575     { "/dev/fd1", 2, 1, },
 576     { "/dev/hda", 3, 1, },
 577 //    { "/dev/ide/host0/bus0/target0/lun0/part1", 3, 1, },
 578 //    { "/dev/hdc", 22, 0, },
 579     { "/dev/hdc", 22, 1, },
 580     { "/dev/ram0 init=/linuxrc", 1, 0, },
 581 };
 582
 583 /* BATU:
 584  * BEPI  : bloc virtual address
 585  * BL    : area size bits (128 kB is 0, 256 1, 512 3, ...
 586  * Vs/Vp
 587  * BATL:
 588  * BPRN  : bloc real address align on 4MB boundary
 589  * WIMG  : cache access mode : not used
 590  * PP    : protection bits
 591  */
 592 static void setup_BAT (CPUPPCState *env, int BAT,
 593                        uint32_t virtual, uint32_t physical,
 594                        uint32_t size, int Vs, int Vp, int PP)
 595 {
 596     uint32_t sz_bits, tmp_sz, align, tmp;
 597
 598     sz_bits = 0;
 599     align = 131072;
 600     for (tmp_sz = size / 131072; tmp_sz != 1; tmp_sz = tmp_sz >> 1) {
 601         sz_bits = (sz_bits << 1) + 1;
 602         align = align << 1;
 603     }
 604     tmp = virtual & ~(align - 1);  /* Align virtual area start */
 605     tmp |= sz_bits << 2;           /* Fix BAT size             */
 606     tmp |= Vs << 1;                /* Supervisor access        */
 607     tmp |= Vp;                     /* User access              */
 608     env->DBAT[0][BAT] = tmp;
 609     env->IBAT[0][BAT] = tmp;
 610     tmp = physical & ~(align - 1); /* Align physical area start */
 611     tmp |= 0;                      /* Don't care about WIMG     */
 612     tmp |= PP;                     /* Protection                */
 613     env->DBAT[1][BAT] = tmp;
 614     env->IBAT[1][BAT] = tmp;
 615     printf("Set BATU0 to 0x%08x BATL0 to 0x%08x\n",
 616            env->DBAT[0][BAT], env->DBAT[1][BAT]);
 617 }
 618
 619 static void VGA_printf (uint8_t *s)
 620 {
 621     uint16_t *arg_ptr;
 622     unsigned int format_width, i;
 623     int in_format;
 624     uint16_t arg, digit, nibble;
 625     uint8_t c;
 626
 627     arg_ptr = (uint16_t *)((void *)&s);
 628     in_format = 0;
 629     format_width = 0;
 630     while ((c = *s) != '\0') {
 631         if (c == '%') {
 632             in_format = 1;
 633             format_width = 0;
 634         } else if (in_format) {
 635             if ((c >= '0') && (c <= '9')) {
 636                 format_width = (format_width * 10) + (c - '0');
 637             } else if (c == 'x') {
 638                 arg_ptr++; // increment to next arg
 639                 arg = *arg_ptr;
 640                 if (format_width == 0)
 641                     format_width = 4;
 642                 digit = format_width - 1;
 643                 for (i = 0; i < format_width; i++) {
 644                     nibble = (arg >> (4 * digit)) & 0x000f;
 645                     if (nibble <= 9)
 646                         PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + '0');
 647                     else
 648                         PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + 'A');
 649                     digit--;
 650                 }
 651                 in_format = 0;
 652             }
 653             //else if (c == 'd') {
 654             //  in_format = 0;
 655             //  }
 656         } else {
 657             PPC_io_writeb(PPC_IO_BASE + 0x500, c);
 658         }
 659         s++;
 660     }
 661 }
 662
 663 static void VGA_init (void)
 664 {
 665     /* Basic VGA init, inspired by plex86 VGAbios */
 666     printf("Init VGA...\n");
 667 #if 1
 668     /* switch to color mode and enable CPU access 480 lines */
 669     PPC_io_writeb(PPC_IO_BASE + 0x3C2, 0xC3);
 670     /* more than 64k 3C4/04 */
 671     PPC_io_writeb(PPC_IO_BASE + 0x3C4, 0x04);
 672     PPC_io_writeb(PPC_IO_BASE + 0x3C5, 0x02);
 673 #endif
 674     VGA_printf("PPC VGA BIOS...\n");
 675 }
 676
 677 extern CPUPPCState *global_env;
 678
 679 static uint32_t get_le32 (void *addr)
 680 {
 681     return le32_to_cpu(*((uint32_t *)addr));
 682 }
 683
 684 void PPC_init_hw (/*CPUPPCState *env,*/ uint32_t mem_size,
 685                   uint32_t kernel_addr, uint32_t kernel_size,
 686                   uint32_t stack_addr, int boot_device,
 687                   const unsigned char *initrd_file)
 688 {
 689     CPUPPCState *env = global_env;
 690     uint8_t *p;
 691 #if !defined (USE_OPEN_FIRMWARE)
 692     char *tmp;
 693     uint32_t tmpi[2];
 694 #endif
 695
 696     printf("RAM size: %u 0x%08x (%u)\n", mem_size, mem_size, mem_size >> 20);
 697 #if defined (USE_OPEN_FIRMWARE)
 698     setup_memory(env, mem_size);
 699 #endif
 700
 701     /* Fake bootloader */
 702     {
 703 #if 1
 704         uint32_t offset = get_le32(phys_ram_base + kernel_addr);
 705 #else
 706         uint32_t offset = 12;
 707 #endif
 708         env->nip = kernel_addr + offset;
 709         printf("Start address: 0x%08x\n", env->nip);
 710     }
 711     /* Set up msr according to PREP specification */
 712     msr_ee = 0;
 713     msr_fp = 1;
 714     msr_pr = 0; /* Start in supervisor mode */
 715     msr_me = 1;
 716     msr_fe0 = msr_fe1 = 0;
 717     msr_ip = 0;
 718     msr_ir = msr_dr = 1;
 719 //    msr_sf = 0;
 720     msr_le = msr_ile = 0;
 721     env->gpr[1] = stack_addr; /* Let's have a stack */
 722     env->gpr[2] = 0;
 723     env->gpr[8] = kernel_addr;
 724     /* There is a bug in  2.4 kernels:
 725      * if a decrementer exception is pending when it enables msr_ee,
 726      * it's not ready to handle it...
 727      */
 728     env->decr = 0xFFFFFFFF;
 729     p = phys_ram_base + kernel_addr;
 730 #if !defined (USE_OPEN_FIRMWARE)
 731     /* Let's register the whole memory available only in supervisor mode */
 732     setup_BAT(env, 0, 0x00000000, 0x00000000, mem_size, 1, 0, 2);
 733     /* Avoid open firmware init call (to get a console)
 734      * This will make the kernel think we are a PREP machine...
 735      */
 736     put_long(p, 0xdeadc0de);
 737     /* Build a real stack room */
 738     p = phys_ram_base + stack_addr;
 739     put_long(p, stack_addr);
 740     p -= 32;
 741     env->gpr[1] -= 32;
 742     /* Pretend there are no residual data */
 743     env->gpr[3] = 0;
 744     if (initrd_file != NULL) {
 745         int size;
 746         env->gpr[4] = (kernel_addr + kernel_size + 4095) & ~4095;
 747         size = load_initrd(initrd_file,
 748                            phys_ram_base + env->gpr[4]);
 749         if (size < 0) {
 750             /* No initrd */
 751             env->gpr[4] = env->gpr[5] = 0;
 752         } else {
 753             env->gpr[5] = size;
 754             boot_device = 'e';
 755         }
 756         printf("Initrd loaded at 0x%08x (%d) (0x%08x 0x%08x)\n",
 757                env->gpr[4], env->gpr[5], kernel_addr, kernel_size);
 758     } else {
 759         env->gpr[4] = env->gpr[5] = 0;
 760     }
 761     /* We have to put bootinfos after the BSS
 762      * The BSS starts after the kernel end.
 763      */
 764 #if 0
 765     p = phys_ram_base + kernel_addr +
 766         kernel_size + (1 << 20) - 1) & ~((1 << 20) - 1);
 767 #else
 768     p = phys_ram_base + kernel_addr + 0x400000;
 769 #endif
 770     if (loglevel > 0) {
 771         fprintf(logfile, "bootinfos: %p 0x%08x\n",
 772                 p, (int)(p - phys_ram_base));
 773     } else {
 774         printf("bootinfos: %p 0x%08x\n",
 775                p, (int)(p - phys_ram_base));
 776     }
 777     /* Command line: let's put it after bootinfos */
 778 #if 0
 779     sprintf(p + 0x1000, "console=ttyS0,9600 root=%02x%02x mem=%dM",
 780             boot_devs[boot_device - 'a'].major,
 781             boot_devs[boot_device - 'a'].minor,
 782             mem_size >> 20);
 783 #else
 784     sprintf(p + 0x1000, "console=ttyS0,9600 console=tty0 root=%s mem=%dM",
 785             boot_devs[boot_device - 'a'].name,
 786             mem_size >> 20);
 787 #endif
 788     env->gpr[6] = p + 0x1000 - phys_ram_base;
 789     env->gpr[7] = env->gpr[6] + strlen(p + 0x1000);
 790     if (loglevel > 0) {
 791         fprintf(logfile, "cmdline: %p 0x%08x [%s]\n",
 792                 p + 0x1000, env->gpr[6], p + 0x1000);
 793     } else {
 794         printf("cmdline: %p 0x%08x [%s]\n",
 795                p + 0x1000, env->gpr[6], p + 0x1000);
 796     }
 797     /* BI_FIRST */
 798     p = set_bootinfo_tag(p, 0x1010, 0, 0);
 799     /* BI_CMD_LINE */
 800     p = set_bootinfo_tag(p, 0x1012, env->gpr[7] - env->gpr[6],
 801                          env->gpr[6] + phys_ram_base);
 802     /* BI_MEM_SIZE */
 803     tmp = (void *)tmpi;
 804     tmp[0] = (mem_size >> 24) & 0xFF;
 805     tmp[1] = (mem_size >> 16) & 0xFF;
 806     tmp[2] = (mem_size >> 8) & 0xFF;
 807     tmp[3] = mem_size & 0xFF;
 808     p = set_bootinfo_tag(p, 0x1017, 4, tmpi);
 809     /* BI_INITRD */
 810     tmp[0] = (env->gpr[4] >> 24) & 0xFF;
 811     tmp[1] = (env->gpr[4] >> 16) & 0xFF;
 812     tmp[2] = (env->gpr[4] >> 8) & 0xFF;
 813     tmp[3] = env->gpr[4] & 0xFF;
 814     tmp[4] = (env->gpr[5] >> 24) & 0xFF;
 815     tmp[5] = (env->gpr[5] >> 16) & 0xFF;
 816     tmp[6] = (env->gpr[5] >> 8) & 0xFF;
 817     tmp[7] = env->gpr[5] & 0xFF;
 818     p = set_bootinfo_tag(p, 0x1014, 8, tmpi);
 819     env->gpr[4] = env->gpr[5] = 0;
 820     /* BI_LAST */
 821     p = set_bootinfo_tag(p, 0x1011, 0, 0);
 822 #else
 823     /* Set up MMU:
 824      * kernel is loaded at kernel_addr and wants to be seen at 0x01000000
 825      */
 826     setup_BAT(env, 0, 0x01000000, kernel_addr, 0x00400000, 1, 0, 2);
 827     {
 828 #if 0
 829         uint32_t offset = get_le32(phys_ram_base + kernel_addr);
 830 #else
 831         uint32_t offset = 12;
 832 #endif
 833         env->nip = 0x01000000 | (kernel_addr + offset);
 834         printf("Start address: 0x%08x\n", env->nip);
 835     }
 836     env->gpr[1] = env->nip + (1 << 22);
 837     p = phys_ram_base + stack_addr;
 838     put_long(p - 32, stack_addr);
 839     env->gpr[1] -= 32;
 840     printf("Kernel starts at 0x%08x stack 0x%08x\n", env->nip, env->gpr[1]);
 841     /* We want all lower address not to be translated */
 842     setup_BAT(env, 1, 0x00000000, 0x00000000, 0x010000000, 1, 1, 2);
 843     /* We also need a BAT to access OF */
 844     setup_BAT(env, 2, 0xFFFE0000, mem_size - 131072, 131072, 1, 0, 1);
 845     /* Setup OF entry point */
 846     {
 847         char *p;
 848         p = (char *)phys_ram_base + mem_size - 131072;
 849         /* Special opcode to call OF */
 850         *p++ = 0x18; *p++ = 0x00; *p++ = 0x00; *p++ = 0x02;
 851         /* blr */
 852         *p++ = 0x4E; *p++ = 0x80; *p++ = 0x00; *p++ = 0x20;
 853     }
 854     env->gpr[5] = 0xFFFE0000;
 855     /* Register translations */
 856     {
 857         OF_transl_t translations[3] = {
 858             { 0x01000000, 0x00400000, kernel_addr, 0x00000002, },
 859             { 0x00000000, 0x01000000, 0x00000000, 0x00000002, },
 860             { 0xFFFE0000, 0x00020000, mem_size - (128 * 1024),
 861               0x00000001, },
 862         };
 863         OF_register_translations(3, translations);
 864     }
 865     /* Quite artificial, for now */
 866     OF_register_bus("isa", "isa");
 867     OF_register_serial("isa", "serial", 4, 0x3f8);
 868     OF_register_stdio("serial", "serial");
 869     /* Set up RTAS service */
 870     RTAS_init();
 871     /* Command line: let's put it just over the stack */
 872 #if 0
 873 #if 0
 874     p = phys_ram_base + kernel_addr +
 875     kernel_size + (1 << 20) - 1) & ~((1 << 20) - 1);
 876 #else
 877     p = phys_ram_base + kernel_addr + 0x400000;
 878 #endif
 879 #if 1
 880     sprintf(p, "console=ttyS0,9600 root=%02x%02x mem=%dM",
 881             boot_devs[boot_device - 'a'].major,
 882             boot_devs[boot_device - 'a'].minor,
 883             mem_size >> 20);
 884 #else
 885     sprintf(p, "console=ttyS0,9600 root=%s mem=%dM ne2000=0x300,9",
 886             boot_devs[boot_device - 'a'].name,
 887             mem_size >> 20);
 888 #endif
 889     OF_register_bootargs(p);
 890 #endif
 891 #endif
 892 }
 893
 894 void PPC_end_init (void)
 895 {
 896     VGA_init();
 897 }
 898
 899 /* PowerPC PREP hardware initialisation */
 900 void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device,
 901                    DisplayState *ds, const char **fd_filename, int snapshot,
 902                    const char *kernel_filename, const char *kernel_cmdline,
 903                    const char *initrd_filename)
 904 {
 905     char buf[1024];
 906     int PPC_io_memory;
 907     int ret, linux_boot, initrd_size, i, nb_nics1, fd;
 908
 909     linux_boot = (kernel_filename != NULL);
 910
 911     /* allocate RAM */
 912     cpu_register_physical_memory(0, ram_size, 0);
 913
 914     isa_mem_base = 0xc0000000;
 915
 916     if (linux_boot) {
 917         /* now we can load the kernel */
 918         ret = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
 919         if (ret < 0) {
 920             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 921                     kernel_filename);
 922             exit(1);
 923         }
 924         /* load initrd */
 925         initrd_size = 0;
 926 #if 0
 927         if (initrd_filename) {
 928             initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
 929             if (initrd_size < 0) {
 930                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 931                         initrd_filename);
 932                 exit(1);
 933             }
 934         }
 935 #endif
 936         PPC_init_hw(/*env,*/ ram_size, KERNEL_LOAD_ADDR, ret,
 937                     KERNEL_STACK_ADDR, boot_device, initrd_filename);
 938     } else {
 939         /* allocate ROM */
 940         //        snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
 941         snprintf(buf, sizeof(buf), "%s", BIOS_FILENAME);
 942         printf("load BIOS at %p\n", phys_ram_base + 0x000f0000);
 943         ret = load_image(buf, phys_ram_base + 0x000f0000);
 944         if (ret != 0x10000) {
 945             fprintf(stderr, "qemu: could not load PPC bios '%s' (%d)\n%m\n",
 946                     buf, ret);
 947             exit(1);
 948         }
 949     }
 950
 951     /* init basic PC hardware */
 952     vga_initialize(ds, phys_ram_base + ram_size, ram_size,
 953                    vga_ram_size);
 954     rtc_init(0x70, 8);
 955     pic_init();
 956     //    pit_init(0x40, 0);
 957
 958     fd = serial_open_device();
 959     serial_init(0x3f8, 4, fd);
 960 #if 1
 961     nb_nics1 = nb_nics;
 962     if (nb_nics1 > NE2000_NB_MAX)
 963         nb_nics1 = NE2000_NB_MAX;
 964     for(i = 0; i < nb_nics1; i++) {
 965         isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]);
 966     }
 967 #endif
 968
 969     for(i = 0; i < 2; i++) {
 970         isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
 971                      bs_table[2 * i], bs_table[2 * i + 1]);
 972     }
 973     kbd_init();
 974     AUD_init();
 975     DMA_init();
 976     //    SB16_init();
 977
 978     fdctrl_init(6, 2, 0, 0x3f0, fd_table);
 979
 980     /* Register 64 kB of IO space */
 981     PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write);
 982     cpu_register_physical_memory(0x80000000, 0x10000, PPC_io_memory);
 983     /* Register fake IO ports for PREP */
 984     register_ioport_read(0x398, 2, 1, &PREP_io_read, NULL);
 985     register_ioport_write(0x398, 2, 1, &PREP_io_write, NULL);
 986     /* System control ports */
 987     register_ioport_write(0x0092, 0x1, 1, &PREP_io_800_writeb, NULL);
 988     register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, NULL);
 989     register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, NULL);
 990     /* PCI intack location (0xfef00000 / 0xbffffff0) */
 991     PPC_io_memory = cpu_register_io_memory(0, PPC_ioB_read, PPC_ioB_write);
 992     cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
 993     //    cpu_register_physical_memory(0xFEF00000, 0x4, PPC_io_memory);
 994     prep_NVRAM_init();
 995
 996     PPC_end_init();
 997 }