target-i386/bpt_helper.c

   1 /*
   2  *  i386 breakpoint helpers
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22
  23
  24 #ifndef CONFIG_USER_ONLY
  25 static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index)
  26 {
  27     return (dr7 >> (index * 2)) & 1;
  28 }
  29
  30 static inline bool hw_global_breakpoint_enabled(unsigned long dr7, int index)
  31 {
  32     return (dr7 >> (index * 2)) & 2;
  33
  34 }
  35 static inline bool hw_breakpoint_enabled(unsigned long dr7, int index)
  36 {
  37     return hw_global_breakpoint_enabled(dr7, index) ||
  38            hw_local_breakpoint_enabled(dr7, index);
  39 }
  40
  41 static inline int hw_breakpoint_type(unsigned long dr7, int index)
  42 {
  43     return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
  44 }
  45
  46 static inline int hw_breakpoint_len(unsigned long dr7, int index)
  47 {
  48     int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
  49     return (len == 2) ? 8 : len + 1;
  50 }
  51
  52 static void hw_breakpoint_insert(CPUX86State *env, int index)
  53 {
  54     CPUState *cs = CPU(x86_env_get_cpu(env));
  55     int type = 0, err = 0;
  56
  57     switch (hw_breakpoint_type(env->dr[7], index)) {
  58     case DR7_TYPE_BP_INST:
  59         if (hw_breakpoint_enabled(env->dr[7], index)) {
  60             err = cpu_breakpoint_insert(cs, env->dr[index], BP_CPU,
  61                                         &env->cpu_breakpoint[index]);
  62         }
  63         break;
  64     case DR7_TYPE_DATA_WR:
  65         type = BP_CPU | BP_MEM_WRITE;
  66         break;
  67     case DR7_TYPE_IO_RW:
  68         /* No support for I/O watchpoints yet */
  69         break;
  70     case DR7_TYPE_DATA_RW:
  71         type = BP_CPU | BP_MEM_ACCESS;
  72         break;
  73     }
  74
  75     if (type != 0) {
  76         err = cpu_watchpoint_insert(cs, env->dr[index],
  77                                     hw_breakpoint_len(env->dr[7], index),
  78                                     type, &env->cpu_watchpoint[index]);
  79     }
  80
  81     if (err) {
  82         env->cpu_breakpoint[index] = NULL;
  83     }
  84 }
  85
  86 static void hw_breakpoint_remove(CPUX86State *env, int index)
  87 {
  88     CPUState *cs;
  89
  90     if (!env->cpu_breakpoint[index]) {
  91         return;
  92     }
  93     cs = CPU(x86_env_get_cpu(env));
  94     switch (hw_breakpoint_type(env->dr[7], index)) {
  95     case DR7_TYPE_BP_INST:
  96         if (hw_breakpoint_enabled(env->dr[7], index)) {
  97             cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]);
  98         }
  99         break;
 100     case DR7_TYPE_DATA_WR:
 101     case DR7_TYPE_DATA_RW:
 102         cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]);
 103         break;
 104     case DR7_TYPE_IO_RW:
 105         /* No support for I/O watchpoints yet */
 106         break;
 107     }
 108 }
 109
 110 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7)
 111 {
 112     target_ulong old_dr7 = env->dr[7];
 113     int i;
 114
 115     new_dr7 |= DR7_FIXED_1;
 116
 117     /* If nothing is changing except the global/local enable bits,
 118        then we can make the change more efficient.  */
 119     if (((old_dr7 ^ new_dr7) & ~0xff) == 0) {
 120         /* Fold the global and local enable bits together into the
 121            global fields, then xor to show which registers have
 122            changed collective enable state.  */
 123         int mod = ((old_dr7 | old_dr7 * 2) ^ (new_dr7 | new_dr7 * 2)) & 0xff;
 124
 125         for (i = 0; i < DR7_MAX_BP; i++) {
 126             if ((mod & (2 << i * 2)) && !hw_breakpoint_enabled(new_dr7, i)) {
 127                 hw_breakpoint_remove(env, i);
 128             }
 129         }
 130         env->dr[7] = new_dr7;
 131         for (i = 0; i < DR7_MAX_BP; i++) {
 132             if (mod & (2 << i * 2) && hw_breakpoint_enabled(new_dr7, i)) {
 133                 hw_breakpoint_insert(env, i);
 134             }
 135         }
 136     } else {
 137         for (i = 0; i < DR7_MAX_BP; i++) {
 138             hw_breakpoint_remove(env, i);
 139         }
 140         env->dr[7] = new_dr7;
 141         for (i = 0; i < DR7_MAX_BP; i++) {
 142             hw_breakpoint_insert(env, i);
 143         }
 144     }
 145 }
 146
 147 static bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update)
 148 {
 149     target_ulong dr6;
 150     int reg;
 151     bool hit_enabled = false;
 152
 153     dr6 = env->dr[6] & ~0xf;
 154     for (reg = 0; reg < DR7_MAX_BP; reg++) {
 155         bool bp_match = false;
 156         bool wp_match = false;
 157
 158         switch (hw_breakpoint_type(env->dr[7], reg)) {
 159         case DR7_TYPE_BP_INST:
 160             if (env->dr[reg] == env->eip) {
 161                 bp_match = true;
 162             }
 163             break;
 164         case DR7_TYPE_DATA_WR:
 165         case DR7_TYPE_DATA_RW:
 166             if (env->cpu_watchpoint[reg] &&
 167                 env->cpu_watchpoint[reg]->flags & BP_WATCHPOINT_HIT) {
 168                 wp_match = true;
 169             }
 170             break;
 171         case DR7_TYPE_IO_RW:
 172             break;
 173         }
 174         if (bp_match || wp_match) {
 175             dr6 |= 1 << reg;
 176             if (hw_breakpoint_enabled(env->dr[7], reg)) {
 177                 hit_enabled = true;
 178             }
 179         }
 180     }
 181
 182     if (hit_enabled || force_dr6_update) {
 183         env->dr[6] = dr6;
 184     }
 185
 186     return hit_enabled;
 187 }
 188
 189 void breakpoint_handler(CPUState *cs)
 190 {
 191     X86CPU *cpu = X86_CPU(cs);
 192     CPUX86State *env = &cpu->env;
 193     CPUBreakpoint *bp;
 194
 195     if (cs->watchpoint_hit) {
 196         if (cs->watchpoint_hit->flags & BP_CPU) {
 197             cs->watchpoint_hit = NULL;
 198             if (check_hw_breakpoints(env, false)) {
 199                 raise_exception(env, EXCP01_DB);
 200             } else {
 201                 cpu_resume_from_signal(cs, NULL);
 202             }
 203         }
 204     } else {
 205         QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
 206             if (bp->pc == env->eip) {
 207                 if (bp->flags & BP_CPU) {
 208                     check_hw_breakpoints(env, true);
 209                     raise_exception(env, EXCP01_DB);
 210                 }
 211                 break;
 212             }
 213         }
 214     }
 215 }
 216 #endif
 217
 218 void helper_single_step(CPUX86State *env)
 219 {
 220 #ifndef CONFIG_USER_ONLY
 221     check_hw_breakpoints(env, true);
 222     env->dr[6] |= DR6_BS;
 223 #endif
 224     raise_exception(env, EXCP01_DB);
 225 }
 226
 227 void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
 228 {
 229 #ifndef CONFIG_USER_ONLY
 230     if (reg < 4) {
 231         hw_breakpoint_remove(env, reg);
 232         env->dr[reg] = t0;
 233         hw_breakpoint_insert(env, reg);
 234     } else if (reg == 7) {
 235         cpu_x86_update_dr7(env, t0);
 236     } else {
 237         env->dr[reg] = t0;
 238     }
 239 #endif
 240 }