target-mips/cpu.c

   1 /*
   2  * QEMU MIPS CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "kvm_mips.h"
  24 #include "qemu-common.h"
  25 #include "sysemu/kvm.h"
  26
  27
  28 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
  29 {
  30     MIPSCPU *cpu = MIPS_CPU(cs);
  31     CPUMIPSState *env = &cpu->env;
  32
  33     env->active_tc.PC = value & ~(target_ulong)1;
  34     if (value & 1) {
  35         env->hflags |= MIPS_HFLAG_M16;
  36     } else {
  37         env->hflags &= ~(MIPS_HFLAG_M16);
  38     }
  39 }
  40
  41 static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  42 {
  43     MIPSCPU *cpu = MIPS_CPU(cs);
  44     CPUMIPSState *env = &cpu->env;
  45
  46     env->active_tc.PC = tb->pc;
  47     env->hflags &= ~MIPS_HFLAG_BMASK;
  48     env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
  49 }
  50
  51 static bool mips_cpu_has_work(CPUState *cs)
  52 {
  53     MIPSCPU *cpu = MIPS_CPU(cs);
  54     CPUMIPSState *env = &cpu->env;
  55     bool has_work = false;
  56
  57     /* Prior to MIPS Release 6 it is implementation dependent if non-enabled
  58        interrupts wake-up the CPU, however most of the implementations only
  59        check for interrupts that can be taken. */
  60     if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
  61         cpu_mips_hw_interrupts_pending(env)) {
  62         if (cpu_mips_hw_interrupts_enabled(env) ||
  63             (env->insn_flags & ISA_MIPS32R6)) {
  64             has_work = true;
  65         }
  66     }
  67
  68     /* MIPS-MT has the ability to halt the CPU.  */
  69     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
  70         /* The QEMU model will issue an _WAKE request whenever the CPUs
  71            should be woken up.  */
  72         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
  73             has_work = true;
  74         }
  75
  76         if (!mips_vpe_active(env)) {
  77             has_work = false;
  78         }
  79     }
  80     /* MIPS Release 6 has the ability to halt the CPU.  */
  81     if (env->CP0_Config5 & (1 << CP0C5_VP)) {
  82         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
  83             has_work = true;
  84         }
  85         if (!mips_vp_active(env)) {
  86             has_work = false;
  87         }
  88     }
  89     return has_work;
  90 }
  91
  92 /* CPUClass::reset() */
  93 static void mips_cpu_reset(CPUState *s)
  94 {
  95     MIPSCPU *cpu = MIPS_CPU(s);
  96     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
  97     CPUMIPSState *env = &cpu->env;
  98
  99     mcc->parent_reset(s);
 100
 101     memset(env, 0, offsetof(CPUMIPSState, mvp));
 102     tlb_flush(s, 1);
 103
 104     cpu_state_reset(env);
 105
 106 #ifndef CONFIG_USER_ONLY
 107     if (kvm_enabled()) {
 108         kvm_mips_reset_vcpu(cpu);
 109     }
 110 #endif
 111 }
 112
 113 static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) {
 114 #ifdef TARGET_WORDS_BIGENDIAN
 115     info->print_insn = print_insn_big_mips;
 116 #else
 117     info->print_insn = print_insn_little_mips;
 118 #endif
 119 }
 120
 121 static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
 122 {
 123     CPUState *cs = CPU(dev);
 124     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
 125
 126     cpu_reset(cs);
 127     qemu_init_vcpu(cs);
 128
 129     mcc->parent_realize(dev, errp);
 130 }
 131
 132 static void mips_cpu_initfn(Object *obj)
 133 {
 134     CPUState *cs = CPU(obj);
 135     MIPSCPU *cpu = MIPS_CPU(obj);
 136     CPUMIPSState *env = &cpu->env;
 137
 138     cs->env_ptr = env;
 139     cpu_exec_init(cs, &error_abort);
 140
 141     if (tcg_enabled()) {
 142         mips_tcg_init();
 143     }
 144 }
 145
 146 static void mips_cpu_class_init(ObjectClass *c, void *data)
 147 {
 148     MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
 149     CPUClass *cc = CPU_CLASS(c);
 150     DeviceClass *dc = DEVICE_CLASS(c);
 151
 152     mcc->parent_realize = dc->realize;
 153     dc->realize = mips_cpu_realizefn;
 154
 155     mcc->parent_reset = cc->reset;
 156     cc->reset = mips_cpu_reset;
 157
 158     cc->has_work = mips_cpu_has_work;
 159     cc->do_interrupt = mips_cpu_do_interrupt;
 160     cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
 161     cc->dump_state = mips_cpu_dump_state;
 162     cc->set_pc = mips_cpu_set_pc;
 163     cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
 164     cc->gdb_read_register = mips_cpu_gdb_read_register;
 165     cc->gdb_write_register = mips_cpu_gdb_write_register;
 166 #ifdef CONFIG_USER_ONLY
 167     cc->handle_mmu_fault = mips_cpu_handle_mmu_fault;
 168 #else
 169     cc->do_unassigned_access = mips_cpu_unassigned_access;
 170     cc->do_unaligned_access = mips_cpu_do_unaligned_access;
 171     cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
 172     cc->vmsd = &vmstate_mips_cpu;
 173 #endif
 174     cc->disas_set_info = mips_cpu_disas_set_info;
 175
 176     cc->gdb_num_core_regs = 73;
 177     cc->gdb_stop_before_watchpoint = true;
 178
 179     /*
 180      * Reason: mips_cpu_initfn() calls cpu_exec_init(), which saves
 181      * the object in cpus -> dangling pointer after final
 182      * object_unref().
 183      */
 184     dc->cannot_destroy_with_object_finalize_yet = true;
 185 }
 186
 187 static const TypeInfo mips_cpu_type_info = {
 188     .name = TYPE_MIPS_CPU,
 189     .parent = TYPE_CPU,
 190     .instance_size = sizeof(MIPSCPU),
 191     .instance_init = mips_cpu_initfn,
 192     .abstract = false,
 193     .class_size = sizeof(MIPSCPUClass),
 194     .class_init = mips_cpu_class_init,
 195 };
 196
 197 static void mips_cpu_register_types(void)
 198 {
 199     type_register_static(&mips_cpu_type_info);
 200 }
 201
 202 type_init(mips_cpu_register_types)